JP2021170609A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of reducing an on-resistance and a method for manufacturing the semiconductor device.SOLUTION: A main semiconductor element 11 is a vertical MOSFET of a trench gate structure in which a source electrode is electrically connected to an n+ type source region 35a and a p++ type contact region 36a in an inner wall of a contact trench 50a. A contact part 51a of the n+ type source region 35a exposed on a side wall of the contact trench 50a is a portion in which an Ohmic contact with the source electrode is formed, and has a higher n type impurity concentration than other portions (portions excluding the contact part 51a). A contact portion 52a of the p++ type contact region 36a exposed on the side wall and a bottom surface of the contact trench 50a is a portion an Ohmic contact with the source electrode is formed, and has a higher p type impurity concentration than other portions (portions excluding the contact part 52a) of the p++ type contact region 36a.SELECTED DRAWING: Figure 2

Description

The present invention relates to semiconductor devices and methods for manufacturing semiconductor devices.

Conventionally, power semiconductor devices that control high voltage and large current include, for example, bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: Metal-Oxide Transistors). There are a plurality of types (MOS type field effect transistors) equipped with an insulating gate (MOS gate) having a three-layer structure, and these are used properly according to the application.

For example, bipolar transistors and IGBTs have a higher current density than MOSFETs and can increase the current, but they cannot be switched at high speed. Specifically, the bipolar transistor is limited to use at a switching frequency of about several kHz, and the IGBT is limited to use at a switching frequency of about several tens of kHz. On the other hand, MOSFETs have a lower current density than bipolar transistors and IGBTs, making it difficult to increase the current, but they can perform high-speed switching operations up to about several MHz.

Further, unlike the IGBT, the MOSFET incorporates a parasitic diode formed by a pn junction between a ^{p-type base region and an n-type drift region inside a semiconductor substrate (semiconductor chip), and protects the parasitic diode itself.} It can be used as a freewheeling diode. Therefore, when the MOSFET is used as an inverter device, it can be used without adding an external freewheeling diode to the MOSFET and connecting it, which is attracting attention in terms of economy.

Silicon (Si) is used as a constituent material of a power semiconductor device. There is a strong demand in the market for power semiconductor devices that have both large current and high speed, and efforts have been made to improve IGBTs and MOSFETs, and development is now progressing to near the material limit. For this reason, semiconductor materials that can replace silicon are being studied from the perspective of power semiconductor devices, and silicon carbide is a semiconductor material that can manufacture (manufacture) next-generation power semiconductor devices with excellent low-on-voltage, high-speed characteristics, and high-temperature characteristics. (SiC) is attracting attention.

Silicon carbide is a chemically stable semiconductor material, has a wide bandgap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures. Further, since silicon carbide has a maximum electric field strength that is an order of magnitude higher than that of silicon, it is expected as a semiconductor material capable of sufficiently reducing the on-resistance. Such features of silicon carbide include not only silicon carbide but also all semiconductors having a bandgap wider than that of silicon (hereinafter referred to as wide bandgap semiconductors).

Further, in the MOSFET, as compared with the case of having a planar gate structure in which a channel (inversion layer) is formed along the front surface of the semiconductor chip as the current increases, the semiconductor chip is formed along the side wall of the gate trench. It is advantageous in terms of cost to have a trench gate structure in which channels are formed in a direction orthogonal to the front surface. The reason is that the trench gate structure can increase the unit cell (constituent unit of the element) density per unit area, so that the current density per unit area can be increased.

As the current density per unit area is increased, the temperature rise rate according to the occupied volume of the unit cell increases, so a double-sided cooling structure is required to improve discharge efficiency and stabilize reliability. .. Further, on the same semiconductor substrate as the main semiconductor element that performs the main operation of the power semiconductor device, high-performance parts such as a current sense part, a temperature sense part, and an overvoltage protection part are used as circuit parts for protecting and controlling the main semiconductor element. A power semiconductor device with improved reliability has been proposed by having a high-performance structure in which the above are arranged.

The structure of a conventional semiconductor device will be described. FIG. 18 is a cross-sectional view showing the structure of a conventional semiconductor device. The conventional semiconductor device 220 shown in FIG. 18 is a vertical MOSFET having a MOS gate having a general trench gate structure on the front surface side of a semiconductor substrate (semiconductor chip) 210 made of silicon carbide. The semiconductor substrate 210 is formed by epitaxially growing each silicon carbide layer 272, 273 which becomes an ^n- type drift region 232 and a p-type base region 234 on the front surface of an ^{n + type starting substrate 271 made of silicon carbide.}

The main surface of the semiconductor substrate 210 on the p-type silicon carbide layer 273 side is the front surface, and the main surface on the n ⁺ type departure substrate 271 side ( ^{the back surface of the n +} type departure substrate 271) is the back surface. The MOS gate is composed of a p-type base region 234, an n ⁺ -type source region 235, a p ⁺⁺ type contact region 236, a gate trench 237, a gate insulating film 238, and a gate electrode 239. The p-type base region 234, the n ⁺ -type source region 235, and the p ^++- type contact region 236 are selectively provided between the gate trenches 237 adjacent to each other.

The n ⁺ type source region 235 and the p ⁺⁺ type contact region 236 are provided between the front surface of the semiconductor substrate 210 and the p-type base region 234 in contact with the p-type base region 234. The n ⁺ type source region 235 and the p ⁺⁺ type contact region 236 are each exposed on the front surface of the semiconductor substrate 210. The exposure on the front surface of the semiconductor substrate 210 means that the n ⁺ type source region 235 and the p ⁺⁺ type contact region 236 are in contact with the NiSi film 241 on the front surface (flat surface) of the semiconductor substrate 210.

The NiSi film 241 is in ohmic contact with the semiconductor substrate 210 inside the contact hole 240a of the interlayer insulating film 240, ^{and is electrically connected to the n +} type source region 235 and the p ⁺⁺ type contact region 236. ^{The source pad 221 is electrically connected to the n +} type source region 235 and the p ⁺⁺ type contact region 236 via the barrier metal 246 and the NiSi film 241. The source pad 221 and the barrier metal 246 and the NiSi film 241 function as source electrodes.

The plating film 247, the terminal pins 248, and the protective films 249,250 constitute a wiring structure on the source pad 221. The wiring structure on the source pad 221 and the cooling fins (not shown) on the back surface side of the semiconductor substrate 210 form a double-sided cooling structure. Reference numerals 231,233 and 251 are an n ⁺ type drain region, an n type current diffusion region and a drain electrode, respectively. Reference numerals 242 to 245 are metal films constituting the barrier metal 246. ^{Reference numerals 261,262 are p +} type regions that relax the electric field applied to the bottom surface of the gate trench 237.

As a conventional semiconductor device, a device ^{in which ohmic contact between a source electrode and an n +} type source region and a p ⁺ type contact region is formed on an inner wall of a contact trench has been proposed (see, for example, Patent Document 1 below). In Patent Document 1, to form a p-type electric field relaxation region along the inner wall of the contact trench cross-sectional shape of the narrowed trapezoidal width of the bottom side to the opening side, a p-type field relaxation region and the n ^- -type By inclining the pn junction with the drift region with respect to the side wall of the gate trench, both improvement of dielectric breakdown withstand voltage and reduction of on-resistance are achieved.

As a conventional semiconductor device, the bottom surface and the n gate trench ^- a p-type base region which is provided between the type drift region, sidewall and n gate trench ^- p-type connection region provided between the type drift region Has proposed a device electrically connected to the p-type base region (see, for example, Patent Document 2 below). In Patent Document 2, turn-off, p-type base region, p-type connection region and the p-type base region and the n ^- by extending the depletion layer to substantially the entire type drift region, ^- from the pn junction between the type drift region n The dielectric breakdown withstand voltage is improved.

As a conventional method for manufacturing a semiconductor device, an ion implantation of n-type impurities (hereinafter referred to as oblique ion implantation) from an oblique direction with respect to the front surface of the semiconductor substrate into the side wall of the trench is performed to obtain a p-type base region. A method of reducing the concentration of p-type impurities in the portion exposed on the side wall of the trench has been proposed (see, for example, Patent Document 3 below). In Patent Document 3 below, the p-type impurity concentration is lowered only in the channel-forming portion of the p-type base region by oblique ion implantation of the n-type impurity, and the gate threshold voltage is increased due to the ion implantation of the p-type impurity into the bottom surface of the trench. Is suppressed.

JP-A-2018-014455 JP-A-2018-060943 Japanese Unexamined Patent Publication No. 2017-188562

In the conventional semiconductor device 220 (see FIG. 18), in order to reduce the on-resistance, the unit cells may be miniaturized and the number of unit cells in one semiconductor substrate 210 may be increased to increase the cell density. In order to miniaturize the unit cells, the distance between the gate trenches 237 adjacent to each other is shortened in each unit cell, and the contact area between the source electrode (NiSi film 241) and the semiconductor substrate 210 (NiSi film 241 and the semiconductor substrate) is shortened. It is necessary to reduce the ohmic contact area with 210).

However, as the contact area between the semiconductor substrate 210 and the source electrode becomes smaller, the contact resistance (contact resistance) between the source electrode and the semiconductor substrate 210 becomes higher, and the etching residue and the semiconductor substrate 210 generated when the contact hole 240a is formed are increased. Due to process factors such as surface roughness, the on-resistance varies widely from unit cell to unit. Therefore, there is a problem that the low on-resistance that should be obtained with the miniaturization of the unit cell cannot be realized.

An object of the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device capable of reducing on-resistance in order to solve the above-mentioned problems caused by the prior art.

In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A first conductive type first semiconductor region is provided inside a semiconductor substrate made of a semiconductor having a bandgap wider than that of silicon. A second conductive type second semiconductor region is provided between the first main surface of the semiconductor substrate and the first semiconductor region. A first conductive type third semiconductor region is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. The gate trench penetrates the third semiconductor region and the second semiconductor region from the first main surface of the semiconductor substrate and reaches the first semiconductor region. A gate electrode is provided inside the gate trench via a gate insulating film.

The contact trench is provided apart from the gate trench, penetrates the third semiconductor region from the first main surface of the semiconductor substrate, and reaches the second semiconductor region. A plurality of unit cells having the first to third semiconductor regions, the gate trench, the gate electrode, and the contact trench are provided. The first electrode is electrically connected to the third semiconductor region at the side wall of the contact trench, and is electrically connected to the second semiconductor region at the side wall and bottom surface of the contact trench. The second electrode is provided on the second main surface of the semiconductor substrate. The third semiconductor region is a first portion exposed on the side wall of the contact trench, and has a higher concentration of first conductive impurities than the second portion excluding the first portion. The first electrode is in contact with the third semiconductor region at the first portion.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the concentration of the first conductive impurity in the first portion of the third semiconductor region is uniform in the depth direction.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the third semiconductor region is further in contact with the first electrode on the first main surface of the semiconductor substrate.

Further, in the above-described invention, the semiconductor device according to the present invention is separated from the gate trench at a depth position inside the semiconductor substrate, which is farther from the first main surface of the semiconductor substrate than the third semiconductor region. A second conductive type fourth semiconductor region provided, which is in contact with the second semiconductor region and is exposed on the side wall and the bottom surface of the contact trench, is further provided. The first electrode is in contact with the fourth semiconductor region.

Further, in the semiconductor device according to the present invention, in the above-described invention, the fourth semiconductor region is a third portion exposed from the side wall of the contact trench to the bottom surface, and is a second portion than the fourth portion excluding the third portion. High concentration of conductive impurities. The first electrode is characterized in that the third portion is in contact with the fourth semiconductor region.

Further, in the semiconductor device according to the present invention, in the above-described invention, the unit cell is composed of a portion between the centers of the gate trenches adjacent to each other. The unit cell has a pitch of 2 μm or less.

Further, in order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a semiconductor device according to the present invention has the following features. The first step of forming a first conductive type first semiconductor region inside a semiconductor substrate made of a semiconductor having a bandgap wider than that of silicon is performed. A second step of forming a second conductive type second semiconductor region in contact with the first semiconductor region is performed between the first main surface of the semiconductor substrate and the first semiconductor region. A third step is performed between the first main surface of the semiconductor substrate and the second semiconductor region in contact with the second semiconductor region to selectively form a first conductive type third semiconductor region. A fourth step is performed in which a gate trench is formed from the first main surface of the semiconductor substrate through the third semiconductor region and the second semiconductor region to reach the first semiconductor region. The fifth step of forming the gate electrode inside the gate trench via the gate insulating film is performed.

A sixth step is performed in which a contact trench is formed apart from the gate trench, from the first main surface of the semiconductor substrate, penetrating the third semiconductor region, and reaching the second semiconductor region. The first conductive impurity is ion-implanted into the side wall of the contact trench from an oblique direction with respect to the first main surface of the semiconductor substrate, and the concentration of the first conductive impurity in the third semiconductor region is set to the contact trench. A seventh step of making the first portion exposed on the side wall higher than the second portion excluding the first portion, and a cell forming step of forming a plurality of unit cells by performing the first to eighth steps are performed. After the cell forming step, the side wall of the contact trench is in contact with the first portion and is electrically connected to the third semiconductor region, and the side wall and bottom surface of the contact trench are electrically connected to the second semiconductor region. The eighth step of forming the connected first electrode is performed. After the cell forming step, a ninth step of forming the second electrode provided on the second main surface of the semiconductor substrate is performed.

Further, in the method for manufacturing a semiconductor device according to the present invention, in the above-described invention, the second conductive type impurity is ion-implanted into the inside of the second semiconductor region, and the second conductive type fourth separated from the gate trench. It further includes a step of selectively forming the semiconductor region. The eighth step is characterized in that the first electrode in contact with the fourth semiconductor region is formed.

Further, the method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above-described invention, in the step of selectively forming the fourth semiconductor region, ions are implanted into the side wall and the bottom surface of the contact trench.

Further, in the method for manufacturing a semiconductor device according to the present invention, in the above-described invention, the steps for selectively forming the fourth semiconductor region are the tenth step performed before the sixth step and the sixth step. The eleventh step, which is performed later than the above, is included. In the tenth step, the fourth semiconductor region is formed in the second semiconductor region below the third semiconductor region. In the eleventh step, ions are implanted into the side wall of the contact trench from an oblique direction with respect to the first main surface of the semiconductor substrate, and the concentration of the second conductive impurity in the fourth semiconductor region is adjusted to the contact trench. The third portion exposed from the side wall to the bottom surface is higher than the fourth portion excluding the third portion. The sixth step is characterized in that the contact trench is formed from the first main surface of the semiconductor substrate through the third semiconductor region and reaches the fourth semiconductor region.

According to the above-described invention, the contact area between the first electrode and the semiconductor substrate is reduced even if the unit cell is miniaturized by electrically connecting the third semiconductor region and the first electrode on the side wall of the contact trench. Is widened by the area of the side wall of the contact trench, and stable contact between the first electrode and the semiconductor substrate can be obtained. As a result, the variation in the on-resistance for each unit cell can be reduced, so that the low on-resistance that should be obtained with the miniaturization of the unit cell can be realized.

Further, according to the above-described invention, the concentration of the first conductive type impurity in the third semiconductor region is uniformly increased in the depth direction at the portion (contact portion) exposed on the side wall of the contact trench, and the third semiconductor The first electrode comes into contact with the contact portion of the region. As a result, the contact resistance between the first electrode and the third semiconductor region can be reduced, and the supply of electrons supplied from the first electrode to the channel (n-type inversion layer) through the third semiconductor region when turned on. Since the amount can be increased, the on-resistance can be reduced.

According to the semiconductor device and the method for manufacturing the semiconductor device according to the present invention, there is an effect that the on-resistance can be reduced.

FIG. 5 is a plan view showing a layout of the semiconductor device according to the embodiment as viewed from the front surface side of the semiconductor substrate. It is sectional drawing which shows the cross-sectional structure of the active region of FIG. It is sectional drawing which shows the cross-sectional structure of the active region of FIG. It is sectional drawing which shows another example of the cross-sectional structure of the active region of FIG. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is a characteristic figure which shows typically the voltage / current characteristic of an Example. It is a characteristic figure which shows typically the voltage / current characteristic of the conventional example. It is a characteristic figure which shows the current amount of the breaking current by the reverse recovery withstand capacity of an Example. It is sectional drawing which shows the structure of the conventional semiconductor device.

Hereinafter, preferred embodiments of the semiconductor device and the method for manufacturing the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that the electrons or holes are a large number of carriers in the layers and regions marked with n or p, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively. In the following description of the embodiment and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted.

(Embodiment)
The semiconductor device according to the embodiment is configured by using a semiconductor (wide bandgap semiconductor) having a bandgap wider than that of silicon (Si) as a semiconductor material. Here, the structure of the semiconductor device according to the embodiment will be described by taking as an example the case where silicon carbide (SiC) is used as the wide bandgap semiconductor material constituting the semiconductor device according to the embodiment. FIG. 1 is a plan view showing a layout of the semiconductor device according to the embodiment as viewed from the front surface side of the semiconductor substrate.

The semiconductor device 20 according to the embodiment shown in FIG. 1 protects and controls the main semiconductor element 11 and the main semiconductor element 11 in the active region 1 of the same semiconductor substrate (semiconductor chip) 10 made of silicon carbide. It has one or more circuit units of the above. The active region 1 is provided in the substantially center (center of the chip) of the semiconductor substrate 10. The main semiconductor element 11 is a vertical MOSFET that performs the main operation of the semiconductor device 20, and is composed of a plurality of unit cells (functional units of the element) connected in parallel to each other by a source pad 21a described later.

The main semiconductor element 11 is arranged in the effective region (hereinafter referred to as the main effective region) 1a of the active region 1. The main effective region 1a is the main current (drift current) of the main semiconductor element 11 in the direction from the back surface to the front surface of the semiconductor substrate 10 (opposite to the depth direction Z) when the main semiconductor element 11 is turned on. Is the area where the current flows. The main effective region 1a has, for example, a substantially rectangular planar shape and occupies most of the surface area of the active region 1. The three sides of the main effective region 1a having a substantially rectangular planar shape are adjacent to the edge termination region 2 described later.

The circuit unit for protecting and controlling the main semiconductor element 11 is, for example, a high-performance unit such as a current sense unit 12, a temperature sense unit 13, an overvoltage protection unit (not shown), and an arithmetic circuit unit (not shown). It is arranged in the main invalid region 1b of the active region 1. The main invalid region 1b is an region in which the unit cell of the main semiconductor element 11 is not arranged, and does not function as the main semiconductor element 11. The main invalid region 1b has, for example, a substantially rectangular planar shape, and is arranged between the remaining one side of the substantially rectangular planar shape main effective region 1a and the edge termination region 2.

The edge termination region 2 is a region between the active region 1 and the end portion (chip end portion) of the semiconductor substrate 10, and is adjacent to the active region 1 and surrounds the active region 1 so as to surround the semiconductor substrate 10. It has the function of relaxing the electric field on the front surface side and maintaining the withstand voltage. In the edge termination region 2, for example, a general pressure resistant structure (not shown) such as a field limiting ring (FLR: Field Limiting Ring) or a junction termination (JTE: Junction Termination Extension) structure is arranged. The withstand voltage is the limit voltage at which the semiconductor device does not malfunction or break.

The source pad (electrode pad) 21a of the main semiconductor element 11 is arranged on the front surface of the semiconductor substrate 10 in the main effective region 1a. The source pad 21a of the main semiconductor element 11 is arranged apart from the electrode pads other than the source pad 21a. The main semiconductor element 11 has a larger current capacity than other circuit units. Therefore, the source pad 21a of the main semiconductor element 11 has a substantially rectangular planar shape that is the same as the planar shape of the main effective region 1a, and covers almost the entire surface of the main effective region 1a.

The electrode pads other than the source pad 21a are arranged apart from each other on the front surface of the semiconductor substrate 10 in the main invalid region 1b. The electrode pads other than the source pad 21a include the gate pad 21b of the main semiconductor element 11, the electrode pad (OC pad) 22 of the current sense unit 12, and the electrode pads (anode pad and cathode pad) 23a and 23b of the temperature sense unit 13. These include an electrode pad of the overvoltage protection unit (hereinafter referred to as an OV pad: not shown), an electrode pad of the arithmetic circuit unit (not shown), and the like.

The electrode pads other than the source pad 21a have, for example, a substantially rectangular planar shape, and have a surface area required for joining terminal pins 46b to 46d (see FIGS. 2 and 3) and wires (not shown), which will be described later. FIG. 1 shows a case where the electrode pads other than the source pad 21a are arranged in a row along the boundary between the main invalid region 1b and the edge termination region 2. Further, in FIG. 1, the source pad 21a, the gate pad 21b, the OC pad 22, the anode pad 23a and the cathode pad 23b are illustrated in a rectangular shape with S, G, OC, A and K, respectively.

The current sense unit 12 is connected in parallel to the main semiconductor element 11 and operates under the same conditions as the main semiconductor element 11 to have a function of detecting an overcurrent (OC: Overcurent) flowing through the main semiconductor element 11. The current sense unit 12 is arranged apart from the main semiconductor element 11. The current sense unit 12 is a vertical type in which the number of unit cells having the same configuration as that of the main semiconductor element 11 is smaller (for example, about 10) than the number of unit cells of the main semiconductor element 11 (for example, about 1,000 or more). It is a MOSFET and has a smaller surface area than the main semiconductor element 11.

The unit cell of the current sense unit 12 is arranged in a part of a region (hereinafter referred to as a sense effective region) 12a of the region covered with the OC pad 22 of the semiconductor substrate 10. The unit cells of the current sense unit 12 are arranged adjacent to each other in the direction parallel to the front surface of the semiconductor substrate 10. The direction in which the unit cells of the current sense unit 12 are adjacent to each other is the same as the direction in which the unit cells of the main semiconductor element 11 are adjacent to each other, for example. The unit cells of the current sense unit 12 are connected in parallel to each other by the OC pad 22.

Further, in the region of the semiconductor substrate 10 covered with the OC pad 22, the region excluding the sense effective region 12a is the sense invalid region 12b that does not function as the current sense unit 12. The unit cell of the current sense unit 12 is not arranged in the sense invalid region 12b. A p-type base region 34b (see FIG. 2), which will be described later, extends from the sense effective region 12a to the surface region of the front surface of the semiconductor substrate 10 in almost the entire region of the main invalid region 1b excluding the sense effective region 12a. Exists.

The temperature sense unit 13 has a function of detecting the temperature of the main semiconductor element 11 by utilizing the temperature characteristics of the diode. The temperature sense unit 13 is arranged directly below the anode pad 23a and the cathode pad 23b. The temperature sense unit 13 may be, for example, a polysilicon diode composed of a polysilicon (poly-Si) layer provided on the interlayer insulating film 40 on the front surface of the semiconductor substrate 10, or the semiconductor substrate. It may be a diffusion diode formed by a pn junction of a p-type region and an n-type region formed inside the 10.

The overvoltage protection unit (not shown) is a diode that protects the main semiconductor element 11 from overvoltage (OV: Over Voltage) such as a surge. The current sense unit 12, the temperature sense unit 13, and the overvoltage protection unit are controlled by the arithmetic circuit unit. The arithmetic circuit unit controls the main semiconductor element 11 based on the output signals of the current sense unit 12, the temperature sense unit 13, and the overvoltage protection unit. The arithmetic circuit unit is composed of a plurality of semiconductor elements such as a CMOS (Complementary MOS) circuit.

Next, the cross-sectional structure of the semiconductor device 20 according to the embodiment will be described. 2 and 3 are cross-sectional views showing a cross-sectional structure of the active region of FIG. FIG. 4 is a cross-sectional view showing another example of the cross-sectional structure of the active region of FIG. FIG. 2 shows the cross-sectional structure (cross-sectional structure in the cutting line X1-X2-X3-X4 of FIG. 1) of the main effective region 1a and the current sense portion 12 (sense effective region 12a and sense invalid region 12b).

FIG. 3 shows the cross-sectional structures of the main effective region 1a, the sense effective region 12a, and the temperature sense unit 13 (cross-sectional structures at the cutting lines X1-X2, cutting lines X3-X4, and cutting lines Y1-Y2 in FIG. 1). Some unit cells are shown in the main effective region 1a and the sense effective region 12a in FIGS. 2 and 3, respectively. FIG. 4 shows another example of the cross-sectional structure of the main effective region 1a of FIG. 1 (cross-sectional structure of the cutting lines X1-X2 of FIG. 1).

The main semiconductor element 11 has a contact trench 50a on the front surface of the semiconductor substrate 10 in the main effective region 1a, and the n ⁺ type source region (third semiconductor region) 35a and p ^{++ on the inner wall of the contact trench 50a.} This is a vertical MOSFET having a trench gate structure in which a source electrode (first electrode) is electrically connected to a mold contact region (fourth semiconductor region) 36a. The semiconductor substrate 10 has an ^n- type drift region (first semiconductor region) 32 and a p-type base region (second semiconductor region) 34a on the front surface of the ^{n + type starting substrate 71 made of silicon carbide.} The silicon layers 72 and 73 are epitaxially grown in this order.

The n ^{+ type starting substrate 71 serves as an n +} type drain region 31 of the main semiconductor element 11 and the current sense unit 12. The main surface of the semiconductor substrate 10 on the p-type silicon carbide layer 73 side is the front surface, and the main surface on the n ⁺ type departure substrate 71 side ( ^{the back surface of the n +} type departure substrate 71) is the back surface. Here, an example is taken in the case where the main semiconductor element 11 and the circuit unit that protects and controls the main semiconductor element 11 have a wiring structure having the same configuration using pin-shaped wiring members (terminal pins 46a to 46d described later). As will be described, a wiring structure using a wire may be used instead of the pin-shaped wiring member.

A MOS gate is composed of a p-type base region 34a, an n ⁺ -type source region 35a, a p ⁺⁺ type contact region 36a, a gate trench 37a, a gate insulating film 38a, and a gate electrode 39a. The gate trench 37a penetrates the p-type silicon carbide layer 73 from the front surface (surface of the p-type silicon carbide layer 73) of the semiconductor substrate 10 ^{and reaches the n-} type silicon carbide layer 72. A gate electrode 39a is provided inside the gate trench 37a via a gate insulating film 38a. The gate electrode 39a is electrically connected to the gate pad 21b (see FIG. 1).

The gate trench 37a may be arranged in a stripe shape extending in the first direction X parallel to the front surface of the semiconductor substrate 10, or may be arranged in a matrix shape when viewed from the front surface side of the semiconductor substrate 10. May be placed in. When the gate trench 37a is striped, for example, all the parts may be arranged in a straight line extending in the first direction X between the gate trenches 37a adjacent to each other, or the p ⁺⁺ type contact region 36a may be arranged. , The contact trench 50a and the contact portions 51a and 52a described later may be scattered in the first direction X.

Between the gate trenches 37a adjacent to each other, a p-type base region 34a, an n ⁺ -type source region 35a, and a p ^++- type contact region 36a are selectively provided on the surface region of the front surface of the semiconductor substrate 10. There is. In addition to this, a contact trench 50a that reaches a predetermined depth from the front surface of the semiconductor substrate 10 is provided, for example, substantially in the center between the gate trenches 37a adjacent to each other. The contact trench 50a ^{may be terminated within the p ++} type contact region 36a or the p-type base region 34a, and its depth can be variously changed.

The n ⁺ type source region 35a is provided between the front surface of the semiconductor substrate 10 and the p-type base region 34a in contact with the p-type base region 34a. The n ⁺ type source region 35a is exposed on the front surface of the semiconductor substrate 10. Exposure on the front surface of the semiconductor substrate 10 means that the n ⁺ type source region 35a is parallel to the front surface of the semiconductor substrate 10 (directions orthogonal to the depth direction Z (first and second directions X and Y)). The flat surface) is in contact with the Ti film 41a described later (FIGS. 2 and 3), or the front surface of the semiconductor substrate 10 is in contact with the interlayer insulating film 40 described later (FIG. 4).

The n ⁺ type source region 35a is provided between the gate trench 37a and the contact trench 50a adjacent to each other, and is provided between the opposite side walls of the gate trench 37a and the contact trench 50a. Therefore, the n ⁺ type source region 35a comes into contact with the gate insulating film 38a on the side wall of the gate trench 37a and reaches the side wall of the contact trench 50a adjacent to each other with the side wall of the gate trench 37a sandwiched from the side wall of the gate trench 37a. In contact with the Ti film 41a on the side wall of the.

The n ⁺ type source region 35a is a diffusion region formed by ion-implanting n-type impurities from a direction substantially orthogonal to the front surface of the semiconductor substrate 10. The n ⁺ type source region 35a has, for example, a peak (maximum value) of the n-type impurity concentration at a depth position close to the front surface of the semiconductor substrate 10 (a position shallow from the front surface of the semiconductor substrate 10). It has an n-type impurity concentration distribution in which the n-type impurity concentration decreases as the distance from the front surface of the semiconductor substrate 10 increases in the depth direction Z from the peak depth position.

The ^{portion (hereinafter referred to as the contact portion (first portion)) 51a of the n +} type source region 35a exposed to the side wall of the contact trench 50a is a portion where ohmic contact with the Ti film 41a is formed, and n ^+. The n-type impurity concentration is higher than the other portions of the mold source region 35a (the portion excluding the contact portion 51a, the second portion). As a result, the contact resistance (contact resistance) between the source electrode and the n ⁺ type source region 35a is reduced, and the amount of electrons supplied to the channel (n-type inversion layer) can be increased, so that the on-resistance is reduced. be able to. The exposure to the side wall of the contact trench 50a means that the contact portion 51a is in contact with the Ti film 41a described later on the side wall of the contact trench 50a.

The contact portion 51a of the n ⁺ type source region 35a is implanted in the surface region of the side wall of the contact trench 50a along the side wall of the contact trench 50a by oblique ion implantation of n-type impurities 96,97 (see FIGS. 9 and 10) described later. It is a formed diffusion region. The concentration of n-type impurities in the contact portion 51a of the ^{n + -type source region 35a is uniform in the depth direction Z.} As a result, stable ohmic contact between the source electrode and the n ⁺ type source region 35a can be obtained. The uniform impurity concentration means that the impurity concentration is the same within a range including an error allowed due to process variation.

Further, in the conventional semiconductor device 220, when an overvoltage is applied between the source and drain at the time of turn-off ^{, not only the inside of the n-} type drift region 232 but also the inside of the ^{n-type drift region 232 from the pn junction between the p-type base region 234 and the n-} type drift region 232. , The depletion layer also spreads inside the p-type base region 234. As the depletion layer spreads inside the ^{p-type base region 234, the electric field rises in the direction from the n-} type drift region 232 toward the p-type base region 234, and this electric field causes holes inside the p-type base region 234 to be source electrodes. It moves to the side and is spit out. The parasitic BJT malfunctions due to the voltage drop caused by the holes inside the p-type base region 234 being discharged to the source electrode.

On the other hand, in the present embodiment, by increasing the concentration of n-type impurities in the contact portion 51a of the ^{n + type source region 35a as described above, the contact resistance between the source electrode and the n +} type source region 35a is reduced. ing. Therefore, the voltage drop caused by the holes inside the p-type base region 34a being discharged to the source electrode at the time of turn-off of the main semiconductor element 11 can be reduced, and the parasitic BJT does not malfunction. Further, even at the time of a short circuit, as in the case of the turn-off, a current several times or more that at the time of the turn-off flows, and a voltage accompanying the current flows. Therefore, it is possible to eliminate the malfunction of the parasitic BJT at the time of a short circuit.

Further, ^{the contact portion 51a of the n +} type source region 35a has a peak (maximum value) of the n-type impurity concentration at a position close to the side wall of the contact trench 50a, and the side wall of the contact trench 50a from the position of the peak. The n-type impurity concentration decreases as the distance from the side wall of the contact trench 50a increases in the direction orthogonal to (here, the second direction Y parallel to the front surface of the semiconductor substrate 10 and orthogonal to the first direction X). .. As a result, the contact resistance between the source electrode and the n ⁺ type source region 35a can be reduced, so that the on-resistance can be reduced. Further, as described above, since the malfunction of the parasitic BJT can be eliminated, the fracture tolerance at the time of transient (during switching or short circuit) can be improved.

Further, ^{since n-type impurities due to oblique ion implantation 96 and 97 are not introduced into the portion of the n +} type source region 35a away from the side wall of the contact trench 50a (the portion excluding the contact portion 51a), the n ⁺ type source region The n-type impurity concentration distribution at the time of formation of 35a is maintained. Therefore, the ^{concentration of n-type impurities in the portion of the n +} -type source region 35a excluding the contact portion 51a decreases in the depth direction Z as the distance from the front surface of the semiconductor substrate 10 increases. As a result, the adverse effects of the oblique ion implantations 96 and 97 do not reach the gate threshold voltage, so that the variation in the gate threshold voltage can be suppressed. As a result, static characteristics (leakage current, withstand voltage) and dynamic characteristics (switching loss, reverse bias safety operating region (RBSOA), short-circuit tolerance) that depend on the gate threshold voltage can be stably obtained. ..

The p ⁺⁺ type contact region 36a is located between the inner wall (bottom surface and side wall) of the contact trench 50a and the p-type base region 34a at a position deeper than the ^{n +} type source region 35a from the front surface of the semiconductor substrate 10. It is provided. The p ⁺⁺ type contact region 36a is provided at a position away from the gate trench 37a in contact with the p type base region 34a and the n ⁺ type source region 35a. The p ⁺⁺ type contact region 36a extends along the inner wall (bottom surface and side wall) of the contact trench 50a.

The p ^{++ type contact region 36a surrounds the inner wall of the contact trench 50a at a position deeper than the n +} type source region 35a from the front surface of the semiconductor substrate 10, and is in contact with the Ti film 41a on the inner wall of the contact trench 50a. The p ⁺⁺ type contact region 36a has, for example, a peak (maximum value) of the n-type impurity concentration at a depth position close to the ^{n + type source region 35a, and n in the depth direction Z from the depth position of the peak. It} has a p-type impurity concentration distribution in which the p-type impurity concentration decreases as the distance from the + -type source region 35a increases.

The p ⁺⁺ type contact region 36a has a size larger than that of the contact trench 50a and has substantially the same planar shape as the contact trench 50a. For example, when the contact trenches 50a are scattered in the first direction X, the p ⁺⁺ type contact region 36a surrounds each contact trench 50a. When the contact trench 50a extends linearly in the first direction X, the p ⁺⁺ type contact region 36a has a width wider than that of the contact trench 50a and extends linearly in the first direction X along the contact trench 50a. Exists.

The ^{portion (contact portion (third portion)) 52a of the p ++} type contact region 36a exposed on the side wall of the contact trench 50a is a portion where ohmic contact with the Ti film 41a is formed, and is a p ⁺⁺ type contact. The p-type impurity concentration may be higher than that of the other portion of the region 36a (the portion excluding the contact portion 52a, the fourth portion). As a result, the contact resistance between the source electrode and the p ⁺⁺ type contact region 36a is reduced, and the hole current (blocking current) drawn to the source pad 21a through the p-type base region 34a at turn-off can be increased. The exposure to the side wall and the bottom surface of the contact trench 50a means that the contact portion 52a is in contact with the Ti film 41a described later on the side wall and the bottom surface of the contact trench 50a.

As ^{will be described later, the contact portion 52a of the p ++} type contact region 36a is implanted in the surface region of the side wall of the contact trench 50a by oblique ion implantation of p-type impurities 98,99 (see FIGS. 11 and 12), which will be described later. It is a diffusion region formed along the side wall of the. The contact portion 52a of the p ⁺⁺ type contact region 36a may extend along the inner wall of the contact trench 50a to the surface region of the bottom surface of the contact trench 50a and may be exposed to the bottom surface of the contact trench 50a. The concentration of p-type impurities in the contact portion 52a of the ^{p ++ type contact region 36a is uniform in the depth direction Z.} As a result, stable ohmic contact between the source electrode and the p ⁺⁺ type contact region 36a can be obtained.

Further, ^{the contact portion 52a of the p ++} type contact region 36a has a peak (maximum value) of the p-type impurity concentration at a position close to the inner wall (bottom surface and side wall) of the contact trench 50a, and the position of the peak. The p-type impurity concentration decreases as the distance from the inner wall of the contact trench 50a increases in the direction orthogonal to the inner wall of the contact trench 50a (depth direction Z and second direction Y). As a result, the contact resistance between the source electrode and the p ⁺⁺ type contact region 36a can be reduced, so that the on-resistance can be reduced. Further, since the current path of the displacement current flowing from the p-type base region 34a to the source electrode at the time of turn-off can be shortened, the malfunction of the parasitic BJT can be suppressed at an excessive time.

Further, ^{since p-type impurities due to oblique ion implantation 98 and 99 are not introduced into the portion of the p ++} type contact region 36a away from the side wall of the contact trench 50a (the portion excluding the contact portion 52a), the p ⁺⁺ type The p-type impurity concentration distribution at the time of forming the contact region 36a is maintained. Therefore, the ^{concentration of p-type impurities in the portion of the p ++} type contact region 36a excluding the contact portion 52a decreases in the depth direction Z as the distance from the front surface of the semiconductor substrate 10 increases. As a result, the adverse effect of the oblique ion implantations 98 and 99 does not reach the gate threshold voltage, so that the variation in the gate threshold voltage can be suppressed. Static characteristics and dynamic characteristics that depend on the gate threshold voltage can be stably obtained.

Inside the semiconductor substrate 10, between the p-type base region 34a and the n ⁺ type drain region 31 (n ⁺ type starting substrate 71), the p-type base region 34a and the n ⁺ type drain region 31 are in contact with each other, and n ⁻ A mold drift region 32 is provided. An n-type current diffusion region 33a may be provided between the p-type base region 34a and the n ^{-type drift region 32 in contact with these regions.} The n-type current diffusion region 33a is a so-called current diffusion layer (Curent Spreading Layer: CSL) that reduces the spread resistance of carriers.

Further, inside the semiconductor substrate 10, first and second p ⁺ type regions 61a and 62a for relaxing the electric field applied to the bottom surface of the gate trench 37a ^{are provided at positions closer to the n + type drain region 31 than the p type base region 34a.} It may have been. The 1p ⁺ -type region 61a is provided apart from the p-type base region 34a, it faces the bottom surface of the gate trench 37a in the depth direction Z. The second p ⁺ type region 62a is provided between the adjacent ^{gate trenches 37a, apart from the first p +} type region 61a and the gate trench 37a, and is in contact with the p type base region 34a.

It is arranged between the gate trenches 37a adjacent to each other, and one unit cell of the main semiconductor element 11 is formed in each portion. By narrowing the pitch (distance between the centers of the gate trenches 37a adjacent to each other: cell pitch) w1 of the unit cell of the main semiconductor element 11, the unit cell can be miniaturized, and the main semiconductor element 11 can be miniaturized. With miniaturization of the unit cell of the main semiconductor element 11, if it is not possible to place a second 2p ⁺ -type region 62a by the narrow cell pitch w1 ', the first 2p ⁺ -type region 62a may not be provided ( FIG. 4). The cell pitches w1 and w1'can be miniaturized to, for example, about 2 μm or less.

The interlayer insulating film 40 is provided on substantially the entire surface of the front surface of the semiconductor substrate 10 and covers the gate electrode 39a. At least the contact trench 50a is exposed in the first contact hole 40a penetrating the interlayer insulating film 40 in the depth direction Z in the main effective region 1a (FIG. 4), and ^{the contact portion of the n +} type source region 35a is exposed on the inner wall of the contact trench 50a. The contact portion 52a of the 51a and the p ⁺⁺ type contact region 36a is exposed. When the cell pitch w1 of the main semiconductor element 11 is relatively wide, the semiconductor is further formed from the portion exposed on the front surface of the semiconductor substrate 10 of the ^{n + type source region 35a and the inner wall of the contact trench 50a in the first contact hole 40a.} The Ti film 41a extending on the front surface of the substrate 10 may be in contact with the Ti film 41a (FIGS. 2 and 3).

The titanium (Ti) film 41a is provided on the entire surface of the interlayer insulating film 40 and the inner wall of the contact trench 50a in the main effective region 1a along the surface of the interlayer insulating film 40 and the inner wall of the contact trench 50a. When the cell pitch w1 of the main semiconductor element 11 is relatively wide, the Ti film 41a extends from the inner wall of the contact trench 50a to the front surface of the semiconductor substrate 10 inside the first contact hole 40a, and the semiconductor substrate It may extend from the front surface of 10 to the surface of the interlayer insulating film 40.

The Ti film 41a is silicidal (TiSi) at a portion of the inner wall of the contact trench 50a that contacts the semiconductor substrate 10, and is in ohmic contact with the semiconductor substrate 10. Specifically, the Ti film 41a is in ohmic contact with the contact portion 51a of ^{the n +} type source region 35a and the contact portion 52a of the ^{p ++} type contact region 36a exposed on the side wall of the contact trench 50a, ^{and the n +} type source. It is electrically connected to the region 35a and the p ^{++ type contact region 36a.}

When the front surface of the semiconductor substrate 10 is exposed to the first contact hole 40a, the Ti film 41a contacts the n ⁺ type source region 35a on the front surface of the semiconductor substrate 10 inside the first contact hole 40a. You may. The titanium nitride (TiN) film 42a is provided on the surface of the Ti film 41a. The Ti film 41a and the TiN film 42a are barrier metals 43a that prevent mutual reactions between the respective parts facing each other across the metal film. Further, the Ti film 41a and the TiN film 42a have a function of improving the adhesion of the W film 44a, which will be described later.

Between the inner wall and the Ti film 41a of the contact trench 50a, a nickel silicide (NiSi, Ni ₂ Si or thermally stable NiSi _2: hereinafter, collectively and NiSi with, not shown) may be film is provided .. In this case, instead of ohmic contact between the Ti film 41a and the semiconductor substrate 10, the NiSi film between the inner wall of the contact trench 50a and the Ti film 41a makes ohmic contact with the semiconductor substrate 10 on the inner wall of the contact trench 50a, and is n ⁺ type. It is electrically connected to the source region 35a and the p ^{++ type contact region 36a.}

A tungsten (W) film 44a is provided on the surface of the TiN film 42a at least inside the contact trench 50a. The W film 44a is completely embedded inside the TiN film 42a inside the contact trench 50a. The W film 44a may be provided on the entire surface of the TiN film 42a. The source pad 21a is provided on the entire surface of the TiN film 42a and the W film 44a (when the W film 44a is provided on the entire surface of the TiN film 42a, the entire surface of the W film 44a).

^{The source pad 21a is electrically connected to the n +} type source region 35a and the p ⁺⁺ type contact region 36a via the barrier metal 43a and the W film 44a. The source pad 21a may be, for example, an aluminum (Al) film, an aluminum-silicon (Al-Si) film, or an aluminum-silicon-copper (Al-Si-Cu) film having a thickness of about 5 μm. The source pad 21a, the W film 44a, and the barrier metal 43a function as source electrodes of the main semiconductor element 11.

One end of the terminal pin 46a is joined onto the source pad 21a via a plating film 45a and a solder layer (not shown). The other end of the terminal pin 46a is joined to a metal bar (not shown) arranged so as to face the front surface of the semiconductor substrate 10. Further, the other end of the terminal pin 46a is exposed to the outside of a case (not shown) on which the semiconductor substrate 10 is mounted, and is electrically connected to an external device (not shown). The terminal pin 46a is solder-bonded to the plating film 45a in a state of standing substantially perpendicular to the front surface of the semiconductor substrate 10.

The terminal pin 46a is a round bar-shaped (cylindrical) wiring member having a predetermined diameter, and is connected to an external ground potential (minimum potential). The terminal pin 46a is an external connection terminal that takes out the potential of the source pad 21a to the outside. The first and second protective films 47a and 48a are, for example, polyimide films. The first protective film 47a covers a portion of the surface of the source pad 21a other than the plating film 45a. The second protective film 48a covers the boundary between the plating film 45a and the first protective film 47a.

The drain electrode (second electrode) 49 is in ohmic contact with the entire back surface of the semiconductor substrate 10 (the back surface of the n ^{+ type starting substrate 71).} On the drain electrode 49, for example, a drain pad (electrode pad: not shown) is provided in a laminated structure in which a Ti film, a nickel (Ni) film, and a gold (Au) film are laminated in this order. The drain pad is solder-bonded to a metal base plate (not shown) formed of, for example, copper foil of an insulating substrate, and at least a part of the drain pad comes into contact with the base portion of the cooling fins (not shown) via the metal base plate. ing.

By joining the terminal pin 46a to the source pad 21a on the front surface of the semiconductor substrate 10 and the drain pad on the back surface to the metal base plate of the insulating substrate in this way, the semiconductor substrate 10 can be attached to both main surfaces. It has a double-sided cooling structure with a cooling structure. The heat generated in the semiconductor substrate 10 is dissipated from the fin portion of the cooling fin via the metal base plate bonded to the drain pad on the back surface of the semiconductor substrate 10, and the terminal pin 46a on the front surface of the semiconductor substrate 10 is dissipated. Heat is dissipated from the joined metal bar.

In the sense effective region 12a of the main invalid region 1b, the current sense unit 12 has a p-type base region 34b, an n ⁺ -type source region 35b, and a p ^++- type contact region 36b having the same configuration as the corresponding portions of the main semiconductor element 11. A gate trench 37b, a gate insulating film 38b, a gate electrode 39b, and an interlayer insulating film 40 are provided. Similar to the main semiconductor element 11, the current sense unit 12 may have a structure in which the source electrodes are electrically connected to the ^{n +} type source region 35b and the p ^{++ type contact region 36b on the inner wall of the contact trench 50b.}

The p-type base region 34b is separated from the p-type base region 34a of the main semiconductor element 11 by ^{the n-} type region 32a of the surface region of the front surface of the semiconductor substrate 10. The p-type base region 34b extends from, for example, the sense effective region 12a to almost the entire area of the main invalid region 1b. The current sense unit 12 may have an n-type current diffusion region 33b and first and second p ⁺ type regions 61b and 62b, similarly to the main semiconductor element 11. With the miniaturization of the unit cell of the current sense unit 12, the second p ⁺ type region 62b may not be provided.

The gate electrode 39b is electrically connected to the gate pad 21b (see FIG. 1). The gate electrode 39b is covered with an interlayer insulating film 40. A second contact hole 40b penetrating the interlayer insulating film 40 is provided in the sense effective region 12a in the depth direction Z. Similar to the inside of the first contact hole 40a of the main effective region 1a, at least the contact trench 50b is exposed in the second contact hole 40b, and the n ⁺ type source region 35b and the p ⁺⁺ type contact region 36b are exposed on the inner wall of the contact trench 50b. Is exposed.

Similar to the main semiconductor element 11, the n-type impurity concentration in the n ⁺ -type source region 35b is relatively high in the portion (contact portion) 51b exposed on the side wall of the contact trench 50b. Similar to the main semiconductor element 11, the p-type impurity concentration in the p ⁺⁺ type contact region 36b may be relatively high in the portion (contact portion) 52b exposed on the side wall of the contact trench 50b. The n ⁺ type source region 35b and the p ⁺⁺ type contact region 36b and these contact portions 51b and 52b are formed at the same time as the corresponding portions of the main semiconductor element 11.

Similar to the main semiconductor element 11, the barrier metal 43b and the W film 44b are provided in the sense effective region 12a. Reference numerals 41b and 42b are Ti films and TiN films constituting the barrier metal 43b, respectively. Similar to the Ti film 41a of the main semiconductor element 11, the Ti film 41b is in ohmic contact with the contact portions 51b and 52b ^{of the n +} type source region 35b and the p ^{++ type contact region 36b on the inner wall of the contact trench 50a.} It is electrically connected to the ^{n +} type source region 35b and the p ^{++ type contact region 36b.}

The OC pad 22 is provided on the entire surface of the barrier metal 43b and the W film 44b apart from the source pad 21a. ^{The OC pad 22 is electrically connected to the n +} type source region 35b and the p ⁺⁺ type contact region 36b via the W film 44b and the barrier metal 43b. The OC pad 22 is made of the same material as the source pad 21a, and is formed at the same time as the source pad 21a. The OC pad 22, the W film 44b, and the barrier metal 43b function as source electrodes of the current sense unit 12.

The terminal pin 46b is joined to the OC pad 22 with the same wiring structure as that on the source pad 21a. The terminal pin 46b is a round bar-shaped (cylindrical) wiring member having a diameter smaller than that of the terminal pin 46a, and connects the OC pad 22 to the ground potential via an external resistor (not shown). The terminal pin 46b is an external connection terminal that takes out the potential of the OC pad 22 to the outside. Reference numerals 45b, 47b, and 48b are plating films and first and second protective films that form a wiring structure on the OC pad 22, respectively, and are arranged in the same manner as the wiring structure on the source pad 21a.

P-type base region 34b of the p-type base region 34a and the sense effective area 12a of the main effective area 1a is shown omitted n of the surface region of the semiconductor substrate 10 ^- by type region, p-type region (not shown for element isolation ) Is separated. The p-type region for element isolation is provided in a substantially rectangular shape surrounding the periphery of the active region 1 in the edge termination region 2, the parasitic diode to electrically isolate the active region 1 and the edge termination region 2 n ^- It is a floating p-type region formed by a pn junction with the type drift region 32.

The temperature sense unit 13 is, for example, a polysilicon diode formed by a pn junction between a p-type polysilicon layer 81, which is a p-type anode region, and an n-type polysilicon layer 82, which is an n-type cathode region (FIG. 3). .. The p-type polysilicon layer 81 and the n-type polysilicon layer 82 are provided on the interlayer insulating film 40 in the main invalid region 1b. The temperature sense unit 13 is electrically insulated from the semiconductor substrate 10, the main semiconductor element 11, and the current sense unit 12 by the interlayer insulating film 40.

The anode pad 23a and the cathode pad 23b are in contact with the p-type polysilicon layer 81 and the n-type polysilicon layer 82 at the third and fourth contact holes 83a and 83b of the interlayer insulating film 83 covering them, respectively. The anode pad 23a and the cathode pad 23b are made of the same material as the source pad 21a, and are formed at the same time as the source pad 21a, for example. Terminal pins 46c and 46d are joined to the anode pad 23a and the cathode pad 23b, respectively, with the same wiring structure as that on the source pad 21a.

The terminal pins 46c and 46d are external connection terminals that take out the potentials of the anode pad 23a and the cathode pad 23b to the outside, respectively. The terminal pins 46c and 46d are round bar-shaped wiring members having a predetermined diameter according to the current capacity of the temperature sense unit 13. Reference numerals 45c and 45d are plating films constituting the wiring structure on the anode pad 23a and the wiring structure on the cathode pad 23b, respectively. Reference numerals 47c and 48c are first and second protective films constituting the wiring structure on the temperature sense unit 13, respectively.

Further, in the main invalid region 1b, a gate pad portion 14 in which the gate pad 21b of the main semiconductor element 11 is arranged is provided (see FIG. 1). The gate pad 21b is provided on the interlayer insulating film 40 in the main invalid region 1b, apart from the other electrode pads. The gate pad 21b is made of the same material as the source pad 21a, and is formed at the same time as the source pad 21a. Terminal pins (not shown) are joined on the gate pad 21b with the same wiring structure as that on the source pad 21a.

The operation of the semiconductor device 20 according to the embodiment will be described. In a state where a positive voltage (forward voltage) is applied to the drain electrode 49 with respect to the source electrode (source pad 21a) of the main semiconductor element 11, a voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 39a of the main semiconductor element 11. When applied, a channel (n-type inverted layer) is formed in a portion of the p-type base region 34a of the main semiconductor element 11 exposed to the gate trench 37a. As a result, ^{a current flows from the n +} type drain region 31 of ^{the main semiconductor element 11 toward the n +} type source region 35a, and the main semiconductor element 11 is turned on.

Under the same conditions as the main semiconductor element 11, the gate electrode of the current sense unit 12 is in a state where a positive voltage (forward voltage) is applied to the drain electrode 49 with respect to the source electrode (OC pad 22) of the current sense unit 12. When a voltage equal to or higher than the gate threshold voltage is applied to 39b, a channel (n-type inversion layer) is formed in a portion exposed to the gate trench 37b of the p-type base region 34b of the current sense unit 12. ^{As a result, a current (hereinafter referred to as a sense current) flows from the n +} type drain region 31 of the current sense unit 12 ^{toward the n +} type source region 35b, and the current sense unit 12 is turned on.

When the main semiconductor element 11 is turned on, the current sense unit 12 is turned on. When the sense current flows through the current sense unit 12, a voltage drop occurs in a resistor (not shown) connected between ^{the n + type source region 35b of the current sense unit 12 and the ground point.} Since the sense current of the current sense unit 12 increases according to the magnitude of the current flowing through the main semiconductor element 11, the voltage drop in the resistor also increases. Therefore, by monitoring the magnitude of the voltage drop in this resistor, the overcurrent in the main semiconductor element 11 can be detected.

On the other hand, when a voltage lower than the gate threshold voltage is applied to the gate electrode 39a, the main semiconductor element 11 has a p-type base region 34a and a first and second p ⁺ type regions 61a and 62a (or a second p ⁺ type region 62a). If is not provided, the pn junction between the p-type base region 34a and the first p ⁺ type region 61a) and the n-type current diffusion region 33a and the n ^- type drift region 32 is reverse-biased to turn off. Maintain the state.

Then, a voltage lower than the gate threshold voltage is also applied to the gate electrode 39b of the current sense unit 12, and the current sense unit 12 has the p-type base region 34b and the first and second p ⁺ type regions 61b and 62b (or the second p ^+). When the mold region 62b is not provided, the pn junction between the p-type base region 34b and the first p ⁺ type region 61b) and the n-type current diffusion region 33b and the n ^- type drift region 32 is reverse-biased. And keep it off.

Next, the manufacturing method of the semiconductor device 20 according to the embodiment will be described using the structures shown in FIGS. 1 to 3 as an example. 5 to 14 are cross-sectional views showing a state in the middle of manufacturing the semiconductor device according to the embodiment. Although only the main semiconductor element 11 is shown in FIGS. 5 to 14, each part of all the semiconductor elements (see FIGS. 1 to 3) manufactured on the same semiconductor substrate 10 has the same impurity concentration as each part of the main semiconductor element 11. And formed at the same time as each part of the depth.

First, as shown in FIG. 5, as an n ⁺ type starting substrate (semiconductor wafer) 71 made of silicon carbide, for example, a nitrogen (N) -doped silicon carbide single crystal substrate is prepared. Then, the front surface of the n ⁺ -type starting substrate 71, n nitrogen is lightly doped than n ⁺ -type starting substrate 71 ^- -type silicon carbide layer 72 is epitaxially grown (the first step). When the main semiconductor element 11 has a withstand voltage of 3300 V class, ^{the thickness t1 of the n-} type silicon carbide layer 72 may be, for example, about 30 μm.

Next, as shown in FIG. 6, by photolithography and ion implantation of a p-type impurity such as Al ^{, the first p +} type region 61a and p in ^{the surface region of the n-} type silicon carbide layer 72 in the main effective region 1a. ^{Each +} type region 91 is selectively formed. The first p ⁺ type region 61a and the p ⁺ type region 91 are alternately and repeatedly arranged in the second direction Y (horizontal direction: see FIGS. 2 and 3) in which the gate trench 37a described later is lined up, for example.

Next, by ion implantation of n-type impurities such as photolithography and example nitrogen, n over the entire main effective area 1a ^- forming the n-type region 92 in the surface region of the -type silicon carbide layer 72. The n-type region 92 is formed between the first p ⁺ type region 61a and the p ⁺ type region 91 in contact with the p ⁺ type regions 61a and 91. The formation order of the n-type region 92 and the p ⁺ -type regions 61a and 91 may be interchanged.

^{The distance d2 between the p +} type regions 61a and 91 adjacent to each other is, for example, about 1.5 μm. The p ⁺ type regions 61a and 91 have, for example, a depth d1 and an impurity concentration of about 0.5 μm and 5.0 × 10 ¹⁸ / cm ³ , respectively. The depth d3 and the impurity concentration of the n-type region 92 are, for example, about 0.4 μm and about 1.0 × 10 ¹⁷ / cm ³ , respectively. The portion of the n ^- type silicon carbide layer 72 that has not been ion-implanted becomes the n ^- type drift region 32.

Next, as shown in FIG. 7, n ^- -type n doped with n-type impurities further on the silicon carbide layer 72 such as nitrogen or the like ^- in the form of a silicon carbide layer for example about 0.5μm thickness t2 is epitaxially grown , The thickness of the n ^- type silicon carbide layer 72 is increased. As a result, ^{the thickness of the n-} type silicon carbide layer 72 becomes a predetermined thickness. The impurity concentration of the thickened portion 72a of the n ^- type silicon carbide layer 72 may be, for example, 3 × 10 ¹⁵ / cm ³ .

Next, by ion implantation of p-type impurities such as photolithography and Al, n ^- the part 72a with an increased thickness of -type silicon carbide layer 72, selectively the p ⁺ -type region 93 to reach the p ⁺ -type region 91 Form. Next, by ion implantation of n-type impurities such as photolithography and example nitrogen, n ^- the part 72a with an increased thickness of -type silicon carbide layer 72, selectively forming an n-type region 94 reaching the n-type region 92 do.

As a result, the p ⁺ type regions 91 and 93 adjacent to each other in the depth direction Z are connected to each other to form the second p ⁺ type region 62a. The n-type regions 92 and 94 adjacent to each other in the depth direction Z are connected to each other to form the n-type current diffusion region 33a. Conditions such as the impurity concentration of the p ⁺ type region 93 and the n-type region 94 are the same as those of the p ⁺ type region 91 and the n-type region 92, respectively. The formation order of the p ⁺ type region 93 and the n-type region 94 may be exchanged.

Next, as shown in FIG. 8, a p-type silicon carbide layer 73 doped with a p-type impurity such as Al is epitaxially grown on ^{the n-type silicon carbide layer 72 (second step).} The thickness t3 and the impurity concentration of the p-type silicon carbide layer 73 are, for example, about 1.3 μm and about 4.0 × 10 ¹⁷ / cm ³ , respectively. Through the steps up to this point, ^{a semiconductor substrate 10 (semiconductor wafer) in which an n-} type silicon carbide layer 72 and a p-type silicon carbide layer 73 are sequentially laminated on an ^{n +} type starting substrate 71 is produced.

Next, by photolithography and ion implantation of an n-type impurity (ion species) such as phosphorus (P), an n ⁺ -type source region 35a is applied to, for example, the entire surface region of the p-type silicon carbide layer 73 in the main effective region 1a. (Third step). ^{Next, a p ++} type contact region 36a is selectively formed in the surface region of the p-type silicon carbide layer 73 in the main effective region 1a by photolithography and ion implantation of a p-type impurity (ion species) such as aluminum. (10th step).

The ion implantation angle for forming the n ⁺ type source region 35a and the p ⁺⁺ type contact region 36a is, for example, perpendicular to the front surface of the semiconductor substrate 10. The formation order of the n ⁺ type source region 35a and the p ⁺⁺ type contact region 36a may be exchanged. ^{Further, the n +} type source region 35a may be formed by epitaxial growth instead of ion implantation. The p ⁺⁺ type contact region 36a is formed at a position deeper than the ^{n +} type source region 35a by ion implantation at a position deeper than the ^{n +} type source region 35a from the front surface of the semiconductor substrate 10, for example. .. The source side end of the p ⁺⁺ type contact region 36a does not have to be in ^{contact with the n + type source region 35a.}

The p ⁺⁺ type contact region 36a is formed by, for example, forming the contact trench 50a described later and then implanting oblique ions into the inner wall of the contact trench 50a with a higher acceleration energy than the oblique ion implantation 98 and 99 described later. May be good. In this case, the tenth step may or may not be carried out. ^{Further, the p ++} type contact region 36a may be formed only by the tenth step without performing the oblique ion implantation 98 and 99 described later. The portion of the p-type silicon carbide layer 73 of the main effective region 1a between the n ⁺ type source region 35a and the p ⁺⁺ type contact region 36a and the n ^- type silicon carbide layer 72 is the p-type base region 34a. ..

Next, as shown in FIG. 9, a mask 95 having an opening portion corresponding to the formation region of the contact trench 50a is formed of a resist film, an oxide film, or the like by photolithography and etching. Next, a contact trench 50a to perform by dry etching, for example using a mask 95, through the n ⁺ -type source region 35a reaches the p ⁺⁺ -type contact region 36a, terminating in a p ⁺⁺ type contact region 36a (6th step).

Due to the adverse effect of the gas used for dry etching for forming the contact trench 50a, the resistance value of the surface region of the inner wall of the contact trench 50a increases. By increasing the concentration of impurities in the surface region of the inner wall (side wall and bottom surface), the contact resistance between the source electrode and the semiconductor substrate 10 on the inner wall of the contact trench 50a can be reduced.

Next, using the same mask 95 used for forming the contact trench 50a, the semiconductor substrate 10 is obliquely oblique with a predetermined implantation angle (tilt angle) θ1 with respect to the direction perpendicular to the front surface (depth direction Z). N-type impurities are ion-implanted (oblique ion-implanted) 96 into one side wall of the contact trench 50a from the above direction. Here, the ion species to be implanted diagonally may be the same as the ion species used in the ion implantation for forming the ^{n + type source region 35a, for example.}

The oblique ion implantation 96 from one side wall of the n ⁺ -type source region 35a of the contact trench 50a, the portion (contact portion 51a) exposed on one side wall of the contact trench 50a of the n ⁺ -type source region 35a, n ⁺ -type The concentration of n-type impurities in the source region 35a can be made uniform in the depth direction Z and higher than the portion separated from one side wall of the contact trench 50a (the portion excluding the contact portion 51a).

Next, as shown in FIG. 10, using the same mask 95 used for forming the contact trench 50a, from an oblique direction at a predetermined implantation angle θ2 with respect to the direction perpendicular to the front surface of the semiconductor substrate 10. , N-type impurities are ion-implanted (diagonal ion implantation) 97 into the other side wall of the contact trench 50a. Here, the ion type to be implanted diagonally may be the same as the ion type used in the ion implantation for forming the ^{n + type source region 35a, for example.}

The implantation angle θ2 of the oblique ion implantation 97 from the other side wall of the contact trench 50a into the n ⁺ -type source region 35a is the contact trench about the central axis of the contact trench 50a perpendicular to the front surface of the semiconductor substrate 10. The angle is line-symmetric with the implantation angle θ1 of the oblique ion implantation 96 from one side wall of 50a into the n ^{+ type source region 35a.} The conditions other than the implantation angles θ1 and θ2 of the oblique ion implantations 96 and 97 are the same.

The oblique ion implantation 97 from the other side wall of the contact trench 50a into the n ⁺ -type source region 35a, in the portion (contact portion 51a) exposed on the other side wall of the contact trench 50a of the n ⁺ -type source region 35a, n ⁺ -type The n-type impurity concentration in the source region 35a can be made uniform in the depth direction Z and higher than the portion of the contact trench 50a away from the other side wall (the portion excluding the contact portion 51a) (7th step). ).

Next, as shown in FIG. 11, using the same mask 95 used for forming the contact trench 50a, from an oblique direction at a predetermined implantation angle θ3 with respect to the direction perpendicular to the front surface of the semiconductor substrate 10. , P-type impurities are ion-implanted (oblique ion-implanted) 98 into one side wall of the contact trench 50a. Here, the ion type to be implanted diagonally may be the same as the ion type used in the ion implantation for forming the ^{p ++ type contact region 36a, for example.}

The oblique ion implantation 98 from one side wall of the p ⁺⁺ -type contact region 36a of the contact trench 50a, the portion exposed from the one side wall of the contact trench 50a of p ⁺⁺ type contact regions 36a to part of the bottom surface (the contact portion In 52a), ^{the p-type impurity concentration in the p ++} type contact region 36a is uniform in the depth direction Z and higher than the portion separated from one side wall of the contact trench 50a (the portion excluding the contact portion 52a). can do.

Next, as shown in FIG. 12, using the same mask 95 used for forming the contact trench 50a, from an oblique direction at a predetermined implantation angle θ4 with respect to the direction perpendicular to the front surface of the semiconductor substrate 10. , P-type impurities are ion-implanted (oblique ion-implanted) 99 into the other side wall of the contact trench 50a. Here, the ion type to be obliquely ion-implanted 99 may be the same as the ion type used in the ion implantation for forming the ^{p ++ type contact region 36a, for example.}

The implantation angle θ4 of the oblique ion implantation 99 from the other side wall of the contact trench 50a into the p ⁺⁺ type contact region 36a is the contact with the central axis of the contact trench 50a perpendicular to the front surface of the semiconductor substrate 10 as an axis. The angle is line-symmetric with the implantation angle θ3 of the oblique ion implantation 98 from one side wall of the trench 50a into the p ^{++ type contact region 36a.} The conditions other than the implantation angles θ3 and θ4 of the oblique ion implantations 98 and 99 are the same.

The oblique ion implantation 99 from the other side wall of the contact trench 50a into p ⁺⁺ -type contact region 36a, the portion exposed from the other side wall of the contact trench 50a of p ⁺⁺ type contact regions 36a to part of the bottom surface (the contact portion In 52a), ^{the p-type impurity concentration in the p ++} type contact region 36a is higher in the depth direction Z than the portion of the contact trench 50a away from the other side wall (the portion excluding the contact portion 52a). Can be done (11th step).

In the eleventh step, ^{the ion implantation for forming the p ++} type contact region 36a may be performed from the direction perpendicular to the contact trench 50a. In this case, p ⁺⁺ type contact region 36a on the side walls of the bottom and surrounding the contact trench 50a is formed, on the upper side of the side wall of the trench 50a is not formed p ⁺⁺ -type contact region 36a. Therefore, it is possible to prevent the impurity concentration of the contact portion 51a of the ^{n +} type source region 35a exposed on the side wall of the contact trench 50a from decreasing.

Next, after removing the mask 95, all the diffusion regions (first and second p ⁺ type regions 61a and 62a, n type current diffusion region 33a, n ⁺ type source region 35a and p ⁺⁺ type contact region) formed by ion implantation. 36a) is activated by heat treatment (activation annealing) for about 2 minutes at a temperature of, for example, about 1700 ° C. The activation annealing may be performed once after the formation of all the diffusion regions, or may be performed after each diffusion region is formed by ion implantation.

Next, as shown in FIG. 13, the n-type current diffusion region 33a is reached from the front surface of the semiconductor substrate 10 through the n ⁺ type source region 35a and the p-type base region 34a by photolithography and etching. ^{A gate trench 37a facing the first p +} type region 61a is formed in the depth direction Z (longitudinal direction: see FIGS. 2 and 3) (fourth step). The gate trench 37a may reach, for example, the first p ⁺ type region 61a and ^{terminate inside the first p +} type region 61a.

Next, as shown in FIG. 14, a gate insulating film 38a is formed along the front surface of the semiconductor substrate 10 and the inner wall of the gate trench 37a. The gate insulating film 38a may be, for example, a thermal oxide film formed by thermally oxidizing the semiconductor surface at a temperature of about 1000 ° C. in _{an oxygen (O 2) atmosphere, or may be a high temperature oxidation (HTO: High Temperature Oxide).} ) May be a deposited film.

Next, for example, a phosphorus-doped polysilicon layer is deposited on the front surface of the semiconductor substrate 10 so as to be embedded inside the gate trench 37a. Next, the polysilicon layer is selectively removed by photolithography and etching, and only the portion of the polysilicon layer that becomes the gate electrode 39a is left inside the gate trench 37a (fifth step). By the steps up to this point, the MOS gate of the unit cell of the main semiconductor element 11 is formed (cell forming step).

The gate trench 37a, the gate insulating film 38a, and the gate electrode 39 may be formed before the contact trench 50a is formed. Further, as described above, when forming each part of the MOS gate of the main semiconductor element 11, all the semiconductor elements (current sense unit 12, overvoltage protection unit (not shown) and arithmetic circuit) manufactured on the same semiconductor substrate 10 are formed. Each part of the high-performance part (not shown) (see FIGS. 2 and 3) may be formed at the same time as each part having the same impurity concentration and depth as each part of the main semiconductor element 11.

By arranging the main semiconductor element 11 in the island-shaped p-type base region 34a formed in the surface region of the front surface of the semiconductor substrate 10, the p-type base region 34a and the n ^- type drift region 32 can be arranged. By pn junction separation, it is separated from other semiconductor elements manufactured on the same semiconductor substrate 10. The current sense unit 12 has the same structure as the main semiconductor element 11, and may be arranged in the island-shaped p-type base region 34b formed in the surface region of the front surface of the semiconductor substrate 10.

Next, an interlayer insulating film 40 such as BPSG (Boro Phospho Silicate Glass) or PSG (Phospho Silicate Glass) is applied to the entire front surface of the semiconductor substrate 10 so as to cover the gate electrode 39a to a thickness of, for example, 1 μm. Formed with. The temperature sense unit 13 may form a p-type polysilicon layer 81 and an n-type polysilicon layer 82 (see FIG. 3) on the interlayer insulating film 40 and cover the interlayer insulating film 83.

Next, the first and second contact holes 40a and 40b penetrating the interlayer insulating film 40 and the gate insulating film 38a are formed in the depth direction Z by photolithography and etching. The third and fourth contact holes 83a and 83b penetrating the interlayer insulating film 83 are formed in the depth direction Z. The contact trench 50a, the n ⁺ type source region 35a, and the p ⁺⁺ type contact region 36a of the main semiconductor element 11 are exposed in the first contact hole 40a.

The contact trench 50b, the n ⁺ type source region 35b, and the p ⁺⁺ type contact region 36b of the current sense portion 12 are exposed in the second contact hole 40b. The p-type polysilicon layer 81 and the n-type polysilicon layer 82 of the temperature sensing unit 13 are exposed in the third and fourth contact holes 83a and 83b, respectively. Next, the interlayer insulating films 40 and 83 are flattened (reflowed) by heat treatment.

Next, the Ti film 41a and the TiN film 42a are sequentially deposited (including the inner wall of the contact trench 50a) on the entire surface of the interlayer insulating film 40 and the semiconductor surface (including the inner wall of the contact trench 50a) in the first contact hole 40a by, for example, a reactive sputtering method. Form. Next, the W film 44a is embedded inside the TiN film 42a inside the contact trench 50a by, for example, a chemical vapor deposition (CVD) method.

The Ti film 41a is silicinated (TiSi) by heat treatment at a portion in contact with the semiconductor substrate 10 and is in ohmic contact with the semiconductor substrate 10. Here, a NiSi film may be formed between the Ti film 41a and the semiconductor surface including the inner wall of the contact trench 50a. In this case, after forming a nickel (Ni) film on the semiconductor surface in the first contact hole 40a and silicating it, the unreacted portion of the Ni film (the portion on the interlayer insulating film 40) can be removed by etching. good.

The thicknesses of the Ti film 41a, the TiN film 42a, and the W film 44a are, for example, about 50 nm, about 100 nm, and about 1 μm, respectively. Further, in the second contact hole 40b, at the same time as the Ti film 41a, the TiN film 42a and the W film 44a, the Ti film 41b, the TiN film 42b and the W film 44b are formed in the same configuration as these metal films, respectively. Next, the source pad 21a is formed on the surfaces of the TiN film 42a and the W film 44a (8th step).

The OC pad 22, the anode pad 23a, and the cathode pad 23b are formed in the second to fourth contact holes 40b, 83a, and 83b at the same time as the source pad 21a in the same configuration as the source pad 21a, respectively. Further, a drain electrode 49 that makes ohmic contact is formed on the back surface of the semiconductor substrate 10, and for example, a Ti film, a Ni film, and a gold (Au) film are sequentially laminated on the surface of the drain electrode 49 to form a drain pad (not shown). (9th step).

Next, first protective films 47a to 47c made of polyimide are selectively formed on the front surface of the semiconductor substrate 10, and different electrode pads 21a, 21b, respectively, are formed in the openings of the first protective films 47a to 47c. 22, 23a, 23b are exposed. Next, after the general pre-plating treatment, the plating film 45a is applied to the portions of the electrode pads 21a, 21b, 22, 23a, 23b exposed to the openings of the first protective films 47a to 49c by the general plating treatment. Form ~ 45d.

Next, the plating films 45a to 45d are dried by heat treatment (baking). Next, the second protective films 48a to 48c made of polyimide are formed to cover the boundaries between the plating films 45a to 45d and the first protective films 47a to 47c. Next, the strength of the polyimide film (first protective film 47a to 47c and second protective film 48a to 48c) is improved by heat treatment (cure). Next, the terminal pins 46a to 46d are joined onto the plating films 45a to 45d by solder layers, respectively.

After that, the semiconductor device 20 shown in FIGS. 1 to 3 is completed by dicing (cutting) the semiconductor substrate 10 (semiconductor wafer) into individual chips.

^{As described above, according to the embodiment, the n +} type source region and the p ⁺⁺ type contact region and the source electrode are electrically connected by the side wall of the contact trench provided between the gate trenches adjacent to each other. Will be done. As a result, even if the unit cell is miniaturized, the contact area between the source electrode and the semiconductor substrate is increased by the area of the side wall of the contact trench, and the n ⁺ type source region and the p ⁺⁺ type contact region and the source electrode are combined. The contacts can be obtained stably.

By stably obtaining contact between the n ⁺ type source region and the p ⁺⁺ type contact region and the source electrode, it is possible to reduce the variation in the on-resistance for each unit cell. As a result, it is possible to realize a low on-resistance obtained with the miniaturization of the unit cell. Further, by reducing the variation in the on-resistance for each unit cell, it is possible to suppress the variation in the drain-source current in the saturation region for each unit cell. Thereby, the conduction loss can be reduced.

Further, according to the embodiment, it has become uniformly high in the depth direction at a portion (contact portion) where the n-type impurity concentration of the n ⁺ -type source region is exposed on the side wall of the contact trench, the n ⁺ -type source The source electrode comes into contact with the contact area of the region. As a result, the contact resistance between the source electrode and the n ⁺ type source region can be reduced, and when the source electrode is turned on, ^{electrons are supplied from the source electrode through the n +} type source region to the channel (n-type inversion layer). Since the amount can be increased, the on-resistance can be reduced.

Further, according to the embodiment, ^{the p-type impurity concentration in the p ++} type contact region is uniformly increased in the depth direction at the portion (contact portion) exposed on the side wall of the contact trench, and the p ⁺⁺ type The source electrode comes into contact with the contact portion of the contact region. As a result, the contact resistance between the source electrode and the p ⁺⁺ type contact region can be reduced, and the n ^- type drift region is pulled out from the n-type drift region to the source electrode through the p-type base region and the p ^{++ type contact region at turn-off.} The amount of hole current (cutting current) can be increased.

As the amount of breaking current at turn-off increases, it is difficult for the parasitic BJT (Bipolar Junction Transistor) formed in ^{the n +} type source region, p-type base region, and n ^{-type drift region to turn on.} As a result, it is possible to suppress the flow of a large current when the parasitic BJT is turned on, and it is possible to improve the avalanche withstand capacity, so that stable operation can be realized.

(Example)
The voltage / current characteristics of the main semiconductor element 11 of the semiconductor device 20 (see FIGS. 1 to 3) according to the above-described embodiment were verified. FIG. 15 is a characteristic diagram schematically showing the voltage / current characteristics of the embodiment. FIG. 16 is a characteristic diagram schematically showing the voltage / current characteristics of the conventional example. In both FIGS. 15 and 16, the horizontal axis is the drain-source voltage Vds, and the vertical axis is the drain-source current Ids.

FIG. 15 schematically shows the results of measuring the drain-source voltage Vds and the drain-source current Ids for each of the three unit cells of the semiconductor device 20 (hereinafter referred to as an embodiment) according to the embodiment. The results of measuring the drain-source voltage Vds and the drain-source current Ids for each of the three unit cells of the conventional semiconductor device 220 (see FIG. 18: hereinafter referred to as a conventional example) are also schematically shown in FIG. ..

From the results shown in FIG. 16, it was confirmed that in the conventional example, the on-resistance varies from unit cell to unit cell, and the drain-source current Ids in the saturation region varies from unit cell to unit cell. This is because the contact resistance between the source electrode (NiSi film 241) and the n ⁺ type source region 235 is large, and ^{the injection of electrons from the source electrode into the n +} type source region 235 is restricted when the source electrode (NiSi film 241) is turned on. This problem was especially noticeable at high currents.

On the other hand, from the results shown in FIG. 15, it was confirmed that in the embodiment, the variation in the on-resistance for each unit cell can be reduced, and the variation in the drain-source current Ids in the saturation region for each unit cell can be reduced. rice field. The reason is that the contact portion 51a of the n ⁺ -type source region 35a, the contact resistance between the source electrode and the n ⁺ -type source region 35a can be made small, and because the ohmic contact can be stably obtained ..

In addition, the reverse recovery tolerance of the above-mentioned examples was examined. FIG. 17 is a characteristic diagram showing the amount of breaking current according to the reverse recovery withstand capacity of the embodiment. In the main semiconductor element 11 of the above-described embodiment and the conventional example (semiconductor device 220), the hole current (disconnection current) drawn to the source pads 21a and 221 through the p-type base regions 34a and 234 at turn-off. The result of comparing the amounts is shown in FIG.

As shown in FIG. 17, it was confirmed that in the examples, the amount of the hole current drawn to the source pad 21a through the p-type base region 34a at the time of turn-off is larger than that in the conventional example. Since ^{the p-type impurity concentration in the p ++} type contact region 36a is high at the contact portion (contact portion 52a) with the source electrode ^{, the contact resistance between the source electrode and the p ++} type contact region 36a is reduced. Because.

On the other hand, in the conventional example, since the contact area between the source electrode and the semiconductor substrate 210 is small ^{, the contact resistance between the source electrode and the p ++} type contact region 236 is high, and the on-resistance varies widely for each unit cell. Therefore, the ^{amount of hole current, which is the displacement current that flows when holes, which are minority carriers in the n-} type drift region 232, are discharged to the source electrode side at turn-off, is small, and the parasitic BJT is likely to turn on. , It was confirmed that the destruction due to the surrender of Avalanche is likely to occur.

In the above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, a configuration in which only the gate pad is arranged in the main invalid area may be used. Further, the present invention can be applied even when a wide bandgap semiconductor other than silicon carbide is used instead of using silicon carbide as a semiconductor material. Further, the present invention holds the same even if the conductive type (n type, p type) is inverted.

As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a power semiconductor device that controls a high voltage or a large current.

1 Active area 1a Main effective area 1b Main invalid area 2 Edge termination area 10 Semiconductor substrate 11 Main semiconductor element 12 Current sense part 12a Sense effective area 12b Sense invalid area 13 Temperature sense part 14 Gate pad part 20 Semiconductor device 21a Source pad (electrode) pad)
21b Gate pad (electrode pad)
22 OC pad (electrode pad)
23a Anode pad (electrode pad)
23b Cathode pad (electrode pad)
31 n ⁺ -type drain region 32 n ^- -type drift region 32a n ^- -type regions 33a, 33b n-type current diffusion regions 34a, 34b p-type base region 35a, 35b n ⁺ -type source region 36a, 36b p ⁺⁺ type contact region 37a , 37b Gate trench 38a, 38b Gate insulating film 39a, 39b Gate electrode 40,83 Interlayer insulating film 40a, 40b, 83a, 83b Contact hole 41a, 41b Ti film 42a, 42b TiN film 43a, 43b Barrier metal 44a, 44b W film 45a to 45d Plating film 46a to 46d Terminal pins 47a to 47c First protective film 48a to 48c Second protective film 49 Drain electrodes 50a, 50b Contact trench 51a, 51b n ⁺ type Contact part of source region 52a, 52b p ⁺⁺ type contact portion 61a of the contact area, 61b, 62a, 62b, 91,93 p + -type region 71 n ⁺ -type starting substrate 72 n ^- type silicon carbide layer 72a n ^- moiety 73 p-type with an increased thickness of the type silicon carbide layer Silicon carbide layer 81 p-type polysilicon layer 82 n-type polysilicon layer 92,94 n-type region 95 Mask 96-99 Diagonal ion injection d1 p ⁺ type region depth d2 ^{Distance between adjacent p +} type regions d3 n Depth of mold region The ^{thickness of the t1 n-} type silicon carbide layer that is first laminated on the ^{n + type starting substrate. The thickness of the thickened portion of the t2 n-} type silicon carbide layer t3 p-type silicon carbide. Layer thickness w1, w1'Cell pitch X Direction parallel to the front surface of the semiconductor substrate (first direction)
Y Direction parallel to the front surface of the semiconductor substrate and orthogonal to the first direction (second direction)
Z Depth direction θ1 to θ4 Diagonal ion implantation injection angle

Claims (10)

A semiconductor substrate made of a semiconductor with a wider bandgap than silicon,
A first conductive type first semiconductor region provided inside the semiconductor substrate, and
A second conductive type second semiconductor region provided between the first main surface of the semiconductor substrate and the first semiconductor region, and
A first conductive type third semiconductor region selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region,
A gate trench that penetrates the third semiconductor region and the second semiconductor region and reaches the first semiconductor region from the first main surface of the semiconductor substrate.
A gate electrode provided inside the gate trench via a gate insulating film,
A plurality of unit cells provided apart from the gate trench and having a contact trench that penetrates the third semiconductor region from the first main surface of the semiconductor substrate and reaches the second semiconductor region.
A first electrode electrically connected to the third semiconductor region at the side wall of the contact trench and electrically connected to the second semiconductor region at the side wall and bottom surface of the contact trench.
A second electrode provided on the second main surface of the semiconductor substrate and
With
The third semiconductor region is a first portion exposed on the side wall of the contact trench, and has a higher concentration of first conductive impurities than the second portion excluding the first portion.
The first electrode is a semiconductor device characterized in that the first portion is in contact with the third semiconductor region. The semiconductor device according to claim 1, wherein the concentration of the first conductive impurity in the first portion of the third semiconductor region is uniform in the depth direction. The semiconductor device according to claim 1 or 2, wherein the third semiconductor region is further in contact with the first electrode on the first main surface of the semiconductor substrate. The contact trench is provided inside the semiconductor substrate at a depth position farther from the first main surface of the semiconductor substrate than the third semiconductor region, away from the gate trench, in contact with the second semiconductor region, and in contact with the second semiconductor region. Further provided with a second conductive type fourth semiconductor region exposed on the side wall and bottom surface of the
The semiconductor device according to any one of claims 1 to 3, wherein the first electrode is in contact with the fourth semiconductor region. The fourth semiconductor region is a third portion exposed from the side wall of the contact trench to the bottom surface, and has a higher concentration of second conductive impurities than the fourth portion excluding the third portion.
The semiconductor device according to claim 4, wherein the first electrode is in contact with the fourth semiconductor region at the third portion. The unit cell is composed of a portion between the centers of the gate trenches adjacent to each other.
The semiconductor device according to any one of claims 1 to 5, wherein the unit cell pitch is 2 μm or less. The first step of forming a first conductive type first semiconductor region inside a semiconductor substrate made of a semiconductor having a bandgap wider than that of silicon, and
A second step of forming a second conductive type second semiconductor region in contact with the first semiconductor region between the first main surface of the semiconductor substrate and the first semiconductor region.
A third step of selectively forming a first conductive type third semiconductor region between the first main surface of the semiconductor substrate and the second semiconductor region in contact with the second semiconductor region.
A fourth step of forming a gate trench from the first main surface of the semiconductor substrate through the third semiconductor region and the second semiconductor region to reach the first semiconductor region.
A fifth step of forming a gate electrode inside the gate trench via a gate insulating film, and
A sixth step of forming a contact trench that is separated from the gate trench, penetrates the third semiconductor region from the first main surface of the semiconductor substrate, and reaches the second semiconductor region.
The first conductive impurity is ion-implanted into the side wall of the contact trench from an oblique direction with respect to the first main surface of the semiconductor substrate, and the concentration of the first conductive impurity in the third semiconductor region is set to the contact trench. A cell forming step of forming a plurality of unit cells by performing a seventh step of making the first portion exposed on the side wall higher than the second portion excluding the first portion, and a cell forming step.
After the cell forming step, the side wall of the contact trench is in contact with the first portion and is electrically connected to the third semiconductor region, and the side wall and bottom surface of the contact trench are electrically connected to the second semiconductor region. The eighth step of forming the connected first electrode and
After the cell forming step, a ninth step of forming a second electrode provided on the second main surface of the semiconductor substrate and a ninth step.
A method for manufacturing a semiconductor device, which comprises. A step of ion-implanting a second conductive type impurity into the second semiconductor region to selectively form a second conductive type fourth semiconductor region separated from the gate trench is further included.
The method for manufacturing a semiconductor device according to claim 7, wherein in the eighth step, the first electrode in contact with the fourth semiconductor region is formed. The method for manufacturing a semiconductor device according to claim 8, wherein in the step of selectively forming the fourth semiconductor region, ions are implanted into the side wall and the bottom surface of the contact trench. The step of selectively forming the fourth semiconductor region is
Prior to the sixth step, the tenth step of forming the fourth semiconductor region in the second semiconductor region below the third semiconductor region, and
After the sixth step, ions are implanted into the side wall of the contact trench from an oblique direction with respect to the first main surface of the semiconductor substrate to adjust the concentration of the second conductive impurity in the fourth semiconductor region to the contact. The eleventh step of making the third portion exposed from the side wall of the trench to the bottom surface higher than the fourth portion excluding the third portion.
Including
The semiconductor device according to claim 8, wherein in the sixth step, the contact trench is formed from the first main surface of the semiconductor substrate through the third semiconductor region and reaches the fourth semiconductor region. Manufacturing method.

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