JP6618235B2 - Imaging device and imaging apparatus - Google Patents

Description

The present invention relates to an imaging equipment having an image pickup device and the image sensor having a laminated structure.

  In general, when a still image or a moving image is captured by an imaging device including an imaging element such as a CCD or a CMOS image sensor, subject information (also referred to as position information) regarding the position of the subject is acquired before shooting, and the subject An optimum exposure condition is determined in accordance with information.

  For example, when obtaining position information of a subject used for focus control in an image pickup apparatus, the position information is obtained according to an image signal output from the image pickup element. When acquiring positional information according to an image signal, it is necessary to continuously capture a plurality of images. Therefore, it is desirable to improve the frame rate by reducing the number of pixels to be read in the image sensor.

  FIG. 22 is a diagram for explaining the timing of an autofocus imaging operation (AF evaluation imaging) during live view in a conventional imaging apparatus.

  In a conventional imaging device, the imaging timing is defined by a vertical synchronizing signal (VD), and when the AF control signal is turned on, an AF evaluation image is captured according to VD after the live view imaging period. The When the AF control signal is turned off, the live view imaging period starts again.

  As described above, since the live view imaging period for obtaining the live view image and the AF operation period for obtaining the AF evaluation image exist serially along the time axis, the live view image and the AF evaluation image are simultaneously captured. It is not possible.

  For this reason, as shown in the figure, an AF evaluation image is captured in the AF operation period located between the live view periods (frames), and there is a time lag between the live view image and the AF evaluation image. To do. In addition, although live view display is performed when an AF evaluation image is captured, live view display is performed according to the AF evaluation image. As shown in FIG. 22, when an AF evaluation image is captured, the frame rate is set higher than that of the live view imaging period. Therefore, the thinning-out rate is increased in reading of the image sensor, and the image quality is inevitably increased. It will be lower.

  In order to avoid this point, for example, a focus signal detection pixel is provided separately from the image signal pixel in the pixel portion of the image sensor. Here, the focus detection / automatic exposure is provided with a live view readout mode for reading out an imaging signal for live view display, and reading out an imaging signal for use in a focus detection signal and photometric information for automatic exposure from an imaging device. The read mode is provided, and these read modes are cyclically repeated for each frame (see Patent Document 1).

JP 2009-89105 A

  However, in Patent Document 1, since an image signal (that is, charge) is read out from the image sensor in units of pixels, not only does it take time to transfer charges, but also the amount of transferred data increases and power consumption increases. . Furthermore, since the image signal that is the output of the image sensor is subjected to image signal processing by a control device or the like provided outside the image sensor, a large transfer data amount only increases the processing load on the control device. Power consumption increases.

  In addition, in Patent Document 1, since the focus signal detection pixel is provided in the pixel portion, the area of the image signal pixel is inevitably reduced, and the focus signal detection pixel is an image signal (image signal). ), It is not used to obtain the image quality.

An object of the present invention is to provide a free imaging device and the imaging equipment of the image quality decreases with shortening the data transfer time.

In order to achieve the above object, an imaging device according to the present invention includes a plurality of pixels, a pixel unit that outputs an image signal according to an optical image, a driving unit that drives the pixel unit, and the driving unit that Output means for outputting the image signal from the pixel unit, input means for inputting the image signal output to the output means, addition processing for adding the input image signal, and output to the output means The image signal is input, and an edge amount of the subject is detected based on the input image signal, or the subject moves based on a difference between frames of the input two consecutive image signals. there is motion and detects the object by the detection means and the case edge amount of the subject detected by the detecting means is equal to or greater than a predetermined amount or said detecting means for detecting whether there is a Said control means for controlling so as not to perform addition processing by the adder means and Rukoto to have a if it.

According to the present invention, it is possible to prevent deterioration of image quality while shortening the data transfer time.

1 is a block diagram illustrating a configuration of an example of an imaging apparatus according to a first embodiment of the present invention. It is a block diagram which shows the example about the structure of the image pick-up element with which the imaging part shown in FIG. 1 was equipped. FIG. 1 is a diagram for explaining timing when a normal image is acquired by the camera. FIG. 3 is a diagram illustrating an example of a configuration of a part of a pixel unit in the image sensor illustrated in FIG. 2. 3 is a timing chart for explaining a read operation performed by the horizontal signal circuit shown in FIG. 2. FIG. 1 is a diagram for explaining timing when a camera simultaneously acquires a plurality of images. FIG. 7 is a block diagram illustrating main stream and substream pixels described in FIG. 6 and a vertical signal circuit connected to a vertical signal line. FIG. 7 is a diagram for explaining the timing of reading the main stream and substream described in FIG. 6. It is a block diagram which shows the structure about an example of the output control part shown in FIG. FIG. 3 is a block diagram for explaining a connection relationship between an evaluation value calculation unit and a circuit condition setting unit in the digital processing circuit shown in FIG. 2. It is a flowchart for demonstrating operation | movement of the evaluation value calculation part shown in FIG. It is a flowchart for demonstrating operation | movement of the circuit condition setting part shown in FIG. It is a flowchart for demonstrating operation | movement of the evaluation value calculation part used with the camera by the 2nd Embodiment of this invention. It is a figure which shows an example of the process which calculates a luminance value per line shown in FIG. It is a flowchart for demonstrating operation | movement of the circuit condition setting part 207 used in the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the digital processing circuit used with the camera by the 3rd Embodiment of this invention. It is a figure which shows the relationship between a to-be-photographed object's brightness | luminance and edge amount. 17 is a flowchart for explaining an operation of a pixel addition unit in the digital processing circuit shown in FIG. 16. It is a figure for demonstrating the detection of the moving body performed by the evaluation value calculation part shown in FIG. It is a block diagram which shows the connection of the circuit condition setting part 207 with which the digital processing circuit 204 used with the camera in the 4th Embodiment of this invention was equipped, and the external output buffer. 21 is a flowchart for explaining control of an external output buffer performed by a circuit condition setting unit 207 shown in FIG. It is a figure for demonstrating the timing of the autofocus imaging operation (AF evaluation imaging) in the case of live view in the conventional imaging device.

  Hereinafter, an example of an imaging apparatus according to an embodiment of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing the configuration of an example of an imaging apparatus according to the first embodiment of the present invention. Note that the illustrated imaging apparatus is applied to, for example, an electronic still camera with a moving image function or a video camera.

  An imaging apparatus (hereinafter simply referred to as a camera) 100 includes a photographing lens unit (hereinafter simply referred to as a lens unit) 101, and the lens unit 101 condenses a subject image (also referred to as an optical image) on the imaging unit 103. . The lens unit 101 includes a focal length changing unit for changing the focal length, a light shielding unit for shielding incident light, and the like.

  A light amount adjustment unit 102 is disposed between the lens unit 101 and the imaging unit 103. For example, the light amount adjustment unit 102 is a neutral density filter insertion mechanism or a diaphragm mechanism. The imaging unit (that is, the imaging device) 103 includes a pixel unit, an A / D conversion circuit, a digital processing unit (both not shown), and the like. The imaging device outputs an electrical signal (analog signal) corresponding to the optical image formed through the lens unit 101 and the light amount adjustment unit 102. The analog signal is converted into a digital signal (digital image signal) by the A / D conversion circuit. The digital processing unit calculates an evaluation value for control described later based on a digital image signal (hereinafter also simply referred to as an image signal).

  The image signal and the evaluation value that are output from the imaging unit 103 are given to the signal processing unit 104, and the signal processing unit 104 generates a correction parameter and corrects the image signal for the image signal.

  The imaging control unit 105 sends a timing signal to the imaging unit 103, the signal processing unit 104, and the like under the control of the overall control / calculation unit 106, and sets a gain setting signal and an exposure time for amplifying the image signal. An exposure time setting signal and other signals necessary for control are generated. The overall control / arithmetic unit 106 controls the entire imaging apparatus 100.

  The overall control / calculation unit 106 includes a storage unit 107, an imaging condition detection unit 108, and an imaging condition calculation unit 109. The storage unit 107 temporarily stores an image signal and an evaluation value that are output from the signal processing unit 104. The shooting condition detection unit 108 detects the position of the subject on the screen according to the output of the imaging unit 103 and obtains position information. The shooting condition calculation unit 109 determines the shooting condition according to the position information as described later.

  The shooting condition calculation unit 109 changes the focal length of the lens unit 101, adjusts the light amount by the light amount adjustment unit 102, or adjusts the exposure time and gain by the imaging control unit 105 based on the determined shooting condition.

  In the example shown in FIG. 1, the signal processing unit 104 is configured differently from the overall control / calculation unit 106, but the overall control / calculation unit 106 may include the signal processing unit 104, and the imaging unit The signal processing unit 104 may be provided in the 103.

  The illustrated camera 100 is provided with an operation unit 110, a recording unit 111, and a display unit 112. The operation unit 110 is provided with a human IF such as a button and a dial. Various operation commands are issued to the arithmetic unit 106. The recording unit 111 records image data generated by the overall control / calculation unit 106 according to the image signal. The display unit 112 displays an image corresponding to the image data generated by the overall control / calculation unit 105 and an icon corresponding to an input operation by the operation unit 108.

  FIG. 2 is a block diagram illustrating an example of the configuration of the image sensor provided in the imaging unit 103 illustrated in FIG.

  In FIG. 2, the image sensor is a CMOS image sensor, for example, and has a pixel unit 201. The pixel unit 201 has a plurality of pixels arranged in a two-dimensional matrix. In each of the pixels, reset and readout operations for charges generated by photoelectric conversion are performed. The pixel unit 201 includes a so-called optical black pixel for determining the black signal level and a dummy pixel used for circuit noise removal or the like.

  The horizontal signal circuit 202 controls the pixel unit 201 and the vertical signal circuits 203a and 203b, and performs the setting of the exposure time of each row and the selection and non-selection setting of the readout row for reading out pixel signals in the pixel unit 201. These settings are performed by the imaging control unit 105 under the control of the overall control / calculation unit 106.

  Each of the vertical signal circuits 203a and 203b includes, for example, a column amplifier circuit, an A / D conversion circuit, a pixel addition circuit, a signal memory, a signal output selection switch, and an output circuit. The pixel portion 201 and the vertical signal circuits 203a and 203b are connected by a vertical signal line that is common between the columns. Here, one vertical signal line is shared every two columns. Different vertical signal lines are alternately connected to the vertical signal colors 203a and 203b.

  A digital processing circuit (signal processing unit) 204 drives and controls a plurality of rows, independently amplifies signals for each row, A / D conversion circuit settings (A / D conversion accuracy, speed, conversion gain, etc.), pixels Controls the presence / absence of addition and output order.

  The digital processing circuit 204 adds header information to the output signals from the vertical signal circuits 203a and 203b and outputs them to the external output buffers 205a and 205b, respectively. As shown in the figure, since the imaging device has a plurality of external output buffers 205a and 205b, a plurality of image signals can be output simultaneously.

  The digital processing circuit 204 is provided with an evaluation value calculation unit 206 and a circuit condition setting unit 207. The evaluation value calculation unit 206 is controlled by the imaging control unit 105, and the image signal of a specific row (that is, here, An evaluation value for control is calculated from the pixel signal. Here, the evaluation value for control is, for example, a subject luminance value, and the evaluation value calculation unit 206 obtains the subject luminance value by averaging the pixel signals in a specific row. The circuit condition setting unit 207 sets the horizontal signal circuit 202 and the vertical signal circuits 203a and 203b according to the evaluation value for control obtained by the evaluation value calculation unit 206 or the control signal sent from the imaging control unit 105.

  In the example shown in FIG. 2, the pixel unit 201, the horizontal signal circuit 202, the vertical signal circuits 203a and 203b, the digital processing circuit 204, and the external output buffers 205a and 205b are formed on different substrates.

  Here, the pixel portion 201, the horizontal signal circuit 202, and the vertical signal circuits 203a and 203b are referred to as first element portions, and the digital processing circuit 204 and the external output buffers 205a and 205b are referred to as second element portions. The first and second element portions have, for example, a stacked structure.

  In this manner, by using the digital processing circuit 204 in which a large number of circuits are integrated as another substrate, the semiconductor area on the substrate can be reduced.

  FIG. 3 is a diagram for explaining the timing when a normal image is acquired by the camera 100 shown in FIG.

  In the illustrated example, exposure and signal readout are performed in accordance with a vertical synchronization signal generated by the overall control / calculation unit 106 or the imaging control unit 105.

  FIG. 4 is a diagram illustrating an example of the configuration of a part of the pixel portion in the image sensor shown in FIG.

  As shown, a shared structural unit 408 is defined here by four photodiodes (PD) 401. The PD 401 photoelectrically converts an optical image incident through the lens unit 102 and outputs a charge signal (also simply referred to as charge). A transfer transistor (transfer Tr) 402 transfers charges generated in the PD 401 to a subsequent stage in response to a transfer signal (TX signal, suffix is omitted here) output from the horizontal signal circuit 202. The signal amplification amplifier 403 amplifies the charge signal transferred from the PD 401 when the transfer Tr 402 is turned on, that is, turned on.

  A signal reset transistor (reset Tr) 404 resets the PD 401 and the signal amplification amplifier 403 in accordance with a reset signal (RS signal, suffix is omitted here) output from the horizontal signal circuit 202. Here, as illustrated, the signal amplification amplifier 403 and the reset Tr 404 are shared by the four PDs 401.

  The vertical signal line 407 transmits the amplified signal that is the output of the signal amplification amplifier 304 to the vertical signal circuit 203a or 203b. A plurality of common structural units 408 are two-dimensionally arranged using the above-described common structural unit 408 as one unit, and the TX signal and the RS signal are commonly connected to two or more shared structural units 408 in the same row. Is done.

  FIG. 5 is a timing chart for explaining a read operation performed by the horizontal signal circuit shown in FIG.

  3 to 5, the horizontal signal circuit 202 raises the RS signal (RS1) at time T501 and sequentially raises the TX signals (TX11 to TX14) according to the horizontal synchronization signal. Here, as shown in the figure, after TX11 is lowered, TX12 is raised at time T502, and TX12 is lowered at the fall of RS1.

  Subsequently, TX11 is raised at time T503, TX11 is lowered, and then TX12 is raised at time T504. Then, after TX12 is lowered, RS1 is raised at time T505, and TX13 is raised. Then, after TX13 is lowered, TX14 is raised at time T506, and TX14 is lowered at the fall of RS1.

  With the above operation, the charge of each PD 401 is reset and exposure is performed sequentially. This operation is also sequentially performed in other pixel units 408 according to the conditions set by the imaging control unit 105.

  As described above, when a predetermined exposure time has elapsed after the reset operation, TX11 and TX12 sequentially rise, and the charge of each PD 401 is sequentially read out to the signal amplification amplifier 403. The amplified signal that is the output of the signal amplifier 403 is read out to the vertical signal line 407 and input to the vertical signal circuit 203a or 203b. This operation is also sequentially performed in other rows according to the conditions set by the imaging control unit 105.

  In this manner, image signal data of one surface (that is, one screen) can be acquired by sequentially performing pixel reset and readout operations in units of rows. In addition, when shooting continuously such as a moving image, the setting of shooting conditions can be changed in synchronization with a vertical synchronization signal.

  This shooting condition is calculated by the shooting condition calculation unit 109 based on the result of detection performed by the shooting condition detection unit 108 according to the acquired image signal. Then, the imaging control unit 105 controls the imaging unit 103 according to the imaging conditions. The digital processing circuit 204 outputs the image data to the signal processing unit 104 via the output buffers 205a and 205b.

  FIG. 6 is a diagram for explaining timing when a plurality of images are simultaneously acquired in the camera 100 shown in FIG.

  In the illustrated example, exposure and signal readout are performed for each of a plurality of images in accordance with a vertical synchronization signal generated by the overall control / calculation unit 106 or the imaging control unit 105. Here, the frame rate of the image data (substream) output to the output buffer 205b is increased with respect to the image data (main stream) output to the output buffer 205a.

  For example, by supplying a vertical synchronization signal for reading a substream with a cycle shorter than the vertical synchronization signal for reading the main stream (here, a quarter cycle), the substream pixels are exposed, Image data is read out in the next vertical synchronizing signal period.

  FIG. 7 is a block diagram showing the main stream and substream pixels described in FIG. 6 and a vertical signal circuit connected to the vertical signal line. The vertical signal circuits 203a and 203b have the same configuration.

  FIG. 8 is a diagram for explaining the read timing of the main stream and the substream described in FIG.

  Referring to FIGS. 7 and 8, the vertical signal circuit 203b has two first switch sections 701, and these first switch sections 701 are connected to the vertical signal line 407 via the buffer 701a. . The first switch unit 701 is ON / OFF controlled by the SW1-1 signal and the SW1-2 signal supplied from the digital processing circuit 204, respectively. The amplified signal (OUT) output to the vertical signal line 407 is supplied to one of the signal memories 702 as the voltage V1-1 when one of the first switch sections 701 is turned on by the SW1-1 signal at time T801. Then, when one of the first switches 701 is turned off by the SW1-1 signal (time T802), a charge (first voltage signal) corresponding to the voltage V1-1 is temporarily accumulated in the signal memory.

  Similarly, the other of the second switch section 701 is turned on / off by the SW1-2 signal, and a charge (second voltage signal) corresponding to the voltage V1-2 is temporarily stored in the other of the signal memory 702. . In this way, by performing on / off control of the first switch unit 701, when reading the main stream (second voltage signal) or the substream (first voltage signal), other streams can be read. The influence can be removed.

  The vertical signal circuit 203b has two second switch sections 703, and the second switch sections 703 are ON / OFF controlled by the SW2-1 signal and the SW2-2 signal supplied from the digital processing circuit 204, respectively. When the first switch unit 703 is turned on by the SW2-1 signal and the SW2-2 signal at time T803, the electric charges accumulated in the signal memory 702 are supplied to the A / D conversion circuit 704 as voltages V1-1 and V1-2, respectively. Given.

  In this way, by inputting the voltages V1-1 and V1-2 to different A / D conversion circuits 704, A / D conversion control according to the shooting state (that is, shooting conditions) can be performed. . At time T804, the A / D conversion circuit 704 converts the voltages (analog signals) V1-1 and V1-2 into digital signals (image signals) D1 according to predetermined A / D conversion conditions under the control of the digital processing circuit 204. -1 and D1-2 (first image data and second image data).

  Examples of the predetermined A / D conversion condition include the presence / absence of operation of the A / D conversion circuit, the bit accuracy in A / D conversion, the A / D conversion speed, the supply current amount or voltage to the A / D conversion circuit, A There is at least one of the / D conversion gain and the start time of the A / D conversion operation.

  Image signals D <b> 1-1 and D <b> 1-2 that are outputs of the A / D conversion circuit 704 are given to the output control unit 705. Then, the output control unit 705 selects at least one of the image signals D1-1 and D1-2 under the control of the digital processing circuit 204, and outputs the selected image signal Dout to the digital processing unit 204 at time T805. That is, the output control unit 705 selectively outputs the first and second image data.

  FIG. 9 is a block diagram showing the configuration of an example of the output control unit 705 shown in FIG.

  The illustrated output control unit 705 includes first and second multipliers 705a and 705b and an adder 705c. The first and second multipliers 705a and 705b are supplied with image signals D1-1 and D1-2, respectively. The first multiplier 705a multiplies the image signal D1-1 by the first coefficient α and outputs a first multiplication signal. On the other hand, the second multiplier 705b multiplies the image signal D1-2 by the second coefficient β and outputs a second multiplied signal.

  The adder 705 adds the first and second multiplication signals and outputs the addition signal as a selected image signal. Here, if the first coefficient α = 0, the output control unit 705 outputs the image signal D1-1 as the selected image signal. On the other hand, when the second coefficient β = 0, the image signal D1-2 is output from the output control unit 705 as the selected image signal. If the first coefficient α is equal to the second coefficient β = 1, the output control unit 705 outputs the image signals D1-1 and D1-2 as selected image signals.

  Although not shown in FIG. 7, a circuit configuration similar to the circuit configuration shown in FIG. 7 is also connected to the other vertical signal lines, and A / D conversion can be performed simultaneously on a plurality of rows. it can.

  FIG. 10 is a block diagram for explaining a connection relationship between the evaluation value calculation unit 206 and the circuit condition setting unit 207 in the digital processing circuit shown in FIG.

  As described above, the digital processing circuit 204 includes the evaluation value calculation unit 206 and the circuit condition setting unit 207. The evaluation value calculation unit 206 receives image signals that are output from the vertical signal circuits 203a and 203b. Then, the evaluation value calculation unit 206 calculates an evaluation value according to the image signal and stores the evaluation value in the memory 1001.

  The aforementioned image signal is also provided to the header adding unit 1002, and the header adding unit 1002 adds header information such as a synchronization code and an exposure condition to the image signal.

  FIG. 11 is a flowchart for explaining the operation of the evaluation value calculation unit 206 shown in FIG.

  The evaluation value calculation unit 206 acquires the substream from the vertical signal circuits 203a and 203b with the frame number N = 0 (step S1100). Subsequently, the evaluation value calculation unit 206 determines whether or not there is an evaluation value calculation target area (target area) for the substream (step S1101). If it is not the target area (NO in step S1101), the evaluation value calculation unit 206 stands by.

  On the other hand, if it is the target area (YES in step S1101), the evaluation value calculation unit 206 obtains the luminance value Y of the subject as the evaluation value (control evaluation value) (step S1102). Then, the evaluation value calculation unit 206 determines whether or not the target area has ended (step S1103).

  If the target area has not ended (NO in step S1103), the evaluation value calculation unit 206 returns to the process of step S1101 and determines whether or not the target area. On the other hand, when the target area ends (YES in step S1103), evaluation value calculation unit 206 stores luminance value Y in memory 1001 (step S1104).

  Subsequently, the evaluation value calculation unit 206 obtains a substream from the vertical signal circuits 203a and 203b with the frame number N = N + 1 (step S1105) (step S1106). The evaluation value calculation unit 206 determines whether or not there is a target area for the substream (step S1107). If it is not the target area (NO in step S1107), the evaluation value calculation unit 206 stands by.

  On the other hand, if it is the target area (YES in step S1107), the evaluation value calculation unit 206 obtains the luminance value Y of the subject as the evaluation value (step S1108). Then, the evaluation value calculation unit 206 determines whether or not the target area has ended (step S1109).

  If the target area has not ended (NO in step S1109), evaluation value calculation unit 206 returns to the process in step S1107 and determines whether or not the target area is the target area. On the other hand, when the target area ends (YES in step S1109), evaluation value calculation unit 206 averages the luminance value (or luminance average value) stored in memory 1001 and the luminance value obtained in step S1108 to obtain the luminance average. A value is obtained (step S1110). Then, the evaluation value calculation unit 206 stores the luminance average value in the memory 1001 (step S1111).

  Subsequently, the evaluation value calculation unit 206 determines whether or not the frame number N has reached the number of calculated frames (Nmax) for obtaining the luminance average value (step S1112). If N = Nmax is not satisfied (NO in step S1112), the evaluation value calculation unit 206 returns to step S1105 and processes the next frame.

  If N = Nmax (YES in step S1112), evaluation value calculation unit 206 outputs the result (luminance average value) Y_sub obtained for the calculated number of frames (Nmax) to circuit condition unit 207 (step S1113). . Then, the evaluation value calculation unit 206 ends the evaluation value calculation process.

  In the above-described example, the luminance value obtained for each frame is averaged. However, a final luminance value may be calculated by performing predetermined weighting. Furthermore, a difference between frames may be used as a calculation result.

  Further, the calculation target region coordinates, the calculation target region number, the calculated frame number (Nmax), and the like can be set from the imaging control unit 105. In addition, a predetermined value may be written in advance from the imaging control unit 105 to the memory 1001 that stores the calculated luminance value.

  As described above, in the illustrated example, four substreams can be acquired while one main stream is acquired. That is, an evaluation value (luminance average value) can be calculated from at least three substreams before reading the main stream.

  FIG. 12 is a flowchart for explaining the operation of the circuit condition setting unit 207 shown in FIG.

  When shooting conditions (that is, the first shooting conditions) are input from the shooting control unit 105 (step S1201), the circuit condition setting unit 207 sets the shooting conditions to the horizontal signal circuit 202 and the vertical signal circuits 203a and 230b. (Step S1202). Here, the circuit condition setting unit 207 performs settings for both the main stream and the substream.

  As described above, when the calculation result Y_sub is input from the evaluation value calculation unit 206 (S1203), the circuit condition setting unit 207 determines whether the calculation result Y_sub is within a predetermined range. Here, the circuit condition setting unit 207 determines whether or not the determination lower limit luminance value Y_b <calculation result Y_sub <the determination upper limit luminance value Y_u (step S1204).

  As a result of the determination, if Y_b <Y_sub <Y_u (YES in step S1204), the circuit condition setting unit 207 returns to the process of step S1201 and inputs the imaging conditions again. On the other hand, if Y_b ≧ Y_sub or Y_sub ≧ Y_u (NO in step S1204), the circuit condition setting unit 207 changes the shooting condition (first shooting condition) to the horizontal signal circuit 202 and the vertical signal circuit 203 and changes the first shooting condition. 2 is set as the shooting condition (step S1205).

  In the process of step S1205, the operation settings of the horizontal signal circuit 202 and the vertical signal circuits 203a and 203b are performed for the main stream. For example, the circuit condition setting unit 207 sets the setting value according to the amount of deviation from the determination range defined by the determination lower limit luminance value and the determination upper limit luminance value in the horizontal signal circuit 202 when acquiring the main stream. Add or subtract from the shutter speed setting value.

  The circuit condition setting unit 207 may change the A / D conversion conditions set in the vertical signal circuits 203a and 203b in accordance with a set value corresponding to the amount of deviation from the determination range. Further, the circuit condition setting unit 207 connects the first switch unit 701, the second switch unit 703, or the A / D conversion result of the output control unit 705, or a coefficient to be multiplied (first and first). (2 coefficient) may be changed. The operation is performed for each frame until the end of the setting process.

  Subsequently, the circuit condition setting unit 207 adds the changed shooting condition to the header by the header adding unit 1002 in order to indicate that the shooting condition has been changed based on the calculation result Y_sub (step S1206). Then, the circuit condition setting unit 207 determines whether or not processing has been performed for all frames (step S1207).

  If the processing has not been completed for all frames (NO in step S1207), circuit condition setting unit 207 returns to the processing in step S1201. On the other hand, when the processing is completed for all the frames (YES in step S1207), the circuit condition setting unit 207 ends the setting processing.

  Thus, in the first embodiment of the present invention, the luminance value, which is the evaluation value for control, is calculated from the substream having a frame rate faster than that of the main stream, and the main stream is related to the luminance value. Since the shooting conditions are changed, even if the subject brightness changes abruptly, it is possible to quickly follow.

  In the first embodiment, the pixel unit 408 is two horizontal pixels and two vertical pixels. However, the same effect can be obtained even in pixel units having different configurations. In addition, here, the pixels used for the main stream and the pixels used for the substream are made different for each row. However, they are not necessarily made for every row, and may be made different for every column. Furthermore, a plurality of pixels that are skipped in the screen may be used.

  In addition, the plurality of A / D conversion circuits illustrated in FIG. 7 may not be of the same type. In other words, different types of A / D conversion circuits may be used as long as they are switched by the second switch unit 703. In order to reduce the circuit scale, an A / D conversion circuit located at the subsequent stage of the second switch unit may be shared. In this case, the A / D conversion circuit is used in a time division manner.

  In the first embodiment, the A / D conversion circuit is included in the vertical signal circuits 203a and 203b. However, the digital processing circuit 204 may include an A / D conversion circuit. That is, the A / D conversion circuit may be disposed on a different substrate from the pixel portion 201. Furthermore, although the evaluation value calculation unit 206 calculates the evaluation value for control according to the substream, the evaluation value may be calculated according to the main stream. In addition, when calculating the luminance value Y, which is an evaluation value for control, the luminance value Y may be calculated according to image signals obtained using different color filters. The luminance value may be calculated according to the obtained image signal.

  In addition, in the first embodiment, the circuit condition setting unit 207 receives the luminance value (luminance average value) from the evaluation value calculation unit 206, but the luminance value may be acquired from the memory 1001. The determination lower limit luminance value Y_b and the determination upper limit luminance value Y_u used in the circuit condition setting unit 207 are set from the overall control calculation unit 106.

[Second Embodiment]
In the first embodiment described above, a plurality of images with different frame rates are simultaneously acquired on the same screen, a control evaluation value is calculated according to the one image, and the other according to the evaluation value. An example of changing the shooting conditions when obtaining the image has been described.

  However, since the luminance of the subject is not uniform within the screen, the evaluation value may vary greatly depending on which area is the target area for evaluation value calculation. For this reason, it may be preferable to change the shooting conditions according to the area in the screen.

  The configuration of the camera in the second embodiment of the present invention is the same as that of the camera shown in FIG. 1, and the configuration of the pixel unit and the image capturing method are the same as those of the first embodiment.

  FIG. 13 is a flowchart for explaining the operation of the evaluation value calculation unit 206 used in the camera according to the second embodiment of the present invention.

  The evaluation value calculation unit 206 acquires a substream from the vertical signal circuits 203a and 203b with the frame number N = 0 and the row number L = 0 (step S1300). Subsequently, the evaluation value calculation unit 206 determines whether or not there is an evaluation value calculation target area (target area) for the substream (step S1301).

  If it is the target area (YES in step S1301), the evaluation value calculation unit 206 obtains the luminance value Y of the subject as the evaluation value in the row (step S1302). Then, the evaluation value calculation unit 206 stores the luminance value Y and the row number L in the memory 1001 (step S1303).

  FIG. 14 is a diagram illustrating an example of processing for calculating a luminance value in units of rows illustrated in FIG.

  As shown in FIG. 14, here, the luminance value Y is sequentially calculated for each row for the calculation target region (target area).

  Next, the evaluation value calculation unit 206 proceeds to the next row with L = L + 1 (step S1304), and determines whether or not the target area has ended (step S1305). If the target area has not ended (NO in step S1305), evaluation value calculation unit 206 returns to the process in step S1301 and determines whether or not the target area is the target area. If it is not the target area (NO in step S1301), the evaluation value calculation unit 206 proceeds to the process of step S1304.

  When the target area ends (YES in step S1305), the evaluation value calculation unit 206 proceeds to the next frame with frame number N = N + 1 (step S1306), and acquires a substream with row number L = 0 (step S1307). . The evaluation value calculation unit 206 determines whether there is a target area for the substream (step S1308).

  If it is the target area (YES in step S1308), the evaluation value calculation unit 206 obtains the luminance value Y of the subject as the evaluation value in the row (step S1309). Then, the evaluation value calculation unit 206 averages the luminance value (or luminance average value) of the same row number L stored in the memory 1001 and the luminance value obtained in step S1309 to obtain the luminance average value (step S1310). Then, the evaluation value calculation unit 206 stores the luminance average value and the row number L in the memory 1001 (step S1311).

  Next, the evaluation value calculation unit 206 proceeds to the next row with L = L + 1 (step S1312), and determines whether or not the target area has ended (step S1313). If the target area has not ended (NO in step S1313), the evaluation value calculation unit 206 returns to the process of step S1308 and determines whether or not the target area. If it is not the target area (NO in step S1308), the evaluation value calculation unit 206 proceeds to the process of step S1312.

  When the target area ends (YES in step S1313), the evaluation value calculation unit 206 determines whether or not the frame number N has reached the calculated number of frames (Nmax) for obtaining the luminance average value (step S1314). . If N = Nmax is not satisfied (NO in step S1314), evaluation value calculation unit 206 returns to step S1306 to perform processing for the next frame.

  If N = Nmax (YES in step S1314), evaluation value calculation section 206 outputs the result (average luminance value) Y_sub (L) obtained for the calculated number of frames (Nmax) to circuit condition section 207 ( Step S1315). Then, the evaluation value calculation unit 206 ends the evaluation value calculation process. In the process of step S1315, the calculation result Y_sub (L) for the number of frames (Nmax) for each L value is given to the circuit condition unit 207.

  In the above example, the luminance value obtained for each row is averaged, but the final luminance value may be calculated by performing predetermined weighting. Furthermore, a difference between frames may be used as a calculation result.

  Further, the calculation target area coordinates, the calculation target area number, the calculated frame number (Nmax), and the like can be set from the imaging control unit 105. In addition, a predetermined value may be written in advance from the imaging control unit 105 to the memory 1001 that stores the calculated luminance value.

  FIG. 15 is a flowchart for explaining the operation of the circuit condition setting unit 207 used in the second embodiment of the present invention.

  When shooting conditions are input from the shooting control unit 105 (step S1501), the circuit condition setting unit 207 sets shooting conditions as operation settings in the horizontal signal circuit 202 and the vertical signal circuits 203a and 230b (step S1502). Here, the circuit condition setting unit 207 performs settings for both the main stream and the substream.

  As described above, when the calculation result Y_sub (L) is input from the evaluation value calculation unit 206 (S1503), the circuit condition setting unit 207 sets the row number L = 0 (step S1504).

  Subsequently, the circuit condition setting unit 207 determines whether or not the calculation result Y_sub (L) is within a predetermined range. Here, the circuit condition setting unit 207 determines whether or not the determination lower limit luminance value Y_b <calculation result Y_sub (L) <the determination upper limit luminance value Y_u (step S1505).

  As a result of the determination, if Y_b <Y_sub <Y_u (YES in step S1505), the circuit condition setting unit 207 proceeds to the process of step S1508 described later. On the other hand, if Y_b ≧ Y_sub (L) or Y_sub (L) ≧ Y_u (NO in step S1505), the circuit condition setting unit 207 changes the imaging condition to the horizontal signal circuit 202 and the vertical signal circuits 203a and 203b. Setting is performed (step S1506).

  In the process of step S1506, operation settings of the horizontal signal circuit 202 and the vertical signal circuits 203a and 203b are performed for the main stream. For example, the circuit condition setting unit 207 sets the setting value according to the amount of deviation from the determination range defined by the determination lower limit luminance value and the determination upper limit luminance value in the horizontal signal circuit 202 when acquiring the main stream. Add or subtract from the shutter speed setting value.

  As described above, the circuit condition setting unit 207 may change the A / D conversion conditions set in the vertical signal circuits 203a and 203b in accordance with the set value corresponding to the deviation amount from the determination range. Good. Further, the circuit condition setting unit 207 connects the first switch unit 701, the second switch unit 703, the A / D conversion result of the output control unit 705, or a coefficient to be multiplied (first and first). (2 coefficient) may be changed. The operation is performed for each frame until the end of the setting process.

  Subsequently, in order to indicate that the imaging condition has been changed based on the calculation result Y_sub (L), the circuit condition setting unit 207 adds the imaging condition changed to the header by the header addition unit 1002 as header information (step S1507). . Then, the circuit condition setting unit 207 sets the row number L = L + 1 (step S1508).

  Subsequently, the circuit condition setting unit 207 determines whether or not the last row has been processed. That is, the circuit condition setting unit 207 determines whether or not the last row has been reached (step S1509). If the final line is not reached (NO in step S1509), the circuit condition setting unit 207 returns to the process in step S1505 and determines whether or not the calculation result Y_sub (L) is within a predetermined range.

  When the final line is reached (YES in step S1509), circuit condition setting unit 207 determines whether or not processing has been performed for all frames (step S1510). If the processing has not been completed for all the frames (NO in step S1510), the circuit condition setting unit 207 returns to the processing in step S1501 and inputs imaging conditions. On the other hand, when the processing is completed for all the frames (YES in step S1510), the circuit condition setting unit 207 ends the setting processing.

  Thus, in the second embodiment of the present invention, the luminance value, which is the evaluation value for control, is calculated for each row from the substream having a frame rate faster than that of the main stream, and the main value is determined according to the luminance value. Since the shooting conditions related to the stream are changed in units of lines, it is possible to cope with a change in subject luminance in the screen.

  In the second embodiment, the evaluation value is calculated in units of rows. However, the evaluation value may be calculated in units of columns or skipped pixels.

[Third Embodiment]
In the above-described first and second embodiments, the example in which the luminance value is used as the evaluation value for control has been described. On the other hand, when acquiring an image, in addition to the exposure condition, it may be better to change the shooting condition according to the area in the screen. Note that the configuration of the camera according to the third embodiment of the present invention is the same as that of the camera shown in FIG.

  FIG. 16 is a block diagram showing the configuration of the digital processing circuit 204 used in the camera according to the third embodiment of the present invention. In FIG. 16, the same components as those of the digital processing circuit 204 shown in FIG.

  A digital processing circuit 204 illustrated in FIG. 16 includes a pixel addition unit 1601, and the pixel addition unit 1601 performs vertical or horizontal pixel data addition processing according to the setting by the imaging control unit 105. By adding pixel data, the data amount of the image signal output from the external output buffer 205 can be reduced. In addition, the evaluation value calculation unit 206 illustrated in FIG. 16 detects a subject edge amount (subject edge amount) as a control evaluation value.

  FIG. 17 is a diagram illustrating the relationship between the luminance of the subject and the edge amount.

  In FIG. 17, the luminance value and the edge amount in the portion (line) indicated by the A-A ′ line of the image are shown, and it can be seen that the edge amount changes according to the change in the luminance value.

  The evaluation value calculation unit 206 obtains the difference between the luminance value of the target pixel (coordinates (x, y)) and the median value of the surrounding pixels before pixel addition based on the following equation (1) in units of rows. The maximum value of the difference is defined as the edge amount T (L).

  FIG. 18 is a flowchart for explaining the operation of the pixel addition unit 1601 in the digital processing circuit 204 shown in FIG.

  When shooting conditions are input from the shooting control unit 105 (step S1801), the circuit condition setting unit 207 sets initial conditions in the pixel addition unit 1601 according to the shooting conditions (S1802). Here, the circuit condition setting unit 207 performs setting for both the main stream and the substream.

  When the edge amount calculation result T (x, y) [hereinafter referred to as T (L)] for each row is input from the evaluation value calculation unit 206 (step S1803), the circuit condition setting unit 207 sets the row number L = 0. (Step S1804). Then, the circuit condition setting unit 207 calculates whether or not the edge amount calculation result T (L) is within a predetermined range. Here, the circuit condition setting unit 207 determines whether or not the edge amount calculation result T (L) <the determination upper limit edge amount T_u (step S1805).

  As a result of the determination, if T (L) <T_u (YES in step S1805), the circuit condition setting unit 207 proceeds to the process of step S1808 described later. On the other hand, if T (L) ≧ T_u (NO in step S1505), the circuit condition setting unit 207 performs setting to change the pixel addition condition of the pixel addition unit 1601 in the main stream (step S1806).

  For example, the circuit condition setting unit 207 performs setting so that the pixel addition operation is not performed on the pixel data of the row for a row whose edge amount is equal to or greater than the determination upper limit edge amount. Then, when the circuit condition setting unit 207 changes the addition condition, the header addition unit 1002 adds that fact to the header information (step S1807).

  Subsequently, the circuit condition setting unit 207 sets the row number L = L + 1 (step S1808), and determines whether or not the last row has been reached (step S1809). If the final line has not been reached (NO in step S1809), the circuit condition setting unit 207 returns to the process in step S1805 and determines whether or not the edge amount calculation result T (L) is within a predetermined range.

  When the final line is reached (YES in step S1809), circuit condition setting unit 207 determines whether or not processing has been performed for all frames (step S1810). If the processing has not been completed for all frames (NO in step S1810), circuit condition setting unit 207 returns to the processing in step S1801 and inputs imaging conditions. On the other hand, when the processing is completed for all frames (YES in step S1810), circuit condition setting section 207 ends the setting processing.

  As described above, in the digital processing circuit 204 shown in FIG. 16, in the edge region where the subject information changes abruptly, an operation of changing the addition condition for each row related to the main stream is performed.

  In the illustrated example, the example using the edge amount calculation result in each row has been described. However, the edge amount calculation result related to the same row of a plurality of frames may be given a predetermined weight. Further, a difference between frames may be stored as an edge amount calculation result.

  Thus, in the third embodiment of the present invention, the edge amount, which is the evaluation value for control, is obtained for each row according to the substream, and the addition condition for the main stream is performed according to the edge amount. Since the change is made in units, it is possible to appropriately cope with changes in the subject on the screen.

  Note that the target for switching between addition and non-addition and the target for edge detection may include not only the horizontal direction but also the vertical direction. Furthermore, as described in the first and second embodiments, switching may be performed according to subject brightness.

  Furthermore, in the third embodiment, the example of switching between addition and non-addition has been described. However, the number of added pixels, the weighting amount at the time of addition, the cutout position of the image signal, or the addition target pixel may be switched.

  In addition, in the above example, the edge amount is determined in units of rows, but the addition condition may be changed by determining the edge amount in units of columns or pixels. Further, although the evaluation value calculation unit 206 detects the edge amount as the evaluation value, a moving object may be detected as the evaluation value.

  FIG. 19 is a diagram for explaining detection of a moving object performed by the evaluation value calculation unit 206 shown in FIG.

  In the illustrated example, the evaluation value calculation unit 206 determines whether or not there is motion between frames (here, the Nth frame and the (N−1) th frame) in a continuous substream. When determining whether or not there is motion between the Nth frame and the (N−1) th frame, the evaluation value calculation unit 206 determines the image of the Nth frame according to the following equation (2) ( A difference Diff between the (reference image) and the (N−1) th frame image is obtained. If the difference Diff is smaller than the predetermined difference threshold Th, the evaluation value calculation unit 206 determines that there is no motion (that is, subject motion amount) in the subject. On the other hand, if the difference Diff is greater than or equal to a predetermined difference threshold, the evaluation value calculation unit 206 determines that the subject has movement.

Here, Fr _N (x, y) is a pixel value at the coordinates (x, y) of the Nth frame (reference image), and Fr _N−1 (x, y) is the coordinates of the (N−1) th frame. It is a pixel value at (x, y). And the sum total of these differences is calculated | required as the whole difference Diff.

  In the above moving object detection process, if the screen is divided into at least two areas and the above process is performed in each area, and the presence and direction of the moving object is determined for each area, the motion detection accuracy is improved. Can be improved.

[Fourth Embodiment]
Next, an example of a camera according to the fourth embodiment of the present invention will be described. The configuration of the camera according to the fourth embodiment of the present invention is the same as that of the camera shown in FIG. 1, and the configuration of the pixel unit and the image capturing method are the same as those of the first and second embodiments.

  FIG. 20 is a block diagram showing the connection between the circuit condition setting unit 207 and the external output buffer provided in the digital processing circuit 204 used in the camera according to the fourth embodiment of the present invention. In the example shown in FIG. 20, the digital processing circuit 204 omits components other than the circuit setting unit 207.

  In the illustrated example, main output external output buffers 205a-1 and 205a-2 are provided as external output buffers, and substream external output buffers 205b-1 and 205b-2 are provided. The circuit condition setting unit 207 selects the plurality of external output buffers according to the shooting conditions set by the shooting control unit 105 and outputs an image signal. That is, the circuit condition setting unit 207 switches the number of external output buffers to be used according to the data rate, and reduces the power consumption.

  In the fourth embodiment, the evaluation value calculation unit 206 calculates, for example, an edge amount T (x, y) as the control evaluation value. Then, the evaluation value calculation unit 206 sends the difference T_diff (y) of the edge amount T (x, y) between the plurality of frames to the circuit condition setting unit 207. The difference T_diff (y) is obtained using Expression (3) according to the edge amount T (x, y) in each row.

Here, T _N (x, y) is the edge amount at the coordinates (x, y) of the Nth frame (reference image), and T _N−1 (x, y) is the (N−1) th frame. The edge amount at the coordinates (x, y). The evaluation value calculation unit 206 sets the total difference T_diff (y) as a result of dividing the sum of these differences by the target pixel number N.

  FIG. 21 is a flowchart for explaining the control of the external output buffer performed by the circuit condition setting unit 207 shown in FIG.

  When shooting conditions are input from the shooting control unit 105 (step S2101), the circuit condition setting unit 207 sets control conditions for the external output buffer according to the shooting conditions (S2102). Here, the circuit condition setting unit 207 performs setting for both the main stream and the substream.

  Note that the number of external output buffers to be used is defined in the above control conditions, and the circuit condition setting unit 207 performs switching control as to which external output buffer is supplied with power according to the control conditions. .

  When the difference calculation result T_diff for each row is input from the evaluation value calculation unit 206 (step S2103), the circuit condition setting unit 207 sets the row number L = 0 (step S2104). Then, the circuit condition setting unit 207 calculates whether or not the difference calculation result T_diff is within a predetermined range. Here, the circuit condition setting unit 207 determines whether or not the difference calculation result T_diff <the determination upper limit edge amount T_u (step S2105).

  As a result of the determination, if T_diff ≧ T_u (NO in step S2105), the circuit condition setting unit 207 proceeds to the process of step S2108 described later. On the other hand, if T_diff <T_u (YES in step S1505), the circuit condition setting unit 207 performs setting for changing the control condition in the external output buffer (step S2106).

  For example, the circuit condition setting unit 207 changes the control condition of the external output buffer related to the main stream or the substream. Then, the circuit condition setting unit 207 controls the external output buffer so that pixel data is not output for a row whose control condition has been changed, assuming that there is less subject change compared to the previous frame. When the circuit condition setting unit 207 changes the control condition, the header addition unit 1002 adds that fact as header information (step S2107).

  Subsequently, the circuit condition setting unit 207 sets the row number L = L + 1 (step S2108), and determines whether or not the last row has been reached (step S2109). If the final line is not reached (NO in step S2109), the circuit condition setting unit 207 returns to the process of step S2105 and determines whether or not the difference calculation result T_diff is within a predetermined range.

  When the final line is reached (YES in step S2109), circuit condition setting unit 207 determines whether or not processing has been performed for all frames (step S2110). If the processing has not been completed for all frames (NO in step S2110), the circuit condition setting unit 207 returns to the processing in step S2101 and inputs the shooting conditions. On the other hand, when the processing is completed for all frames (YES in step S2110), circuit condition setting unit 207 ends the control processing.

  In this manner, in the fourth embodiment, output control is performed on each row as described above, and when the change in subject information is small, control is performed to reduce the data amount of output data (image signal). Do.

  As described above, in the fourth embodiment of the present invention, the control evaluation value is calculated from the substream between the frames, and the control condition of the external output buffer is changed in units of lines. Power consumption can be reduced according to changes in information.

  In the fourth embodiment, as in the third embodiment, the detection target of the edge amount may include not only the horizontal direction but also the vertical direction. Similarly to the third embodiment, a moving object may be detected, and the external output buffer may be controlled according to the detection result. In addition, the clock frequency, supply current, or voltage may be switched as a control condition.

  The present invention has been described based on the embodiments. However, the present invention is not limited to these embodiments, and various forms within the scope of the present invention are also included in the present invention. .

  For example, the function of the above embodiment may be used as a control method, and this control method may be executed by the imaging apparatus. Further, a program having the functions of the above-described embodiments may be used as a control program, and the control program may be executed by a computer included in the imaging apparatus. The control program is recorded on a computer-readable recording medium, for example.

  The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various recording media, and the computer (or CPU, MPU, etc.) of the system or apparatus reads the program. To be executed.

DESCRIPTION OF SYMBOLS 103 Image pick-up part 104 Signal processing part 105 Image pick-up control part 106 Whole control and calculating part 201 Pixel part 202 Horizontal signal circuit 203a, 203b Vertical signal circuit 204 Digital processing circuit 206 Evaluation value calculation part 207 Circuit condition setting part

Claims (8)

A pixel unit that includes a plurality of pixels and outputs an image signal corresponding to the optical image;
Driving means for driving the pixel portion;
Output means for outputting the image signal from the pixel unit by the driving means;
An adding means for inputting the image signal output to the output means and performing an addition process of the input image signal;
The image signal output to the output means is input, the edge amount of the subject is detected based on the input image signal, or the difference between frames of the input two consecutive image signals is detected. Detecting means for detecting whether or not the subject is moving based on;
Control to prevent addition processing by the addition means when the edge amount of the subject detected by the detection means is greater than or equal to a predetermined amount or when the detection means detects that the subject is moving Means,
Imaging device according to claim Rukoto to have a.   The image pickup device according to claim 1, further comprising header addition means for adding header information to the image signal output from the addition means. A first element unit including the pixel unit, the driving unit , and the output unit; and a second element unit including the addition unit, the detection unit, and the control unit.
The imaging device according to claim 1, wherein the first element portion and the second element portion are stacked on each other. A pixel unit that includes a plurality of pixels and outputs an image signal corresponding to the optical image;
Driving means for driving the pixel portion;
An external output means for outputting the image signal read from the pixel unit by the driving means to the outside of the image sensor;
Detecting means for detecting an edge amount of the subject based on the image signal;
Control means for controlling to reduce the data amount of the image signal output by the external output means when the difference between the plurality of frames in the edge amount of the subject detected by the detection means is less than a predetermined amount When,
An imaging device comprising: The external output means comprises at least two output buffers;
5. The imaging according to claim 4, wherein the control unit switches the number of the output buffers when a difference between a plurality of frames of the edge amount of the subject detected by the detection unit is less than a predetermined amount. element. A first element unit including the pixel unit and the driving unit; and a second element unit including the external output unit, the detection unit, and the control unit.
The imaging device according to claim 4, wherein the first element portion and the second element portion are stacked on each other.   The image pickup device according to claim 1, wherein the driving unit drives the pixel unit so as to acquire the image signal in units of rows. The imaging device according to any one of claims 1 to 7,
Signal processing means for performing a predetermined correction process on the image signal output from the image sensor; display means for displaying an image obtained by the image sensor;
Recording means for recording image data obtained by the signal processing means;
An imaging device comprising:

Images