JP6612856B2 - 読出しディスターバンスの低減された７トランジスタスタティックランダムアクセスメモリビットセル - Google Patents

読出しディスターバンスの低減された７トランジスタスタティックランダムアクセスメモリビットセル Download PDF

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JP6612856B2
JP6612856B2 JP2017515940A JP2017515940A JP6612856B2 JP 6612856 B2 JP6612856 B2 JP 6612856B2 JP 2017515940 A JP2017515940 A JP 2017515940A JP 2017515940 A JP2017515940 A JP 2017515940A JP 6612856 B2 JP6612856 B2 JP 6612856B2
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transistor
storage node
inverter
bit cell
write
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Japanese (ja)
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JP2017532710A (ja
JP2017532710A5 (enExample
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ソン−ウク・ジュン
ヨンフェイ・ヤン
スタンリー・スンチュル・ソン
ジョンゼ・ワン
チョー・フェイ・イェプ
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Industry Academic Cooperation Foundation of Yonsei University
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Industry Academic Cooperation Foundation of Yonsei University
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
JP2017515940A 2014-09-27 2015-09-15 読出しディスターバンスの低減された７トランジスタスタティックランダムアクセスメモリビットセル Active JP6612856B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/499,149 2014-09-27
US14/499,149 US10037795B2 (en) 2014-09-27 2014-09-27 Seven-transistor static random-access memory bitcell with reduced read disturbance
PCT/US2015/050236 WO2016048722A1 (en) 2014-09-27 2015-09-15 Seven-transistor sram bitcell with transmission gate providing reduced read disturbance

Publications (3)

Publication Number Publication Date
JP2017532710A JP2017532710A (ja) 2017-11-02
JP2017532710A5 JP2017532710A5 (enExample) 2018-10-18
JP6612856B2 true JP6612856B2 (ja) 2019-11-27

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JP2017515940A Active JP6612856B2 (ja) 2014-09-27 2015-09-15 読出しディスターバンスの低減された７トランジスタスタティックランダムアクセスメモリビットセル

Country Status (5)

Country Link
US (1) US10037795B2 (enExample)
EP (1) EP3198607B1 (enExample)
JP (1) JP6612856B2 (enExample)
CN (1) CN107077884B (enExample)
WO (1) WO2016048722A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI698871B (zh) * 2017-01-03 2020-07-11 聯華電子股份有限公司 六電晶體靜態隨機存取記憶體單元及其操作方法
KR101935664B1 (ko) 2017-04-26 2019-04-03 연세대학교 산학협력단 차등 동작이 가능한 정적 랜덤 액세스 메모리 셀
US10163493B2 (en) * 2017-05-08 2018-12-25 International Business Machines Corporation SRAM margin recovery during burn-in
US10790013B1 (en) * 2017-06-30 2020-09-29 Synopsys, Inc. Read-write architecture for low voltage SRAMs
CN112489701B (zh) * 2017-09-22 2023-12-05 联华电子股份有限公司 静态随机存取存储器组成的存储器元件
CN108231100B (zh) * 2018-03-26 2023-09-19 安徽大学 失调电压自适应数字校准型灵敏放大器
CN109684665B (zh) * 2018-11-21 2024-02-02 浙江大学城市学院 基于FinFET的三值SRAM单元电路及控制方法
TWI704575B (zh) * 2019-10-24 2020-09-11 修平學校財團法人修平科技大學 具高存取速度之７ｔ靜態隨機存取記憶體
US11462282B2 (en) * 2020-04-01 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor memory structure
TWI723944B (zh) * 2020-09-21 2021-04-01 崛智科技有限公司 記憶體裝置
EP3979248A1 (en) * 2020-09-30 2022-04-06 Imec VZW A memory macro
CN115662483B (zh) * 2022-12-26 2023-03-10 华中科技大学 Sram存储单元阵列、读写方法、控制器及系统
CN116204490B (zh) * 2023-03-03 2025-10-14 安徽大学 一种基于低电压技术的7t存算电路、乘累加运算电路

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW299448B (enExample) * 1995-07-20 1997-03-01 Matsushita Electric Industrial Co Ltd
JPH1196767A (ja) * 1997-09-26 1999-04-09 Mitsubishi Electric Corp 半導体記憶装置
US6853578B1 (en) * 2002-03-18 2005-02-08 Piconetics, Inc. Pulse driven single bit line SRAM cell
GB2417588B (en) * 2004-08-23 2008-06-04 Seiko Epson Corp Memory cell
FR2888423B1 (fr) * 2005-07-05 2008-04-11 Iroc Technologies Sa Cellule de memorisation durcie
US7420836B1 (en) 2007-02-13 2008-09-02 International Business Machines Corporation Single-ended memory cell with improved read stability and memory using the cell
US7920409B1 (en) 2007-06-05 2011-04-05 Arizona Board Of Regents For And On Behalf Of Arizona State University SRAM cell with intrinsically high stability and low leakage
US7684232B1 (en) * 2007-09-11 2010-03-23 Xilinx, Inc. Memory cell for storing a data bit value despite atomic radiation
JP5083889B2 (ja) * 2007-12-19 2012-11-28 独立行政法人産業技術総合研究所 Ｓｒａｍセル回路およびその駆動方法
US7706174B2 (en) * 2008-05-15 2010-04-27 The University Of Bristol Static random access memory
US8441829B2 (en) 2009-06-12 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Stable SRAM cell
JP5382886B2 (ja) * 2009-07-29 2014-01-08 独立行政法人産業技術総合研究所 Ｓｒａｍセル
WO2011017843A1 (zh) * 2009-08-13 2011-02-17 东南大学 一种高密度、高鲁棒性的亚阈值存储单元电路
US8345469B2 (en) * 2010-09-16 2013-01-01 Freescale Semiconductor, Inc. Static random access memory (SRAM) having bit cells accessible by separate read and write paths
US8498143B2 (en) 2011-03-04 2013-07-30 Texas Instruments Incorporated Solid-state memory cell with improved read stability
TWI463493B (zh) * 2011-03-08 2014-12-01 Univ Nat Chiao Tung 靜態隨機存取記憶體胞元及其操作方法
TWI476768B (zh) 2011-10-21 2015-03-11 Univ Nat Chiao Tung 獨立閘極控制靜態隨機存取記憶體
CN102903386A (zh) * 2012-09-19 2013-01-30 上海集成电路研发中心有限公司 一种静态随机存储单元

Also Published As

Publication number Publication date
EP3198607B1 (en) 2018-12-26
CN107077884A (zh) 2017-08-18
US20160093365A1 (en) 2016-03-31
JP2017532710A (ja) 2017-11-02
WO2016048722A1 (en) 2016-03-31
CN107077884B (zh) 2021-03-30
EP3198607A1 (en) 2017-08-02
US10037795B2 (en) 2018-07-31

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