JP6612565B2 - Display panel, display device, and display panel manufacturing method - Google Patents

Description

  Embodiments described herein relate generally to a display panel, a display device, and a method for manufacturing the display panel.

  Liquid crystal display panels, organic EL panels, and the like are known as high-definition and small display panels. These existing display panels have problems such as response speed and lifetime due to the material used. By using a semiconductor light emitting element (Light-Emitting Diode, LED), a high-definition display with a high-speed response and a long life can be realized. However, in the structure in which individual package products incorporating semiconductor light emitting elements are mounted for each pixel, the number of manufacturing steps is large, and it is difficult to increase the definition of the display.

JP 2000-114203 A

  Embodiments provide a display panel, a display device, and a method for manufacturing the display panel that can be implemented with a small number of man-hours.

Display panel according to the embodiment includes a plurality of first semiconductor layer including a first light-emitting layer, respectively, on the side of one surface of the plurality of first semiconductor layer, each of said plurality of first semiconductor layer a first anode terminal and a first cathode terminal connected to, on the side of one surface of the first semiconductor layer, said plurality of first semiconductor layer, the first anode terminal and said first cathode terminal a first resin layer that supports integrally, on the side of the other surface of said first semiconductor layer, and a first phosphor layer provided over at least a portion of said plurality of first semiconductor layer A first display block including a plurality of second semiconductor layers each including a second light-emitting layer; and a plurality of second semiconductor layers on one surface side of each of the plurality of second semiconductor layers. Connected second anode terminal and second cathode terminal A second resin layer that integrally supports the plurality of second semiconductor layers, the second anode terminal, and the second cathode terminal on one surface side of the second semiconductor layer; A second display block including a second phosphor layer provided to cover at least a part of the plurality of second semiconductor layers on the other surface side of the semiconductor layer . Said plurality of first semiconductor layer, n-number in the first direction (n is a natural number) are arranged, m pieces in a second direction crossing the first direction (m is an integer of 2 or more) are arranged. The plurality of second semiconductor layers are arranged p (p is a natural number) in the first direction and q (q is an integer of 2 or more) in the second direction. The first display block and the second display block are disposed adjacent to each other. The length of the first display block in the first direction is different from the length of the second display block in the first direction.

FIG. 1 is a plan view illustrating the appearance of a display panel according to the first embodiment. FIG. 2A is an enlarged plan view illustrating the appearance of the pixels of the display panel of the first embodiment. FIG. 2B is an enlarged bottom view illustrating the appearance of the pixels of the display panel of this embodiment. FIG. 3A is a cross-sectional view taken along line AA in FIG. FIG. 3B is a cross-sectional view taken along the line BB in FIG. FIG. 3C is a bottom view of the semiconductor layer of the light emitting element. FIG. 5 is an exploded view illustrating the method for manufacturing the display panel of the first embodiment. It is a block diagram which illustrates a part of circuit of the display panel of 1st Embodiment. It is a top view which illustrates the appearance of the display panel of a 2nd embodiment. FIG. 10 is an exploded view illustrating a method for manufacturing a display panel of a second embodiment. It is a flowchart for demonstrating the manufacturing method of the display panel of 2nd Embodiment. FIG. 9A and FIG. 9B are conceptual diagrams for explaining correction of variation in characteristics of light emitting elements. It is a flowchart for demonstrating the manufacturing method of the display panel which concerns on the modification of 2nd Embodiment. It is a top view which illustrates the appearance of some display panels of a 3rd embodiment. It is a conceptual diagram which illustrates the manufacturing method of the display panel of 3rd Embodiment. It is a block which illustrates the display apparatus of 4th Embodiment. It is a block diagram which illustrates the display apparatus of the modification of 4th Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
In the present specification and drawings, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
FIG. 1 is a plan view illustrating the appearance of the display panel of this embodiment.
2A and 2B are enlarged plan views illustrating the appearance of the pixels of the display panel of this embodiment.
FIG. 3A is a cross-sectional view taken along line AA in FIG. FIG. 3B is a cross-sectional view taken along the line BB in FIG. FIG. 3C is a bottom view of the semiconductor layer of the light emitting element constituting the pixel.
As shown in FIGS. 1 and 2, the display panel 1 of this embodiment includes a plurality of pixels 10. Each of the plurality of pixels 10 has a substantially rectangular shape. Each of the plurality of pixels 10 is arranged in a grid, for example. A plurality of the pixels 10 are arranged along the X-axis direction, and m pixels are arranged along the Y-axis orthogonal to the X-axis. That is, the display panel 1 has n × m pixels. When the dimension of the side along the X-axis direction of the pixel 10 is a and the dimension of the side along the Y-axis direction is b, the display panel 1 has a horizontal (X-axis direction) dimension of n × a and a vertical (Y-axis direction). ) Is a rectangle having a size of m × b.

  In FIG. 1, the wafer 2 is shown together by a one-dot chain line. The wafer 2 includes the display panel 1 in the manufacturing process. As will be described later, the display panel 1 is cut out from the wafer 2 through a dicing process. In this example, one display panel 1 is cut out from one wafer 2. For example, one display panel 1 has the largest dimension that can be cut from one wafer 2. In this case, the length C of the diagonal line of the display panel 1 is set substantially equal to the diameter of the wafer 2.

  The dimensions in the X-axis direction and the Y-axis direction of the display panel 1 are determined by the number of pixels and the panel size required by the display device on which the display panel 1 is mounted. Here, the number of pixels is the number n × m of pixels included in the display panel 1 and is, for example, 1280 × 800 (WXGA, Wide eXtended Graphics Array), 1920 × 1080 (full HD, High Definition), etc. It is expressed in The panel size is the diagonal length of the display panel 1 and is expressed as 8 inches, for example. When the number of pixels and the panel size are smaller, as shown by the broken line in FIG. 1, one wafer 2 may have a plurality (six in this example) of display panels 1. . When a plurality of display panels 1 are taken from one wafer 2, the yield can be improved.

As shown in FIG. 2A, the pixel 10 includes a plurality of light emitting elements 12. In this example, one pixel 10 includes four light emitting elements 12. Phosphor layers 41 a and 41 b are provided above three of the four light emitting elements 12. The phosphor layers 41 a and 41 b are not provided above the remaining light emitting elements 12. The four light emitting elements 12 are all blue light emitting diodes having substantially the same wavelength and the same light output. The phosphor layer 41a includes a fluorescent material that emits red light when excited by blue light. The fluorescent material that emits red light is an inorganic material, such as Sr ₂ Si ₇ Al ₃ ON ₁₃ : Eu. The phosphor layer 41b includes a fluorescent material that emits green light when excited by blue light. The fluorescent material that emits green light is an inorganic material, such as Sr ₃ Si ₁₃ Al ₃ O ₂ N ₂₁ : Eu.

  The red light emitting element 12a includes the light emitting element 12 and a phosphor layer 41a that emits red light thereon. The green light emitting elements 12b and 12c include the light emitting element 12 and a phosphor layer 41b that emits green light on the light emitting element 12. The blue light emitting element 12 d includes the light emitting element 12.

  In this example, the red light emitting element 12a, the green light emitting elements 12b and 12c, and the blue light emitting element 12d are arranged as follows. The blue light emitting element 12d is disposed adjacent to the green light emitting element 12c in the positive X-axis direction. The red light emitting element 12a is disposed adjacent to the green light emitting element 12c in the positive Y-axis direction. The green light emitting element 12b is arranged adjacent to the red light emitting element 12a in the positive X-axis direction and is arranged adjacent to the blue light emitting element 12d in the Y-axis positive direction. In other words, the red light emitting elements 12a, the green light emitting elements 12b and 12c, and the blue light emitting elements 12d are arranged in a square shape of 2 rows × 2 columns. In the display panel 1, such pixels 10 are arranged in a grid in the X-axis direction and the Y-axis direction.

  The arrangement of the light emitting elements of each color in the pixel 10 is not limited to an array of 2 rows × 2 columns. For example, one red light emitting element, one green light emitting element, and one blue light emitting element are arranged in one column along the Y-axis direction. A stripe structure or the like may be used. Further, the pixels are not limited to being arranged in a grid pattern, and may be arranged in a staggered pattern, for example.

  As shown in FIG. 2B, each of the red light emitting element 12a, the green light emitting elements 12b and 12c, and the blue light emitting element 12d has two terminals. The two terminals are cathode terminals 33a to 33d and anode terminals 34a to 34d, respectively. The cathode terminals 33 a to 33 d are electrically connected to the n-side electrode 25 of the semiconductor layer 24 inside each light emitting element 12. The anode terminals 34 a to 34 d are electrically connected to the p-side electrode 26 of the semiconductor layer 24 inside each light emitting element 12. As in this example, the cathode electrodes 33a to 33d may be formed as a cathode mark by making the shape without one corner. In the display panel 1, since the terminals of the light emitting elements 12a to 12d are exposed to the outside, the light emitting elements 12a to 12d can be electrically connected to an external circuit, and each light emitting element is driven independently. be able to.

  The display panel 1 is a multi-chip device including a plurality of light emitting elements (chips) 12 in a package structure formed at a wafer level. The plurality of light emitting elements 12 are electrically insulated from each other. The plurality of light emitting elements 12 all have the same structure. Below, the structure of each light emitting element 12 is demonstrated. As a coordinate axis, a Z axis orthogonal to the X axis and the Y axis is used in addition to the above X axis and Y axis.

  As shown in FIGS. 3A and 3B, the light emitting element 12 includes a semiconductor layer 24, a p-side electrode 26, and an n-side electrode 25.

  The semiconductor layer 24 has a first main surface 24a and a second main surface 24b. The first main surface 24a is a surface on the Z-axis positive direction side of the semiconductor layer 24, and the second main surface 24b is a surface on the Z-axis negative direction side. An electrode and a wiring part are provided on the second main surface 24b side. The light emitted from the light emitting element 12 is mainly emitted from the first main surface 24a to the outside.

The semiconductor layer 24 includes a first semiconductor layer 21 and a second semiconductor layer 22. The first semiconductor layer 21 and the second semiconductor layer 22 are made of a material containing, for example, gallium nitride (GaN). First semiconductor layer 21 includes, for example, a base buffer layer and an n-type layer. The n-type layer functions as a lateral path for current. Here, the horizontal direction is a direction along a plane including the X axis and the Y axis. Second semiconductor layer 22 includes, for example, a p-type layer, a layer containing impurities for forming a p-type semiconductor, and the like. A light emitting layer (active layer) 23 is provided between the first semiconductor layer 21 and the second semiconductor layer 22, and the light emitting layer (active layer) 23 includes one or a plurality of quantum well structures.
The material of the semiconductor layer is not limited to the specific examples described above, and various GaN-based nitride semiconductors, other III-V group compound semiconductors, and other various compound semiconductors can be used.

  The side of the second major surface 24b of the semiconductor layer 24 is processed into an uneven shape. The convex portion formed on the second main surface 24 b side includes the light emitting layer 23. A p-side electrode 26 is provided on the surface of the second semiconductor layer 22 that is the surface of the convex portion. That is, the p-side electrode 26 is provided on the region having the light emitting layer 23.

  On the second main surface 24 b side of the semiconductor layer 24, a region where the light emitting layer 23 and the second semiconductor layer 22 are not provided is provided around the convex portion. An n-side electrode 25 is provided on the surface of the first semiconductor layer 21 in that region. That is, the n-side electrode 25 is provided on a region not including the light emitting layer 23.

  As shown in FIG. 3C, the n-side electrode 25 continuously surrounds the p-side electrode 26. The p-side electrode 26 and the n-side electrode 25 are not limited to this planar layout, and other layouts are possible.

  On the second main surface 24 b side, the area of the second semiconductor layer 22 including the light emitting layer 23 is larger than the area of the first semiconductor layer 21 not including the light emitting layer 23. The area of the p-side electrode 26 is wider than the area of the n-side electrode 25. Therefore, a wide light emitting region can be obtained.

  An insulating film 27 is provided on the side surface of the second semiconductor layer 22 including the light emitting layer 23. The insulating film 27 is also provided on the second main surface 24b side where the p-side electrode 26 and the n-side electrode 25 are not provided. The insulating film 27 is an inorganic insulating film such as a silicon oxide film or a silicon nitride film.

  The side of the second main surface 24 b on which the insulating film 27, the p-side electrode 26 and the n-side electrode 25 are provided is covered with an insulating layer 28. The first major surface 24 a is not covered with the insulating layer 28. The insulating layer 28 is filled between adjacent light emitting elements 12 and 12 separated from each other, and covers the side surfaces of the light emitting elements 12 and 12. A side surface of the semiconductor layer 24 continuing from the first main surface 24 a is covered with an insulating layer 28. The insulating layer 28 that covers the side surfaces of the light emitting elements 12, 12 constitutes the side surface of the display panel 1 together with a resin layer 29 that covers the side surfaces of the wiring portions described later.

  The insulating layer 28 is, for example, an insulating resin such as polyimide having excellent patterning characteristics for fine openings. Alternatively, an insulating inorganic material such as silicon oxide or silicon nitride may be used as the insulating layer 28.

  A first via 28 a reaching the p-side electrode 26 and a second via 28 b reaching the n-side electrode 25 are formed in the insulating layer 28. The first insulating layer 28 has a wiring surface 28c on the side opposite to the first main surface 24a.

  On the wiring surface 28c, the p-side wiring layer 32 and the n-side wiring layer 31 are provided apart from each other. One p-side wiring layer 32 and one n-side wiring layer 31 are provided for each light emitting element 12.

  The p-side wiring layer 32 is also provided in the first via 28a. The p-side wiring layer 32 is electrically connected to the p-side electrode 26 through a plurality of first vias 28a.

  The n-side wiring layer 31 is also provided in the second via 28b. The n-side wiring layer 31 is electrically connected to the n-side electrode 25 through, for example, one second via 28b.

  A p-side metal pillar 34 is provided on the surface opposite to the light emitting element 12 in the p-side wiring layer 32. The p-side metal pillar 34 is thicker than the p-side wiring layer 32. The p-side wiring layer 32 and the p-side metal pillar 34 constitute an anode terminal 34a.

  An n-side metal pillar 33 is provided on the surface opposite to the light emitting element 12 in the n-side wiring layer 31. The n-side metal pillar 33 is thicker than the n-side wiring layer 31. The n-side wiring layer 31 and the n-side metal pillar 33 constitute a cathode terminal 33a.

  Further, a resin layer 29 is provided as another insulating layer on the wiring surface 28 c of the insulating layer 28. The resin layer 29 covers the periphery of the anode terminal 34a and the periphery of the cathode terminal 33a.

  The surface other than the connection surface with the p-side metal pillar 34 in the p-side wiring layer 32 and the surface other than the connection surface with the n-side metal pillar 33 in the n-side wiring layer 31 are covered with the resin layer 29. The resin layer 29 is provided between the p-side metal pillar 34 and the n-side metal pillar 33 and covers the side surface of the p-side metal pillar 34 and the side surface of the n-side metal pillar 33. The resin layer 29 is provided between the p-side metal pillar 34 and the n-side metal pillar 33.

  The surface of the p-side metal pillar 34 opposite to the p-side wiring layer 32 is exposed without being covered with the resin layer 29 and functions as an anode terminal 34a bonded to the mounting substrate. The surface of the n-side metal pillar 33 opposite to the n-side wiring layer 31 is exposed without being covered with the resin layer 29, and functions as a cathode terminal 33a bonded to the mounting board.

  The p-side metal pillar 34, the n-side metal pillar 33, and the resin layer 29 that reinforces these function as a support for the light emitting element 12 and also as a support for the display panel 1. Therefore, even if the growth substrate used for forming the semiconductor layer 24 is removed, the light emitting element 12 is stably supported by the support including the p-side metal pillar 34, the n-side metal pillar 33, and the resin layer 29. The mechanical strength of the display panel 1 can be increased.

  Further, in the case of the display panel 1 mounted on the mounting substrate, the stress applied to the semiconductor layer 24 can be relaxed by the p-side metal pillar 34, the n-side metal pillar 33 and the resin layer 29 absorbing.

  As a material of the p-side wiring layer 32, the n-side wiring layer 31, the p-side metal pillar 34, and the n-side metal pillar 33, copper, gold, nickel, silver, or the like can be used. Among these, when copper is used, good thermal conductivity, high migration resistance, and excellent adhesion with an insulating material can be obtained.

  It is desirable to use a resin layer 29 having the same or similar thermal expansion coefficient as that of the mounting substrate. As such a resin layer, an epoxy resin, a silicone resin, a fluororesin, etc. can be mentioned as an example, for example.

  Further, the resin layer 29 may contain, for example, carbon black so as to impart light shielding properties to the light emitted from the light emitting layer 23. Further, the resin layer 29 may contain a powder having reflectivity with respect to light emitted from the light emitting layer 23.

  The first semiconductor layer 21 is electrically connected to the n-side metal pillar 33 via the n-side electrode 25 and the n-side wiring layer 31. The second semiconductor layer 22 is electrically connected to the p-side metal pillar 34 via the p-side electrode 26 and the p-side wiring layer 32.

  A part of the n-side wiring layer 31 overlaps the insulating layer 28 on the light emitting region including the light emitting layer 23. The area of the n-side wiring layer 31 is larger than the area of the n-side electrode 25. Further, the area of the n-side wiring layer 31 extending on the insulating layer 28 is larger than the area where the n-side wiring layer 31 is connected to the n-side electrode 25 through the second via 28b.

  Since the light emitting element 12 has the light emitting layer 23 formed over a region wider than the n-side electrode 25, a high light output can be obtained. Further, the n-side electrode provided in a region narrower than the light emitting region without including the light emitting layer 23 is connected to the n side wiring layer 31 having a larger area, thereby realizing a low resistance wiring structure. be able to.

  The area where the p-side wiring layer 32 is connected to the p-side electrode 26 through the plurality of first vias 28a is larger than the area where the n-side wiring layer 31 is connected to the n-side electrode 25 through the second via 28b. Therefore, the current distribution to the light emitting layer 23 is improved, and the heat dissipation of the heat generated in the light emitting layer 23 can be improved.

  As shown in FIG. 3A, the red light-emitting element 12a and the green light-emitting element 12b arranged along the X-axis direction have a phosphor layer 41a and a fluorescent light on the first main surface 24a of each semiconductor layer 24. A body layer 41b is provided. The phosphor layers 41a and 41b are, for example, a fluorescent resin containing phosphor particles. Alternatively, the phosphor layers 41a and 41b may be phosphor sheets obtained by thinly stretching a resin sheet containing phosphor particles.

  The phosphor layer 41a includes phosphor particles that are excited by blue light emitted from the light emitting element 12 and emit red light. The phosphor layer 41b includes phosphor particles that are excited by blue light emitted from the light emitting element 12 and emit green light.

  As shown in FIG. 3B, a phosphor layer 41b is provided on the first main surface 24a of the semiconductor layer 24 of the green light emitting element 12c. The phosphor layer is not provided on the first main surface 24a of the semiconductor layer 24 of the blue light emitting element 12d, but as shown by the alternate long and short dash line in FIG. 3B, the other light emitting elements 12a, 12b, 12c. A transparent resin having the same shape may be provided.

  By driving the above-described light emitting elements 12 that emit red, green, and blue with constant current sources having independent current values, the respective light emitting elements emit light in red, green, and blue with luminance according to the current values. To do. Each pixel 10 outputs mixed light by the light emitted from the respective light emitting elements. This mixed light is toned according to the ratio of the luminance of red, green, and blue. That is, the color of the light emitted from the pixel 10 can be set by setting the currents flowing through the light emitting elements included in the pixel 10. An image can be displayed on the display panel 1 by performing gradation control for controlling the brightness from turning off of mixed light to turning on for each pixel 10.

A method for manufacturing the display panel of this embodiment will be described.
In the display panel 1, n × m pixels 10 are formed in the state of the wafer 2. The pixel forming process includes the following processes, for example.

  The light emitting element 12 including the light emitting layer 23 is formed on a growth substrate to be removed later. A first semiconductor layer 21 is formed on the main surface of the growth substrate, and a second semiconductor layer 22 is formed on the first semiconductor layer 21. For example, the first semiconductor layer 21 and the second semiconductor layer 22 made of a gallium nitride-based material can be epitaxially grown on a sapphire substrate or a silicon substrate by MOCVD (metal organic chemical vapor deposition).

  After the semiconductor layer 24 is formed on the substrate, the second semiconductor layer 22 is selectively removed by, for example, RIE (Reactive Ion Etching) using a resist or the like, so that the first semiconductor layer 21 is selectively exposed. The region where the first semiconductor layer 21 is exposed does not include the light emitting layer 23.

  A p-side electrode 26 is formed on the surface of the second semiconductor layer 22, and an n-side electrode 25 is formed on the surface of the first semiconductor layer 21. The p-side electrode 26 and the n-side electrode 25 are formed by, for example, a sputtering method or a vapor deposition method. Either the p-side electrode 26 or the n-side electrode 25 may be formed first, or may be formed of the same material at the same time.

  An insulating film 27 is formed on the second main surface 24b side. The insulating film 27 may be formed before the p-side electrode 26 and the n-side electrode 25 are formed.

  Using the resist mask, a groove reaching the substrate is formed in the semiconductor layer 24 by, for example, RIE, and the semiconductor layer 24 is separated into a plurality by the groove. The semiconductor layer 24 has a planar layout arranged in a lattice pattern on a wafer-like substrate.

  All exposed portions on the substrate are covered with an insulating film 27. Thereafter, the first via 28 a and the second via 28 b are formed in the insulating film 27 by etching using a resist mask. The first via 28 a reaches the p-side electrode 26. The second via 28 b reaches the n-side electrode 25.

  A metal film functioning as a seed metal for plating is formed on the wiring surface 28c, which is the upper surface of the insulating layer 28, the inner wall of the first via 28a, and the inner wall of the second via 28b. Then, a resist is selectively formed on the metal film, and Cu electrolytic plating using the metal film as a current path is performed. By this plating, the p-side wiring layer 32 and the n-side wiring layer 31 are selectively formed on the wiring surface 28c. The p-side wiring layer 32 and the n-side wiring layer 32 are made of, for example, a copper material that is simultaneously formed by a plating method. The seed metal may be formed on the electrodes when the p-side electrode 26 and the n-side electrode 25 are formed.

  The p-side wiring layer 32 is also formed in the first via 28a and is electrically connected to the p-side electrode 26 through the metal film that is a seed metal. The n-side wiring layer 31 is also formed in the second via 28b and is electrically connected to the n-side electrode 25 through the metal film that is a seed metal.

  Using the resist as a mask, Cu electroplating is performed using the remaining metal film as a current path. By this plating, a p-side metal pillar 34 and an n-side metal pillar 33 are formed. The p-side metal pillar 34 is formed on the p-side wiring layer 32, and the n-side metal pillar 33 is formed on the n-side wiring layer 31.

  After the p-side metal pillar 34 and the n-side metal pillar 33 are formed, the exposed portion of the metal film used as the seed metal is removed. Therefore, the metal film connected between the p-side wiring layer 32 and the n-side wiring layer 31 is divided.

  Next, the resin layer 29 is formed. When the growth substrate is a sapphire substrate, for example, with a support including the p-side metal pillar 34, the n-side metal pillar 33 and the resin layer 29 supported by the chip, the laser lift-off method is used. Remove. When the growth substrate is a silicon substrate, the growth substrate is removed by an etching method.

  Since the semiconductor layer 24 is supported by a supporter thicker than this, the wafer state can be maintained even if the growth substrate disappears. Further, the resin constituting the resin layer 29 and the metal constituting the p-side metal pillar 34 and the n-side metal pillar 33 are flexible materials compared to the semiconductor layer 24 made of a GaN-based material. Therefore, even if a large internal stress generated in the epitaxial growth for forming the semiconductor layer 24 on the growth substrate is released at a time when the growth substrate is peeled off, the light emitting element 12 can be prevented from being destroyed.

  After removing the growth substrate, the first main surface 24a is cleaned, and a frost process is performed to form irregularities as necessary. The light extraction efficiency can be improved by forming minute irregularities on the first main surface 24a.

  The electrical characteristics and optical characteristics of the light-emitting element 12 are measured in the state of the wafer, and the quality is determined. Although the number of defects is preferably zero, there may be no problem in the performance of the display panel 1 even when several non-lighting defects of the single light emitting element 12 occur with respect to the total number of pixels. Therefore, the display panels 1 having a predetermined defect rate or less may be selected.

  After measuring electrical and optical characteristics and determining good or bad, red and green phosphor layers 41a and 41b are formed on the first major surface 24a of the semiconductor layer 24 of the four light emitting elements 12. To do.

  The display panel 1 is cut out from the wafer 2 by a dicing process. Based on the distribution of the characteristics of the light emitting elements on the wafer 2 and the panel size, the position for dicing is determined in advance. When the panel size of the display panel 1 is sufficiently smaller than the diameter of the wafer 2, the dicing position may be set every time dicing is performed according to the distribution of characteristics of the light emitting elements on the wafer 2.

  As shown in FIG. 4, the display panel 1 cut out from the wafer 2 is disposed with the surface opposite to the side on which the phosphor layers 41 a and 41 b are formed facing the mounting surface of the mounting substrate 51. The On this surface of the display panel 1, anode terminals 34a to 34d and cathode terminals 33a to 33d of the light emitting element 12 are formed, and the connection surfaces of the respective terminals are exposed. The connection surface of the anode terminals 34 a to 34 d and the cathode terminals 33 a to 33 d of the light emitting element 12 is connected to the wiring 52 formed on the mounting substrate 51. For connecting the anode terminals 34a to 34d and the cathode terminals 33a to 33d and the wiring 52, for example, a solder connection technique using reflow can be used.

  On the mounting substrate 51, a driving circuit for driving the display panel 1, a control circuit, and the like may be mounted in advance. The drive circuit, the control circuit, and the like may be mounted on the same surface as the display panel 1 of the mounting substrate 51, or may be mounted on the surface opposite to the display panel 1. The mounting substrate 51 is, for example, a flexible printed circuit board having a resinous substrate such as polyimide.

  Thus, in the display panel 1 of this embodiment, since the display panel 1 can be directly cut out from the wafer 2 by dicing, only one mounting stroke on the mounting substrate 51 is required, and individual light emitting elements are mounted individually. Compared to this assembly process, the assembly process of the display panel 1 can be reduced.

The operation of the display panel 1 of the present embodiment will be described.
FIG. 5 is a block diagram illustrating a part of the circuit of the display panel of this embodiment.
As described above, the display panel 1 is placed on the mounting substrate 51 in which the wiring 52 is drawn in advance by etching or the like, and the anode terminals 34 a to 34 d and the cathode terminals 33 a to 33 d of the light emitting element 12 are electrically connected to the wiring 52. It is connected to the.

  As shown in FIG. 5, for example, a column driving circuit 62 and a row driving circuit 64 are mounted on the mounting substrate 51 and are electrically connected to the wiring 52 (52a, 52b, 52c, 52d). The column drive circuit 62 includes constant current circuits 63a and 63b. The current inflow sides of the constant current circuits 63a and 63b are connected to a power supply circuit (not shown). The current outflow sides of the constant current circuits 63a and 63b are connected to the wirings 52a and 52b, respectively. The constant current circuits 63a and 63b are set with constant current values by a control circuit (not shown). Row drive circuit 64 includes row selection switch circuits 65a and 65b. The current selection sides of the row selection switch circuits 65a and 65b are connected to each other and connected to the ground. Current inflow sides of the row selection switch circuits 65a and 65b are connected to wirings 52c and 52d, respectively.

  The anode terminal 34a of the red light emitting element 12a is connected to the current outflow side of the constant current circuit 63a through the wiring 52a. The cathode terminal 33a is connected to the current inflow side of the row selection switch circuit 65a through the wiring 52c.

  The anode terminal 34b of the green light emitting element 12b is connected to the current outflow side of the constant current circuit 63b through the wiring 52b. The cathode terminal 33b is connected to the current inflow side of the row selection switch circuit 65a through the wiring 52c.

  The anode terminal 34c of the green light emitting element 12c is connected to the current outflow side of the constant current circuit 63a through the wiring 52a. The cathode terminal 33c is connected to the current inflow side of the row selection switch circuit 65b via the wiring 52d.

  The anode terminal 34d of the blue light emitting element 12d is connected to the current outflow side of the constant current circuit 63b through the wiring 52b. The cathode terminal 33d is connected to the current inflow side of the row selection switch circuit 65b via the wiring 52d.

  The current values of the constant current circuits 63a and 63b are set for each light emitting element. The current value is set by a control circuit (not shown) or the like. The constant current circuits 63a and 63b have a switch circuit connected in series to the constant current, and allow current to flow or cut off by turning on or off the column selection signal supplied from the control circuit.

  The row selection switch circuits 65a and 65b close or open the switches by turning on or off a row selection signal supplied from the control circuit.

  The constant current circuits 63a and 63b and the row selection switch circuits 65a and 65b operate as follows, for example. That is, the constant current circuit 63a is turned on at the current value Ia, and the row selection switch circuit 65a is turned on. The constant current circuit 63b and the row selection switch circuit 65b are off. In this case, since a current path from the constant current circuit 63a to the row selection switch circuit 65a is formed, a current having a current value Ia flows through the red light emitting element 12a. The red light emitting element 12a lights up with a luminance corresponding to the current value Ia.

  Next, the constant current circuit 63a is turned off, and the constant current circuit 63b is turned on at the current value Ib. The row selection switch circuit 65a is on. The row selection switch circuit 65b is off. In this case, since a current path from the constant current circuit 63b to the row selection switch circuit 65a is formed, a current having a current value Ib flows through the green light emitting element 12b. The green light emitting element 12b lights up with a luminance corresponding to the current value Ib.

  Next, the constant current circuit 63b is turned off, and the constant current circuit 63a is turned on at the current value Ic. The row selection switch circuit 65a is turned off and the row selection switch circuit 65b is turned on. In this case, since a current path from the constant current circuit 63a to the row selection switch circuit 65b is formed, a current having a current value Ic flows through the green light emitting element 12c. The green light emitting element 12c is lit with a luminance corresponding to the current value Ic.

  Next, the constant current circuit 63a is turned off, and the constant current circuit 63b is turned on at the current value Id. The row selection switch circuit 65a is off and the row selection switch circuit 65b is on. In this case, since a current path from the constant current circuit 63b to the row selection switch circuit 65b is formed, a current having a current value Id flows through the blue light emitting element 12d. The blue light emitting element 12d is lit with a luminance corresponding to the current value Id.

  In this way, each of the light emitting elements 12a to 12d is lit at a luminance corresponding to the current value by passing a current sequentially, thereby setting the emission color of the pixel 10 and determining the gradation. In this way, an image or a moving image is displayed by the large number of pixels 10 in which the emission color and gradation are set.

The operation and effect of the display panel 1 of the present embodiment will be described.
A display capable of high-definition display requires a very large number of pixels, and the number of light-emitting elements constituting the pixels is enormous. For example, in a 4K television, the number of pixels is required to be 8,294,400 pixels of horizontal 3840 pixels × vertical 2160 pixels. More than 33 million light emitting elements, which are four times the number, are required. In a display panel used for a display of a tablet computer, for example, it is necessary to mount WXGA of 1280 × 800 pixels on a 7-inch panel, and even in this case, it is necessary to mount 4 million or more light-emitting elements. When such a large number of light-emitting elements are realized by individual components and mounted on a board, the mounting machine requires a mounting stroke of 33 million times or 4 million times or more, which is not realistic. The mounting area of individual components mounted on a quality-guaranteed package is about 1 [mm] × 1 [mm] even if it is the smallest, and when this is applied to the number of pixels of a 4K television, Even if it is simply arranged without considering the mounting clearance between components, it becomes a huge display of horizontal 3.8 [m] x vertical 2.2 [m], which is not realistic unless it is for signage or the like.

  The display panel 1 according to this embodiment includes a multichip in which the light emitting elements 12 constituting the pixels 10 are integrally supported by the resin layer 29 together with the p-side metal pillar (anode terminal) 34 and the n-side metal pillar (cathode terminal) 33. It has a package structure. Therefore, the quality of the display panel 1 is guaranteed as one semiconductor device, and the characteristics are guaranteed. Therefore, the display can be easily increased in size.

For example, when the display panel 1 is formed on an 8-inch wafer 2, the sizes of the pixels 10 and the light emitting elements 12 are as follows. When the size of the pixel 10 is a [μm] × a [μm], the length A in the horizontal direction (along the X-axis direction) of the display panel 1 is 3840 × a [μm] and vertical (along the Y-axis direction). ) Direction length B is 2160 × a [μm]. If the length of the A × B diagonal line is equal to the wafer diameter, (3840 × a) ² + (2160 × a) ² = (25.4 × 1000 × 8) ² , where a is about 46 [μm]. It becomes. When the pixel 10 is constituted by four light emitting elements 12, the size of the light emitting elements 12 is 23 [μm] × 23 [μm]. This dimension is a value that can be sufficiently realized by the capability of the current manufacturing process. That is, the display panel 1 having a panel size of 7 inches to 8 inches and 4K television image quality can be configured by one semiconductor device. Note that the size of the display panel 1 at this time is 177 [mm] × 99 [mm] in length, and by adding an optical system, a large screen of 50 inches or 60 inches is possible.

  Thus, in the display panel 1 of this embodiment, a display used for one display device can be configured from one wafer 2. In the display panel 1 of the present embodiment, it is also possible to obtain a plurality of display panels 1 from one wafer 2 in accordance with the number of pixels and the panel size. A display used in the apparatus can be configured. It is possible to provide a display panel corresponding to a display having a smaller panel size, for example, a display for a smartphone or a tablet computer.

  Since the display panel 1 as described above includes all the pixels 10 constituting the display, the mounting stroke on the mounting substrate 51 is completed in one time, and the assembly process of the display device is shortened and simplified. Can do.

  Furthermore, since the display panel 1 of the present embodiment uses the light emitting element 12 having the semiconductor light emitting layer for the pixel 10, the response speed of light emission is high. In addition, since an inorganic material is used for the phosphor layer, the operating life can be extended.

(Second Embodiment)
Although the case where one display panel 1 is used for one display device has been described above, the display panel is divided, and a plurality of display panel blocks are combined as a display block for one display device. be able to.
FIG. 6 is a plan view illustrating the appearance of the display panel 1a of this embodiment.
As shown in FIG. 6, the display panel 1 a according to this embodiment includes a plurality of display blocks 71 to 73. The plurality of display blocks 71 to 73 include a first display block 71, a second display block 72, and a third display block 73. Each of the display blocks 71 to 73 has a plurality of pixels 10 arranged in a lattice pattern. Each pixel 10 has a plurality of light emitting elements 12, for example, four light emitting elements 12. On top of the light emitting element 12, phosphor layers 41a and 41b are provided. The configuration of the pixel 10 is the same as that of the display panel 1 of the first embodiment, and the same reference numerals are given and detailed description thereof is omitted.

  The display panel 1a has a rectangular shape, and the rectangular shape has a size of horizontal A1 × vertical B1. The first display block 71 has a rectangular shape of horizontal A2 × vertical B2. The second display block 72 has a rectangular shape of horizontal (A2 / 2) × vertical B2. The third display block 73 has a rectangular shape of horizontal A2 × vertical (B2 / 2). That is, each display block is a rectangular display block having different vertical and horizontal dimensions, that is, a different number of pixels.

The first display block 71a is disposed adjacent to the second display block 72a at a position where the vertical dimension B2 of the first display block 71a and the second display block 72a is the same. The first display block 71b is disposed adjacent to the first display block 71a at a position where the vertical dimensions of the first display block 71b and the first display block 71a are the same. The second display block 72b is disposed adjacent to the first display block 71b at a position where the vertical dimensions of the second display block 72b and the first display block 71b are the same.

The first display block 71c is disposed adjacent to the second display block 72c at a position where the vertical dimensions of the first display block 71c and the second display block 72c are the same. The first display block 71d is arranged adjacent to the first display block 71c at a position where the vertical dimensions of the first display block 71d and the first display block 71c are the same. The second display block 72d is disposed adjacent to the first display block 71d at a position where the vertical dimensions of the second display block 72d and the first display block 71d are the same. The first display blocks 71c and 71d and the second display blocks 72c and 72d are arranged adjacent to the first display blocks 71a and 71b and the second display blocks 72a and 72b in the positive Y-axis direction.

  The third display block 73b is arranged adjacent to the third display block 73a at a position where the vertical dimensions of the third display block 73b and the third display block 73a are the same. The third display block 73c is arranged adjacent to the third display block 73b at a position where the vertical dimensions of the third display block 73c and the third display block 73b are the same. The third display blocks 73a to 73c are arranged so as to be adjacent to the first display blocks 71c and 71d and the second display blocks 72c and 72d in the positive Y-axis direction.

  Each of the display blocks 71 to 73 is arranged as described above, and constitutes a rectangular display panel 1a having a panel size of horizontal A1 × vertical B1. Here, the relationship is A1 = 3 × A2 and B1 = 2.5 × B2. The dimensions of the display blocks 71 to 73 described above are determined by the positions cut out from the wafer. The dimensions of each display block are not limited to those described above, but are determined by the distribution of characteristics of the light emitting elements.

A method for manufacturing the display panel 1a of the present embodiment will be described.
FIG. 7 is a conceptual diagram partially including an exploded view illustrating a method for manufacturing the display panel 1a of this embodiment.
FIG. 8 is a flowchart for explaining a method of manufacturing the display panel 1a of the present embodiment.
As shown in FIG. 7, one wafer 2a includes display blocks 71d to 73d that are divided into a plurality of pieces. The first display block 71d is provided at the center of the wafer 2a. The second display blocks 72d are provided at both ends along the X-axis direction of the wafer 2a. The third display blocks 73d are provided at both ends along the Y-axis direction of the wafer 2a. The other wafer 2b also includes display blocks 71e to 73e divided into a plurality of pieces, and the display blocks 71e to 73e are provided at the same positions as in the case of the wafer 2a.

  The characteristics of the light emitting elements 12 constituting each pixel 10 may vary depending on the positions on the wafers 2a and 2b. For example, the wafers 2a and 2b may be warped from the central portion toward the peripheral portion due to a thermal history during manufacture. Due to this warpage, characteristics such as light output and wavelength of the light emitting element 12 are affected. As the wafer size becomes larger, the influence on the characteristics due to warpage or the like becomes more significant, and the variation in characteristics becomes larger. In one display panel, if the variation in characteristics of the light emitting elements 12 is large, the display quality is affected. Therefore, it is necessary to reduce the variation in characteristics.

  As described above, since the characteristic variation of the light emitting element 12 is related to the position on the wafers 2a and 2b, the display panel 1a may be divided into predetermined sections and rearranged so as to absorb the characteristic variation. It is valid. Here, the predetermined section is the display block described above.

  As characteristics that affect the display quality, the light output and wavelength are acquired for each light emitting element 12, and only the display block having the light emitting element 12 within a predetermined standard is acquired as a non-defective product. For example, it is an area where the characteristics of the light emitting element 12 inside the alternate long and short dash line on the wafer 2a are good. In this case, the two first display blocks 71d on the Y axis positive direction side are non-defective products. On the other hand, in the wafer 2b, the two first display blocks 71e on the X axis positive direction side are non-defective products. These non-defective display blocks are rearranged at positions on the mounting substrate 51. When the display block is rearranged on the mounting substrate 51, the display block may be arranged at the position of the display block having the same shape and size among the display blocks of FIG. For example, the first display block 71d on the wafer 2a may be arranged at any position of the first display blocks 71a to 71d in FIG. 6 as long as it is a non-defective product determination. As for the other display blocks, a non-defective product is acquired and rearranged on the mounting substrate 51. That is, the display blocks mounted on one mounting substrate 51 are not limited to being acquired as non-defective products from the same wafer, but include those acquired as non-defective products from other wafers. Of course, all the display blocks mounted on one mounting substrate 51 may be display blocks acquired from the same wafer.

The manufacturing method of the display panel 1a of this embodiment is demonstrated using the flowchart of FIG.
As shown in FIG. 8, n × m pixels 10 are formed on the wafers 2a, 2b,. After filling and curing the resin layer 29, the growth substrate is removed (step S1).

  In step S2, the characteristics (light output and wavelength) of the light emitting element 12 are measured.

  In step S3, the measured data is stored in association with the wafer and the display block (which corresponds to the first to third). The characteristic data is stored as a database in a memory area of a storage device provided in a measuring instrument such as a tester.

  In step S4, phosphor layers 41a and 41b are formed.

  In step S5, dicing is performed for each display block.

  In step S6, the quality of each display block is determined based on the associated and stored characteristic data. The good / bad determination may be performed in step S3. Rearrange the display blocks determined to be non-defective items to the corresponding locations. For example, if the first display block 71 is a non-defective product, the display block is picked up by the mounter device and placed at the arrangement position of the first display block 71 on the mounting substrate 51. Note that the rearrangement destination of the display block is not necessarily the mounting substrate 51. For example, you may make it mount in the chip carrier etc. in which each display block is accommodated in the same position as a mounting substrate.

  In the above manufacturing method, the shape and position of each display block are set in advance based on, for example, the acquired characteristics of the light emitting element and the panel size. Generally, since there is a tendency that the characteristic variation is small near the center of the wafer, it is conceivable to increase the display block size near the center and reduce the peripheral display block size.

The operation and effect of the display panel of this embodiment will be described.
In the display panel 1a of the present embodiment, one wafer 2a, 2b is divided into a plurality of display blocks, and the pass / fail judgment is performed for each display block, so that the yield of non-defective products is improved. The display blocks have the same shape and the same size for each wafer, and pass / fail judgment is made based on the same reference. Therefore, one display panel 1a can be composed of display blocks acquired from a plurality of wafers 2a and 2b. Therefore, the yield of the display panel 1a can be further improved. In addition, since the shape and dimensions of each display block are set according to variations in the characteristics of the light emitting elements, a stable yield can be maintained.

(Second, a modification of the embodiment)
In the case of the manufacturing method described above, in order to improve the display quality of the display panel, it is necessary to set the non-defective product determination threshold value strictly. On the other hand, when the threshold value is tightened, the yield may decrease depending on the size of the display block. If the threshold value for determining the non-defective product is set loosely, the display quality may be impaired due to variations in light emission of the pixels. Therefore, in the following, a method for suppressing variation in light emission of pixels will be described.
FIG. 9A and FIG. 9B are conceptual diagrams for explaining correction of variation in characteristics of light emitting elements.
FIG. 10 is a flowchart for explaining a method of manufacturing the display panel according to this modification.

  When the phosphor layers 41a and 41b applied to each light emitting element 12 are increased in thickness, the number of fluorescent particles per unit volume increases, so that the wavelength is substantially shifted to the longer wavelength side. When the phosphor layers 41a and 41b are thick, the light output emitted from the light emitting element 12 is absorbed by the phosphor layers 41a and 41b, so that the light output decreases. Therefore, the light output and wavelength can be corrected by adjusting the thickness of the phosphor layers 41a and 41b based on the light output and wavelength data acquired by the tester.

  The characteristic classification based on the light output data and the wavelength data acquired for each light emitting element 12 is set in advance. For example, the light output is classified into whether it is larger or smaller than a predetermined value and whether the wavelength is longer or shorter than the predetermined value. In this example, four characteristic divisions are provided. As shown in FIG. 9A, when the wavelength λ of the light emitting element is plotted on the horizontal axis and the light output of the light emitting element is plotted on the vertical axis, the minimum value for non-defective product determination of the wavelength λ is λmin, Is λmax. The minimum value for determining the non-defective product of the light output is Pmin, and the maximum value is Pmax. The threshold value for setting the characteristic classification is λth for the wavelength λ and Pth for the optical output. λmin, λmax, λth, Pmin, Pmax, and Pth are set based on, for example, variations in characteristics of the light emitting elements and display quality of the display block. In this example, in the A section, as for the characteristics of the light emitting element, the wavelength λ is in the range of λmin to λth, and the light output P is in the range of Pmin to Pth. In the B section, the characteristics of the light emitting element are such that the wavelength λ is in the range of λth to λmax, and the light output P is in the range of Pmin to Pth as in the A section. In C section, the characteristics of the light emitting element are such that the wavelength is in the range of λmin to λth, and the light output is in the range of Pth to Pmax. In the D section, the characteristics of the light emitting element are such that the wavelength is in the range of λth to λmax, and the light output is in the range of Pth to Pmax, as in the C section.

  In the case of such a classification, a case will be described in which the reference phosphor layer thickness is set, the light output and the wavelength are corrected by setting the thickness in the direction of increasing the thickness from the reference value. As described above, by increasing the thickness of the phosphor layer, it is possible to reduce the light output and correct the wavelength in a longer direction. In the case of each of the above-described sections, the light emitting elements classified into the A section and the B section have a small light output, and thus correction by the phosphor layer is not performed. Further, since the light emitting elements 12 classified into the B section and the D section have a long wavelength, correction by the phosphor layer is not performed. For the light emitting elements 12 classified into the C category, the light output can be reduced and the wavelength can be corrected to be longer by setting the phosphor layer thick.

  For example, among the light emitting elements belonging to the C category, in the case of data c1 where the wavelength λ is short and the light output P is also small, the wavelength is increased by increasing the thickness of the phosphor layer, and the light output is increased. As a result of the reduction, the position is corrected to the position of the data a1 of the A section, and the characteristics equivalent to those of the light emitting element having the phosphor layer of the A section can be obtained. Among the light emitting elements belonging to the C section, when both the wavelength λ and the light output P are intermediate data c2, the light is corrected to the position of b2 of the B section and is equivalent to the light emitting element having the phosphor layer of the B section. Characteristics. In the case of data c3 where the wavelength λ is long and the light output P is large, the data is corrected to the position of the data D3 of the D section, and the characteristics equivalent to those of the light emitting element having the phosphor layer of the D section can be obtained.

  The light output and wavelength data of each light emitting element 12 are stored in association with the display block name, and by adjusting which display block belongs to the C section, the thickness of the phosphor layer is adjusted. Correct the wavelength and light output. By correcting the wavelength and the light output, it is possible to reduce variations in characteristics of the light emitting elements on the same display block.

  Further, by correcting the wavelength and light output of the light emitting element, it is possible to relieve a display block that is determined to be defective due to its characteristics.

  As shown in FIG. 9 (b), by increasing the thickness of the phosphor layer, the wavelength can be increased and the light output can be reduced. Therefore, the region of the C section is expanded to the C ′ section, and D The partition can be extended to the D ′ partition. In the C ′ section, the minimum value of the wavelength λ is expanded in relation to the light output. That is, the minimum value is expanded to λmin1 having a value smaller than the initial minimum value λmin when the light output P is Pmax1 (> 0). When the optical output P is less than or equal to Pmax1, the minimum value of the wavelength λ increases as Pmax1 decreases. The maximum value of the light output P is expanded to Pmax2 having a value larger than Pmax. Note that Pmax2> Pmax1.

  In the D ′ section, the maximum value of the light output P is expanded in relation to the wavelength λ. That is, the maximum value of the optical output P is extended to Pmax2 when the wavelength λ is in the range of λth to λmax1 (<λmax). When the wavelength λ is in the range of λmax1 to λmax, the maximum value of the wavelength decreases as the wavelength λ increases.

  As described above, when the criteria for determining whether the display block is good or bad is extended, the wavelength and light output of the light emitting element can be corrected by adjusting the thickness of the phosphor layer. By correcting the wavelength and light output of the light emitting element, the number of defective display blocks can be reduced, and the yield can be improved.

  As shown in FIG. 10, in step S3a, the optical output and wavelength data of the light emitting element 12 are acquired and classified into characteristic categories. The characteristic classification is set on the basis of a value (predetermined value) that can correct the optical output and wavelength described above in addition to the quality classification.

  In step S4a, the phosphor layer is formed with the reference thickness for the display blocks belonging to the sections A, B, and D, and the thickness considering the correction of the optical output and wavelength data for the display blocks belonging to the section C. Thus, a phosphor layer is formed. The thickness of the phosphor layer is set by, for example, forming all the phosphor layers by coating or the like, and then forming a mask that exposes the display block to be corrected and then performing additional coating of the phosphor. Can do.

  In the above description, it is assumed that all the light emitting elements 12 in the display block are classified into the same characteristic category. However, a certain percentage of the light emitting elements 12 in the display block are classified into the same characteristic category. In addition, the classification may be set. That is, the classification may be set in consideration of whether the light emitting elements belonging to any of the characteristic categories are dominant in the characteristic distribution.

  In the above description, the thickness of the phosphor layer is set for each display block. However, the thickness of the phosphor layer may be adjusted by further dividing the display block.

  Furthermore, the classification number of the characteristic divisions may be further classified into 6 divisions, 8 divisions, etc. according to the light output and / or wavelength.

  The adjustment of the thicknesses of the phosphor layers 41a and 41b is not limited to the adjustment to increase the thickness, and the adjustment may be made to reduce the thickness. The thickness of the phosphor layers 41a and 41b can be selectively reduced by, for example, scraping a necessary portion of the phosphor layer once applied.

(Third embodiment)
FIG. 11 is a plan view illustrating the appearance of a part of the display panel 1b of this embodiment.
FIG. 12 is a conceptual diagram illustrating a method for manufacturing the display panel of this embodiment.
As described in the display panel 1 a of the second embodiment, the display panel 1 a includes a plurality of display blocks 71. Each of the plurality of display blocks 71 is placed on the mounting substrate 51, and the anode terminal 34a and the cathode terminal 33a are mutually connected to the wiring 52 by solder bonding or the like. The distance between the light emitting elements 12 including the display blocks, that is, the element pitch P needs to be constant. That is, the distance L between the light emitting elements 12 arranged adjacent to each other is constant. Note that the inter-element pitch P is as follows when the X-axis direction and the Y-axis direction are equal. The inter-element pitch P is a distance from the center in the X-axis direction of the semiconductor layer 24 to the center in the X-axis direction of the semiconductor layer 24 of the adjacent light emitting element. That is, the pixel pitch P is equal to the length in the X-axis direction of the first main surface 24a of the semiconductor layer 24 of the light emitting element, and the distance between the first main surfaces 24a of the light emitting layer 23 between the adjacent light emitting elements (insulating layer 28). (Length in the X direction) is a length obtained by adding 1/2. In the following description, the distance between the first major surfaces 24a of the light emitting layer 23 is simply referred to as the distance between the light emitting elements.

  On the other hand, in the display panel 1 a of the second embodiment, the display block diced from the wafer 2 is placed on the mounting substrate 51. Each display block is arranged at the end of the display block with a gap s from the end of the adjacent display block. The gap s is set to a value smaller than the length in the X direction of the insulating layer 28 between the light emitting layers 23 between adjacent light emitting elements. Further, the gap s is set to a value larger than the length when the display block expands due to a high temperature environment such as in use. When there is no gap s (zero), or when the gap s is smaller than the length of the display block during thermal expansion, there is a possibility of causing interference such as cutting and contact with an adjacent display block.

  FIG. 12 shows the arrangement of the light emitting elements 12 in the wafer state. As shown in FIG. 12, in the wafer state, the distance M between the light emitting elements 12 including the dicing position d is set shorter than the distance L between the light emitting elements 12 not including the dicing position d. The distance M between the light emitting elements 12 including the dicing position d is set equal to the length obtained by subtracting the gap s from the distance L between the light emitting elements not including the dicing position d. Therefore, even when adjacent display blocks are mounted on the mounting substrate 51 with a gap s, all the element pitches P can be made equal.

  When a wider dicing blade can be selected, by setting the width of the dicing blade equal to the gap s, the inter-pixel distance not including the dicing position d can be changed between the pixels including the dicing position d. It can be made equal to the distance L.

The operation and effect of the display panel 1b of this embodiment will be described.
Since there is a gap s between adjacent display blocks, a clearance between the display blocks when the display blocks are mounted on the mounting board 51 is secured, and mounting on the mounting board 51 becomes easy. Since adjacent display blocks do not interfere with each other, it is possible to suppress the occurrence of image distortion or the like due to the pixels receiving interference in the vicinity of the end of the display block.

  Since there is a gap s between adjacent display blocks, even if the display block expands due to heat generated by a light emitting element or the like after being mounted on the mounting substrate 51, it is prevented from interfering with the adjacent display block. The Therefore, even when the resin layer 29 of the light emitting element 12 is slightly deformed due to heat generation, image distortion can be made difficult to occur.

(Fourth embodiment)
FIG. 13 is a block illustrating the display device of this embodiment.
As shown in FIG. 13, the display device 80 of the present embodiment includes the display panel 1 and a drive circuit 61. The display panel 1 is the display panel 1 according to the first embodiment described above. The display panel may be the display panels 1a and 1b of other embodiments. The drive circuit 61 is the drive circuit 61 described in the first embodiment.

  The display panel 1 is mounted on the mounting substrate 51. The drive circuit 61 is preferably mounted on the mounting substrate 51. A control circuit 82 is preferably mounted on the mounting substrate 51. The control circuit 82 is connected to the drive circuit 61, selects an appropriate pixel 10, and drives the light emitting element 12 with an appropriate current value. The control circuit 82 is connected to, for example, the interface circuit 90, and is connected to an external device of the display device 80, for example, a monitor output terminal of a computer via the interface circuit 90.

  The dimensions of the display panel 1 are determined according to the number of pixels and the panel size. The display panel 1 is built in an information communication terminal device having a diagonal size of 5 inches. The information communication terminal device is, for example, a so-called smartphone. In this case, typically, the number of pixels of the display panel 1 is, for example, 1920 × 1080. In this case, since the display panel 1 has a panel size of 5 inches diagonal, a plurality of display panels 1 can be cut out from, for example, an 8-inch wafer.

The operation and effect of the display device 80 of the present embodiment will be described.
In addition to the same operations and effects as the display panels 1 to 1b of the other embodiments described above, the following operations and effects are provided. That is, the display device 80 includes the display panels 1 to 1b, the column drive circuit 62, and the row drive circuit 64, and these are mounted on the same mounting board 51, so that a small display module can be configured. .

(Modification of the fourth embodiment)
FIG. 14 is a block diagram illustrating a display device 100 according to a modification of this embodiment.
As shown in FIG. 14, the display device 100 according to this modification includes a display panel 1, a drive circuit 61, and an optical system 110. The display device 100 of the present modification can arbitrarily set the screen size by adding the optical system 110 to the display device 80 of the fourth embodiment. The display device 100 is a high-definition receiver having a large screen exceeding 50 inches or 60 inches, for example. The high-definition receiver is, for example, a 4K television receiver.

The operation and effect of the display device 100 of this modification will be described.
Since the display device 100 according to the present modification includes the optical system 110 that enlarges and displays the screen output of the display panel 1, a display device having an arbitrary panel size can be realized.

When one display panel is divided into a plurality of display blocks as in the display panel 1a of the second embodiment, the display blocks can be cut out by effectively using one wafer. For example, since the area of an 8-inch wafer is 32,412,838,400 μm ² , the area per pixel is 3,908 μm ² . When this pixel is assigned for each color of RGB (three light emitting elements), 36 μm × 36 μm is the light emitting element size per unit color. That is, a display panel capable of displaying a screen of a 4K television receiver can be configured from an 8-inch wafer. In this case, the display panel can have a panel size of 8 inches diagonal (200 mm) or more, but the optical system 110 can realize a screen size of 50 inches or more.

  In the embodiment and the modification described above, specific examples in which RGB is developed using a combination of a light emitting element that emits blue light, a red phosphor, and a green phosphor have been described. Any combination that can generate light is not limited to the above. For example, a light emitting element that outputs ultraviolet light may be combined with red, green, and blue phosphors to generate a mixed color of RGB. Moreover, it is good also as an RGB element by changing the composition (In, Ga, Al) of the light emitting layer of each light emitting element, without using fluorescent substance.

  According to the embodiment described above, it is possible to realize a display panel, a display device, and a display panel manufacturing method capable of mounting a large number of pixels with a small number of man-hours.

  As mentioned above, although several embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and the equivalents thereof. Further, the above-described embodiments can be implemented in combination with each other.

  1, 1a, 1b Display panel, 2, 2a, 2b Wafer, 10 pixels, 12 light emitting elements, 12a Red light emitting elements, 12b, 12c Green light emitting elements, 12d Blue light emitting elements, 21 First semiconductor layer, 22 Second semiconductor layer , 23 Light emitting layer, 24 Semiconductor layer, 24a First main surface, 24b Second main surface, 25 n side electrode, 26 p side electrode, 27 insulating film, 28 insulating layer, 28a first via, 28b second via, 29 Resin layer, 31 n-side wiring layer, 32 p-side wiring layer, 33 n-side metal pillar, 33a-33d cathode terminal, 34p-side metal pillar, 34a-34d anode terminal, 41a, 41 phosphor layer, 51 mounting substrate, 52 wiring, 61 drive circuit, 62 column drive circuit, 63a, 63b constant current circuit, 64 row drive circuit, 65a, 65b row selection switch circuit, 7 To 73 display blocks, 80 display device, 82 control circuit, 90 an interface circuit, 100 a display apparatus, 110 an optical system

Claims (12)

A plurality of first semiconductor layer including a first light-emitting layer, respectively,
On the side of one surface of the plurality of first semiconductor layer, a first anode terminal and a first cathode terminal connected to each of the plurality of first semiconductor layer,
On the side of one surface of the first semiconductor layer, said plurality of first semiconductor layer, a first resin layer supporting the first anode terminal and said first cathode terminal as an integral,
On the side of the other surface of the first semiconductor layer, a first phosphor layer provided over at least a portion of said plurality of first semiconductor layer,
A first display block including :
A plurality of second semiconductor layers each including a second light emitting layer;
A second anode terminal and a second cathode terminal connected to each of the plurality of second semiconductor layers on one surface side of the plurality of second semiconductor layers;
A second resin layer that integrally supports the plurality of second semiconductor layers, the second anode terminal, and the second cathode terminal on one surface side of the second semiconductor layer;
A second phosphor layer provided on the other surface side of the second semiconductor layer so as to cover at least a part of the plurality of second semiconductor layers;
A second display block including
With
Said plurality of first semiconductor layer (n is a natural number) n-number in the first direction are arranged, m pieces in a second direction crossing the first direction (m is an integer of 2 or more) are arranged,
The plurality of second semiconductor layers are arranged p (p is a natural number) in the first direction, and q (q is an integer of 2 or more) are arranged in the second direction.
The first display block and the second display block are arranged adjacent to each other,
The length of the first display block in the first direction is different from the length of the second display block in the first direction . The first display block and the second display block are arranged adjacent to each other with a predetermined gap,
The distance between the first semiconductor layer and the other of the first semiconductor layer adjacent thereto of one of the plurality of first semiconductor layer, and, first of one of said plurality of second semiconductor layer the distance between the second semiconductor layer and the other second semiconductor layer adjacent thereto, a first semiconductor layer a first semiconductor layer adjacent one of said plurality of first semiconductor layer is not present, in which adjacent distance equal claim 1 display panel according to the second semiconductor layer having no second semiconductor layer adjacent one of the plurality of second semiconductor layers. The phosphor layer display panel according to claim 1 or 2 including a phosphor sheet. The phosphor layer display panel according to claim 1 or 2 including a fluorescent resin. The display panel according to claim 4 , wherein the phosphor layers are provided in different thicknesses on a plane including the first direction and the second direction. A display panel according to any one of claims 1 to 5 ;
A drive circuit for driving the display panel;
A display device comprising: The display device according to claim 1 , further comprising an optical system for enlarging the display of the display panel. Forming a plurality of semiconductor layers each including a light emitting layer;
Forming an anode terminal and a cathode terminal connected to each of the plurality of semiconductor layers on one surface side of the plurality of semiconductor layers;
Forming a resin layer that integrally supports the plurality of semiconductor layers, the anode terminal, and the cathode terminal on one surface side of the semiconductor layer;
Forming a phosphor layer on the other surface of the semiconductor layer;
Cutting the first display block and the second display block by dicing the resin layer on the outer periphery of the plurality of semiconductor layers;
Connecting the first display block and the second display block to a mounting substrate;
Have a,
Wherein the first length of the first display block, the method for producing a first direction length and different Do that display panel of the second display block. 9. The method of manufacturing a display panel according to claim 8 , further comprising a step of measuring electrical characteristics of each of the plurality of semiconductor layers and classifying the first display block and the second display block according to the electrical characteristics. . The display panel according to claim 9 , wherein the step of connecting the first display block and the second display block to a mounting substrate includes a step of arranging the first display block and the second display block based on the classification. Manufacturing method. The method of manufacturing a display panel according to claim 9 , wherein the step of forming the phosphor layer includes a step of forming the phosphor layer having a different thickness based on the classification.   The plurality of semiconductor layers are formed on one wafer;
  12. The step of cutting out the first display block and the second display block includes cutting out the second display block from a peripheral portion side of the wafer with respect to the first display block. The manufacturing method of the display panel as described in one.

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