JP6571078B2 - メモリにアクセスするための並列処理装置、コンピュータにより実施される方法、システム、コンピュータ可読媒体 - Google Patents

メモリにアクセスするための並列処理装置、コンピュータにより実施される方法、システム、コンピュータ可読媒体 Download PDF

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JP6571078B2
JP6571078B2 JP2016532759A JP2016532759A JP6571078B2 JP 6571078 B2 JP6571078 B2 JP 6571078B2 JP 2016532759 A JP2016532759 A JP 2016532759A JP 2016532759 A JP2016532759 A JP 2016532759A JP 6571078 B2 JP6571078 B2 JP 6571078B2
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memory
address encoder
processing element
address
processor
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JP2016536692A5 (enExample
JP2016536692A (ja
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デイヴィッド モロニー，
デイヴィッド モロニー，
リチャード リッチモンド，
リチャード リッチモンド，
デイヴィッド ドノホー，
デイヴィッド ドノホー，
ブレンダン バリー，
ブレンダン バリー，
コーマック ブリック，
コーマック ブリック，
オヴィディウ， アンドレイ ベサ，
オヴィディウ， アンドレイ ベサ，
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Priority claimed from GBGB1314263.3A external-priority patent/GB201314263D0/en
Priority claimed from ROA201300812A external-priority patent/RO129804A0/ro
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    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
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    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
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    • G09G2360/126—The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Graphics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Image Processing (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
  • Image Analysis (AREA)
JP2016532759A 2013-08-08 2014-08-06 メモリにアクセスするための並列処理装置、コンピュータにより実施される方法、システム、コンピュータ可読媒体 Active JP6571078B2 (ja)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
GB1314263.3 2013-08-08
GBGB1314263.3A GB201314263D0 (en) 2013-08-08 2013-08-08 Configurable and composable computational imaging pipeline
ROA/00812 2013-11-06
ROA201300812A RO129804A0 (ro) 2013-11-06 2013-11-06 Aparat, sistem şi metodă pentru a realiza o bandă configurabilă şi extensibilă de procesare de imagini
US14/082,396 US9934043B2 (en) 2013-08-08 2013-11-18 Apparatus, systems, and methods for providing computational imaging pipeline
US14/082,396 2013-11-18
US14/082,645 2013-11-18
US14/082,645 US9146747B2 (en) 2013-08-08 2013-11-18 Apparatus, systems, and methods for providing configurable computational imaging pipeline
PCT/IB2014/002541 WO2015019197A2 (en) 2013-08-08 2014-08-06 Computational imaging pipeline

Related Child Applications (1)

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JP2019145645A Division JP7025617B2 (ja) 2013-08-08 2019-08-07 メモリにアクセスするための並列処理装置、コンピュータにより実施される方法、システム、コンピュータ可読媒体

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JP2016536692A JP2016536692A (ja) 2016-11-24
JP2016536692A5 JP2016536692A5 (enExample) 2017-09-21
JP6571078B2 true JP6571078B2 (ja) 2019-09-04

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JP2016532759A Active JP6571078B2 (ja) 2013-08-08 2014-08-06 メモリにアクセスするための並列処理装置、コンピュータにより実施される方法、システム、コンピュータ可読媒体
JP2019145645A Active JP7025617B2 (ja) 2013-08-08 2019-08-07 メモリにアクセスするための並列処理装置、コンピュータにより実施される方法、システム、コンピュータ可読媒体
JP2022004451A Active JP7384534B2 (ja) 2013-08-08 2022-01-14 並列処理装置、コンピュータ可読記憶装置および方法

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JP2022004451A Active JP7384534B2 (ja) 2013-08-08 2022-01-14 並列処理装置、コンピュータ可読記憶装置および方法

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US (6) US9146747B2 (enExample)
EP (1) EP3031047B1 (enExample)
JP (3) JP6571078B2 (enExample)
KR (4) KR20230107412A (enExample)
CN (2) CN112037115B (enExample)
WO (1) WO2015019197A2 (enExample)

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