JP6535163B2 - Signal processing circuit and image sensor - Google Patents

Description

  The present invention relates to a signal processing circuit and an image sensor (image pickup device), and more particularly to a signal processing circuit that performs analog / digital conversion of a photoelectrically converted signal in each pixel of the image sensor and an image sensor using the signal processing circuit. It is a thing.

  Conventionally, the image sensor processes the photoelectrically converted signal charge as an analog signal, but the signal charge (charge amount) is AD (analog / digital) converted in the image sensor and output as digital data. While expanding the dynamic range of photoelectric conversion, processing of an output signal can be facilitated.

  Heretofore, a column parallel signal processing image sensor has been manufactured in which an AD conversion circuit is shared for each column of pixels arranged in an array in vertical and horizontal directions. However, in a configuration in which AD conversion processing of pixels in one row is performed by one AD conversion circuit, AD conversion is performed as the resolution of the image sensor increases (that is, as the number of pixels per row increases). The time taken for processing is prolonged, and it is becoming difficult to perform signal processing of all pixels within the time of one frame rate in moving image processing.

  In order to address this problem, pixel-parallel signal processing image sensors have been proposed as an image sensor for moving images, which include an AD conversion circuit in each pixel and can output all photoelectrically converted signals in parallel. . The pixel parallel signal processing image sensor can eliminate the trade-off between the number of scanning lines and the frame rate, which is a drawback of the conventional column parallel signal processing image sensor, and is therefore studied as a good candidate for future high performance image sensors. It is in progress. Above all, the image sensor described in Non-Patent Document 1 incorporates a circuit called a 1-bit AD converter circuit (1 bit ADC), and is considered to be able to significantly improve the dynamic range of the image sensor. There is.

  The operation of the signal processing circuit of the image sensor proposed in Non-Patent Document 1 will be described below. Non-Patent Document 1 in FIG. Although the circuit is illustrated in FIG. 3, the transistors (Tr1, Tr3 and Tr4) not essential to the circuit operation and the circuit including the details of the feedback circuit and counter including them are omitted for simplification of the description (FIG. 8) This will be described using

  FIG. 8 shows a signal processing circuit using the conventional 1-bit type AD converter circuit (1 bit ADC) described in Non-Patent Document 1. As shown in FIG.

91 is a photodiode (PD) as a photoelectric conversion element, 92 is a transistor (TR) for applying a voltage V _dd to the electrode of the photodiode 91. Reference numeral 94 denotes an inverter group (inverter circuit), and inverters (Inv_1, Inv_2,... Inv_n) are connected in odd stages. The potential at the connection point 93 between the photodiode 91 and the transistor 92 is input to the inverter group 94. The output of the inverter group 94 is input to the counter 95 as an AD conversion circuit output (ADC_OUT) and is applied to the gate electrode of the transistor 92. The voltage V _rs is applied to the counter 95, and the number of pulses of the AD conversion circuit output (ADC_OUT) is counted and output as an 8-bit counter output, for example.

  Next, the operation of the signal processing circuit of FIG. 8 will be described.

(1) First, with the potential of the photodiode 91 reset (≒ V _dd ), the input of the first stage inverter (Inv_1) is Hi, the output is Lo, and the output of the second stage inverter (Inv_2) is Hi, It is assumed that the output of the final-stage inverter (Inv_n), that is, the AD conversion circuit output (ADC_OUT) is Lo, and the transistor (TR) 92 is in the OFF state. [Initialization status]

  (2) When light is incident on the photodiode 91, electrons generated by photoelectric conversion are accumulated in the photodiode 91, and the potential of the photodiode 91 (the voltage at the connection point 93) decreases.

(3) When the potential of the photodiode 91 (the voltage at the connection point 93) reaches the inversion voltage (V _T ) of the inverter (Inv_1) of the first stage, the output of the inverter (Inv_1) is inverted to Hi. The n stages (n is an odd number) of inverters are connected, and the output is sequentially inverted and transmitted, and the output of the final stage inverter (Inv_n), that is, the AD conversion circuit output (ADC_OUT) becomes Hi. The reason why the inverters are connected in n stages rather than in one stage is to stabilize the circuit operation using the delay due to the n stages of inverters.

(4) When the output (ADC_OUT) of the AD conversion circuit becomes Hi, the transistor 92 is turned on, the voltage V _dd is applied to the electrode of the photodiode 91, and the photodiode 91 is reset again.

  (5) When the photodiode 91 is reset, the input of the first-stage inverter (Inv_1) becomes Hi, the AD conversion circuit output (ADC_OUT) becomes Lo, and the process returns to (1).

  Thereafter, the above (1) to (5) are repeated, and the output of the inverter group 94 repeats Hi and Lo. If the amount of light incident on the photodiode 91 is large, the potential change of the photodiode 91 becomes fast, and the inversion timing of the inverter group 94 becomes early. Therefore, within one frame period of the moving image, a number of pulses proportional to the light amount are generated at the output of the AD conversion circuit (ADC_OUT).

  The counter 95 sequentially accumulates pulses, and reads the counter output after one frame period ends. In the prototype of Non-Patent Document 1, although the counter is 8 bits, it is described that the capability of a 1-bit ADC can realize a dynamic range of 18 to 19 bits by an operation of 60 fields / second.

F. Andoh et. Al, "A Digital Pixel Image Sensor for Real-Time Readout", IEEE Transaction on electron devices, (2000), vol. 47, No. 11, pp. 2123-2127

Conventional 1-bit AD converter circuit (1bit ADC) is until the voltage of the photodiode reaches the inversion voltage V _T of the inverter does not occur voltage inversion pulse is not output. The number of charges N (minimum number of detected charges) required to invert the inverter is expressed by the following. Here, C _PD is the capacitance of the photodiode, V _T is the inverted voltage of the inverter (voltage with reference to V _dd ), and e is the elementary charge (1.6 × 10 ⁻¹⁹ C).

N = C _PD · V _T / e (Equation 1)

The capacitance C _PD is represented by the following equation when the pn junction of the photodiode (PD) is approximated by a step junction.

C _PD = ε ₀ · ε _r · S / W (Equation 2)

Here, ε ₀ is a vacuum dielectric constant (8.85 × 10 ⁻¹² F / m), ε _r is a relative dielectric constant, 12 in the case of a silicon photodiode, S is the area of the photodiode, and W is that of the photodiode It is a depletion layer thickness. When calculated as S = 16 μm ² and W = 2 μm as an example of a moving image sensor, C _{PD is} 0.85 fF. In order to operate stably 1bit ADC is inverted voltage V _T of the inverter it is reasonable to at least 10mV about. Substituting these values into (Expression 1),

N = 0.85 x 10 ^-15 x 10 ^-2 /1.6 x 10 ^-19 = 53 (pieces)

It is estimated. In the current mainstream of the column parallel signal processing type CMOS image sensor having similar photodiodes, it is general to detect 10 or less electrons. Therefore, a pixel parallel signal processing image sensor using a 1 bit ADC is There is a problem that the detection sensitivity of electrons is low (the minimum number of detected charges is large) compared to the current mainstream CMOS image sensor.

In order to improve detection sensitivity, that is, in order to detect a smaller number of charges N, it is conceivable to reduce C _PD and V _{T according} to (Expression 1). Then, in order to reduce the capacitance C _PD , the area S may be reduced or the depletion layer thickness W may be increased according to (Expression 2). However, if the area S of the photodiode is reduced, the number of photons received by the photodiode per unit time is reduced even with the same illuminance, so the number of electrons generated in photoelectric conversion is reduced. Therefore, even if the detection sensitivity of electrons is improved, imaging at a lower illuminance can not be achieved, and the improvement of the imaging sensitivity as an image sensor can not be achieved. In addition, when the depletion layer width W of the pn junction is increased, the dark current is increased and the S / N ratio of the image sensor is decreased. Therefore, it is not preferable to reduce the capacitance of the photodiode.

On the other hand, the inverted voltage V _T of the inverter, in order to operate the circuit stably, it is difficult to lower voltage than necessary, even realistic that by reducing the V _T to improve the detection sensitivity of the electronic is not. Therefore, it is difficult to improve the electron detection sensitivity of a pixel parallel signal processing image sensor using a conventional 1-bit ADC by an easily conceivable method.

  Therefore, an object of the present invention, which was made in view of the above problems, is a signal processing circuit using an AD conversion circuit that can improve the detection sensitivity of electrons (image signal) as compared to the prior art. A processing circuit and an image sensor using the circuit.

  In order to solve the above problems, a signal processing circuit according to the present invention includes a storage capacitance that is separate from the photodiode, and enables detection of a small number of charges by transferring electrons generated by the photodiode to the storage capacitance. It is a thing.

A signal processing circuit according to the present invention is a signal processing circuit that performs analog / digital conversion of an amount of charge generated by a photoelectric conversion element, and includes a storage capacitor connected in parallel with the photoelectric conversion element, a voltage of the storage capacitor, and a reference. The comparator includes: a comparator that compares a voltage and outputs a pulse when both match; and a reset unit that returns the voltage of the storage capacitor to a reset voltage by the output of the comparator, and counts the pulse A transfer gate transistor is provided between the photoelectric conversion element and the storage capacitor, and the transfer gate transistor is controlled based on the output of the comparator, and during operation of the reset means next is OFF, with reference to the substrate potential or ground potential, built-in potential V _B of the photoelectric conversion element, the transfer gate transistor Potential V _CH of the channel when the N, the reset voltage V _R, and the reference voltage V _REF of the comparator of the storage _{capacitor, | V R |> | V} REF |> | V CH |> | V B | of It is characterized in that it is set to be in a relationship .

Further, a signal processing circuit according to the present invention is a signal processing circuit that performs analog / digital conversion of an amount of charge generated by a photoelectric conversion element, and includes a storage capacitor connected in parallel with the photoelectric conversion element, and a voltage of the storage capacitor. And an inverter circuit which inverts the output at a predetermined inversion voltage, and reset means for returning the voltage of the storage capacitor to a reset voltage by the output of the inverter circuit, and the output pulse of the inverter circuit In the signal processing circuit which counts and outputs, a transfer gate transistor is provided between the photoelectric conversion element and the storage capacitor, and the transfer gate transistor is controlled based on the output of the inverter circuit, and the operation period of the reset means It is characterized in that the inside is turned off .

  In the signal processing circuit according to the present invention, the reset means is turned on after a predetermined time after the transfer gate transistor is turned off, and the transfer gate transistor is turned on after a predetermined time after the reset means is turned off. Is desirable.

  In the signal processing circuit according to the present invention, the transfer gate transistor is turned off during a period in which at least one of an output pulse of a comparator or an inverter circuit and a delay pulse obtained by delaying the output pulse is output. Preferably, the means is turned on in a period in which both the output pulse of the comparator or inverter circuit and the delayed pulse obtained by delaying the output pulse are output.

  Further, an image sensor of a pixel parallel signal processing system according to the present invention is characterized by including the above signal processing circuit in each pixel and outputting a photoelectric conversion signal as a digital signal.

According to the present invention, the detection sensitivity of electrons can be improved without reducing the capacitance C _PD of the photodiode or reducing the reversal voltage V _{T of the} inverter more than necessary, and a pixel parallel signal processing image sensor It is possible to improve the imaging sensitivity of

1 is a signal processing circuit according to a first embodiment of the present invention. FIG. 2 is a schematic circuit configuration and a potential diagram of the first embodiment of the present invention. It is a timing chart of the 1st example of the present invention. It is a signal processing circuit of the 2nd example of the present invention. It is a signal processing circuit of the 3rd example of the present invention. It is a timing chart of a 3rd example of the present invention. It is a conceptual diagram of the image sensor of this invention. This is a signal processing circuit using a conventional 1-bit type AD converter circuit.

  Hereinafter, embodiments of the present invention will be described.

Embodiment 1
The first embodiment of the present invention is a signal processing circuit in which the detection sensitivity is improved.

(First embodiment)
FIG. 1 shows a signal processing circuit of an image sensor as a first embodiment of the present invention. A characteristic part of the circuit of the present invention is to have a storage capacitor for storing the signal charge generated by the photodiode.

  The circuit configuration will be described. Reference numeral 1 denotes a photodiode (PD) as a photoelectric conversion element, which is formed of, for example, a buried photodiode having a small dark current. The form of the photoelectric conversion element is not limited to this, and it may be an element having a photoelectric conversion function, such as a normal PN junction photodiode formed on the substrate surface, a MOS type photodiode, or a thin film type photodiode. For example, any thing can be used.

  A storage capacitor (FD) 2 is connected in parallel to the photodiode 1 and stores signal charges generated by photoelectric conversion in the photodiode 1. A reference potential (for example, a substrate potential) is given to one electrode of the photodiode 1 and the storage capacitor 2. When the capacitance of the storage capacitor 2 is smaller than that of the photodiode 1, the light detection sensitivity can be enhanced. The structure of the storage capacitor 2 may be a normal PN junction capacitor or a MOS capacitor formed on the substrate surface, and it is also possible to utilize parasitic capacitance without positively forming a capacitive element. .

Reference numeral 3 denotes a transistor (TR ₁ ) which functions as a transfer gate for transferring the signal charge generated by the photodiode 1 to the storage capacitor 2. The transfer gate transistor (TR ₁ ) 3 is an enhancement type, and in the present embodiment, the output pulse of the inverter (Inv) 6 described later is applied to the gate electrode of the transistor (TR ₁ ) 3 to control ON / OFF. Ru. At the connection point between the storage capacitor 2 and the transistor (TR ₁ ) 3, the voltage V _{FD of the} storage capacitor (FD) 2 based on the signal charge appears.

Reference numeral 4 denotes a reset transistor (TR ₂ ) for resetting the electrode potential of the storage capacitor 2. Becomes conductive (ON) state on the basis of the signal (output pulse of the comparator 5) applied to the gate electrode, and connecting the electrode storage capacitor 2 and the reset voltage V _R, the signal charge accumulated in the storage capacitor 2 While discharging, the potential of the storage capacity (FD) 2 is reset (V _R ). The reset transistor (TR ₂ ) 4 constitutes a reset means of the present invention together with a reset voltage source.

Reference numeral 5 denotes a comparator (Comp), which compares the voltage V _{FD of} the storage capacitance (FD) 2 with the reference voltage V _REF , and outputs a pulse when both are in agreement. This pulse is input to the counter (not shown) as an AD conversion circuit output (ADC_OUT), is applied to the gate electrode of the reset transistor (TR ₂ ) 4, and is also input to the inverter (Inv) 6 .

An inverter (Inv) 6 receives the output pulse (ADC_OUT) of the comparator (Comp) 5, inverts it, and applies it to the gate electrode of the transfer gate transistor (TR ₁ ) 3. Therefore, in the present embodiment, the transfer gate transistor (TR ₁ ) 3 and the reset transistor (TR ₂ ) 4 are alternately turned ON / OFF.

In the circuit configuration of FIG. 1, the built-in potential V _B of the photodiode (PD) 1, the channel potential V _CH when the transistor (TR ₁ ) 3 is turned on, and the storage capacitance based on the substrate potential or the ground potential. The reset voltage V _R of (FD) 2 and the reference voltage V _REF of the comparator (Comp) are set to have the following relationship.

| V _R |> | V _REF |> | V _CH |> | V _B |

Each voltage can be set appropriately so as to maintain the above relationship, for example, a built-in potential V _B is about 0.6V, the channel potential V _CH of the transistor (TR ₁₎ 3 and the front and rear 1V, the reset voltage V _By setting _R to about 3 V, the reference voltage V _REF can be set to a voltage close to the reset voltage V _R. Due to this relationship, the signal charge generated by the photodiode 1 flows into the storage capacitor 2. Further, as described later, the light detection sensitivity can be improved by reducing the difference between the reference voltage V _REF and the reset voltage V _R.

  Next, the signal processing circuit of FIG. 1 will be described in more detail using the schematic circuit configuration and potential diagram of FIG. 2 and the timing chart of FIG.

FIG. 2A is a schematic circuit configuration in which a part of the signal processing circuit of FIG. 1 is represented by a pn junction region and a gate electrode or the like, and the same configuration as that of FIG. However, FIG. 2 (a) does not limit each element structure of the present invention. The photoelectric conversion element is, for example, an embedded type photodiode (PD) 1 formed on a substrate (for example, a p-type semiconductor substrate) and having an n-type semiconductor region 11 and a relatively high concentration p-type semiconductor region 12 on the surface. It consists of The storage capacitance (FD) 2 is composed of an n-type impurity region 21 formed in the substrate, and uses a pn junction capacitance between the substrate and the n-type impurity region 21 as a storage capacitance. A gate electrode 31 is provided on the substrate surface between the photodiode 1 and the storage capacitor 2 via a gate insulating film (not shown), and a transfer gate is formed by the gate electrode 31 and the n-type impurity regions 11 and 21. The transistor (TR ₁ ) 3 is configured. An n-type impurity region 42 connected to a reset voltage (V _R ) is provided in the vicinity of the impurity region 21 forming the storage capacitance 2. A gate electrode 41 is provided on the surface of the substrate between n-type impurity region 42 and storage capacitance 2 via a gate insulating film (not shown), and gate electrode 41 and n-type impurity regions 21 and 42 The reset transistor (TR ₂ ) 4 is configured. The connection relationship between the comparator 5 and the inverter 6 is the same as in FIG.

  FIGS. 2 (b) and 2 (c) are potential diagrams corresponding to the schematic circuit configuration of FIG. 2 (a). Based on the potential of the substrate, the positive potential of each region is taken downward in the figure to indicate the potential for electrons. 2B shows the state [reset state] when the reset transistor 4 is conductive (ON) with the transfer gate transistor 3 nonconductive (OFF), and FIG. 2C shows the reset transistor 4 OFF. The state (storage state) is shown when the transfer gate transistor 3 is conductive (ON) and charge storage is performed on the storage capacitor 2.

Further, in FIG. 3, (a) is the AD conversion circuit output (ADC_OUT), (b) is ON / OFF of the transfer gate transistor (TR ₁ ), (c) is ON / OFF of the reset transistor (TR ₂ ), d) is a timing chart of each of the potential V _FD of the storage capacitance (FD), showing changes in the reset state and the storage state.

  The circuit operation will be described below.

(1) The operation will be described from the state where a pulse is generated at the output of the AD conversion circuit (ADC_OUT). When a pulse of Hi to the AD conversion circuit output (ADC_OUT) is generated, the inversion pulse via an inverter 6 (Lo) is applied to the gate electrode 31, the transfer gate transistor (TR ₁₎ 3 is non-conductive (OFF), and the Also, an AD conversion circuit output pulse is applied to the gate electrode 41, and the reset transistor (TR ₂ ) 4 is turned on (ON). As a result, at the same time as the photodiode (PD) 1 is disconnected from the storage capacitance (FD) 2, the potential of the region 21 becomes equal to the reset voltage V _R and the potential of the storage capacitance (FD) 2 is reset (V _R ) Ru. This state is the “reset state” shown in FIG. 2B. In FIG. 3, the output of the AD conversion circuit of (a) is Hi, the transfer gate transistor (TR ₁ ) 3 of (b) is off, (c) reset transistor (TR ₂₎ is ON), the state of the potential V _R of the storage capacitor (FD) of (d).

(2) When the pulse of the AD conversion circuit output (ADC_OUT) falls and becomes Lo, the reset transistor (TR ₂ ) 4 is turned off, and the inversion pulse through the inverter 6 turns on the transfer gate transistor (TR ₁ ) 3 It becomes. Region 21 and region 42 are cut off by the OFF potential of the channel of reset transistor 4, and storage capacitance 2 becomes a potential well. When light is incident on the photodiode (PD) 1 in this state, electrons are generated in the photodiode 1, but the channel potential of the transistor (TR ₁ ) 3 in the ON state is V _CH and the potential V of the storage capacitor 2 is _{Since FD} is approximately reset voltage V _R and there is a relation of | V _R |> | V _CH |> | V _B |, the generated charge is transferred to the storage capacity 2. Then, as the charge is accumulated, the potential V _FD of the storage capacitor 2 gradually changes. This state is the "accumulation state" shown in FIG. 2C. In FIG. 3, the output of the AD conversion circuit of (a) is Lo, the transfer gate transistor (TR ₁ ) 3 of (b) is ON, (c). ) of the reset transistor (TR ₂₎ is OFF, the state gradually approaches the reference voltage V _REF is changed potential V _FD of the storage capacitor (FD) of (d).

(3) When the potential V _FD of the storage capacitor 2 reaches the reference voltage V _REF of the comparator 5, the comparator 5 generates a pulse of Hi as an AD conversion circuit output (ADC_OUT), and returns to the state of (1) . The time for which the potential V _FD of the storage capacitor 2 changes from the reset voltage V _R to the reference voltage V _REF becomes short in accordance with the photoelectrically converted charge amount, and hence the light reception amount. In addition, the pulse width (period Hi) of the comparator 5 is designed to cause the reset transistor 4 to conduct for a minimum time sufficient for the storage capacitor 2 to release all stored charges and return to the reset voltage (V _R ). It is desirable to do.

  Thereafter, (1) to (3) are repeated, and within one frame period of the moving image, a number of pulses proportional to the light amount are generated in the output of the AD conversion circuit (ADC_OUT). A counter (not shown) integrates pulses sequentially, and reads the counter output after one frame period ends.

In this embodiment, the reset transistor (TR ₂₎ 4 can be prevented turned ON at the same time the transfer gate transistor (TR ₁₎ 3 is turned OFF, that the potential of the photodiode 1 becomes the reset voltage V _R. In addition, charges generated by light incident on the photodiode 1 in the reset period can be temporarily accumulated in the photodiode 1, and thereafter, charges are transferred to the storage capacitor 2 after the reset period is completed. Thus, the charge generated by the photodiode 1 can be detected without error.

In the conventional 1-bit ADC, the photodiode has functions of both photoelectric conversion and accumulation of electrons. Therefore, in order to increase the detection sensitivity of electrons (to detect a small number of electrons), it is necessary to reduce the photodiode capacitance. Although the area (proportional to the capacitance) of the photodiode needs to be constant for the photoelectric conversion function despite the expression (1), it is difficult to improve the detection sensitivity of electrons. In the circuit of the present invention, since the photodiode responsible for photoelectric conversion and the storage capacitance for storing the charge generated by the photodiode are separated, the magnitude of the storage capacitance closely related to the detection sensitivity is It can be set independently. In the first embodiment, the detection sensitivity of the signal charge can be easily adjusted by adjusting the setting of the reference voltage V _REF of the comparator.

The detection sensitivity of the present invention is estimated. In the first embodiment, the minimum charge detection number N is expressed by the following equation, where C _FD is the capacitance of the storage capacitor (FD).

N = C _FD (V _R −V _REF ) / e (Equation 3)

That is, by making the storage capacitance smaller than the photodiode capacitance, the minimum charge detection number N can be reduced compared to the prior art. In other words, the detection sensitivity of electrons can be improved to C _PD / C _FD times as compared to the conventional 1-bit ADC. For example, assuming that C _FD is 0.08 fF, N becomes 5 with (V _R −V _REF ) = 10 mV, and it is possible to obtain the detection sensitivity of electrons comparable to the current mainstream column parallel signal processing CMOS image sensor it can. On the other hand, since this circuit follows the operation of the 1-bit ADC, a wider dynamic range can be realized as compared with the column parallel signal processing circuit. The dynamic range can be, for example, up to about 10 ⁸ .

Second Embodiment
A second embodiment is shown in FIG. The signal processing circuit of the second embodiment is obtained by replacing the comparator 5 with an inverter circuit (inverter group) 7 in the first embodiment (FIG. 1). Similar to the conventional 1-bit ADC, in the inverter circuit 7, inverters (Inv_1, Inv_2,... Inv_n) are connected in an odd number stage. The potential of the storage capacitor 2 is input to the first stage inverter (Inv_1) of the inverter circuit 7. The output of the inverter circuit 7 is input to the counter (not shown) as an AD conversion circuit output (ADC_OUT) and is applied to the gate electrode of the reset transistor (TR ₂ ) 4, and to the inverter (Inv) 6. It is input.

  The circuit operation of the second embodiment is basically the same as that of the signal processing circuit of FIGS. 1 and 2, but during the period when the reset transistor 4 is in the ON state, the charge stored in the storage capacitor is reset transistor It is designed by the time which it discharges and the delay time by an inverter group.

  In the second embodiment, the circuit can be configured by a simple inverter, which simplifies the design.

Third Embodiment
FIG. 5 shows a signal processing circuit as a third embodiment of the present invention. Further, FIG. 6 shows a timing chart thereof. In the third embodiment, the ON / OFF operation timings of the transfer gate transistor 3 and the reset transistor 4 of the first embodiment are improved.

In the signal processing circuit shown in FIG. 5, the circuit configuration of the photodiode (PD) 1, storage capacitance (FD) 2, transfer gate transistor (TR ₁ ) 3, reset transistor (TR ₂ ) 4 and comparator (Comp) 5 Is the same as the first embodiment of FIG.

  In the circuit of FIG. 5, the output of the comparator (Comp) 5, that is, the output of the AD conversion circuit output (ADC_OUT) is branched, and one of them is connected to the delay circuit (Delay) 81. The delay circuit (Delay) 81 generates a waveform (D_OUT) delayed from the input by a predetermined time (ΔT). Therefore, with respect to the output pulse of the comparator 5, the delayed pulse whose rising and falling are delayed by a predetermined time (ΔT) is output. In FIG. 5, the delay circuit (Delay) 81 is configured by an even number of inverters, but may be any circuit configuration that generates a predetermined delay time.

The NOR circuit 82 receives the output pulse of the AD conversion circuit output (ADC_OUT) and the output pulse (delay pulse: D_OUT) of the delay circuit (Delay) 81, and the output thereof is the gate electrode of the transfer gate transistor (TR ₁ ) 3 Connected to

The AND circuit 83 receives the output pulse of the AD conversion circuit output (ADC_OUT) and the output pulse (delay pulse: D_OUT) of the delay circuit (Delay) 81, and the output thereof is the gate of the reset transistor (TR ₂ ) 4 Connected to the electrode.

  The circuit operation of the signal processing circuit of FIG. 5 will be described with reference to the timing chart of FIG.

(1) The operation will be described from the state where a pulse is generated at the output of the AD conversion circuit (ADC_OUT). When a pulse of Hi is generated at the AD conversion circuit output (ADC_OUT), the pulse is input to the delay circuit (Delay) 81, one input terminal of the NOR circuit 82, and one input terminal of the AND circuit 83. The NOR circuit 82 immediately outputs a Lo pulse regardless of the input of the other input terminal, and this Lo pulse is applied to the gate electrode 31 so that the transfer gate transistor (TR ₁ ) 3 becomes nonconductive (OFF). Become. At this time, since the output of the delay circuit 81 is still Lo, the output of the AND circuit 83 is Lo, and the reset transistor (TR ₂ ) 4 is also nonconductive (OFF). As a result, the photodiode (PD) 1 and the storage capacitance (FD) 2 are electrically disconnected.

(2) The delay circuit (Delay) 81 outputs a Hi pulse after a predetermined time (ΔT) after the AD conversion circuit output (ADC_OUT) generates a pulse, and the other input terminal of the NOR circuit 82 and the AND circuit Input to the other input terminal of 83. The AND circuit 83 performs an AND operation of the output of the AD conversion circuit (ADC_OUT) and the output (D_OUT) of the delay circuit (Delay) 81, outputs a pulse of Hi, and the Hi pulse is applied to the gate electrode of the reset transistor 4 Thus, the reset transistor (TR ₂ ) 4 is turned on (ON). As a result, the potential of the storage capacitor (FD) 2 is equal to the reset voltage V _R, the reset state. At this time, since the transfer gate transistor (TR ₁ ) 3 remains nonconductive (OFF) and the photodiode (PD) 1 is separated from the storage capacitance (FD) 2, photoelectric conversion is performed during this period by the incident light. The charge generated by the conversion is held in the photodiode (PD) 1.

(3) When the output of the AD conversion circuit (ADC_OUT) returns to the Lo level, the pulse of the AND circuit 83 also becomes the Lo level, and this Lo pulse is applied to the gate electrode of the reset transistor 4 and the reset transistor (TR ₂ ) 4 becomes nonconductive (OFF). At this time, the transfer gate transistor (TR ₁ ) 3 remains nonconductive (OFF). As a result, the storage capacity (FD) 2 becomes a potential well, and the storage capacity 2 maintains the reset voltage V _R.

(4) The delay circuit (Delay) 81 returns to the Lo level a predetermined time (ΔT) after the output of the AD conversion circuit output (ADC_OUT) returns to the Lo level. The NOR circuit 82 performs a NOR operation on the output (ADC_OUT) of the AD conversion circuit and the output (D_OUT) of the delay circuit (Delay) 81, outputs a pulse of Hi, and applies the Hi pulse to the gate electrode of the transfer gate transistor 3. As a result, the transfer gate transistor (TR ₁ ) 3 conducts. At this time, the reset transistor (TR ₂ ) 4 is nonconductive (OFF). In this state, charges (electrons) generated in the photodiode 1 by light incident on the photodiode (PD) 1 are transferred to the storage capacitor 2 through the channel of the transistor (TR ₁ ) 3. Then, as the charge is accumulated, the potential V _FD of the storage capacitor 2 is gradually changed, which results in an accumulation state.

(5) When a predetermined amount of charge is stored in the storage capacitor 2 and the potential V _FD of the storage capacitor 2 reaches the reference voltage V _REF of the comparator 5, the comparator 5 outputs Hi as the AD conversion circuit output (ADC_OUT). Generate a pulse and return to the state of (1). At this time, both transistors (3, 4) are nonconductive, storage capacitor 2 is floating, the voltage of storage capacitor (FD) 2 is maintained at reference voltage V _REF , and then reset transistor (TR ₂ ) 4 when There was conductive, that the reset voltage V _R is as described above.

In the first embodiment, when a pulse is generated at the output of the AD conversion circuit (ADC_OUT), the transfer gate transistor (TR ₁ ) 3 is turned off and the reset transistor (TR ₂ ) 4 is turned on at the same time. Due to the delay due to the delay time etc., there is a possibility that the time when the reset transistor (TR ₂ ) 4 is turned on may occur even though the transfer gate transistor (TR ₁ ) 3 is not turned off. If the transfer gate transistor (TR ₁ ) 3 and the reset transistor (TR ₂ ) 4 are simultaneously turned on at the same time, the photodiode (PD) 1 is reset to the reset voltage V _R , and the above-mentioned photodiode (PD) 1 The charge transfer from the storage capacitor (FD) to the storage capacitor (FD) 2 is not properly performed. According to the circuit of the third embodiment, a period from the start of the transfer gate transistor (TR ₁ ) 3 OFF to the start of the reset transistor (TR ₂ ) 4 ON, and transfer from the end of the reset transistor (TR ₂ ) 4 ON The period until the OFF end of the gate transistor (TR ₁ ) 3 can be determined as ΔT determined by the delay circuit (Delay) 81. Thus, in a state of surely disconnected photodiodes (PD) from the storage capacitors (FD), it is possible to reset the potential of the storage capacitor (FD) to the reset voltage V _R, as compared with the first embodiment , Stable operation is possible.

  Although the comparator (Comp) 5 is used to detect the potential of the storage capacitance (FD) 2 in this embodiment, an inverter circuit (odd-numbered stage) is used instead of the comparator 5 as in the second embodiment. A circuit configuration using the inverter group 7) is also possible.

  Further, in the present invention, the transistors constituting the signal processing circuit are described as n-type, but a circuit configuration using p-type transistors is also possible. At this time, since the relationship between Hi / Lo of the pulse and the ON / OFF of the transistor is reversed, the NOR circuit is changed to an OR circuit, the AND circuit is changed to a NAND circuit, and so on. Appropriate changes will be made.

  Although the present invention is described on the assumption of a circuit that detects electrons, a circuit that detects holes by changing the conductivity type of the semiconductor region and the sign of the power supply voltage with the same circuit configuration is also possible. It is self-explanatory.

Second Embodiment
Next, a second embodiment of the present invention will be described. FIG. 7 shows a conceptual diagram of an image sensor (imaging device) 100 according to a second embodiment of the present invention.

  The image sensor 100 of FIG. 7 is a pixel parallel signal processing type image sensor in which each pixel outputs digital data.

  In the sensor area 101 of the image sensor 100, pixels 103 are arrayed in the vertical and horizontal directions. Each pixel 103 internally includes a signal processing circuit, a photodiode (PD) 104 as a photoelectric conversion element, and an AD conversion circuit (ADC) 105 that digitizes the amount of signal charge from the photodiode 104. And a counter 106 which counts the number of pulses of the AD conversion circuit output (ADC_OUT) and outputs it as data of a predetermined number of bits. The signal processing circuit of each pixel 103 is any of the signal processing circuits of the first to third embodiments.

  The output from each pixel is processed by the output processing circuit 102 and output as imaging data of digital data. In the output processing circuit 102, for example, after data from each pixel 103 is once stored in a buffer memory or the like, processing for sequentially reading out the data is performed. Further, the output data of all the pixels can be sequentially scanned and output by a scanning circuit (not shown), and any appropriate readout processing can be performed.

  In the image sensor 100 according to the present invention, each pixel 103 includes the signal processing circuit according to any one of the first to third embodiments, and the detection sensitivity can be improved as compared with the conventional case.

  Although the present invention has been described based on the drawings and examples, it should be noted that those skilled in the art can easily make various changes and modifications based on the present disclosure. Therefore, it should be noted that these variations and modifications are included in the scope of the present invention. For example, the functions and the like included in each means can be rearranged so as not to be logically contradictory, and it is possible to combine or divide a plurality of means, steps, etc. into one.

1 Photodiode (PD)
2 Storage capacity (FD)
3 Transfer gate transistor (TR ₁ )
4 Reset transistor (TR ₂ )
5 Comparator (Comp)
6 Inverter (Inv)
7 Inverter circuit 81 Delay circuit (Delay)
82 NOR circuit 83 AND circuit 100 image sensor 101 sensor area 102 output processing circuit 103 pixel 104 photodiode 105 AD conversion circuit 106 counter

Claims (5)

A signal processing circuit that analog-to-digital converts a charge amount generated by a photoelectric conversion element, comprising:
A storage capacitor connected in parallel with the photoelectric conversion element,
A comparator that compares the voltage of the storage capacitor with a reference voltage and outputs a pulse when both match.
Reset means for returning the voltage of the storage capacitor to a reset voltage by the output of the comparator;
Signal processing circuit that counts and outputs the pulses ,
Providing a transfer gate transistor between the photoelectric conversion element and the storage capacitance;
The transfer gate transistor is controlled based on the output of the comparator, and is turned off during the operation of the reset means,
The built-in potential V _B of the photoelectric conversion element, the channel potential V _CH when the transfer gate transistor is turned on, the reset voltage V _{R of} the storage capacitor , and the reference of the comparator based on the substrate potential or the ground potential The voltage V _REF is
| V _R |> | V _REF |> | V _CH |> | V _B |
A signal processing circuit set so as to have a relationship of A signal processing circuit that analog-to-digital converts a charge amount generated by a photoelectric conversion element, comprising:
A storage capacitor connected in parallel with the photoelectric conversion element,
An inverter circuit which receives the voltage of the storage capacitor and inverts the output at a predetermined inversion voltage;
Reset means for returning the voltage of the storage capacitor to a reset voltage by the output of the inverter circuit;
A signal processing circuit that counts and outputs an output pulse of the inverter circuit ,
Providing a transfer gate transistor between the photoelectric conversion element and the storage capacitance;
A signal processing circuit characterized in that the transfer gate transistor is controlled based on the output of the inverter circuit, and is turned off during the operation period of the reset means. The signal processing circuit according to claim 1 or 2 , wherein the reset means is turned on a predetermined time after the transfer gate transistor is turned off, and the transfer gate transistor is a predetermined time after the reset means is turned off. A signal processing circuit characterized by being turned on. 4. The signal processing circuit according to claim 3 , wherein the transfer gate transistor is turned off during a period in which at least one of an output pulse of a comparator or an inverter circuit and a delayed pulse obtained by delaying the output pulse is output. The signal processing circuit is characterized in that it is turned on in a period in which both the output pulse of the comparator or the inverter circuit and the delayed pulse obtained by delaying the output pulse are output. An image sensor of a pixel parallel signal processing system which comprises the signal processing circuit according to any one of claims 1 to 4 in each pixel and outputs a photoelectric conversion signal as a digital signal.

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