JP2010226679A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To ensure a satisfactory SNR (signal-to-noise ratio) at low illumination while increasing the number of saturation electrons in a solid-state imaging device. <P>SOLUTION: The solid-state imaging device includes: a pixel section 22 in which a plurality of cells 12 are two-dimensionally arranged on a semiconductor substrate; and an exposure time control means 32 for controlling the exposure time for performing photoelectric conversion in photodiodes PD. The cell includes: a photodiode for generating a signal charge by photoelectrically converting an optical signal; a readout means Td for reading out the signal charge generated in the photodiode into a detection section; the detection means Tb for converting the signal charge into a voltage that corresponds to the charge quantity and detecting the voltage thereof; an output means Ta for outputting the voltage detected by the detection means; and a reset means Tc for resetting the detection means. The exposure time control means includes: a readout pulse amplitude control means 23 for dividing the signal charge accumulated in the photodiode and reading out the divided signal charges; and a combining means 19 for combining the divided readout signals into one signal. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device such as a CMOS image sensor, and is applied to, for example, a mobile phone with an image sensor, a digital camera, a video camera, and the like.

  In general, the image sensor is designed so that the storage capacity of the photodiode portion is as large as possible in order to increase the number of saturated electrons of the photodiode (PD). At this time, the capacity of the detection unit (FD) for detecting the signal charge is designed to be larger than the storage capacity of the photodiode unit, thereby ensuring a dynamic range of the signal charge generated in the photodiode unit. (For example, refer nonpatent literature 1). That is, when the capacitance of the photodiode portion is Cpd and the capacitance of the detection portion is Cfd, “capacitance Cpd <capacitance Cfd” is designed. However, the image sensor having such a configuration inevitably has a small voltage / charge conversion gain determined by the capacitance of the detection unit when the signal charge amount is low and the illuminance is low. For this reason, since the ratio of noise generated after the output circuit is increased, the SNR (signal-to-noise ratio) is deteriorated.

  On the other hand, by reducing the capacitance of the detection unit of the image sensor and increasing the voltage / charge conversion gain, the influence of circuit noise after the detection unit is reduced, so that the SNR at low illuminance can be improved. However, the storage capacity of the photodiode portion is inevitably designed to be small. For this reason, since the ratio of shot noise increases due to a decrease in the number of saturated electrons, there is a problem that the SNR at the time of light decreases.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.39, NO.12, DECEMBER 2004 Mabuchi et al. "CMOS Image Sensors Comprised of Floating Diffusion Driving Pixels With Buried Photodiode" pp.2408-2416.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a solid-state imaging device capable of ensuring SNR at low illuminance while increasing the number of saturated electrons.

  In order to solve the above problems, a solid-state imaging device according to one embodiment of the present invention includes a photodiode that photoelectrically converts an optical signal to generate a signal charge, and reads out the signal charge generated by the photodiode to a detection unit. Readout means, detection means for converting the signal charge into a voltage corresponding to the charge amount and detecting, output means for outputting the voltage detected by the detection means, and reset means for resetting the detection means The cell comprises a pixel portion two-dimensionally arranged on a semiconductor substrate, and an exposure time control means for controlling an exposure time for photoelectric conversion by the photodiode, and the exposure time control means is provided on the photodiode. Read pulse amplitude control means for dividing and reading the accumulated signal charge, and combining means for combining the divided and read signals into one signal That.

  According to the present invention, it is possible to obtain a solid-state imaging device that can secure SNR at low illuminance while increasing the number of saturated electrons.

1 is a block diagram illustrating a schematic configuration of an amplification type CMOS image sensor for explaining a solid-state imaging device according to a first embodiment of the present invention. FIG. FIG. 2 is a circuit diagram illustrating a specific configuration example of a pixel portion, a CDS circuit, and an ADC in the amplification type CMOS image sensor illustrated in FIG. 1. FIG. 3 is a waveform diagram showing operation timing of the amplification type CMOS image sensor shown in FIGS. 1 and 2. FIG. 4 is a cross-sectional view and potential diagram of a pixel portion at time points t1 to t4 in the operation timing chart illustrated in FIG. 3. FIG. 5 is a circuit diagram illustrating another configuration example of the column type ADC illustrated in FIG. 1 for describing a solid-state imaging device according to a second embodiment of the present invention. FIG. 6 is a timing chart of the addition operation of the column type ADC shown in FIG. 5. FIG. 9 is a circuit diagram illustrating another configuration example of a cell for explaining a solid-state imaging device according to a third embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram illustrating a schematic configuration of an amplification type CMOS image sensor for explaining a solid-state imaging device according to the first embodiment of the present invention. The sensor core unit 11 includes a pixel unit 12, a column type noise cancellation circuit (CDS circuit) 13, a column type analog-digital converter (ADC) 14, a latch circuit 15, two line memories (MSH and MSL) 16, 17 and a horizontal shift. A register 18 and the like are provided.

  Light is incident on the pixel portion 12 through the lens 21, and a charge (signal charge) corresponding to the amount of incident light is generated by photoelectric conversion. In the pixel portion 12, cells (pixels) 22 are two-dimensionally arranged in rows and columns on a semiconductor substrate. In this example, one cell 22 includes four transistors (a row selection transistor Ta, an amplification transistor Tb, a reset transistor Tc, and a read transistor Td) and a photodiode PD that functions as photoelectric conversion means. Pulse signals ADRESn, RESETn, and READn for operation control are supplied.

  The current paths of the transistors Ta and Tb are connected in series between the power supply VDD and the vertical signal line VLIN. A pulse signal (address pulse) ADRESn is supplied to the gate of the transistor Ta. The current path of the transistor Tc is connected between the power supply VDD and the gate (detector FD) of the transistor Tb, and a pulse signal (reset pulse) RESETn is supplied to the gate. One end of the current path of the transistor Td is connected to the detection unit FD, and a pulse signal (readout pulse) READn is supplied to the gate thereof. The cathode of the photodiode PD is connected to the other end of the current path of the transistor Td, and the anode of the photodiode PD is grounded.

  In order to increase the number of saturated electrons, the storage capacitor Cpd of the photodiode PD is increased, and the capacitor Cfd of the detection unit FD is designed to be smaller than the conventional one. That is, “capacitance Cpd> capacitance Cfd”.

  A load transistor TLM for the source follower circuit is arranged for each cell column at the end of the pixel unit 12, and one end of the current path of each load transistor TLM is connected to the vertical signal line VLIN, and the other end is connected. Connected to a point. The vertical signal line VLIN is connected to the CDS circuit 13 through the current path of the transistor TS1.

  An analog signal corresponding to the signal charge generated in the pixel unit 12 is supplied to the ADC 14 through the CDS circuit 13, converted into a digital signal, and latched in the latch circuit 15. The digital signal latched by the latch circuit 15 is taken into the line memory MSH16 and the line memory MSL17, and sequentially read out from the sensor core unit 11 by the horizontal shift register 18.

  Two 10-bit digital signals SH and SL (OUT0 to OUT9) read from the line memory MSH16 and the line memory MSL17 are added by an adder 19 to generate one 11-bit signal. Thereafter, the signal processing circuit 20 performs normal signal processing and outputs the signals RGB / YUV to the outside of the image sensor chip.

  Further, a pulse selector circuit (selector) 24, a signal readout vertical register (VR register) 25, and an accumulation time control vertical register (ES register) 26 are disposed adjacent to the pixel portion 12. .

  Reading signal charges from the pixel unit 12 and controlling the CDS circuit 13, selector 24, VR register 25 and ES register 26 are pulse signals S 1 to S 4, READ, RESET / output from a timing generator (TG) 30. This is done by ADRES / READ, VRR, ESR. The pulse signal S1 is supplied to the gate of the transistor TS1, and the pulse signals S2 to S4 are supplied to the CDS circuit 13. The pulse signals RESET / ADRES / READ are supplied to the selector 24. The pulse signal READ is supplied to the pulse amplitude control circuit 23, and the output signal VREAD of the pulse amplitude control circuit 23 is supplied to the selector 24.

  The pulse signal VRR output from the timing generator 30 is supplied to the VR register 25, and the pulse signal ESR is supplied to the ES register 26, respectively. The vertical register line VLIN of the pixel unit 12 is selected by the VR register 25, and pulse signals RESET / ADRES / READ (represented by RESETn, ADRESn, and READn in FIG. 1) are supplied to the pixel unit 12 through the selector 24. Is done. The pulse signal (address pulse) ADRESn is supplied to the gate of the row selection transistor Ta in the cell 22, and the pulse signal (reset pulse) RESETn is supplied to the gate of the reset transistor Tc in the cell 22. READn is supplied to the gate of the read transistor Td in the cell 22.

  Further, a bias voltage VVL is applied to the pixel portion 12 from a bias generation circuit (bias 1) 31. This bias voltage VVL is supplied to the gate of the load transistor TLM for the source follower circuit.

  The VREF generation circuit 32 is a circuit that operates in response to the main clock signal MCK and generates a reference waveform for AD conversion (ADC 14). The amplitude of this reference waveform is controlled by data DATA input to the serial interface (serial I / F) 33. A command input to the serial interface 33 is supplied to the command decoder 34, decoded, and supplied to the timing generator 30 together with the main clock signal MCK.

  The VREF generation circuit 32 generates triangular waves VREFGH and VREFGL and supplies them to the ADC 14 in order to execute AD conversion twice in one horizontal scanning period. The first input signal is AD-converted at the 1023 level with the first-half VREF amplitude. In the second half, the second different input signal is AD-converted at the 1023 level with the same VREF amplitude. Then, in the next horizontal period, the signals SH and SL are simultaneously read from the line memory MSH16 and the line memory MSL17, and the adder 19 adds the two signals to combine them into one signal, which is supplied to the signal processing circuit 20. To do.

  FIG. 2 is a circuit diagram showing a specific configuration example of the pixel unit 12, the CDS circuit 13, and the ADC 14 in the amplification type CMOS image sensor shown in FIG. As described above, each cell (pixel) 22 includes the row selection transistor Ta, the amplification transistor Tb, the reset transistor Tc, the read transistor Td, and the photodiode PD. The cells 22 having such a configuration are two-dimensionally arranged in rows and columns to form the pixel portion 12.

  At the end of the pixel section 12, a load transistor TLM for a source follower circuit is arranged in the horizontal direction for each cell column. One end of the current path of these load transistors TLM is connected to the corresponding vertical signal line VLIN, the other end is connected between the ground points, and a bias voltage VVL is applied from the bias generation circuit 31 to the gate thereof. In the CDS circuit 13 and the ADC 14, noise canceller capacitors C1 and C2 are disposed, a transistor TS1 for transmitting a signal of the vertical signal line VLIN, a transistor TS2 for inputting a reference waveform for AD conversion, In addition, two-stage comparator circuits COMP1 and COMP2 are provided. A capacitor C3 is connected between the comparator circuits COMP1 and COMP2.

  The comparator circuit COMP1 includes an inverter INV1 and a transistor TS3 having a current path connected between an input terminal and an output terminal of the inverter INV1. The comparator circuit COMP2 includes an inverter INV2 and a transistor TS4 having a current path connected between the input terminal and the output terminal of the inverter INV2.

  A pulse signal S1 output from the timing generator 30 is provided to the gate of the transistor TS1, a pulse signal S2 is provided to the gate of the transistor TS2, a pulse signal S3 is provided to the gate of the transistor TS3, and a pulse signal is provided to the gate of the transistor TS4. S4 is supplied.

  The digital signal output from the comparator circuit COMP2 is latched by the latch circuit 15 and input to the two line memories MSH16 and MSL17. As the shift register 18 operates, 10-bit digital signals SH and SL (OUT0 to OUT9) are sequentially output from the line memory MSH16 and the line memory MSL17.

  In the configuration as described above, for example, when a signal on the n-th line in the vertical signal line VLIN is read, the source follower circuit including the amplification transistor Tb and the load transistor TLM is set by setting the address pulse ADRESn to the “H” level. To work. Then, the signal charge obtained by photoelectric conversion by the photodiode PD is accumulated for a certain period, and the reset pulse RESETn is set to “H” level in order to remove noise signals such as dark current in the detection unit FD before reading. Then, the transistor Tc is turned on to set the detection unit FD to the voltage of the power supply VDD (= 2.8V).

  As a result, a voltage (reset level) in a state where there is no signal in the reference detection unit FD is output to the vertical signal line VLIN. At this time, the pulse signals S1, S3, S4 are set to "H" level to turn on the transistors TS1, TS3, TS4, thereby setting the AD conversion levels of the comparator circuits COMP1 and COMP2 of the ADC 14 and the vertical signal line VLIN. The charge corresponding to the reset level is accumulated in the capacitor C1.

  Next, the read pulse READn is set to “H” level to turn on the read transistor Td, and the signal charge generated and accumulated by the photodiode PD is transferred to the detection unit FD.

  As a result, the voltage (signal + reset) level of the detection unit FD is read out to the vertical signal line VLIN. At this time, by setting the pulse signal S1 to the “H” level, the pulse signal S3 to the “L” level, the pulse signal S4 to the “L” level, and the pulse signal S2 to the “H” level, the transistor TS1 is turned on, and the transistor TS3 Is turned off, the transistor TS4 is turned off, and the transistor TS2 is turned on, and the charge corresponding to “the signal of the vertical signal line VLIN + the reset level” is accumulated in the capacitor C2.

  At this time, since the input terminal of the comparator circuit COMP1 is in a high impedance state, the capacitor C1 is kept at the reset level.

  Thereafter, the level of the reference waveform output from the VREF generation circuit 32 is increased (triangular wave VREF is changed from a low level to a high level), and AD conversion is performed by the comparator circuits COMP1 and COMP2 via the combined capacitance of the capacitors C1 and C2. The triangular wave is generated at 10 bits (0 to 1023 level), the AD conversion level is determined by a 10-bit counter, and the latch circuit 15 holds the data. After AD conversion at the 1023 level, the data in the latch circuit 15 is transferred to the line memory MSH16 and the line memory MSL17.

  Since the polarity of the reset level stored in the capacitor C1 is opposite to that of the reset level stored in the capacitor C2, the reset level is canceled and AD conversion is performed substantially using the signal component of the capacitor C2. This operation of removing the reset level is called a noise reduction processing operation (CDS operation: Correlated Double Sampling).

  In order to execute this AD conversion operation twice in one horizontal scanning period, the VREF generation circuit 32 generates triangular waves VREFGH and VREFGL and supplies them to one end of the current path of the transistor TS2. The digital signal AD-converted by the first half triangular wave VREFGH is held in the line memory MSH16. On the other hand, the digital signal AD-converted by the latter half triangular wave VREFGL is held in the line memory MSL17. These two signals are simultaneously read out in the next horizontal scanning period and added by the adder 19.

  FIG. 3 is a waveform diagram showing operation timings of the amplification type CMOS image sensor shown in FIGS. This example is a VGA, and an accumulation time (maximum accumulation time for low-illuminance photography) TL = 525H in which an optical signal is photoelectrically converted by a vertical n-line photodiode PD and signal charges are accumulated. In addition, the selector 24 is controlled by setting the amplitude of the output signal VREAD of the pulse amplitude control circuit 23 to a high level (Vn = 2.8 V). The accumulation time TL can be controlled by the ES register 26 every 1H. Further, control of 1H or less can be performed by changing the input timing of the pulse signal to the selector 24.

  At the time of the first read operation from the pixel unit 12 (t3), pulse signals RESETn, READn, ADRESn are supplied to the pixel unit 12 in synchronization with the horizontal synchronization pulse HP and photoelectrically converted by the photodiode PD and stored. Read out signal charge. First, the reset level when the reset pulse RESETn is set to “H” level and then to “L” level is taken into the capacitor C1 of FIG. At this time, the amplitude of the reference waveform is set to an intermediate level for reading. This intermediate level is automatically adjusted in the sensor so that the shading pixel (OB) portion of the pixel portion is 64 LSB.

  Next, by setting the read pulse READn to the intermediate voltage Vm, signal charges that are about half or more of the saturation level accumulated in the photodiode PD are output. The read signal charge (a signal obtained by adding the reset level and the signal level) is held in the capacitor C2 in FIG. A 10-bit AD conversion is performed on the read signal charges by generating a triangular wave as a reference waveform in the first 0.5H period of the horizontal scanning period. Digital data obtained by AD conversion is held in the latch circuit 15 and input to the line memory MSH16 after AD conversion is completed.

  The second reading operation from the pixel unit 12 is performed after 0.5H of the first time (t4). As in the first time, the reset level when the reset pulse RESETn is set to the “L” level after the reset pulse RESETn is set to the “H” level is taken into the capacitor C1 of FIG. Then, the signal charge remaining in the photodiode PD is output by setting the read pulse READn to the high voltage Vh. This read signal is a signal obtained by adding the reset level and the signal level, and is held in the capacitor C2 of the CDS circuit 13 (FIG. 2). With respect to this read signal, a triangular wave is generated as a reference waveform during the 0.5H period in the latter half of the horizontal scanning period, and 10-bit AD conversion is performed. Digital data obtained by AD conversion is held in the latch circuit 15 and input to the line memory MSL 17 after AD conversion is completed.

  In the next one horizontal scanning period, 10-bit digital signals SH and SL (OUT0 to OUT9) are simultaneously output from the two line memories MSH and MSL16 and 17, and the two signals in units of pixels are added to form one signal. Synthesizing. In this operation, by adding the two signals, the signal level is increased to 11 bits, and the dark level is added to 128 LSB. At this time, random noise is also averaged, so that the SNR can be improved. Also, the signal resolution increases from 10 bits to 11 bits. When operating at a high speed, the operating frequency can be doubled by performing a 9-bit ADC operation. The resolution of the signal at this time is 10 bits, which is the same as the conventional one.

  4A to 4D respectively show a cross-sectional view and a potential diagram of the pixel portion 12 at each time point t1 to t4 in the operation timing chart shown in FIG.

  In this example, an n-type impurity diffusion region 42 is provided on a p-type semiconductor substrate 41 to form a photodiode PD, and the surface of the n-type impurity diffusion region 42 is shielded by a p-type impurity diffusion region 43. As a result, the embedded photodiode PD with small scratches and dark unevenness is formed. The detection unit FD is formed of an n-type impurity diffusion region 44, and functions as a source and drain region of the read transistor (read gate) Td together with the n-type impurity diffusion region 41 of the photodiode PD.

  A gate electrode 45 made of polysilicon is provided on the substrate between these n-type impurity diffusion regions 41 and 44 with a gate insulating film (not shown) interposed therebetween. A read pulse READ is supplied to the gate electrode 45. An n-type impurity diffusion region 46 is provided adjacent to the n-type impurity diffusion region 44 as the detection unit FD. The n-type impurity diffusion region 46 functions as a drain region of a reset transistor (reset gate) Tc, and the n-type impurity diffusion region 44 of the detection unit FD functions as a source region.

  A drain voltage VD (= 2.8 V, for example, VDD) is applied to the drain region. A gate electrode 47 made of polysilicon is provided on the substrate 41 between the n-type impurity diffusion regions 44 and 46 with a gate insulating film (not shown) interposed therebetween. A reset pulse RESET is supplied to the gate electrode 47. The reset transistor Tc can reset the detection unit FD to the drain voltage VD.

  The accumulation of signal charges starts from time t0. When light is incident on the photodiode PD, signal charges corresponding to the amount of incident light are generated and accumulated by photoelectric conversion. This accumulation operation is continued at times t1 and t2 (FIGS. 4A and 4B). At time t3 (FIG. 4C), in order to read out the accumulated signal charges, first, a reset pulse RESET is applied to reset the detection unit FD to the potential of the power supply voltage VD = 2.8V. Next, a read pulse READ of the voltage Vm is applied to the gate electrode 45, and the signal charge accumulated about ½ or more of the saturation capacity of the photodiode PD part is read to the detection part FD. Similarly, at time t4 (FIG. 4D), a reset pulse RESET is applied to the gate electrode 47 to reset the detection unit FD to the potential of the power supply voltage VD = 2.8V.

  Next, a read pulse READ of voltage Vh is applied to the gate electrode 45 to transfer the signal charge remaining in the photodiode PD portion to the detection portion FD and read it out.

  The storage capacitor Cpd of the photodiode PD unit is designed to be larger than the capacitor Cfd of the detection unit FD. Thus, by increasing the storage capacity of the photodiode PD part, the number of saturated electrons can be increased and the SNR at the time of light can be improved. If the number of saturated electrons is doubled, an optical shot is generated at the square root of the signal, so the SNR can be improved by 3 dB.

  On the other hand, by reducing the capacitance Cfd of the detection unit FD, a large voltage can be generated even with a small signal charge. For this reason, the influence of the noise after the source follower circuit can be reduced. If this conversion gain is doubled, the influence of circuit noise in the subsequent stage can be reduced to ½.

  In a fine pixel of 2 μm or less, the conversion gain is increased by forming the detection portion small, and the SNR with low illuminance can be improved by reducing the influence of noise generated in the subsequent stage. In addition, since the area of the photodiode PD can be increased by reducing the detection unit FD, the number of saturated electrons can be increased from this point. This makes it possible to satisfy both a demand for increasing the number of saturated electrons and a demand for improving the SNR at low illuminance, which were difficult in the past.

  With the relationship between the capacitances Cpd and Cfd as described above, if a large amount of signal charge accumulated in the photodiode PD portion is read to the detection portion FD at once, the signal charge overflows from the detection portion FD and flows back into the photodiode PD. Or a problem of spreading to the surrounding photodiode PD occurs. However, in the present embodiment, the signal charge is read out twice, so that such a problem can be prevented.

  In the present embodiment, the method of reading the signal charge by dividing it into two parts has been shown, but it is also possible to read out the signal charge divided into a plurality of times of three or more. Also, the synthesis process of the two signals can be performed during the ADC operation, and can be realized by providing an adder circuit in the previous stage of the ADC. Furthermore, processing other than addition may be performed.

[Second Embodiment]
FIG. 5 is a diagram for explaining a solid-state imaging device according to the second embodiment of the present invention, and shows another configuration example of the column type ADC shown in FIG. The ADC 27 has an addition function, and also performs a synthesis process during the ADC operation, and the added digital signals OUT0 to OUT9 are output from the line memory 28.

  Vertical signal lines VLIN are respectively connected to the columns of the cells (pixels) 22, and one ends of these vertical signal lines VLIN are respectively connected to one input terminal of the comparator circuit COMP3. The other input terminal of the comparator circuit COMP3 is commonly connected to the VREF generation circuit 32, and a reference waveform is applied thereto. Then, when the voltage of the vertical signal line VLIN becomes equal to the voltage of the reference waveform, the output of the comparator circuit COMP3 changes from 0 to 1, for example. An up / down (U / D) counter 29 is connected to each output terminal of the comparator circuit COMP3. The U / D counter 29 performs up-counting or down-counting based on the clock signal CK. When the output of the comparator circuit COMP3 changes, the U / D counter 29 stops the count operation and stores this count value in the line memory 28.

  FIG. 6 shows a timing chart of the addition operation of the column type ADC shown in FIG. First, the detection unit FD is reset by a reset pulse RESETn. Thereafter, by setting the address pulse ADRESn to the “H” level, this reset level is output to the vertical signal line VLIN. The output signal is compared with the output voltage of the VREF generation circuit 32 by the comparator circuit COMP3. At this time, the U / D counter 29 counts down. When the voltage of the vertical signal line VLIN becomes equal to the output voltage of the VREF generation circuit 32, the U / D counter 29 stops counting.

  Next, the pixel unit 12 applies a voltage Vm as a read pulse READn, thereby reading about half of the signal accumulated in the PD unit at the time of saturation of the PD unit and converting it into a voltage by the detection unit FD. Output to the signal line VLIN. The output signal is compared with the output voltage of the VREF generation circuit 32 by the comparator circuit COMP3. At this time, the U / D counter 29 counts up. When the voltage of the vertical signal line VLIN and the voltage of the VREF generation circuit 32 become the same, the U / D counter 29 stops counting. By the down-counting and up-counting operations, fluctuations after the reset of the detection unit FD can be canceled from the output signal. Therefore, only the signal component is obtained as the count value.

  Similarly, in the second half of one horizontal period HP, the detection unit FD is reset again with the reset pulse RESETn. This reset level is output to the vertical signal line VLIN by setting the address pulse ADRESn to the “H” level. The output signal is compared with the output voltage of the VREF generation circuit 32 by the comparator circuit 29. At this time, starting from the count value obtained first, the U / D counter 29 counts down. When the voltage of the vertical signal line VLIN becomes equal to the output voltage of the VREF generation circuit 32, the U / D counter 29 stops counting.

  Next, the pixel unit 12 applies the voltage Vh as the read pulse READn, so that the signal charge left unread in the photodiode PD unit is transferred to the detection unit FD and read, and converted into a voltage by the detection unit FD. Output to the vertical signal line VLIN. The output signal is compared with the VREF voltage by the comparator circuit COMP3. At this time, the U / D counter 29 counts up. When the voltage of the vertical signal line VLIN becomes equal to the output voltage of the VREF generation circuit, the U / D counter 29 stops counting. In this way, the signal charge of the photodiode PD can be divided and read, and the addition operation can be performed.

  At the end of one horizontal period HP, the count value obtained by performing the same ADC operation in each column is simultaneously transferred to the line memory 28 as Vsig. Then, it is sequentially read out in the next one horizontal period HP, and is output from the image sensor chip after signal processing.

[Third Embodiment]
FIGS. 7A to 7D are diagrams for explaining a solid-state imaging device according to the third embodiment of the present invention, and show another configuration example of the cell (pixel) 22. 1 and 2, the pixel configuration of one pixel and one cell in which one output circuit is provided in one photodiode PD has been described as an example.

  On the other hand, the cell shown in FIG. 7A has a pixel configuration of two pixels and one cell in which one output circuit is provided for two photodiodes PD. That is, the cell 51 is composed of five transistors (row selection transistor Ta, amplification transistor Tb, reset transistor Tc, readout transistors Td1, Td2) and two photodiodes (photoelectric conversion means) PD1, PD2. Are supplied with pulse signals ADRESn, RESETn, READn, READn + 1, respectively.

  The current paths of the transistors Ta and Tb are connected in series between the power supply VDD and the vertical signal line VLIN. A pulse signal (address pulse) ADRESn is supplied to the gate of the transistor Ta. The current path of the transistor Tc is connected between the power supply VDD and the gate (detector FD) of the transistor Tb, and a pulse signal (reset pulse) RESETn is supplied to the gate. One end of the current path of the transistor Td1 is connected to the detection unit FD, and a pulse signal (readout pulse) READn is supplied to its gate. The cathode of the photodiode PD1 is connected to the other end of the current path of the transistor Td1, and the anode of the photodiode PD1 is grounded. Further, one end of the current path of the transistor Td2 is connected to the detection unit FD, and a read pulse READn + 1 is supplied to the gate thereof. The other end of the current path of the transistor Td2 is connected to the cathode of the photodiode PD2, and the anode of the photodiode PD2 is grounded.

  In the configuration as described above, the relationship between the sum Cspd of the storage capacitors of the photodiodes PD1 and PD2 and the capacitor Cfd of the detection unit FD is “capacitance Cspd> capacitance Cfd”.

  FIG. 7B shows a pixel configuration of four pixels and one cell in which one output circuit is provided for the four photodiodes PD1, PD2, PD3, and PD4. That is, the cell 52 includes seven transistors (row selection transistor Ta, amplification transistor Tb, reset transistor Tc, readout transistors Td1, Td2, Td3, Td4) and four photodiodes (photoelectric conversion means) PD1, PD2, PD3, PD4. The cell 52 is supplied with pulse signals ADRESn, RESETn, READn, READn + 1, READn + 2, and READn + 3, respectively.

  Even in this configuration, the relationship between the sum Csspd of the storage capacitors of the photodiodes PD1, PD2, PD3, and PD4 and the capacitor Cfd of the detection unit FD is “capacitance Csspd> capacitance Cfd”.

  Further, FIG. 7C shows a pixel configuration of one pixel and one cell, but a pixel configuration in which the row selection transistor is omitted. One cell 53 includes three transistors (amplification transistor Tb, reset transistor Tc, and read transistor Td) and a photodiode (photoelectric conversion means) PD, and pulse signals RESETn and READn are supplied to the cell 53, respectively.

  The current path of the transistor Tb is connected in series between the power supply VDD and the vertical signal line VLIN. The current path of the transistor Tc is connected between the power supply VDD and the gate (detector FD) of the transistor Tb, and a reset pulse RESETn is supplied to the gate. One end of the current path of the transistor Td is connected to the detection unit FD, and a read pulse READn is supplied to the gate thereof. The cathode of the photodiode PD is connected to the other end of the current path of the transistor Td, and the anode of the photodiode PD is grounded. The storage capacitor Cpd of the photodiode PD and the capacitor Cfd of the detection unit FD have a relationship of “capacitance Cpd> capacitance Cfd”.

  The present invention can also be applied to a pixel configuration of one pixel and one cell as shown in FIG. Since the photodiode PD and the detection unit are connected, the storage capacitor Cpd and the detection unit capacitor Cfd have the same capacitance. That is, “capacitance Cpd = capacitance Cfd”. This pixel configuration is a pixel configuration in which the readout transistor is omitted. The cell 54 includes three transistors (row selection transistor Ta, amplification transistor Tb, reset transistor Tc) and photodiode (photoelectric conversion means) PD, and pulse signals ADRESn and RESETn are supplied to the cell 54, respectively.

  The current paths of the transistors Ta and Tb are connected in series between the power supply VDD and the vertical signal line VLIN. An address pulse ADRESn is supplied to the gate of the transistor Ta. The current path of the transistor Tc is connected between the power supply VDD and the gate (detector FD) of the transistor Tb, and a reset pulse RESETn is supplied to the gate. Further, the cathode of the photodiode PD is connected to the detection unit FD, and the anode of the photodiode PD is grounded.

  In particular, when the VDD voltage is lowered to, for example, 1.5V (usually 2.8V), the dynamic range of the source follower circuit composed of the transistors Ta and Tb is lowered. For this reason, all the signals converted into voltages by the detection unit FD cannot be output. By applying the present invention to such a problem, it is possible to divide the signal charge accumulated in the photodiode and read it out to the detection unit so that it can be output within the dynamic range of the source follower circuit.

  This cell configuration can be realized by switching the voltage of the reset pulse RESET to the voltage Vm or the voltage Vh. Further, the present invention can also be applied when the power supply voltage in FIGS. 7A, 7B, and 7C is lowered.

  The cell (pixel) is not limited to the above-described example, and can be applied to a further modified pixel configuration.

  As described above, according to one aspect of the present invention, in the amplification type CMOS image sensor, high sensitivity can be realized by increasing the voltage conversion gain by reducing the capacitance of the detection unit. In this high-sensitivity structure, since the capacitance of the detection unit is smaller than the storage capacitance of the photodiode, the signal charge accumulated in the photodiode is divided and read out, and the signals divided in the subsequent stage are added to form one signal. . As a result, an image sensor with high sensitivity and a wide dynamic range can be realized.

  Therefore, it is possible to obtain a solid-state imaging device that can secure SNR at low illumination while increasing the number of saturated electrons.

  Although the present invention has been described using the first to third embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention in the implementation stage. It is possible. Each of the above embodiments includes inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in each embodiment, at least one of the issues described in the column of the problem to be solved by the invention can be solved, and is described in the column of the effect of the invention. In the case where at least one of the above effects can be obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.

  DESCRIPTION OF SYMBOLS 11 ... Sensor core part, 12 ... Pixel part, 13 ... Column type noise cancellation circuit (CDS), 14 ... Column type analog-digital converter (ADC), 15 ... Latch circuit, 16 ... Line memory (MSGH), 17 ... Line memory ( MSGL), 18 ... horizontal shift register, 19 ... adder (combining means), 20 ... signal processing circuit, 21 ... lens, 22, 51, 52, 53, 54 ... cell (pixel), 23 ... pulse amplitude control circuit, 24... Pulse selector circuit (selector), 25... Vertical register for reading signals (VR register), 26... Vertical register for controlling accumulation time (ES register), 27... ADC, 28. ... Timing generator (TG), 31 ... Bias generation circuit (bias 1), 32 ... VREF generation circuit, 33 Serial interface (serial I / F), 34 ... command decoder, PD, PD1, PD2, PD3, PD4 ... photodiode (photoelectric conversion means), FD ... detector, Ta ... row selection transistor, Tb ... amplification transistor, Tc ... Reset transistor, Td: Read transistor, COMP1, COMP2, COMP3: Comparator circuit.

Claims (5)

A photodiode that photoelectrically converts an optical signal to generate a signal charge, a reading unit that reads the signal charge generated by the photodiode to a detection unit, and a detection that detects the signal charge by converting it to a voltage corresponding to the amount of charge A pixel portion two-dimensionally arranged on a semiconductor substrate, a cell comprising: a means; an output means for outputting a voltage detected by the detection means; and a reset means for resetting the detection means;
Exposure time control means for controlling the exposure time for photoelectric conversion by the photodiode,
The exposure time control means includes a read pulse amplitude control means for dividing and reading the signal charges accumulated in the photodiode, and a combining means for combining the divided and read signals into one signal. A solid-state imaging device.   The solid-state imaging device according to claim 1, wherein a storage capacity of the photodiode is larger than a capacity of the detection unit.   An AD conversion means for AD converting the signal voltage detected by the detection means and a storage means for storing a digital signal obtained by AD conversion by the AD conversion means are further provided, corresponding to the divided and read signals 2. The solid-state imaging device according to claim 1, wherein AD conversion is performed a plurality of times, and the AD signal is combined by the combining unit.   The solid-state imaging device according to claim 1, wherein the read pulse amplitude control unit controls the first read amplitude to be smaller than the second read amplitude.   5. The solid-state imaging device according to claim 4, wherein the detection unit performs control so that only the second signal charge is detected after resetting the signal charge read first time by the reset unit.

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