JP2007235488A - Imaging element device and its signal processing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging element device providing a detecting signal displaying an accurate imaging state without being subject to the effect of the saturation of the quantity of charges stored, and without being subject to the effect of a smear phenomenon or the like. <P>SOLUTION: Whether the quantity of charges stored in a photo diode (PD) 11 exceeds a specified level is detected by a comparison circuit 23. When the quantity of charges stored exceeds the specified level, a switch 22 is closed, and charges stored in the PD 11 are discharged, and detections by the comparison circuit 23 are counted by a counter 32. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to an image sensor device and a signal processing circuit thereof.
More specifically, the present invention relates to signal processing of an image sensor device using a charge storage type device such as a charge coupled (CDD) type device or a C-MOS sensor.

An imaging device such as a digital camera or a video camera device uses a CCD element, a C-MOS sensor, or the like as an imaging element.
The imaging element has a plurality of CCD elements or a plurality of C-MOS elements, and converts the light received by each element into an electrical signal and accumulates it. Therefore, the image sensor is provided with an element that performs photosensitivity and charge accumulation, such as a photodiode. The amount of charge accumulated in the image sensor represents the intensity (amplitude) of the received light.
When the detection signal of the image sensor is taken out, the voltage signal accumulated by the photodiode is transferred and used in the subsequent circuit.
The subsequent circuit includes a selection circuit that selects an analog voltage signal detected by a plurality of photodiodes constituting the image sensor, an A / D conversion circuit that converts the analog voltage signal selected by the selection circuit into a digital signal, and A / A frame memory for storing the imaging signal converted by the D conversion circuit as image data in one frame, a signal circuit for displaying the image data stored in the frame memory on, for example, a liquid crystal display, or the like There is.

Hereinafter, a CCD element will be exemplified and described as a typical imaging element.
In the imaging device, as illustrated in FIGS. 4A and 4B, a reset pulse is output from the control circuit at a predetermined cycle, for example, at a cycle of one frame period, and the photodiode constituting the CCD device. The amount of charge accumulated in the image sensor is transferred and captured by the circuit at the subsequent stage of the image sensor described above.
As illustrated in FIGS. 4A and 4B, when the amount of light received by the photodiode is small, the charge accumulation amount is not legal. However, when strong light is received, the charge accumulation amount of the photodiode is saturated, and there is a problem that an accurate light reception amount is not shown.

  Furthermore, an image pickup device using a CCD device has a transfer path, and a pseudo signal called smear is generated due to leakage of electric charge, and there is a problem that an accurate image pickup state is not shown.

Patent Document 1 discloses a technique for activating an imaging device by scanning with a pulse bias signal in order to convert infrared light into image data.
Japanese National Patent Publication No. 11-514084

  The technique described in Patent Document 1 still cannot overcome the above-described problem described with reference to FIGS. 4 (A) and 4 (B).

An object of the present invention is to provide an image sensor device that provides a detection signal indicating an accurate imaging state that is not affected by saturation of the charge accumulation amount and is not affected by a smear phenomenon or the like.
It is another object of the present invention to provide a signal processing circuit used for such an image sensor device.

  According to the present invention, a charge storage type image sensor, a comparison circuit, a first switch element that discharges charges accumulated in the charge storage type image sensor, and an output signal of the charge storage type image sensor are used as the comparison circuit. The first switch element selectively switches to the second switch element, and the output signal of the charge storage image sensor input to the comparison circuit via the second switch element is a predetermined value. When the level is exceeded, the second switch element is opened, and the first switch element is closed, and the reset circuit that releases the charge accumulated in the charge storage type image sensor is cleared at a predetermined cycle. A counter circuit that counts pulses output when the output signal of the charge storage type image sensor input to the comparator circuit exceeds a predetermined level. It is provided.

According to the invention, the comparison circuit, the first switch element for discharging the charge accumulated in the charge storage type image sensor, and the output signal of the charge storage type image sensor are selectively guided to the comparison circuit, The first switch element performs reverse switching operation, and when the output signal of the charge storage type image sensor input to the comparison circuit via the second switch element and the second switch element exceeds a predetermined level, There is provided a signal processing circuit of an image sensor device having a reset circuit that opens a second switch element and closes the first switch element to release charges accumulated in the charge accumulation type image sensor. .
Preferably, the signal processing circuit is cleared at a predetermined cycle, and the comparison circuit counts pulses output when the output signal of the charge storage type image pickup element input to the comparison circuit exceeds a predetermined level. A counter circuit is included.

  In the present invention, the comparison circuit detects before the charge storage type image sensor is saturated, and resets it before the charge storage amount of the charge storage type image sensor is saturated. The amount of charge accumulated so far is counted by a counter circuit. Therefore, no matter what strong light enters the image sensor, the charge storage type image sensor is not saturated and can be detected accurately.

First Embodiment A first embodiment of an image sensor device and a signal processing circuit according to the present invention will be described with reference to FIGS.
The image sensor device according to the embodiment of the present invention includes an image sensor device 1 and a signal processing unit 3.
The image sensor device of the present invention includes all the configurations illustrated in FIG.
On the other hand, the signal processing circuit of the present invention means, in the image pickup device 1, the preprocessing circuit unit 20 excluding the CCD portion 10, or the unit that combines the preprocessing circuit unit 20 and the signal processing unit 3. .

The image sensor device 1 includes a CCD portion 10 as an example of an image sensor and a preprocessing circuit unit 20.
In the present embodiment, a CCD element is described as an example of the imaging element, but the same applies to other charge storage type imaging elements such as a C-MOC imaging element.
In FIG. 1, a single photodiode (PD) 11 is illustrated as a representative CCD element in the CCD portion 10. The photodiode (PD) 11 converts received light into electric charge and accumulates it.
The preprocessing circuit unit 20 includes a first switch 21, a second switch 22, a comparison circuit 23, a waveform shaping circuit 24, and a reset circuit 25.
The first switch 21 and the second switch 22 are preferably analog switches using transistors.

The signal processing unit 3 includes a control circuit 31, a counter 32, and a compensation circuit 33.
The compensation circuit 33 is not essential. Details will be described later.

The circuit operation illustrated in FIG. 1 will be described with reference to FIGS.
The clear (reset) operation control circuit 31 outputs the first clear signal CLR1 to the counter 32 and the second clear signal CLR2 to the reset circuit 25 at a predetermined period, for example, every frame of the image. As a result, the counter 32 clears the count value. Similarly, the reset circuit 25 opens the first switch 21 by the first reset signal RST1 in response to the first clear signal CLR1, so that the charge accumulation amount of the PD 11 is not input to the comparison circuit 23, and the second reset signal The second switch 22 is closed by RST2, and the charge accumulation amount of the PD 11 is discharged.

The reset circuit 25 is basically configured so that when the first switch 21 and the second switch 22 are in reverse operation, for example, when the first switch 21 is in a closing operation, the second switch 22 is in an opening operation. 1 reset signal RST1 and 2nd reset signal RST2 are output.
In the case of analog switches using transistors as the first switch 21 and the second switch 22, the first reset signal RST1 and the second reset signal RST2 are logic signals that are applied to the gates of the transistors to turn on / off the transistors.

The first clear signal CLR1 output from the control circuit 31 has a pulse width of the time when the count value of the counter 32 is cleared, and the second clear signal CLR2 is a pulse that triggers the reset circuit 25.
The second reset signal RST2 output from the reset circuit 25 is a signal of an effective level, for example, a high level during the period when the PD 11 is completely discharged.

When the pulse time of the first clear signal CLR1 ends, the counter 32 can count.
When the pulse time of the second reset signal RST2 elapses, the second switch 22 is opened and the PD 11 is not discharged, the first switch 21 is closed and converted into electric charge by the PD 11, and the accumulated PD detection signal S11. Is input to the comparison circuit 23.
As illustrated in FIG. 2A, when the charge accumulation amount of the PD 11 increases as light is received, the signal level of the PD detection signal S 11 increases and is input to the comparison circuit 23 via the first switch 21. The FD detection signal S21 increases.
When the FD detection signal S21 input to the comparison circuit 23 reaches the reference voltage _VREF , the comparison circuit 23 outputs an effective level, for example, a high level pulse signal.
The waveform shaping circuit 24 shapes the pulse signal output from the comparison circuit 23 in order to stabilize the circuit operations of the reset circuit 25 and the counter 32 described later. The waveform shaping pulse signal S24 from the waveform shaping circuit 24 is output to the reset circuit 25 and the counter 32.

  The reset circuit 25 outputs a first reset signal RST1 for opening the first switch 21, and outputs a second reset signal RST2 for closing the second switch 22. As a result, the charge accumulation amount of the PD 11 is discharged, and the charge accumulation amount of the PD 11 is not input to the comparison circuit 23.

The counter 32 counts the waveform shaping pulse signal S24 output from the waveform shaping circuit 24. For example, the counter 32 increases the count value by one. The count value of the counter 32 indicates how many times the charge accumulation amount of the PD 11 is discharged in a predetermined period, for example, in one frame period.
For example, in the illustration of FIG. 2A, the charge accumulation amount of the PD 11 is discharged three times in the first frame, and the charge accumulation amount of the PD 11 is discharged five times in the second frame. Yes. As the count value of the counter 32 increases in the predetermined period, the intensity of light received by the PD 11 is stronger as shown in FIG.

In the present embodiment, PD11 is not saturated by setting the reference voltage V _REF to a value before PD11 is saturated. Therefore, no matter how strong light is irradiated, the PD 11 does not saturate.

The reference voltage V _REF can be set to an appropriate value lower than the level at which the PD 11 is saturated.
For example, when the reference voltage V _REF is set to a low value, the number of times that the PD 11 is reset (discharged) increases, but the detection resolution in the counter 32 increases. On the other hand, when the reference voltage V _REF is set to a high value, the number of times that the PD 11 is reset (discharged) decreases, but the detection resolution in the counter 32 decreases.

When the next frame is reached, the frame end control circuit 31 causes the count value of the counter 32 to be read by a subsequent circuit (not shown).
When the input of the count value of the counter 32 is completed by the lower house path, the control circuit 31 outputs the first clear signal CLR1 and the second clear signal CLR2 and restarts the detection operation of the next frame.

Variant will be described below compensation circuit 33.

The first example compensation circuit 33 of the compensation circuit 33 compensates the count value of the counter 32.
The count value of the counter 32 only counts how many times the comparison circuit 23 has accumulated the charge storage amount of the PD 11 beyond the reference voltage V _REF .
As illustrated in FIG. 2A, there are many cases where the number of times the charge accumulation amount of the PD 11 exceeds the reference voltage V _REF is small within one frame. These times may not necessarily be proportional. Therefore, the compensation circuit 33 compensates the count value of the counter 32 for the count value of the counter 32. Compensation can be performed by a table lookup method by holding a compensation count corresponding to the count value as a table.
Note that the processing of the compensation circuit 33 can also be performed in a signal processing circuit in the subsequent stage, not shown.

Second Example of Compensation Circuit 33 Preferably, the compensation circuit 33 inputs the first clear signal CLR1 from the control circuit 31, and calculates the time when the count value of the counter 32 immediately before the first clear signal CLR1 is inputted is updated. Measure, estimate the amount of charge accumulated in PD 11 during that period, and add to the count value of counter 32. As a result, the comparison circuit 23 immediately before the first clear signal CLR1 is input becomes the reference voltage V _REF.
It is possible to estimate the amount of charge accumulated in the PD 11 that has not been accumulated until the value exceeds.
When the compensation circuit 33 is operated in this way, the charge accumulation amount of the PD 11 can be detected with high resolution even if the reference voltage V _REF is increased and the number of discharges of the PD 11 is reduced.

The preprocessing circuit unit 20 and the signal processing unit 3 of the present embodiment described with reference to FIG. 1 have a simple configuration.
In particular, the signal processing circuit described with reference to FIG. 1 is output as a digital count value of the counter 32 or a digital value compensated by the compensation circuit 33. As a result, in addition to the above-described advantages, there is an advantage that an A / D conversion process is not required in a subsequent circuit and an advantage that it is not easily affected by noise encountered when an analog signal is transmitted.

Detailed Circuit Configuration Example Since the preprocessing circuit unit 20 is usually disposed in the vicinity of the CCD portion 10, a simple circuit configuration is desirable.
In particular, it is desirable that the first switch 21, the second switch 22, the comparison circuit 23, the waveform shaping circuit 24, and the reset circuit 25 connected in correspondence with the PD 11 have a simple circuit configuration.
Since the first switch 21 and the second switch 22 can be configured as a switch circuit using a transistor, they are very simple circuits.
The comparison circuit 23 can be composed of, for example, one transistor 231 and one level conversion circuit 232 illustrated in FIG. The level conversion circuit 232 is a circuit including, for example, a resistor that converts the reference voltage V _REF into a level, for example, to the threshold value of the transistor 231. With such a circuit configuration, the comparison circuit 23 is also a simple circuit.
The waveform shaping circuit 24 is not essential. Therefore, the identification signal of the comparison circuit 23 can be used in the counter 32 and the reset circuit 25.
The reset circuit 25 can be composed of one inverter. For example, an inverter is used as a circuit that inverts the identification signal of the comparison circuit 23.

  Since the counter 32 in the signal processing unit 3 is also provided corresponding to the PD 11, a simple circuit is preferable. For example, it can be realized by a counter in which registers of about 8 bits are combined.

The embodiment of the present invention is not limited to the above-described example.
Of course, the CCD portion 10 may be replaced with another charge storage type imaging device such as a C-MOS sensor.

FIG. 1 shows a circuit configuration of an embodiment of an image sensor device of the present invention. FIG. 2 is a signal waveform diagram in the image sensor device illustrated in FIG. FIG. 3 is a diagram showing a circuit configuration example of the comparison circuit illustrated in FIG. FIG. 4 is a signal waveform diagram in a conventional image sensor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Imaging device 10 ... CCD part, 11 ... Photodiode (PD)
20: Pre-processing circuit unit,
21, 22 ... switch, 23 ... comparison circuit,
24 ... Waveform shaping circuit, 25 ... Reset circuit
RST1, RST2 ... first reset signal 3 ... signal processing unit 31 ... control circuit
CLR1, CLR2 ... Clear signal 32 ... Counter 33 ... Compensation circuit

Claims (10)

A charge storage type imaging device;
A comparison circuit;
A first switch element for discharging the charge stored in the charge storage type image sensor;
A second switch element that selectively conducts an output signal of the charge storage type image sensor to the comparison circuit, the first switch element performs a reverse switching operation;
When the output signal of the charge storage type image sensor input to the comparison circuit via the second switch element exceeds a predetermined level, the second switch element is opened, and the first switch element is A reset circuit that closes and releases the charge accumulated in the charge storage type imaging device;
And a counter circuit that counts pulses output when the output signal of the charge storage type image sensor input to the comparator circuit exceeds a predetermined level, which is cleared at a predetermined cycle. A compensation circuit for compensating the count value of the counter circuit is further provided at the subsequent stage of the counter circuit.
The image sensor device according to claim 1. A control circuit;
The control circuit outputs a clear signal to the counter circuit for each frame period as the predetermined period.
The image sensor device according to claim 1. The control circuit outputs a clear signal to the counter circuit at each predetermined cycle, opens the second switch element, and closes the first switch element.
The image sensor device according to claim 3. The charge storage type imaging device includes a CCD imaging device,
The image sensor device according to claim 1. The charge storage type image sensor includes a C-MOS image sensor,
The image sensor device according to claim 1. A comparison circuit;
A first switch element that discharges charges accumulated in the charge storage type image sensor;
A second switch element that selectively conducts an output signal of the charge storage type image sensor to the comparison circuit, the first switch element performs a reverse switching operation;
When the output signal of the charge storage type image sensor input to the comparison circuit via the second switch element exceeds a predetermined level, the second switch element is opened, and the first switch element is A signal processing circuit of an image sensor device, comprising: a reset circuit that closes and releases the charge accumulated in the charge storage image sensor. The signal processing circuit includes a counter circuit that counts pulses output when the output signal of the charge storage type image sensor input to the comparison circuit exceeds a predetermined level, which is cleared at a predetermined cycle. Have
The signal processing circuit according to claim 7. A compensation circuit for compensating the count value of the counter circuit is further provided at the subsequent stage of the counter circuit.
The signal processing circuit according to claim 8. A control circuit;
The control circuit outputs a clear signal to the counter circuit for each frame period as the predetermined period.
The signal processing circuit according to claim 8 or 9.

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