JP6422073B2 - Ａ／ｄ変換回路 - Google Patents
Ａ／ｄ変換回路 Download PDFInfo
- Publication number
- JP6422073B2 JP6422073B2 JP2014159978A JP2014159978A JP6422073B2 JP 6422073 B2 JP6422073 B2 JP 6422073B2 JP 2014159978 A JP2014159978 A JP 2014159978A JP 2014159978 A JP2014159978 A JP 2014159978A JP 6422073 B2 JP6422073 B2 JP 6422073B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- conversion
- arithmetic
- analog
- tent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000006243 chemical reaction Methods 0.000 title claims description 177
- 238000013507 mapping Methods 0.000 claims description 103
- 238000004364 calculation method Methods 0.000 claims description 76
- 239000000284 extract Substances 0.000 claims description 2
- 238000012886 linear function Methods 0.000 claims description 2
- 238000011144 upstream manufacturing Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 15
- 230000004044 response Effects 0.000 description 7
- 238000004458 analytical method Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000005070 sampling Methods 0.000 description 6
- 230000010354 integration Effects 0.000 description 4
- 101100464779 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CNA1 gene Proteins 0.000 description 3
- 230000003321 amplification Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 230000003252 repetitive effect Effects 0.000 description 3
- 230000001174 ascending effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000013139 quantization Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000000739 chaotic effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000013016 damping Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
Images
Landscapes
- Analogue/Digital Conversion (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014159978A JP6422073B2 (ja) | 2014-08-06 | 2014-08-06 | Ａ／ｄ変換回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014159978A JP6422073B2 (ja) | 2014-08-06 | 2014-08-06 | Ａ／ｄ変換回路 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018106711A Division JP6633135B2 (ja) | 2018-06-04 | 2018-06-04 | テント写像演算回路及びａ／ｄ変換回路 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2016039418A JP2016039418A (ja) | 2016-03-22 |
| JP2016039418A5 JP2016039418A5 (https=) | 2016-10-13 |
| JP6422073B2 true JP6422073B2 (ja) | 2018-11-14 |
Family
ID=55530198
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014159978A Expired - Fee Related JP6422073B2 (ja) | 2014-08-06 | 2014-08-06 | Ａ／ｄ変換回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP6422073B2 (https=) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6762733B2 (ja) * | 2016-03-01 | 2020-09-30 | 東芝情報システム株式会社 | Ｄ／ａ変換装置及びｄ／ａ変換方法 |
| JP7019475B2 (ja) * | 2018-03-23 | 2022-02-15 | 東芝情報システム株式会社 | 乱数生成装置 |
| JP6633135B2 (ja) * | 2018-06-04 | 2020-01-22 | 東芝情報システム株式会社 | テント写像演算回路及びａ／ｄ変換回路 |
| JP7344000B2 (ja) * | 2019-04-05 | 2023-09-13 | 株式会社ミツトヨ | アナログ－デジタル変換器、アナログ－デジタル変換方法及び変位検出装置 |
| CN113972915B (zh) * | 2020-07-23 | 2024-07-16 | 中核核电运行管理有限公司 | 一种压水堆棒位测量系统格雷码信号整定阈值电路 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2306575A1 (fr) * | 1975-04-02 | 1976-10-29 | Nadler Morton | Procede et dispositif de conversion de signal electrique analogique en code binaire |
| JPS60127820A (ja) * | 1983-12-15 | 1985-07-08 | Matsushita Electric Ind Co Ltd | 縦続型ａ／ｄ変換器 |
| DE19506020A1 (de) * | 1995-02-22 | 1996-08-29 | Telefunken Microelectron | Faltungsverstärker für den Aufbau eines A/D-Umsetzers |
| US6163290A (en) * | 1999-07-13 | 2000-12-19 | Analog Devices, Inc. | Linearizing structures and methods for unity-gain folding amplifiers |
| JP4184921B2 (ja) * | 2002-11-06 | 2008-11-19 | 松下電器産業株式会社 | 確率型演算素子 |
| US7449967B2 (en) * | 2003-02-28 | 2008-11-11 | Panasonic Corporation | Probabilistic pulse generator and differential absolute value computing element and manhattan distance arithmetic unit using this |
| WO2011125296A1 (ja) * | 2010-04-01 | 2011-10-13 | 独立行政法人科学技術振興機構 | スケール付きβ写像に基づくデータコンバート方式 |
| WO2011125297A1 (ja) * | 2010-04-06 | 2011-10-13 | 独立行政法人科学技術振興機構 | 負のβ写像に基づくデータコンバート方式 |
-
2014
- 2014-08-06 JP JP2014159978A patent/JP6422073B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2016039418A (ja) | 2016-03-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10110242B2 (en) | Interleaving successive approximation analog-to-digital converter with noise shaping | |
| Siragusa et al. | Gain error correction technique for pipelined analogue-to-digital converters | |
| JP6422073B2 (ja) | Ａ／ｄ変換回路 | |
| US9160359B2 (en) | Analog-to-digital converter and analog-to-digital conversion method | |
| JP5795729B2 (ja) | 多チャネル量子化器および量子化の方法 | |
| EP3113366A1 (en) | Method for testing analog-to-digital converter and system therefor | |
| JP2015103856A (ja) | アナログ／ディジタル変換器及びアナログ／ディジタル変換方法 | |
| SE520277C2 (sv) | Införande av kalibreringssekvens hos en A/D-omvandlare | |
| JP5494273B2 (ja) | Ａｄ変換回路およびａｄ変換方法 | |
| JP6692574B2 (ja) | 一時記憶バッファ装置 | |
| JP6633135B2 (ja) | テント写像演算回路及びａ／ｄ変換回路 | |
| JP5094916B2 (ja) | パイプライン・ａｄ変換回路 | |
| JP4684028B2 (ja) | パイプラインａ／ｄ変換器 | |
| Del Corso et al. | A taxonomy of ADC architectures for ICT engineering curricula | |
| CN114337672B (zh) | 模数转换器及模数转换方法 | |
| CN111295843B (zh) | 具有至少三条采样信道的流水线模数转换器 | |
| KR20110090669A (ko) | 축차근사 레지스터형 아날로그-디지털 변환기 | |
| US20230116954A1 (en) | Analog-to-digital converter circuit | |
| Kunapareddy et al. | Performance-Driven Design of Flash-SAR Sub ranging ADC with Power Scaling Techniques | |
| Adsul et al. | Reconfigurable successive approximation register ADC and SAR-assisted pipeline ADC | |
| Sinha | Implementation of an 8-bit ADC using successive subtraction technique | |
| JP2019168963A (ja) | 乱数生成装置 | |
| JP2010226356A (ja) | Ａ／ｄ変換器およびその制御方法 | |
| US10566985B2 (en) | Method for analog-to-digital conversion of analog input signals | |
| Crasso | Background Calibration of a 6-Bit 1Gsps Split-Flash ADC. |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160823 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20160823 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20170502 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170711 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170906 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20180403 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180601 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20181009 |
|
| RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20181009 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20181009 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 6422073 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |