JP6406330B2 - Power supply - Google Patents

Description

  The present invention relates to a power supply apparatus having an inverter circuit that is supplied with DC power from a DC voltage source and outputs AC power to a resonant load having series resonance characteristics.

  A capacitive load configured to include an ozone generator, a plasma processing apparatus, and the like operates by receiving high-frequency power from a high-frequency power supply device. Generally, a high-frequency power supply device that supplies power to an ozone generator or the like is supplied with DC power from a DC power source and performs voltage adjustment, and DC power is supplied from the DCDC converter to perform DC-AC conversion. And an inverter circuit to be implemented.

  Here, the impedance when the capacitive load side is viewed from the high frequency power supply device may change. For example, in the case of an ozone generator, the capacitive load constituting the ozone generator changes in capacity according to the applied voltage, and is equivalent to the ratio of the discharge period to the period from the start to the end of voltage application. Act as capacity. When the impedance of the capacitive load changes, the frequency of the inverter circuit is set to a frequency higher than the resonance frequency determined by the equivalent capacity of the reactor and the capacitive load. Patent Document 1 describes a method of controlling electric power with a delay phase amount of an output current of an inverter circuit.

Japanese Patent No. 5681943

  When the output power is suppressed with a delayed phase (higher frequency), the power suppression associated with the power factor deterioration is used. However, since higher frequencies have the contradictory effect of increasing output power, power suppression is driven at a high frequency that deviates from the resonance frequency, leading to an increase in switching loss and a deterioration in power conversion efficiency. There is a problem. Therefore, when driving at a frequency near the lag phase of the resonance frequency, it is necessary to control the output voltage using a DCDC converter.

  The present invention has been made in view of the above problems, and it is a main object to realize a power conversion device only with an inverter while preventing deterioration of power conversion efficiency in output power control for a capacitive load. To do.

  The present configuration is a power supply device (20) having an inverter circuit (21) that is supplied with DC power from a DC voltage source (10) and outputs AC power to a capacitive load (31), wherein the inverter circuit Is connected to a transformer (Tr) having a primary coil (L1) having a center tap (CT) and a secondary coil (L2) magnetically coupled to the primary coil, and to both ends of the primary coil. The first switch (SW1) and the second switch (SW2), which are semiconductor switching elements, and the first diode (D1) and the second diode (D2) connected in antiparallel to the first switch and the second switch, respectively. The center tap is connected to one terminal of the DC voltage source, and the first switch and the second switch are the other of the DC voltage source. A push-pull type inverter circuit connected to a terminal of the resonance circuit having a secondary side conversion (Lsb) of leakage inductance between the primary and secondary sides of the transformer and a capacity of the capacitive load (30) A drive unit (40) that alternately drives the first switch and the second switch at a drive frequency close to or near the resonance frequency, and an output voltage of the inverter circuit and the drive frequency A calculation unit (40) that calculates a ratio between the output power that can be output from the inverter circuit and the target power that is a target value of the supply power to be supplied to the capacitive load. In this case, a time corresponding to the product of the predetermined cycle and the ratio calculated by the calculation unit is defined as an output period, and the first switch and the second switch are output over the output period. While the ON state of the switch alternately in the predetermined period, the period other than the output period and the stop period, over the stop period, to cut off the current flowing from the DC voltage source to the primary coil.

  A push-pull inverter circuit is applied to a power supply device that supplies power to a resonant load. Thereby, compared with a full bridge type inverter circuit, the number of switching elements and floating power supplies can be reduced, and the configuration can be simplified. Moreover, generation | occurrence | production of turn-on loss can be suppressed. Here, in the push-pull type inverter, there is a concern that a surge voltage is generated when an off operation is performed on the switch in a state where a forward current flows in the switch. Therefore, by setting the drive frequency so that the switch current has the same phase or the leading phase with respect to the drive signal, the switch current is set to a negative value when the first switch and the second switch are turned off. Thus, the surge voltage can be suppressed. That is, in the output power control with respect to the capacitive load, it is possible to realize the power conversion device only by the inverter while preventing the deterioration of the converter efficiency. In the case of a full-bridge inverter, when the switch current is turned off with a negative value in the lead phase, a recovery surge voltage is generated due to the recovery characteristics of the diode, so the drive frequency is set to the high frequency side with respect to the resonance frequency. On the other hand, in a push-pull inverter, when the switch current is turned off at a negative value in the lead phase, the diode recovers softly due to the transformer leakage inductance described above, so the recovery surge voltage is smaller than that of the full-bridge inverter. Become.

The figure showing the electric constitution of a 1st embodiment. The figure showing the change of the capacity | capacitance of a capacitive discharge load. The figure showing the flow of an electric current when a surge voltage arises. The timing chart showing the time change of the switch voltage, switch current, and drive signal when a surge voltage arises. 6 is a timing chart showing a time change of a load current, a switch current, and a drive signal when the switch current is in the same phase and a leading phase with respect to the drive signal. The figure showing the relationship between drive frequency and output electric power. The figure showing the intermittent output of 1st Embodiment. The flowchart showing the intermittent output process of 1st Embodiment. The figure showing the flow of exciting current in the equivalent circuit of a transformer. The timing chart when the exciting current becomes excessive when the output is resumed. The flowchart showing the switching process of the output period and stop period in 1st Embodiment. The timing chart showing the change of the exciting current at the time of performing control in a 1st embodiment. The timing chart showing the change of the excitation current at the time of performing control in a 2nd embodiment. The figure showing the electric constitution of 3rd Embodiment. The figure showing the electric constitution of 4th Embodiment. The timing chart showing the change of the voltage between terminals of a smoothing capacitor. The figure showing the modulation | alteration of the output voltage amplitude in this embodiment. The timing chart showing the change of the voltage between the terminals of a smoothing capacitor at the time of implementing control of a 4th embodiment. The figure showing each frequency component of output voltage Vout. The figure showing the electric constitution of a modification. The timing chart showing the change of the exciting current at the time of implementing control in a modification. The timing chart showing the change of the exciting current at the time of implementing control in a modification.

(First embodiment)
FIG. 1 shows an equivalent circuit of a power supply device 20 and a discharge load 31 to which power is supplied from the power supply device 20 in the present embodiment.

  The inverter circuit 21 constituting the power supply device 20 converts DC power supplied from the DC voltage source 10 into AC power, and outputs AC power to the resonant load 30 including the discharge load 31. The inverter circuit 21 is a push-pull type inverter circuit, and includes a smoothing capacitor Cin, a transformer Tr, a first switch SW1, a second switch SW2, a first diode D1, and a second diode D2.

  The smoothing capacitor Cin smoothes the voltage input from the DC voltage source 10 and suppresses the influence of voltage fluctuation due to the operation of the inverter circuit 21 on the output voltage of the DC voltage source 10. The transformer Tr includes a primary coil L1 and a secondary coil L2 that are magnetically coupled. In FIG. 1, the leakage inductance between the primary and secondary sides of the transformer Tr is represented as primary side leakage inductances Ls1 and Ls2. Further, the secondary side converted value of the leakage inductance between the primary and secondary sides of the transformer Tr is Lsb (not shown). Assuming that the winding ratio of the primary coil L1 and the secondary coil L2 is n, the secondary conversion value Lsb is Lsb = n ^ 2 · Ls1 when the current flows through the switch SW1, and the current flows through the switch SW2. Can be expressed as Lsb = n ^ 2 · Ls2. A center tap CT is provided at the midpoint of the primary coil L1. The center tap CT is connected to the positive electrode of the DC voltage source 10.

  The first switch SW1 and the second switch SW2 are connected to both ends (terminals P1, P2) of the primary coil L1. Each of the switches SW1 and SW2 is a semiconductor switching element, specifically, an N-channel MOS-FET. The switches SW1 and SW2 are collectively referred to as a switch SW.

  A first diode D1 and a second diode D2 are connected in antiparallel to the first switch SW1 and the second switch SW2, respectively. Diodes D1 and D2 are body diodes of the switches SW1 and SW2. The cathodes of the diodes D1, D2 are connected to the drains of the switches SW1, SW2, and the anodes of the diodes D1, D2 are connected to the sources of the switches SW1, SW2.

  The switches SW1 and SW2 are turned on when the driving signals gSW1 and gSW2 in the high state are input from the driver circuit 50, respectively, and are turned off when the driving signals gSW1 and gSW2 in the low state are input. Is done. The AC power is output from the inverter circuit 21 by alternately turning on the first switch SW1 and the second switch SW2.

  Specifically, when the first switch SW1 is turned on, the voltage of the DC voltage source 10 is applied to a portion between the center tap CT of the primary coil L1 and the terminal P1. When a voltage is applied to the primary coil L1 and a current flows, an induced current flows downward in the drawing (from the terminal P4 to the terminal P3) with respect to the secondary coil L2. When the second switch SW2 is turned on, the voltage of the DC voltage source 10 is applied to a portion between the center tap CT of the primary coil L1 and the terminal P2. When a voltage is applied to the primary coil L1 and a current flows, an induced current flows upward in the drawing (from the terminal P3 to the terminal P4) with respect to the secondary coil L2.

  The control device 40 acquires the detected value of the output voltage Vout (load voltage) of the inverter circuit 21 from the voltage sensor 42 and acquires the detected value of the output current Iout (load current) of the inverter circuit 21 from the current sensor 43. Then, the drive frequency fsw of the switches SW1 and SW2 is set based on the detection values of the sensors 42 and 43 and the required power of the discharge load 31. Then, the control device 40 outputs a command signal corresponding to the drive frequency fsw to the driver circuit 50. The driver circuit 50 outputs drive signals gSW1 and gSW2 to the gates of the switches SW1 and SW2 according to the command signal.

  Specifically, the discharge load 31 is an ozone generator, and an electrode protected by two plate-like dielectrics is provided with an air layer (discharge gap) in between. A ceramic substrate is provided on the surface opposite to the air layer. The discharge load 31 is a “capacitive discharge load”. The equivalent circuit of the discharge load 31 can be expressed as a series connection body of an air layer capacitance Cg that is a capacitance of a discharge gap and a dielectric capacitance Cp that is a capacitance of a dielectric.

  When the voltage applied to the discharge gap exceeds the discharge sustain voltage Va, barrier discharge occurs in the discharge gap. In the state where the barrier discharge is generated, the voltage of the discharge gap is maintained at the discharge sustain voltage Va. The characteristics of the discharge load 31 during discharge can be expressed as Zener diodes DT1, DT2 connected in parallel to the air layer capacitance Cg, having a breakdown voltage Va, and connected in opposite directions.

  The discharge load 31 has an equivalent capacitance C that changes according to the applied voltage. The equivalent capacitance C of the discharge load 31 is dominated by the air layer capacitance Cg in a region where the applied voltage is low, and is dominant in the region where the applied voltage is high.

  The characteristic of the equivalent capacity C of the discharge load 31 with respect to the applied voltage is shown using FIG. FIG. 2 shows a time change of the voltage Vb between the terminals of the discharge load 31 when the predetermined voltages Vb1 and Vb2 having a relationship of Vb1> Vb2> Va are applied to the discharge load 31.

  When the high voltage Vb1 is applied, the terminal voltage Vb increases from time T0 and exceeds the discharge sustain voltage Va at time Ta1. Thereby, barrier discharge is started from time Ta1. Thereafter, after the inter-terminal voltage Vb reaches the high voltage Vb1, the inter-terminal voltage Vb decreases due to discharge due to resonance. Since the inter-terminal voltage Vb falls below the discharge sustain voltage Va at time Ta4, the barrier discharge is stopped at time Ta4. Thereafter, the inter-terminal voltage Vb becomes 0 at time Ta5.

  When the low voltage Vb2 is applied, the inter-terminal voltage Vb increases from time T0 and exceeds the discharge sustain voltage Va at time Ta2. Thereby, barrier discharge is started from time Ta2. Thereafter, after the inter-terminal voltage Vb reaches the low voltage Vb2, the inter-terminal voltage Vb decreases due to discharge due to resonance. Since the inter-terminal voltage Vb falls below the discharge sustain voltage Va at time Ta3, the barrier discharge is stopped at time Ta3. Thereafter, the inter-terminal voltage Vb becomes 0 at time T5.

  Compared with the case where the high voltage Vb1 is applied, the rise of the inter-terminal voltage Vb is slow, so that when the low voltage Vb2 is applied, the start of the barrier discharge is slow (Ta2> Ta1). Further, since the apex of the inter-terminal voltage Vb is lower than when the high voltage Vb1 is applied, when the low voltage Vb2 is applied, the end of the barrier discharge is early (Ta4> Ta3). For this reason, the period during which the barrier discharge is maintained differs between when the high voltage Vb1 is applied and when the high voltage Vb1 is applied, and becomes longer when the high voltage Vb1 is applied.

  The capacity of the discharge load 31 during the period in which the barrier discharge is maintained is the dielectric capacity Cp. In addition, the capacity of the discharge load 31 during a period when no barrier discharge occurs is the pre-discharge equivalent capacity Cb, and the pre-discharge equivalent capacity Cb is given by the following equation.

Further, the equivalent capacity Ce of the discharge load 31 at the time of barrier discharge is expressed as follows: d is the ratio of the sustain period of the barrier discharge in the voltage application period (Ta0 to Ta5 in FIG. 2).

It can be expressed as.

  A resonant load 30 is constituted by a discharge load 31 that is a capacitive load and a secondary side converted value Lsb of a leakage inductance between the primary and secondary sides of the transformer Tr. The resonance frequency fr of the resonance load 30 changes with the change in the equivalent capacity C of the discharge load 31 described above.

  For this reason, the frequency of the current (load current Iout) flowing through the secondary coil L2 changes, and the frequency of the current flowing through the primary coil L1 (switch current Isw flowing through the switch SW) changes with the change in the frequency of the load current Iout. Change. Due to the change in the frequency fsw of the switch current Isw, a surge voltage is generated with respect to the switches SW1 and SW2, and there is a concern that the switches SW1 and SW2 may be damaged or a power loss may occur. The generation of a surge voltage accompanying the change in the frequency of the switch current Isw in the push-pull inverter circuit 21 will be described below.

  In FIG. 3, the current that flows when the first switch SW1 is in the on state is indicated by a one-dot chain line, and immediately after the first switch SW1 is turned off while the forward current is flowing to the first switch SW1. The flowing current is indicated by a broken line.

  As indicated by the alternate long and short dash line, in a situation where the first switch SW1 is turned on and a forward current flows through the first switch SW1, a current flows through the leakage inductance Ls1 of the primary coil L1, thereby causing leakage. Magnetic field energy is stored in the inductance Ls1. When the first switch SW1 is turned off in this state, a current flows from the leakage inductance Ls1 to the parasitic capacitance Coss of the first switch SW1, as indicated by a broken line. That is, the magnetic field energy accumulated in the leakage inductance Ls1 is accumulated as electric field energy in the parasitic capacitance Coss, and a surge voltage is generated. It is feared that a surge voltage is similarly generated when the second switch SW2 is turned off.

  FIG. 4 shows a surge voltage generated when the switch SW is turned off in a state where a forward current flows through the switch SW. When the switch current Isw is flowing in the positive direction (for example, 10 A), the drive signal gSW is changed from the high state to the low state and the switch SW is turned off. High voltage (surge voltage) is generated. Note that in a full-bridge inverter, even when a forward current is flowing, even if the switch is turned off, there is a return path due to the return diode, so no surge voltage is generated.

  FIG. 5 (a) shows a timing chart showing a time change of the load current Iout, the switch current Isw, and the drive signal gSW when the resonance frequency fr of the resonance load 30 and the drive frequency fsw of the switch SW coincide with each other. . The load current Iout does not depend on the drive frequency fsw but changes at the resonance frequency fr. Further, during the ON period of the switch SW, the switch current Isw operates at the same frequency as the load current Iout. When the resonance frequency fr and the drive frequency fsw coincide with each other, the switch SW off time coincides with the time when the load current Iout crosses zero, that is, when the switch current Isw crosses zero, so that a surge voltage occurs in the switch SW. Absent.

  FIG. 5B shows temporal changes in the load current Iout, the switch current Isw, and the drive signal gSW when the resonance frequency fr and the drive frequency fsw are substantially equal and the resonance frequency fr is higher than the drive frequency fsw. A timing chart is shown. Similar to FIG. 5A, the load current Iout does not depend on the drive frequency fsw but changes at the resonance frequency fr. Further, during the ON period of the switch SW, the switch current Isw operates at the same frequency as the load current Iout. Since the resonance frequency fr is higher than the drive frequency fsw, the switch SW off time is later than the time when the load current Iout crosses zero, that is, the time when the switch current Isw crosses zero. For this reason, a surge voltage does not occur in the switch SW.

  Thus, by setting the frequency fsw of the drive signal gSW so that the switch current Isw has the same phase (fsw = fr) or the leading phase (fsw <fr) with respect to the drive signal gSW of the switch SW, In the push-pull inverter, it is possible to suppress the occurrence of a surge voltage when turned off.

  Here, when the frequency fsw of the drive signal gSW is set so that the switch current Isw has the same phase (fsw = fr) or the leading phase (fsw <fr) with respect to the drive signal gSW of the switch SW, the switch SW The power efficiency is highest when the switch current Isw has the same phase with respect to the drive signal gSW. That is, when the drive frequency fsw is set substantially the same as the resonance frequency fr, the power efficiency becomes the highest. Further, as shown in FIG. 6, the output power Pout of the power supply device 20 increases as the drive frequency fsw approaches the resonance frequency fr.

  Therefore, in the present embodiment, the drive frequency fsw is set in the vicinity of the resonance frequency fr, and intermittent output as shown in FIG. 7 is performed. In the intermittent output in this embodiment, the ratio (duty) of the ON time in one drive cycle of the switches SW1 and SW2 is kept at 50%. Further, the number of ON operations of the first switch SW1 and the second switch SW2 in a predetermined cycle, that is, the length of the period during which power is output in the predetermined cycle, is determined by the power command value Pout * (target value of supplied power) and the drive frequency. It sets based on ratio (Rate) with output electric power Pout (output possible electric power) output according to fsw.

  When the ratio between the output power Pout and the power command value Pout * (required power of the discharge load 31) is (Pout *: Pout = 1: x, x is an arbitrary real number), the output period of power in a predetermined cycle ( The length of the switches SW1 and SW2 are alternately turned on) is set to be 1 / x of the entire predetermined period. Thereby, when the switches SW1 and SW2 are driven, the power supplied from the power supply device 20 to the discharge load 31 can be brought close to the power command value Pout * while the drive frequency fsw is made close to the resonance frequency fr.

  For example, in the example shown in FIG. 7, the output power Pout is twice the power command value Pout * (required power of the discharge load 31) (Pout *: Pout = 1: 2). Therefore, the length of the power output period in the predetermined cycle is set to be ½ of the entire predetermined period. More specifically, in the example shown in FIG. 7, the predetermined cycle is set to a period 16 times longer than the drive cycle of the switches SW1 and SW2, and the first switch SW1 and the second switch SW2 in the predetermined cycle. The number of ON operations is 8 times (8 = 16/2).

  FIG. 8 shows a flowchart representing the intermittent output processing of this embodiment. This process is periodically performed by the control device 40 as the “calculation unit”.

  In step S01, it is determined whether or not the drive frequency fsw is substantially the same as the resonance frequency fr. Here, when the power output command is not input, the ratio (Rate) between the power command value Pout * and the output power Pout is a value that allows the output power Pout to be calculated in step S04. As small as possible. Specifically, the power command value Pout * and the output are set so that the length of the output period can be turned on at a duty of 50% in at least one of the switches SW1 and SW2 in one drive cycle of the switches SW1 and SW2. A ratio (Rate) with the power Pout is set. With this control, when a power output command is input, it is possible to bring the power supplied from the power supply device 20 to the discharge load 31 close to the power command value Pout * with high responsiveness, and the power output command is input. If not, power consumption can be reduced. When the drive frequency fsw and the resonance frequency fr are not substantially the same (S01: YES), in step S02, control is performed to bring the drive frequency fsw closer to the resonance frequency fr, and the process is terminated. In step S02, specifically, the drive frequency fsw is advanced and kept in the phase region, and control is performed to change the drive frequency fsw so that the output power Pout is increased.

  When the drive frequency fsw and the resonance frequency fr are substantially the same (S01: NO), is an electric power output command from the power supply device 20 to the discharge load 31 input from the host ECU to the control device 40 in step S03. Determine whether or not. When no power output command is input to the control device 40 (S03: NO), the process is terminated.

  When a power output command is input to the control device 40 (S03: YES), in step S04, the output power supplied to the resonant load 30 based on the detected values of the load voltage Vout and the load current Iout. Pout is calculated. In step S05, the ratio between the power command value Pout * and the output power Pout is calculated. In step S06, a time corresponding to the product of the ratio between the power command value Pout * and the output power Pout and a predetermined period is set as the output period, and the process is terminated.

  Here, when the output state and the stop state of the power supply device 20 are repeated by the intermittent output operation, when the output state is changed to the stop state and then returned to the output state, the transformer Tr is demagnetized. It becomes a problem. More specifically, there is a concern that the excitation current ILM flowing through the transformer Tr becomes excessive, and as a result, the transformer Tr is magnetically saturated.

  FIG. 9 is a model diagram showing the flow of the exciting current ILM of the transformer Tr. The transformer Tr can be expressed as a T-shaped equivalent circuit composed of an excitation inductance LM, a primary side leakage inductance Lsa, and a secondary side leakage inductance Lsb. An exciting current ILM for exciting the transformer Tr flows on the primary side of the transformer Tr (solid line).

  Here, when the power supply device 20 is changed from the output state to the stopped state by turning off both the switches SW1 and SW2, the exciting current ILM cannot flow on the primary side of the transformer Tr. For this reason, the exciting current ILM flows to the secondary side of the transformer Tr (broken line). The exciting current ILM flowing on the secondary side resonates with the exciting inductance LM and the leakage inductance Lsb and the capacitive discharge load 31. For this reason, there is a concern that the excitation current ILM increases due to the DC voltage source 10 being connected to the primary coil L1 and the transformer Tr is magnetically saturated depending on the timing of output restart.

  FIG. 10 is a timing chart showing the temporal change of the excitation current ILM when intermittent output is performed. In the output period, the switch SW1 and the switch SW2 are alternately turned on and off. At time T1, the switch SW2 is turned off and the switch SW1 is kept off, so that the switches SW1 and SW2 are both turned off, and the output period is shifted to the stop period.

  After time T1, the exciting current ILM flows through the exciting inductance LM, the secondary side leakage inductance Lsb, and the discharge load 31. In the stop period, the excitation current ILM is the resonance frequency 1 / (2π√ ((LM + Lsb) · Cb) in the LC resonance circuit including the excitation inductance LM, the secondary leakage inductance Lsb, and the discharge load 31. ). On the other hand, in the output period, the excitation current ILM changes at the resonance frequency fr (= 1 / (2π√ (Lsb · Ce))) of the resonance circuit formed by the secondary side leakage inductance Lsb and the discharge load 31. The excitation inductance LM is larger than the secondary side leakage inductance Lsb, and the frequency of the excitation current ILM in the stop period is lower than that in the output period. As a result, the excitation current ILM during the stop period has a larger amplitude than the output period.

  At time T2, the switch SW1 is turned on, so that the transition from the stop period to the output period occurs. Here, immediately after time T2, which is the transition from the output period to the stop period, the excitation current ILM increases due to the increase in the excitation current ILM due to the connection of the DC voltage source 10 to the primary coil L1. Therefore, there is a concern that the transformer Tr is magnetically saturated.

  Therefore, in the configuration of the present embodiment, as shown in FIG. 1, the third switch SW <b> 3 is provided between the connection lines connecting the center tap CT and the DC voltage source 10. More specifically, the switch SW3 is provided on the center tap CT side with respect to the smoothing capacitor Cin. A body diode D3 is connected in antiparallel to the switch SW3. The cathode of the diode D3 is connected to the drain of the switch SW3, and the anode of the diode D3 is connected to the source of the switch SW3. The switch SW3 is turned on when the drive signal gSW3 in the high state is input from the driver circuit 50, and is turned off when the drive signal gSW3 in the low state is input.

  In the output period, the control device 40 always turns on the switch SW3 and alternately turns on and off the switches SW1 and SW2 to output power to the discharge load 31. In addition, the control device 40 stops the power output to the discharge load 31 and keeps the excitation current ILM primary by setting the switch SW3 to the normally off state and the switches SW1 and SW2 to the always on state during the stop period. Reflux on the coil L1 side. By these controls, it is possible to suppress the excitation current ILM from becoming excessive immediately after the transition from the stop period to the output period.

  FIG. 11 is a flowchart showing the switching process between the output period and the stop period. This process is periodically performed by the control device 40 as a “drive unit”.

  In step S11, it is determined whether it is the current output period. If it is the output period (S11: YES), it is determined in step S12 whether or not it is the switching timing from the output period to the stop period. If it is not the switching timing to the stop period (S12: NO), the switch SW3 is turned on in step S13, and the switches SW1 and SW2 are alternately turned on and off at the drive frequency fsw (resonance frequency fr) in step S14. The process is terminated.

  If it is the switching timing from the output period to the stop period (S12: YES), the current on / off states of the switches SW1 and SW2 are stored in step S15. In step S16, the switches SW1 and SW2 are turned on and the switch SW3 is turned off, thereby switching from the output period to the stop period.

  If it is determined in step S11 that it is the stop period (S11: NO), it is determined in step S17 whether it is the timing for switching to the output period. When it is not the switching timing to the output period (S17: NO), in step S18, the switches SW1 and SW2 are turned on and the switch SW3 is turned off.

  When it is the switching timing from the stop period to the output period (S17: YES), in step S19, the switch SW3 is turned on, and the on / off states of the switches SW1 and SW2 are reversed from those stored in step S15. Set and finish the process. In step S19, specifically, when the switch SW1 is in the on state and the switch SW2 is in the off state in step S15, the switch SW1 is set to the off state and the switch SW2 is set to the on state. If the switch SW1 is off and the switch SW2 is on in step S15, the switch SW1 is set on and the switch SW2 is off.

  FIG. 12 is a timing chart showing the temporal change of the excitation current ILM when intermittent output is performed according to this embodiment. In the output period, the switch SW1 and the switch SW2 are alternately turned on and off. Immediately before time T11, the switch SW1 is turned off, the switch SW2 is turned on, and the switch SW3 is turned on. Immediately before time T11, the duty of the switch SW2 is 50%.

  After time T11, the excitation current ILM flows through the primary side closed circuit having the primary side leakage inductances Ls1, Ls2 and the switches SW1, SW2. In the stop period, the excitation current ILM becomes a substantially constant value. Further, the connection between the transformer Tr and the DC voltage source 10 is cut off, whereby the secondary side voltage Vout is attenuated while oscillating.

  Thereafter, at time T12, the switches SW1 and SW2 are both turned on and the switch SW3 is turned off, so that the output period is shifted to the stop period. Immediately after time T12, the duty of the switch SW1 is 50%.

  At time T12, the switch SW2 is turned off and the third switch SW3 is turned on, so that the transition from the stop period to the output period occurs. Here, at time T12, a switch (SW2 in FIG. 10) different from the switch (SW1 in FIG. 11) that was turned on immediately before time T11 among the switches SW1 and SW2 is turned on. As a result, immediately after time T12, the absolute value of the excitation current ILM changes in a decreasing direction. Further, the duty of the switch SW1 immediately before time T11 (50% in FIG. 11) and the duty of the switch SW2 immediately after time T12 (50% in FIG. 11) are substantially the same. By these controls, the center of the alternating vibration of the exciting current ILM can be set to 0 A, and the occurrence of magnetic saturation in the transformer Tr can be suppressed.

  The effects of this embodiment will be described below.

  By using the push-pull type inverter circuit 21 and setting the drive frequency to be equal to or lower than the resonance frequency, the current I1 flowing through the switches SW1 and SW2 is set to a leading phase with respect to the voltage V1 applied to the switches SW1 and SW2. The generation of surge voltage can be suppressed. Further, the drive frequency fsw is set in the vicinity of the resonance frequency fr, and power is output from the inverter circuit 21 in an output period set based on the power command value Pout * and the outputtable power Pout in a predetermined cycle. With such a configuration, the power supplied to the discharge load 31 that is a capacitive load can be brought close to the power command value Pout *, and the power efficiency can be improved.

  During the output period, the exciting current ILM flows through the primary coil L1. When the DC voltage source 10 and the primary coil L1 are cut off during the stop period, the magnetic energy accumulated in the transformer Tr by the excitation current ILM flows to the secondary side. If the output period is restarted while the excitation current ILM is flowing on the secondary side during the stop period, the excitation current ILM increases depending on the timing, and there is a concern that the transformer Tr may be magnetically saturated. Therefore, by providing the third switch SW3, magnetic saturation at the start of the output period is suppressed.

  Specifically, during the stop period, the power output is stopped by turning off the third switch SW3, and the both ends of the primary coil L1 are turned on by turning on the first switch SW1 and the second switch SW2. Short-circuit the child. Thereby, since the exciting current ILM flows to the primary side, it is possible to suppress the exciting current ILM from flowing to the secondary side of the transformer Tr. As a result, an increase in the amplitude of the excitation current ILM due to a reduction in the frequency of the excitation current ILM can be suppressed.

  When switching from the output period to the stop period, when one of the switches SW1 and SW2 is turned on and the other of the switches SW1 and SW2 is turned off, the next stop period is changed to the output period. At the time of switching, one of the switches SW1 and SW2, which is different from the one that was turned off during the output period, is turned off, and the other of the switches SW1, SW2 that is different from the one that was turned on during the output period is turned on The configuration is as follows. Thereby, at the start of the output period, a voltage can be applied to the transformer Tr in a direction to decrease the excitation current ILM flowing in the stop period, and the excitation current in a direction in which the absolute value of the excitation current ILM decreases. By changing the ILM, magnetic saturation in the transformer Tr can be suppressed.

(Second Embodiment)
When switching from the output period to the stop period, the control device 40 according to the second embodiment turns on one of the switches SW1 and SW2 and turns off the other over a period of ¼ of the drive cycle that is the inverse of the drive frequency After setting the state, the switches SW1 and SW2 are both turned on to switch from the output period to the stop period.

  Specifically, as shown in FIG. 13, the on-time (duty) of the switches SW1 and SW2 immediately before switching from the output period to the stop period (time T21) is reduced from about 50% to about 25%. Thereby, when switching from the output period to the stop period, the primary side current I becomes a 1/8 cycle delayed phase with respect to the primary side voltage V.

  In the output period, when one of the switches SW1 and SW2 is turned on for a quarter of the driving cycle, the exciting current ILM becomes substantially zero, and the magnetic energy accumulated in the transformer Tr becomes substantially zero.

  Further, at the time of switching from the stop period to the output period (time T22), one of the switches SW1 and SW2 is turned on and the other of the switches SW1 and SW2 is turned off over a quarter of the drive cycle. That is, when shifting from the stop period to the output period, the ON time (duty) of the switches SW1 and SW2 is decreased from approximately 50% to approximately 25%. As a result, the maximum value of the excitation current ILM immediately after the start of the output period can be made substantially constant with the maximum value of the steady output period, and the magnetic saturation of the transformer Tr can be suppressed.

(Third embodiment)
FIG. 14 shows the electrical configuration of the third embodiment. In the configuration of the present embodiment, the third switch SW3 is omitted. And it is set as the structure provided with 4th switch SW4 which is a semiconductor switching element connected between the connection point of the primary coil L1 and 1st switch SW1, and the connection point of the primary coil L1 and 2nd switch SW2. More specifically, the fourth switch SW4 is configured by connecting two MOSFETs (switches SW4a and SW4b) in series. Further, body diodes (diodes D4a and D4b) connected in parallel to the two MOSFETs are connected in opposite directions. That is, the body diode is connected so that the anodes or the cathodes are connected. An IGBT may be used as the fourth switch.

  During the output period, the exciting current ILM flows through the primary coil L1. When the DC voltage source 10 and the primary coil L1 are cut off during the stop period, the magnetic energy accumulated in the transformer Tr by the excitation current ILM flows to the secondary side. If the output period is restarted while the excitation current ILM is flowing on the secondary side during the stop period, the excitation current ILM increases depending on the timing, and there is a concern that the transformer Tr may be magnetically saturated. Therefore, by providing the fourth switch SW4, magnetic saturation at the start of the output period is suppressed.

  Specifically, the control device 40 as the “driving unit” turns off both the first switch SW1 and the second switch SW2 over the stop period, thereby causing the current flowing from the DC voltage source 10 to the primary coil L1. At the same time, the fourth switch SW4 is turned on. Further, the control device 40 turns off the fourth switch SW4 and turns on the first switch SW1 and the second switch SW2 alternately over the output period.

  During the stop period, the switches SW1 and SW2 are both turned off to stop the power output, and the fourth switch SW4 is turned on to short-circuit both terminals of the primary coil L1. Thereby, since the exciting current ILM flows to the primary side, it is possible to suppress the exciting current ILM from flowing to the secondary side of the transformer Tr, and it is possible to suppress an increase in the amplitude of the exciting current ILM due to the lower frequency of the exciting current ILM. Further, by setting the fourth switch SW4 to the OFF state during the output period, it is possible to normally output power from the primary side to the secondary side.

(Fourth embodiment)
FIG. 15 shows the electrical configuration of the fourth embodiment. The configuration of this embodiment is a configuration in which an LC filter circuit 22 is added to the configuration of the first embodiment shown in FIG.

  In the configuration of the fourth embodiment, as in the configuration of the first embodiment, the connection point between the third switch SW3 and the positive electrode of the DC voltage source 10 is connected to the connection point between the first switch SW1 and the second switch SW2. And a smoothing capacitor Cin is provided on the path. By providing the smoothing capacitor Cin, the voltage input to the inverter circuit 21 is smoothed (stabilized).

  Furthermore, in the configuration of the present embodiment, the LC filter circuit 22 is provided between the smoothing capacitor Cin and the DC voltage source 10. The inductor Lf constituting the LC filter circuit 22 is provided on a path connecting the positive electrode of the DC voltage source 10 and the third switch SW3. The capacitor Cf constituting the LC filter circuit 22 is provided on the path connecting the positive electrode and the negative electrode of the DC voltage source 10 closer to the DC voltage source 10 than the inductor Lf. The LC filter circuit 22 suppresses the high frequency noise accompanying the operation of the inverter circuit 21 from being input to the DC voltage source 10.

  Here, when switching from the output period to the stop period, the DC voltage source 10 and the inverter circuit 21 are cut off by turning off the third switch SW3. At this time, the current flowing from the inductor Lf toward the inverter circuit 21 (center tap CT), that is, the energy stored in the inductor Lf flows into the smoothing capacitor Cin. As a current flows from the inductor Lf to the smoothing capacitor Cin, the voltage across the terminals of the smoothing capacitor Cin increases. For this reason, it is necessary to increase the withstand voltage of the smoothing capacitor Cin, and an increase in the size of the smoothing capacitor Cin becomes a problem.

  A change in the voltage across the terminals of the smoothing capacitor Cin at the time of switching from the output period to the stop period will be described with reference to FIG. In FIG. 16, time T40 is a switching time point from the output period to the stop period. The input current Iin is a current supplied from the power source, and the center tap current Ict is a current that flows toward the center tap CT via the third switch SW3.

  In the output period before time T40, the drive signal gSW3 (not shown) is always in the high state, so that the switch SW3 is always in the on state, and the drive signals gSW1 and gSW2 are alternately in the high state. The switches SW1 and SW2 are alternately turned on. Further, the LC filter circuit 22 makes the input current Iin a direct current. Further, the input current Iin periodically changes in the driving cycle in which the switches SW1 and SW2 are driven.

  At time T40, both the drive signals gSW1 and gSW2 are set to the high state by the control device 40, so that both the switches SW1 and SW2 are turned on, and the drive signal gSW3 (not shown) is always set to the low state. Thus, the third switch SW3 is turned off, and the power supply device 20 shifts from the output period to the stop period. At time T40, the electrical connection between the inductor Lf and the inverter circuit 21 is disconnected, that is, there is no closed circuit including both the inductor Lf and the primary coil L1. For this reason, the center tap current Ict flowing from the inductor Lf to the center tap CT becomes zero. Further, the inductor current flowing from the inductor Lf to the smoothing capacitor Cin and the center tap CT flows into the smoothing capacitor Cin.

  That is, at time T40, LC resonance occurs between the inductor Lf and the smoothing capacitor Cin due to the energy accumulated in the inductor Lf. The maximum change amount ΔVc value of the inter-terminal voltage Vc of the smoothing capacitor Cin caused by LC resonance is Cin as the capacitance value of the smoothing capacitor Cin, Lf as the inductance value of the inductor Lf, Iin0 as the input current Iin at time T40, and the center at time T40. When the tap current Ict is Ict0, it can be expressed as ΔVc = √ {(Lf / Cin) (Iin0−Ict0) ^ 2}. That is, the peak value of the inter-terminal voltage Vc of the smoothing capacitor Cin is proportional to the input current Iin0 at the time of switching from the output period to the stop period.

  Therefore, the control device 40 as the “drive unit” of the present embodiment alternately drives the first switch SW1 and the second switch SW2 with a predetermined drive frequency fsw and a predetermined duty of 50% or less during the output period. To do. Furthermore, the control device 40 changes the duty in a decreasing direction in a predetermined period including a time point when the output period is switched to the stop period. With this control, at the time of switching from the output period to the stop period, the energy stored in the inductor Lf can be reduced, and an increase in the voltage across the terminals of the smoothing capacitor Cin can be suppressed.

  In addition, in the inverter circuit 21, the control device 40 outputs the output current Iout in the output period, and performs burst output that stops the output current Iout in the stop period. That is, the output current Iout of the inverter circuit 21 changes periodically with a period including one output period and one stop period as one period (burst period). For this reason, the output current Iout of the inverter circuit 21 has a frequency component corresponding to the reciprocal of the burst period and its n-th harmonic frequency component. The frequency component resulting from this burst period is low in frequency compared to the resonance frequency fr and the like, and there is a concern that it may include an audible range. Due to the burst period, adverse effects due to the frequency component of the output current Iout belonging to the audible range, for example, the generation of noise due to magnetostriction, etc., become a problem.

  Therefore, the control device 40 changes the duty in the increasing direction from the start point of the output period to the predetermined time point in the output period, and changes the duty in the decreasing direction from the predetermined time point to the end point of the output period. The duty cycle is changed so that the amplitude of the output voltage Vout changes at a cycle twice that of the output period. More specifically, as shown in FIG. 17, the duty of the switches SW1 and SW2 is changed so that the amplitude of the output voltage Vout of the inverter circuit 21 (the vertical width of the envelope of the output voltage Vout) changes sinusoidally. did. More specifically, the duty of the switches SW1 and SW2 is changed so that the absolute value (modulation factor) of the amplitude of the output voltage Vout changes into a half-wave rectified wave shape of a sine wave. That is, the control device 40 substantially reduces the amplitude of the output voltage Vout at the start of the output period, and then increases the amplitude of the output voltage Vout in a sine wave shape. Then, at the intermediate time between the start and end of the output period, the amplitude of the output voltage Vout is set to the maximum value, and then the amplitude of the output voltage Vout is decreased in a sine wave shape. At the end of the output period, the amplitude of the output voltage Vout is set to approximately zero. With this configuration, it is possible to weaken each frequency component of the output voltage Vout due to the burst period and suppress an adverse effect due to the frequency component of the output current Iout belonging to the audible range.

  Also, in the configuration in which the duty is changed in the increasing direction from the start point of the output period to a predetermined point in the output period, and the duty is changed in the decreasing direction from the predetermined point to the end point of the output period, the duty is stopped in the output period. In a predetermined period including the time point when the period is switched, the duty of the switches SW1 and SW2 (the ratio of the on time in the driving cycle) changes in a decreasing direction. That is, at the time of switching from the output period to the stop period, the energy stored in the inductive component can be reduced, and an increase in the inter-terminal voltage Vc of the smoothing capacitor Cin can be suppressed.

  Here, when the control of the present embodiment is performed, the duty of the switches SW1 and SW2 in the output period is lower than 50%, and the output is compared with the case where the duty of the switches SW1 and SW2 is set to 50%. The voltage Vout is lowered. For this reason, there is a concern about a decrease in power supplied to the discharge load 31. Therefore, when reducing the duty of the switches SW1 and SW2, the control device 40 sets the output period to be long in order to compensate for the decrease in the output power Pout accompanying the decrease in the duty.

  A change in the voltage across the terminals of the smoothing capacitor Cin when the duty is changed so that the amplitude of the output voltage in the output period changes in a sine wave shape will be described with reference to FIG.

  In the period before the time T50 in the output period (the period before the predetermined time T50 in the output period from the start time of the output period), the duty of each of the switches SW1, SW2 (drive signals gSW1, gSW2) increases. At time T50, the duty of each of the switches SW1 and SW2 reaches the maximum value (50%). In the period before time T50 in the output period, the amplitude of the output voltage Vout (the vertical width of the envelope) changes in the increasing direction, and the amplitude (peak value) of the center tap current Ict of the inverter circuit 21 increases. The input current Iin changes in an increasing direction.

  After time T50, the duty of each of the switches SW1 and SW2 changes in a decreasing direction over a period from time T50 to time T51, which is the end point of the output period. During the period from time T50 to time T51, the amplitude of the output voltage Vout (the vertical width of the envelope) changes in the decreasing direction, and the amplitude (peak value) of the center tap current Ict changes in the decreasing direction. The input current Iin changes in a decreasing direction.

  At time T51, both the drive signals gSW1 and gSW2 are set to the high state, so that both the switches SW1 and SW2 are turned on, and the drive signal gSW3 (not shown) is set to the low state, so that the switch SW3 Is turned off, and the output period is switched to the stop period. Since the energy stored in the inductor Lf is reduced by reducing the input current Iin when switching from the output period to the stop period, the smoothing capacitor accompanying the flow of current from the inductor Lf to the smoothing capacitor Cin An increase in the voltage between terminals of Cin can be suppressed.

  Further, the discharge load 31 to which power is supplied from the inverter circuit 21 is a non-linear element in which the voltage and the current do not have a proportional relationship. For this reason, the duty of the switches SW1 and SW2 is set so that the amplitude of the output voltage Vout changes in a sine wave shape, but the actual amplitude of the output voltage Vout changes in a distorted sine wave shape.

  FIG. 19 shows the magnitude of the frequency component of the noise terminal voltage of the inverter circuit 21 resulting from the burst period. In the output period, the frequency component of the noise terminal voltage when the duty of the switches SW1 and SW2 is always 50% is shown in black. Further, the frequency component of the noise terminal voltage when the duty of the switches SW1 and SW2 of the present embodiment is changed in a sine wave shape is shown in gray. As shown in FIG. 19, by performing the control of the present embodiment, the nth-order harmonic component of the burst frequency can be reduced.

  In the above description, the LC filter circuit 22 is provided between the DC voltage source 10 and the smoothing capacitor Cin, but this may be omitted. Even in the configuration in which the LC filter circuit 22 is omitted, a current flows from the parasitic inductor existing between the DC voltage source 10 and the smoothing capacitor Cin to the smoothing capacitor Cin when switching from the output period to the stop period. For this reason, even when the configuration in which the duty of the switches SW1 and SW2 is decreased in a predetermined period including the time point when the output period is switched to the stop period is applied to the configuration in which the LC filter circuit 22 is omitted, the smoothing capacitor Cin An increase in voltage between terminals can be suppressed.

  The duty of the switches SW1 and SW2 is changed in the increasing direction from the start point of the output period to a predetermined point in the output period, and the duty of the switches SW1 and SW2 is changed in the decreasing direction from the predetermined point to the end point of the output period. As a modification of the configuration, the control device 40 may set the duty of the switches SW1 and SW2 so that the output voltage Vout changes in a triangular wave shape. Here, the duty of the switches SW1 and SW2 at each time point may be set to be substantially equal.

  As a modification of the configuration in which the duty is changed in a decreasing direction in a predetermined period including the time point when the output period is switched to the stop period, the control device 40 sets the duty of the switches SW1 and SW2 to 50% until the predetermined time point in the output period. It is good also as a structure which sets and reduces the duty of switch SW1, SW2 after a predetermined time.

  In the description of the present embodiment, the electrical configuration of the first embodiment is assumed. However, this may be changed and the electrical configuration of the third embodiment may be assumed. Assuming the electrical configuration of the third embodiment, in the output period, the duty of the switches SW1 and SW2 is changed in the increasing direction from the start point of the output period to a predetermined point in the output period, and at a predetermined point in time. The duty may be changed in the decreasing direction from the end of the output period to the end of the output period. In addition, the fourth switch SW4 may be turned off in the output period. In the stop period, both the switches SW1 and SW2 may be turned off and the fourth switch SW4 may be turned on.

(Other embodiments)
-It is good also as a structure which abbreviate | omits the smoothing capacitor Cin.

  In the first, second, and fourth embodiments, the switch SW3 is provided between the DC voltage source 10 and the center tap CT, but this is changed to connect the first switch SW1 and the second switch SW2. A switch SW3 may be provided between the point (a connection point between the emitter of the first switch SW1 and the emitter of the second switch SW2) and the DC voltage source 10. In the configuration in which the smoothing capacitor Cin is provided, the switch SW3 may be provided on the connection point side of the first switch SW1 and the second switch SW2 with respect to the smoothing capacitor Cin.

  In the second embodiment, as shown in FIG. 20, in addition to the electrical configuration of the first embodiment shown in FIG. 1, the center tap CT and the first switch SW are closer to the primary coil L1 than the third switch SW3. And it is good to set it as the structure which provides the free-wheeling diode DT on the path | route which connects the connection point of 2nd switch SW.

  In this configuration, when one of the switches SW1 and SW2 is turned on for a quarter of the drive cycle, the output period is shifted to the stop period. In this configuration, the switch SW3 is turned off while a current is flowing through the switch SW3, and a surge voltage is generated in the switch SW3. Therefore, by providing the free wheel diode DT, it is possible to suppress the surge voltage generated in the switch SW3.

  Further, in the configuration in which the switch SW3 is provided between the connection point between the first switch SW1 and the second switch SW2 and the DC voltage source 10, the center tap CT and the first tap are closer to the primary coil L1 than the third switch SW3. A configuration in which a free-wheeling diode DT is provided on a path connecting the connection point of the first switch SW and the second switch SW is preferable.

  In the first embodiment, immediately before switching from the output period to the stop period, one of the switches SW1 and SW2 is turned on with a duty of 50%, and immediately after the subsequent switch from the stop period to the output period, the switch SW1 Although the other SW2 is turned on with a duty of 50%, this may be changed. For example, immediately before switching from the output period to the stop period, one of the switches SW1 and SW2 is turned on at a predetermined duty (A%), and immediately before the subsequent switch from the stop period to the output period, the switches SW1 and SW2 are turned on. It is good also as a structure which turns on the other of these by the said predetermined duty (A%) (A is arbitrary values among 0-50).

  -It is good also as a structure which inserts a coil in series with the discharge load 31 on the secondary side. In this configuration, the resonance frequency fr is determined by the secondary conversion value Lsb of the leakage inductance between the primary and secondary sides of the transformer Tr, the inductance of the coil, and the capacitance component of the discharge load 31.

  -You may change switch SW1, SW2 from N channel MOS-FET. For example, an IGBT may be used. In addition, when using IGBT for switch SW1, SW2, it is good to set it as the structure which provides a free-wheeling diode.

  In the above embodiment, the power output is stopped by turning on the switches SW1 and SW2 and turning off the switch SW3 during the stop period. This may be changed, the switch SW3 may be omitted, and the SW1 and SW2 may be turned off during the stop period.

  Further, in the configuration in which the switch SW3 is omitted, it is preferable to shift from the stop period to the output period at the timing when the excitation current ILM becomes substantially zero. Here, during the stop period, the exciting current ILM resonates at a resonance period corresponding to the exciting inductance LM, the pre-discharge equivalent capacitance Cb of the discharge load 31, and the secondary side parasitic capacitance. Therefore, by shifting from the output period to the stop period at a timing when the excitation current ILM becomes substantially 0, and by shifting from the stop period to the output period at a timing when k × resonance period (k is an arbitrary natural number) has elapsed, It is possible to shift from the stop period to the output period when the excitation current ILM becomes substantially zero.

  FIG. 21 is a timing chart showing the time change of the excitation current ILM when intermittent output is performed in the present modification. At time T31 when the excitation current ILM becomes substantially 0, switching from the output period to the stop period is performed. That is, at time T31, the switch SW2 that is turned on is turned off, so that the switches SW1 and SW2 are both turned off. After that, a period of 7 × resonance period has elapsed from time T31, and switching from the stop period to the output period is performed at time T32 when the excitation current ILM becomes substantially zero. Thereby, it can suppress that the exciting current ILM becomes excessive.

  The excitation current ILM has a correlation with the secondary side current flowing through the secondary coil L2 and the secondary side voltage generated in the secondary coil L2. The control device 40 as the “detection value acquisition unit” can acquire the detection value of the output current Iout as the detection value of the secondary current flowing in the secondary coil L2. Further, the control device 40 as the “detection value acquisition unit” can acquire the detection value of the output voltage Vout as the detection value of the secondary side voltage generated in the secondary coil L2.

  Therefore, the control device 40 shifts from the stop period to the output period when the excitation current ILM flowing through the transformer Tr is smaller than a predetermined value based on the detected value of the secondary current or the detected value of the secondary voltage. Switch.

  More specifically, as shown in FIG. 22, when the absolute value of the detected value of the secondary side voltage (detected value of the output voltage Vout) is substantially maximum, switching from the stop period to the output period is performed. Since the secondary side voltage and the excitation current ILM have a phase difference of about 90 degrees, the excitation current ILM becomes substantially zero when the absolute value of the secondary side voltage becomes substantially maximum. For this reason, when the excitation current ILM becomes substantially zero, it is possible to switch from the stop period to the output period, and as a result, it is possible to suppress magnetic saturation in the transformer Tr.

  As shown in FIG. 22, when switching from the stop period to the output period, one of the first switch SW1 and the second switch SW2 (switch SW2) is turned on and the other (switch SW1) is switched with respect to the drive cycle. The ratio of the period in the off state is set to half of the target ratio (for example, 1/2). After that, the ratio of the period in which the other of the first switch SW1 and the second switch SW2 (switch SW2) is in the on state and one (switch SW1) is in the off state with respect to the driving cycle is set as the target ratio. With such a configuration, it is possible to prevent the excitation current ILM from becoming excessive immediately after the transition from the stop period to the output period.

  Here, at the time of switching from the stop period to the output period, the ratio of the period in which one of the first switch SW1 and the second switch SW2 is in the on state and the other in the off state with respect to the drive cycle is set as the target ratio (for example, 1 / 2) It may be configured to be set to a predetermined value smaller than that. Further, after a predetermined period, the ratio of the period in which one of the first switch SW1 and the second switch SW2 is turned on and the other is turned off may be increased to the target ratio with respect to the driving cycle. Here, the ratio of the period in which one of the first switch SW1 and the second switch SW2 is on and the other is off may be gradually increased with respect to the driving cycle. With such a configuration, it is possible to prevent the excitation current ILM from becoming excessive immediately after the transition from the stop period to the output period.

  DESCRIPTION OF SYMBOLS 10 ... DC voltage source, 20 ... Power supply device, 21 ... Inverter circuit, 30 ... Resonant load, 31 ... Discharge load, 40 ... Control device, D1, D2 ... Diode, SW1, SW2 ... Switch, Tr ... Transformer, L1 ... Primary Coil, L2 ... secondary coil, CT ... center tap, Lsb ... secondary side conversion value of leakage inductance between primary and secondary sides.

Claims (15)

A power supply device (20) having an inverter circuit (21) supplied with DC power from a DC voltage source (10) and outputting AC power to a capacitive load (31),
The inverter circuit includes a primary coil (L1) having a center tap (CT), a transformer (Tr) having a secondary coil (L2) magnetically coupled to the primary coil, and both ends of the primary coil. A first switch (SW1) and a second switch (SW2), which are semiconductor switching elements connected to the first switch, and a first diode (D1) and a second switch connected in antiparallel to the first switch and the second switch, respectively. A diode (D2), wherein the center tap is connected to one terminal of the DC voltage source, and the first switch and the second switch are connected to the other terminal of the DC voltage source. Push-pull inverter circuit
At a drive frequency that is equal to or lower than the resonance frequency of the resonance circuit (30) having a secondary side converted value (Lsb) of leakage inductance between the primary and secondary sides of the transformer and the capacity of the capacitive load, and in the vicinity of the resonance frequency. A drive unit (40) for alternately driving the first switch and the second switch;
A calculation unit (40) that calculates a ratio between the output power of the inverter circuit determined according to the output voltage of the inverter circuit and the drive frequency and the target power that is a target value of the supply power supplied to the capacitive load. ) And
In the predetermined period, the driving unit sets a time corresponding to a product of the predetermined period and the ratio calculated by the calculation unit as an output period, and turns on the first switch and the second switch alternately over the output period. A power supply device that is in a state, and in the predetermined cycle, a period other than the output period is set as a stop period, and the current flowing from the DC voltage source to the primary coil is cut off during the stop period.   A third switch (SW3) which is a semiconductor switching element connected between the center tap and the DC voltage source or between a connection point of the first switch and the second switch and the DC voltage source; The power supply device according to claim 1 provided. The drive unit is
The third switch is turned on over the output period,
3. The third switch is turned off over the stop period to cut off a current flowing from the DC voltage source to the primary coil, and to turn on the first switch and the second switch. The power supply device described in 1.   4. The power supply device according to claim 3, further comprising a free-wheeling diode (DT) on a path connecting the center tap and a connection point of the first switch and the second switch closer to the primary coil than the third switch. .   The fourth switch (SW4), which is a semiconductor switching element connected between the connection point of the primary coil and the first switch, and the connection point of the primary coil and the second switch. Power supply. The drive unit is
Over the output period, the fourth switch is turned off,
6. The first switch and the second switch are turned off over the stop period to cut off the current flowing from the DC voltage source to the primary coil and turn the fourth switch on. The power supply device described in 1.   In the driving unit, when switching from the output period to the stop period, one of the first switch and the second switch is turned on, and the other of the first switch and the second switch is turned off. In the case of being in a state, at the time of switching from the stop period to the output period, one of the first switch and the second switch that is different from the off state in the output period is turned off. The power supply device according to any one of claims 3 to 6, wherein the other of the first switch and the second switch different from that turned on during the output period is turned on.   The drive unit turns on the first switch and turns off the second switch over a period of ¼ of the drive cycle that is the reciprocal of the drive frequency when switching from the output period to the stop period. The power supply device according to any one of claims 3 to 6, wherein the first switch and the second switch are both turned on to switch from the output period to the stop period.   The driving unit turns on one of the first switch and the second switch over a period of ¼ of a driving cycle that is a reciprocal of the driving frequency when switching from the stop period to the output period. The power supply device according to claim 8, wherein the other of the first switch and the second switch is turned off. A detection value acquisition unit for acquiring a detection value of a secondary side current flowing in the secondary coil or a detection value of a secondary side voltage generated in the secondary coil;
The drive unit performs switching from the output period to the stop period by turning off both the first switch and the second switch at the time of switching from the output period to the stop period, The power supply device according to claim 1, wherein switching from the stop period to the output period is performed when an excitation current flowing through the transformer is smaller than a predetermined value based on a detection value acquired by a detection value acquisition unit. The detection value acquisition unit acquires a detection value of a secondary side voltage generated in the secondary coil,
The power supply device according to claim 10, wherein the drive unit performs switching from the stop period to the output period when the absolute value of the detection value acquired by the detection value acquisition unit is substantially maximum.   The driving unit turns on one of the first switch and the second switch with respect to a driving cycle that is a reciprocal of the driving frequency when switching from the stop period to the output period. After the ratio of the period during which the other of the second switches is turned off is half of the target ratio, the ratio of the period during which the other of the first switch and the second switch is turned on and the other is turned off is set to the target The power supply device according to claim 10 or 11, which is a ratio.   In the switching from the stop period to the output period, the drive unit sets one of the first switch and the second switch to an on state and the other to an off state with respect to a drive cycle that is a reciprocal of the drive frequency. The ratio of the period during which the first switch and the second switch are turned on and the other is turned off after the lapse of the predetermined period is set to a predetermined value smaller than the target ratio. The power supply device according to claim 10 or 11, wherein the power supply device is increased up to. A smoothing capacitor is provided on a path connecting the center tap and the connection point of the first switch and the second switch,
The drive unit is
In the output period, the first switch and the second switch are alternately driven with the driving frequency and a predetermined duty,
The power supply device according to any one of claims 1 to 13, wherein the duty is changed in a decreasing direction in a predetermined period including a time point when the output period is switched to the stop period. The drive unit is
In the output period, the first switch and the second switch are alternately driven with the driving frequency and a predetermined duty,
15. The duty is changed in an increasing direction from a start time of the output period to a predetermined time in the output period, and is changed in a decreasing direction from the predetermined time to an end time of the output period. The power supply device according to any one of the above.