DE112017001909T5 - Power source means - Google Patents

Abstract

A current source device (20) comprising a push-pull inverter circuit (21) adapted to output an alternating current to a capacitive discharge load (31) comprises a control device (40) which is adapted to switch (SW1, SW2) alternating with a drive frequency which is at most as large as a resonant frequency of a resonant circuit (30) having a secondary side corresponding value of the separate leakage inductance of the primary and secondary side of a transformer (Tr) and the capacity of the discharge load and the is close to the resonant frequency, and a ratio between a dispersible power of the inverter circuit, which is determined according to the output voltage of the inverter circuit and the drive frequency, and a target value for the discharge load supplied supply power to calculate. In a predetermined period of time, the control device sets a time corresponding to the product of the predetermined time period and the ratio calculated by the calculation unit as an output period to alternately change the switches to an ON state during the output period.

Description

[Cross reference to related application]

This application is based on the Japanese Patent Application No. 2016-077264 , filed on April 7, 2016, and the Japanese Patent Application No. 2016-200351 , filed on Oct. 11, 2016, the contents of which are hereby incorporated by reference in the present text.

[Technical area]

The present disclosure relates to a power source device including an inverter circuit configured to receive DC power supplied from a DC power source and to output AC power to a resonance load having series resonance characteristics.

[Background of the Invention]

A capacitive load including an ozone generating device, a plasma processing device, or the like is configured to be operated by receiving high frequency power supplied from a high frequency power source device. In general, the high-frequency power source apparatus configured to supply the power to, for example, the ozone generating apparatus includes a DC-DC converter configured to receive a DC power supplied from a DC power source to perform voltage adjustment, and an inverter circuit, configured to receive the DC power supplied from the DC-DC converter to perform AC / DC conversion.

In some cases, an impedance on a capacitive load side, as viewed from the high frequency power source device, could change. For example, in a case of the ozone generating apparatus, the capacitive load constituting the ozone generating apparatus changes its capacity according to an applied voltage and serves as a replacement capacity corresponding to the percentage of a discharge period in a period from the beginning to the end of the voltage application. In such a change in the impedance of the capacitive load, the frequency of the inverter circuit is set to a frequency higher than a resonance frequency determined by the equivalent capacity of a reactance and the capacitive load. Further, in Patent Literature 1, the method of controlling a power based on a delay phase amount of an output current of an inverter circuit will be described.

[Citation List]

[Patent Literature]

[PTL 1] Japanese Patent No. 5681943

[Brief Description of the Invention]

In a case of reducing an output power having a delay phase (a high frequency), a power reduction is used in conjunction with the lowering of a power factor. However, the high frequency has the counteracting effect of increasing the output power, and therefore it is driven at a high frequency deviating from the resonance frequency for power reduction. As a result, there are problems that an increase in switching loss is caused and the efficiency of power conversion is lowered. For these reasons, in the case of driving at a frequency near the deceleration phase of the resonance frequency, an output voltage must be controlled by using a DC-DC converter.

The present disclosure is based on the above-described problems and, more particularly, serves to prevent a lowering of the efficiency of power conversion in the control of the output power for a capacitive load while implementing a power conversion device only by an inverter.

The present embodiment relates to a power source device including an inverter circuit configured to receive a DC power supplied from a DC power source and output AC power to a capacitive load. The inverter circuit is a push-pull inverter circuit comprising: a transformer having a primary coil with a center tap and a secondary coil magnetically coupled to the primary coil; a first switch and a second switch as semiconductor switching elements, each with both ends of the primary coil are connected, and a first diode and a second diode, which are connected in parallel with the first and the second switch in reverse direction, the center tap is connected to a terminal of the DC voltage source and the first and the second switch with the other connection of the DC voltage source are connected. The power source device further comprises a drive unit configured to drive the first switch and the second switch in alternation with a drive frequency that is at most as large as a resonance frequency of a resonance circuit having a secondary side corresponding value separate leakage inductance of the primary and the secondary side of the transformer and the capacitance of the capacitive load and which is close to the resonance frequency, and a calculation unit configured to a ratio between a output power of the inverter circuit, which according to the output voltage of the inverter circuit and the Driving frequency is determined, and a target power as a target value for the supply power, which is supplied to the capacitive load to calculate. The driving unit takes, in a predetermined period of time, a time corresponding to the product of the predetermined time period and the ratio calculated by the calculating unit as an output period to change the first switch and the second switch to an ON state during the output period and, in the predetermined period, takes a period other than the output period as a stop period to disable the current flowing from the DC power source to the primary coil during the stop period.

The power source device configured to supply the power to the resonance load uses a push-pull inverter circuit. In this way, as compared with a full-bridge inverter circuit, the number of switching elements or floating current sources can be reduced, and the configuration can be simplified. In addition, the occurrence of a turn-on loss can be reduced. In the push-pull inverter circuit described herein, there is a risk that a surge voltage may occur when an OFF operation is performed for the switch when a forward current flows in the switch. For this reason, the drive frequency is set so that a switch current has the same phase or a leading phase with respect to a drive signal, and thus the switch current at the time when the first switch and the second switch turn into an OFF state. Condition can be brought to a negative value, and therefore the surge voltage can be reduced. That is, in the control of the output power for the capacitive load, a decrease in the converter efficiency can be prevented while a power conversion device is implemented only by the inverter. It should be noted that, in the case where the switch current is turned off, the recovery phase and the negative value of the switch current in the full-bridge inverter due to the recovery characteristics of a diode, a recovery surge voltage occurs, and therefore, the drive frequency to the high-frequency side with Reference to the resonant frequency set. On the other hand, in the push-pull inverter, in the case where the switch current is turned off, with the leading phase and the negative value of the switch current, "soft" recovery of the diode is performed by the above-described leakage inductance of the transformer, and therefore Recovery shock voltage smaller than that of the full-bridge inverter.

list of figures

• 1 ist ein Schaubild einer elektrischen Ausgestaltung einer ersten Ausführungsform;
• 2 ist ein Kurvendiagramm einer Änderung einer Kapazität einer kapazitiven Entladungslast;
• 3 ist ein Schaubild eines Stromflusses, wenn eine Stoßspannung auftritt;
• 4 ist ein Zeitdiagramm einer zeitlichen Änderung einer Schalterspannung, einen Schalterstrom und einen Ansteuerungssignal, wenn die Stoßspannung auftritt;
• 5 ist ein Zeitdiagramm einer zeitlichen Änderung eines Laststroms, des Schalterstroms und des Ansteuerungssignal für den Fall, dass der Schalterstrom die gleiche Phase oder eine vorauseilende Phase mit Bezug auf das Ansteuerungssignal hat;
• 6 ist ein Kurvendiagramm einer Beziehung zwischen einer Ansteuerungsfrequenz und einer Ausgangsleistung;
• 7 ist ein Kurvendiagramm einer intermittierenden Ausgabe der ersten Ausführungsform;
• 8 ist ein Flussdiagramm einer intermittierenden Ausgabeverarbeitung der ersten Ausführungsform;
• 9 ist eine Ansicht des Flusses von Erregungsstrom in einer Ersatzschaltung eines Transformators;
• 10 ist ein Zeitdiagramm für den Fall, dass der Erregungsstrom übermäßig hoch ist, wenn die Ausgabe wieder aufgenommen wird;
• 11 ist ein Flussdiagramm der Verarbeitung des Umschaltens zwischen einem Ausgabezeitraum und einem Stopp-Zeitraum in der ersten Ausführungsform;
• 12 ist ein Zeitdiagramm einer Änderung des Erregungsstroms in einem Fall des Ausführens einer Steuerung in der ersten Ausführungsform;
• 13 ist ein Zeitdiagramm einer Änderung des Erregungsstroms in einem Fall des Ausführens einer Steuerung in einer zweiten Ausführungsform;
• 14 ist ein Schaubild einer elektrischen Ausgestaltung einer dritten Ausführungsform;
• 15 ist ein Schaubild einer elektrischen Ausgestaltung einer vierten Ausführungsform;
• 16 ist ein Zeitdiagramm einer Änderung der Zwischen-Anschluss-Spannung eines Glättungskondensators;
• 17 ist ein Diagramm der Modulation einer Ausgangsspannungsamplitude in der vorliegenden Ausführungsform;
• 18 ist ein Zeitdiagramm einer Änderung der Zwischen-Anschluss-Spannung des Glättungskondensators in einem Fall des Ausführens einer Steuerung der vierten Ausführungsform;
• 19 ist ein Kurvendiagramm jeder Frequenzkomponente einer Ausgangsspannung Vout;
• 20 ist ein Schaubild einer elektrischen Ausgestaltung einer Modifizierung;
• 21 ist ein Zeitdiagramm einer Änderung des Erregungsstroms im Fall des Ausführens einer Steuerung in der Modifizierung; und
• 22 ist ein Zeitdiagramm einer Änderung des Erregungsstroms im Fall des Ausführens einer Steuerung in der Modifizierung.

The above-described object of the present disclosure, as well as other objects, features, and advantages, will become more apparent from the following detailed description made with reference to the accompanying drawings. The drawings show the following:

• 1 is a diagram of an electrical embodiment of a first embodiment;
• 2 Fig. 10 is a graph of a change of capacitance of a discharge capacitive load;
• 3 FIG. 12 is a graph of current flow when a surge voltage occurs; FIG.
• 4 Fig. 10 is a timing chart showing a change in the timing of a switch voltage, a switch current, and a drive signal when the surge voltage occurs;
• 5 Fig. 12 is a timing chart showing a change in a load current, the switch current and the drive signal in a case where the switch current has the same phase or a leading phase with respect to the drive signal;
• 6 Fig. 10 is a graph of a relationship between a drive frequency and an output power;
• 7 Fig. 10 is a graph of an intermittent output of the first embodiment;
• 8th Fig. 10 is a flowchart of an intermittent output processing of the first embodiment;
• 9 Fig. 10 is a view of the flow of excitation current in an equivalent circuit of a transformer;
• 10 Fig. 11 is a timing chart in the case where the exciting current is excessively high when the output is resumed;
• 11 Fig. 10 is a flowchart of the processing of switching between an output period and a stop period in the first embodiment;
• twelve Fig. 10 is a time chart of a change of the exciting current in a case of executing a control in the first embodiment;
• 13 Fig. 10 is a time chart of a change of the exciting current in a case of carrying out a controller in a second embodiment;
• 14 is a diagram of an electrical embodiment of a third embodiment;
• 15 is a diagram of an electrical embodiment of a fourth embodiment;
• 16 Fig. 10 is a timing chart showing a change in the inter-terminal voltage of a smoothing capacitor;
• 17 FIG. 15 is a diagram of the modulation of an output voltage amplitude in the present embodiment; FIG.
• 18 Fig. 10 is a time chart showing a change of the inter-terminal voltage of the smoothing capacitor in a case of executing a control of the fourth embodiment;
• 19 Fig. 12 is a graph of each frequency component of an output voltage Vout;
• 20 is a diagram of an electrical embodiment of a modification;
• 21 Fig. 10 is a time chart of a change of the exciting current in the case of executing a control in the modification; and
• 22 FIG. 12 is a time chart of a change of the exciting current in the case of executing a control in the modification. FIG.

[Description of Embodiments]

First Embodiment

1 illustrates equivalent circuits of a power source device 20 and a discharge load 31 designed for one of the power source device 20 to receive supplied energy in the present embodiment.

An inverter circuit 21 which the power source device 20 is designed, one of a DC voltage source 10 converted direct current into an alternating current, whereby the alternating current to a resonance load 30 is output, which is the discharge load 31 includes. The inverter circuit 21 is a push-pull inverter circuit and includes a smoothing capacitor Cin, a transformer Tr , a first switch SW1 , a second switch SW2 , a first diode D1 and a second diode D2 ,

The smoothing capacitor Cin is designed to be that of the DC voltage source 10 Smooth in the injected voltage and the influence of voltage fluctuations due to the operation of the inverter circuit 21 to the output voltage of the DC voltage source 10 to reduce. The transformer Tr includes a primary coil L1 and a secondary coil L2 that are magnetically coupled together. In 1 becomes the separate leakage inductance of the primary and the secondary side of the transformer Tr as a primary leakage inductance Ls1 . Ls2 shown. In addition, a secondary side corresponding value of the separate leakage inductance of the primary and the secondary side of the transformer Tr lsb (Not shown). When a winding ratio between the primary coil L1 and the secondary coil L2 n is, the secondary-side corresponding value can lsb when lsb = n ^ 2 · Ls1 are represented when a current in the switch SW1 flows, and can be considered lsb = n ^ 2 · Ls2 are represented when a current in the switch SW2 flows. Beyond that is a center tap CT at a center of the primary coil L1 arranged. The center tap CT is with a positive connection of the DC voltage source 10 connected.

The first switch SW1 and the second switch SW2 are each with both ends (connections P1 . P2 ) of the primary coil L1 connected. Each of the switches SW1 . SW2 is a semiconductor switching element and is more specifically an N-channel MOSFET. The switches SW1 . SW2 are collectively referred to as a "SW switch".

The first diode D1 and the second diode D2 are each with the first switch SW1 or the second switch SW2 connected in parallel in the reverse direction. The diodes D1 . D2 Body diodes are the switches SW1 . SW2 , Cathodes of the diodes D1 . D2 are each with drains the switch SW1 . SW2 connected, and anodes of the diodes D1 . D2 are each with sources of the switch SW1 . SW2 connected.

If he has a drive signal GSW1 . GSW2 in a HIGH state of a drive circuit 50 receives, then the switch SW1 . SW2 brought into an ON state. If he has the drive signal GSW1 . GSW2 in a LOW state, the switch becomes SW1 . SW2 brought into an OFF state. The alternating current is supplied by the inverter circuit 21 issued in such a way that the first switch SW1 and the second switch SW2 be alternately brought into the ON state.

Specifically, if the first switch SW1 is brought into the ON state, so will the voltage of the DC voltage source 10 to a section between the center tap CT the primary coil L1 and the connection P1 created. Because the voltage to the primary coil L1 is applied and the current in the primary coil L1 flows, an induced current flows downward (one direction from one terminal P4 in the direction of a connection P3 ), as shown in the figure, in the secondary coil L2 , If the second switch SW2 is brought into the ON state, so the voltage of the DC voltage source 10 to a section between the center tap CT the primary coil L1 and the connection P2 created. Because the voltage to the primary coil L1 is applied and the current in the primary coil L1 flows, an induced current flows upward (one direction from the terminal P3 in the direction of the connection P4 ), as shown in the figure, in the secondary coil L2 ,

A control device 40 is configured to detect a detection value of the output voltage Vout (a load voltage) of the inverter circuit 21 from a voltage sensor 42 and detecting a detection value of the output current Iout (a load current) of the inverter circuit 21 from a current sensor 43 capture. Based on the detection values of the sensors 42 . 43 and one for the discharge load 31 required power becomes the driving frequency fsw of the switch SW1 . SW2 set. Then the control device gives 40 an instruction signal corresponding to the drive frequency fsw to the drive circuit 50 out. In accordance with the instruction signal, the driver circuit outputs 50 the drive signal GSW1 . GSW2 to a gate of the switch SW1 . SW2 out.

The discharge load 31 More specifically, it is an ozone generating device and is configured such that two plate-shaped electrodes protected with a dielectric are provided to sandwich an air layer (a discharge gap) therebetween, and a ceramic substrate is on one of two surfaces of each electrode on the opposite side Side of the air layer arranged. The discharge load 31 is a "capacitive discharge load". The equivalent circuit of the discharge load 31 can be considered as a series connected body of air-layer capacity cg as an electrostatic capacity of the discharge gap and a dielectric capacity Cp be represented as an electrostatic capacity of the dielectric.

Further, when the voltage applied to the discharge gap is a discharge sustaining voltage Va exceeds, so there is a Sperrentladung in the discharge gap. In a state in which the reverse discharge occurs, the voltage of the discharge gap becomes at the discharge sustaining voltage Va held. The properties when unloading the discharge load 31 can be called zener diodes DT1 . DT2 are shown with the air layer capacity cg are connected in parallel, the withstand voltage Va and are connected in opposite directions.

The spare capacity C the discharge load 31 changes according to the voltage to be applied. For the spare capacity C the discharge load 31 dominates the air layer capacity cg in a region of lower applied voltage, and the dielectric capacity Cp dominated in a region of high voltage.

The properties of the spare capacity C the discharge load 31 with respect to the applied voltage are based on 2 shown. 2 shows a temporal change of the inter-terminal voltage Vb the discharge load 31 in the event that to the discharge load 31 a predetermined voltage Vb1 . Vb2 in a relationship of Vb1 > Vb2 > Va is created.

In a case of applying the high voltage Vb1 begins the inter-terminal voltage Vb from one point in time T0 to rise and a discharge sustain voltage Va at a time Ta1 exceeds. Thus, the lock discharge starts at the time Ta1 , Subsequently, after the intermediate connection voltage Vb the high voltage Vb1 has reached, the intermediate connection voltage decreases Vb due to unloading by resonance. The intermediate connection voltage Vb drops below the discharge sustain voltage Va at a time Ta4 , and therefore the blocking discharge is at the time Ta4 stopped. Subsequently, the intermediate connection voltage is reached Vb at a time Ta5 zero.

In a case of applying the low voltage Vb2 begins the inter-terminal voltage Vb from the time T0 to rise and exceeds the discharge sustaining voltage Va at a time ta2 , Thus, the lock discharge starts at the time ta2 , Subsequently, after the intermediate connection voltage Vb the low voltage Vb2 has reached, the intermediate connection voltage decreases Vb due to unloading by resonance. The intermediate connection voltage Vb drops below the discharge sustain voltage Va at a time T a3 , and therefore the blocking discharge is at the time T a3 stopped. Subsequently, the intermediate connection voltage is reached Vb at the time T5 zero.

Compared to the case of applying the high voltage Vb1 occurs the increase of the inter-terminal voltage Vb later. Thus, the beginning of the blocking discharge occurs in the case of applying the low voltage Vb2 later ( ta2 > Ta1 ). In addition, in comparison with the case of applying the high voltage Vb1 , the tip of the inter-terminal voltage Vb lower. Thus, in the case of applying the low voltage Vb2 the end of the blocking discharge earlier ( Ta4 > T a3 ). For these reasons, ON period is for maintaining the reverse discharge between the case of applying the high voltage Vb1 and the case of applying the low voltage Vb2 different, and the period in the case of applying the high voltage Vb1 is longer.

The capacity of the discharge load 31 in the period for maintaining the reverse discharge is the dielectric capacity Cp , In addition, the capacity of the discharge load 31 in a period for generating no blocking discharge, a pre-discharge replacement capacity cb , The pre-discharge replacement capacity cb is obtained by the following expression: $$C_b=\frac{C_p{C}_G}{C_p+C_G}$$

In addition, if the percentage of the period for maintaining the blocking discharge in a voltage application period ( Ta0 to Ta5 in 2 ) d is the spare capacity Ce the discharge load 31 in the blocking discharge are represented as: $$C_e=d{C}_p+\left(1-d\right)C_b$$

The discharge load 31 as the capacitive load and the secondary side corresponding value lsb the separate leakage inductance of the primary and the secondary side of the transformer Tr form the resonance load 30 , The resonance frequency Fri. the resonance load 30 changes in conjunction with a change in replacement capacity C the discharge load 31 , as described above.

Thus, the frequency of the current (the load current lout ), which is in the secondary coil L2 flows. In conjunction with a change in the frequency of the load current lout the frequency of the current changes (a switch current sw flowing in the switch SW) in the primary coil L1 flows. Due to a change in the frequency fsw of the switch current sw becomes a surge voltage for the switch SW1 . SW2 generated. Thus there is a risk that the switches SW1 . SW2 may be damaged or a loss of performance is caused. The occurrence of the surge voltage in conjunction with a change in the frequency of the switch current sw in the push-pull inverter circuit 21 is described below.

In 3 is the current that flows in the event that the first switch SW1 in the ON state, indicated by a dash-dot line, and the current flowing immediately after the OFF operation of the first switch SW1 was performed in a state in which a forward current in the first switch SW1 flows is indicated by a dashed line.

As indicated by the dash-and-dot line, in a situation where the first switch SW1 is in the ON state and the forward current in the first switch SW1 flows, current flows in the leakage inductance Ls1 the primary coil L1 , and magnetic field energy becomes in the leakage inductance Ls1 accumulated. In this state, when the OFF operation of the first switch SW1 is executed, the current flows from the leakage inductance Ls1 into the parasitic capacitance Coss of the first switch SW1 as indicated by the dashed line. That is, those in the leakage inductance Ls1 accumulated magnetic field energy is accumulated as electric field energy in the parasitic capacitance Coss, and therefore the surge voltage occurs. It should be noted that there is a risk that the surge voltage similarly when the second switch OFF SW2 can occur.

4 FIG. 15 shows the surge voltage generated in a case where the OFF operation of the switch SW is performed in a state in which the on-state current flows in the switch SW. In a state where the switch current sw in a forward direction (for example 10 A) flows when the drive signal GSW is brought from the HIGH state to the LOW state and the OFF operation of the switch SW is executed, an extremely high voltage (the surge voltage) is generated in comparison to a voltage Vsw to be applied in a steady state. It should be noted that, in a full-bridge inverter, when a forward current flows, even if an OFF operation of a switch is performed, there is a return path due to a reflux diode, therefore no surge voltage is generated.

5 (a) shows a timing diagram of a change over time of the load current lout , of switch current sw and the drive signal GSW in the event that the resonant frequency Fri. the resonance load 30 and the driving frequency fsw of the switch SW coincide with each other. The load current lout changes according to the resonance frequency Fri. without being dependent on the drive frequency fsw. Moreover, in an ON period of the switch SW, the switch current sw designed to operate at the same frequency as the load current lout , In the event that the resonant frequency Fri. and the driving frequency fsw coincide with each other, an OFF timing for the switch SW and a zero-crossing timing for the load current are correct lout ie, a zero crossing time for the switch current sw , and therefore no surge voltage is generated in the switch SW.

5 (b) shows a timing diagram of a change over time of the load current lout , the switch current sw and the drive signal GSW in the event that the resonant frequency Fri. and the drive frequency sw are essentially the same and the resonant frequency Fri. is higher than the drive frequency sw , As in 5 (a) the load current changes lout according to the resonance frequency Fri. , without from the driving frequency sw to be dependent. In addition, the switch current sw in the ON period of the switch SW, is designed to operate at the same frequency as that of the load current lout , Because the resonant frequency Fri. is higher than the drive frequency sw , the OFF timing for the switch SW comes later than the zero-crossing point for the load current lout ie the zero crossing time for the switch current sw , Thus, no surge voltage is generated in the switch SW.

As described above, the frequency sw of the drive signal GSW adjusted so that the switch current sw the same phase ( sw = Fri. ) or the anticipatory phase ( sw < Fri. ) with respect to the drive signal GSW the SW switch has. Thus, the occurrence of the surge voltage in an OFF state in the push-pull inverter can be reduced.

In the event that the frequency sw of the drive signal GSW is set so that the switch current sw the same phase ( sw = Fri. ) or the anticipatory phase ( sw < Fri. ) with respect to the drive signal GSW of the switch SW, a power efficiency is at the maximum level when the switch current sw the same phase with respect to the drive signal GSW the SW switch has. That is, in the event that the driving frequency sw essentially equal to the resonant frequency Fri. is set, the power efficiency is at the maximum level. In addition, as in 6 2, the output power Pout of the power source device decreases 20 as the driving frequency increases sw the resonant frequency Fri. approaches.

For this reason, in the present embodiment, the driving frequency becomes sw near the resonance frequency Fri. is set and an intermittent output is executed as in 7 shown. In the intermittent output in the present embodiment, the percentage (duty ratio) of an ON time in each drive cycle of the switch becomes SW1 . SW2 kept at 50%. Further, the number of times of the ON operation of the first switch becomes SW1 and the second switch SW2 in a predetermined period, that is, the length of a power output period in the predetermined period, based on a ratio (rate) between a power instruction value Pout * (a supply power target value) and the output power Pout (a chargeable power), which is in accordance with the driving frequency sw is output, set.

In the event that the ratio between the output power Pout and the power instruction value Pout * (which for the discharge load 31 required power) = ( Pout * : Pout = 1: x, where x is an optional real number), it is set so that the length of the power output period (the period for alternately turning ON the switches SW1 . SW2 ) in the given period = 1 / x of the full predetermined period. Thus, when driving the switch SW1 . SW2 the driving frequency sw near the resonance frequency Fri. be adjusted while that of the power source device 20 to the discharge load 31 supplied energy near the power instruction value Pout * is set.

For example, in an in 7 shown example, the output power Pout a value twice the power instruction value Pout * (which for the discharge load 31 required power) ( Pout * : Pout = 1: 2). It is thus set so that the length of the power output period in the given period is half of a whole predetermined period. More specifically, in the in 7 Example shown, the predetermined period of time to a period of a length of 16 times the driving cycle of the switch SW1 . SW2 and the number of times of ON operation of each of the first switches SW1 and the second switch SW2 in the given period is eight (8 = 16/2).

8th FIG. 12 is a flowchart showing an intermittent output processing of the present embodiment. FIG. The processing discussed here is periodically performed by the controller 40 as a "calculation unit".

At step S01 it is determined whether the drive frequency sw essentially the same as the resonant frequency Fri. is or not. In this step, in the case where no power output instruction is input, the ratio (rate) between the power instruction value becomes Pout * and the output power Pout set to the smallest possible value based on which at step S04 the output power Pout can be calculated. More specifically, for the length of the output period, the ratio (rate) between the power instruction value becomes Pout * and the output power Pout set so that the ON operation of at least one of the switches SW1 . SW2 with a duty cycle of 50% in each drive cycle of the switch SW1 . SW2 can be executed. By the above-described control, in the case of inputting the power output instruction, that of the Power source means 20 to the discharge load 31 supplied power with favorable response near the power instruction value Pout * can be set. Moreover, in the case of inputting no power output instruction, the power consumption can be reduced. In the event that the driving frequency sw and the resonance frequency Fri. are not essentially the same S01 : YES), the control for setting the drive frequency sw near the resonance frequency Fri. at step S02 executed, and then the processing ends. More precisely, will be at step S02 the driving frequency sw held in the region of a leading phase, and the control for changing the driving frequency sw such that the output power Pout increases, is executed.

In the event that the driving frequency sw and the resonance frequency Fri. are essentially equal to each other ( S01 : NO), becomes at step S03 , determines whether the instruction for power output from the power source device 20 to the discharge load 31 from a parent ECU into the controller 40 is entered or not. In the event that no power output instruction in the control device 40 is entered ( S03 : NO), the processing ends.

In the event that the power output instruction in the control device 40 is entered ( S03 : YES), that becomes the resonance load 30 supplied output power Pout at step S04 on the basis of the detection values of the output voltage Vout and the load current lout calculated. At step S05 becomes the ratio between the power instruction value Pout * and the output power Pout calculated. Then at step S06 a time corresponding to the product of the ratio between the power instruction value Pout * and the output power Pout and the predetermined period of time as the output period, and the processing ends.

When an output state and a stop state of the power source device 20 are repeated by the intermittent output operation, and when the stop state enters the output state and the output state again occurs, so here becomes the bias magnetization of the transformer Tr to a problem. More specifically, it is feared that excitation current ILM who is in the transformer Tr flows, becomes excessively high, causing the transformer Tr becomes magnetically saturated.

9 illustrates a model diagram of the flow of excitation current ILM of the transformer Tr , The transformer Tr can be represented as a T-shaped equivalent circuit having an excitation inductance LM , a primary-side leakage inductance Lsa and a secondary-side leakage inductance lsb includes. The excitation current ILM to energize the transformer Tr flows on the primary side of the transformer Tr (a solid line).

In this state, when both switches SW1 . SW2 be brought into the OFF state to the power source device 20 switch from the output state to the stop state, the excitation current ILM no longer on the primary side of the transformer Tr flow. Thus, the excitation current flows ILM on the secondary side of the transformer Tr (a dashed line). The excitation current ILM , which flows on the secondary side, comes at the excitation inductance LM , the leakage inductance lsb and the capacitive discharge load 31 in resonance. Thus, there is a risk that the DC source 10 , depending on the time of resuming the output, with the primary coil L1 is connected to the excitation current ILM lift, and the transformer Tr becomes magnetically saturated.

10 shows a timing diagram of a temporal change of the excitation current ILM when executing the intermittent output. In the issue period, the switch SW1 and the switch SW2 alternately ON / OFF switched. At a time T1 becomes the switch SW2 brought into the OFF state, and the OFF state of the switch SW1 to be continued. In this way, both switches SW1 . SW2 brought into the OFF state, and therefore the output period goes to the stop period.

After the time T1 the excitation current flows ILM in the excitation inductance LM , the secondary side leakage inductance lsb and the discharge load 31 , In the stop period, the excitation current changes ILM with a resonant frequency 1 / (2π√ ((LM + Lsb) CCb)) in an LC resonant circuit which detects the excitation inductance LM , the secondary side leakage inductance lsb and the discharge load 31 includes. On the other hand, in the output period, the exciting current changes ILM with the resonance frequency Fri. (= 1 / (2π√ (Lsb · Ce))) of the resonant circuit, which is the secondary side leakage inductance lsb and the discharge load 31 includes. The excitation inductance LM is greater than the secondary-side leakage inductance lsb , and the frequency of the excitation current ILM in the stop period is lower than that of the output period. Thus, the excitation current has ILM in the stop period, a larger amplitude than that of the output period.

At a time T2 becomes the switch SW1 is brought into the ON state and transitions from the stop period to the issue period. At this point there is a risk that right after the time T2 at the transition from the Output period to the stop period, the DC power source 10 with the primary coil L1 can be connected to the excitation current ILM and therefore the excitation current ILM excessively high, and the transformer Tr becomes magnetically saturated.

For this reason, in the embodiment of the present embodiment, a third switch SW3 arranged in the middle of a connecting line, which is the center tap CT and the DC voltage source 10 connects, as in 1 illustrated. More precisely, the switch SW3 closer to the center tap CT arranged as the smoothing capacitor Cin. A body diode D3 is in the reverse direction with the switch SW3 connected in parallel. A cathode of the diode D3 is with a drain of the switch SW3 connected, and an anode of the diode D3 is with a source of the switch SW3 connected. The desk SW3 is brought into an ON state by a drive signal GSW3 in a HIGH state from the driver circuit 50 receives, and is brought into an OFF state by the drive signal GSW3 in a LOW state.

In the output period, the control device stops 40 the switch SW3 constant in the ON state and switches the switches SW1 . SW2 alternately ON / OFF, thus leading the power output to the discharge load 31 out. In addition, the control device stops 40 in the stop period the switch SW3 constant in the OFF state and holds the switches SW1 . SW2 constant in the ON state and thus stops the power output to the discharge load 31 and leaves the excitation current ILM on the side of the primary coil L1 flow back. These types of control can provide an excessively high excitation current ILM be reduced immediately after the transition from the stop period to the output period.

11 FIG. 12 is a flowchart showing the processing of switching between the output period and the stop period. FIG. The processing discussed here is periodically performed by the controller 40 as a "driving unit" executed.

At step S11 It is determined whether the output period is currently present or not. In the case of the issue period ( S11 : YES) will step at S12 determines whether the timing of switching from the output period to the stop period has come or not. If the time of switching to the stop period has not yet arrived ( S12 : NO), the switch becomes SW3 at step S13 brought into the ON state, and the process of alternately turning ON / OFF the switch SW1 . SW2 with the drive frequency sw (the resonance frequency Fri. ) is executed at step S14. Then the processing ends.

In the event that the time of switching from the issue period to the stop period has come ( S12 : YES), the current ON / OFF states become the switches SW1 . SW2 at step S15 saved. Then the switches SW1 . SW2 at step S16 brought into the ON state, and the switch SW3 is brought into the OFF state. In this way, the switching from the output period to the stop period is executed.

If at step S11 the stop period is detected ( S11 : NO), so at step S17 determines whether the timing of switching has come to the output period or not. In the event that the time of switching to the issue period has not yet arrived ( S17 : NO), the switches become SW1 . SW2 at step S18 brought into the ON state, and the switch SW3 is brought into the OFF state.

In the event that the time of switching from the stop period to the output period has come ( S17 : YES), the switch becomes SW3 at step S19 brought into the ON state, and the ON / OFF states of the switches SW1 . SW2 are set to the state opposite to that in step S15 was saved. More precisely, will be at step S19 the desk SW1 set to the OFF state, and the switch SW2 is set to the ON state if at step S15 the desk SW1 is in the ON state and the switch SW2 is in the OFF state. Alternatively, the switch SW1 set to the ON state, and the switch SW2 is set to the OFF state, if at step S15 the desk SW1 in the OFF state is and the switch SW2 is in the ON state.

twelve shows a timing diagram of a temporal change of the excitation current ILM upon execution of an intermittent output of the present embodiment. In the issue period, the switch SW1 and the switch SW2 alternately ON / OFF switched. Immediately before a time T11 is the switch SW1 in OFF state, the switch SW2 is in the ON state, and the switch SW3 is in the ON state. Immediately before the time T11 is the duty cycle of the switch SW2 50%.

After the time T11 the excitation current flows ILM to a primary-side closed circuit, which is the primary leakage inductance Ls1 . Ls2 and the switches SW1 . SW2 having. In the stop period, the excitation current is ILM a substantially constant value. In addition, will a connection between the transformer Tr and the DC voltage source 10 locked, and therefore vibrates the secondary-side voltage Vout during damping.

Subsequently, at a time T12 both switches SW1 . SW2 brought into the ON state, and the switch SW3 is brought into the OFF state. In this way, the output period goes to the stop period. Right after the time T12 is the duty cycle of the switch SW1 50%.

At the time T12 becomes the switch SW2 put in the off state, and the third switch SW3 is brought into the ON state. In this way, the stop period goes to the output period. At the time T12 will the switch ( SW2 in 10 ) who is other than one ( SW1 in 11 ) the desk SW1 . SW2 in the ON state right before the time T11 , brought into the ON state. This changes, right after the time T12 , the excitation current ILM in the direction of decreasing an absolute value of the excitation current ILM , In addition, the duty cycle (50% in 11 ) of the switch SW1 right before the time T11 and the duty cycle (50% in 11 ) of the switch SW2 right after the time T12 essentially equal to each other. By these kinds of control, 0 A can be considered the center of an ac-type oscillation of the excitation current ILM can be taken, and therefore, a magnetic saturation in the transformer Tr be reduced.

Hereinafter, advantageous effects of the present embodiment will be described.

Using the push-pull inverter circuit 21 The drive frequency is set to a maximum of the resonance frequency. That's the way the electricity works I1 who is in the switch SW1 . SW2 flows, a leading phase with respect to the switch SW1 . SW2 applied voltage V1 and therefore, the occurrence of the surge voltage can be reduced. Furthermore, the embodiment is such that the drive frequency sw near the resonance frequency Fri. is set and that the power output from the inverter circuit 21 is executed in the output period based on the power instruction value Pout * and the output power Pout is set in the given period. With this configuration, the energy, the discharge load 31 as the capacitive load is supplied near the power instruction value Pout * can be adjusted, and the power efficiency can be improved.

In the output period, the exciting current flows ILM in the primary coil L1 , When the DC voltage source 10 and the primary coil L1 be brought into a locked state in the stop period, the magnetic energy flowing in the transformer flows Tr through the excitation current ILM accumulated to the secondary side. In the stop period, when the output period is resumed in a state in which the excitation current ILM flows on the secondary side, the excitation current increases ILM depending on the time, and for this reason, it is feared that the transformer Tr becomes magnetically saturated. Therefore, the third switch SW3 arranged to reduce the magnetic saturation at the beginning of the output period.

More specifically, in the stop period, the third switch SW3 brought into the OFF state, so that the power output is stopped. In addition, the first switch SW1 and the second switch SW2 brought into the ON state, causing a short circuit of both terminals of the primary coil L1 entry. In this way, the excitation current flows ILM to the primary side, and therefore the flow of the excitation current ILM to the secondary side of the transformer Tr be reduced. Consequently, an increase in the amplitude of the excitation current ILM due to a reduction in the frequency of the excitation current ILM be reduced.

The design is such that in the event that one of the switches SW1 . SW2 when switching from the output period to the stop period is in the ON state and the other is the switch SW1 . SW2 is in the off state, one of the switches SW1 . SW2 which is not the switch in the OFF state in the output period, is brought to the OFF state on subsequent switching from the stop period to the output period, and the other of the switches SW1 . SW2 which is not the switch in the ON state in the output period is brought into the ON state. With this configuration, the voltage at the beginning of the output period to the transformer Tr in the direction of reducing the excitation current ILM which flows in the stop period, and the excitation current ILM can be in the direction of reducing the absolute value of the excitation current ILM be changed. Thus, a magnetic saturation in the transformer Tr be reduced.

Second Embodiment

A control device 40 In a second embodiment, when switching from the output period to the stop period, during ¼ period of a drive cycle as the inversion of a drive frequency, one of the switches SW1 . SW2 in an ON state and brings the other the switch SW1 . SW2 in an OFF state. Subsequently, the control device brings 40 both switches SW1 . SW2 in the ON state, thus switching the output period to the stop period.

More specifically, as in 13 is shown, an ON time (a duty cycle) of the switch SW1 . SW2 just before switching from the output period to the stop period (a time T21) is reduced from about 50% to about 25%. Accordingly, when switching from the output period to the stop period, a primary current I has a delay phase of 1/8 cycle with respect to a primary side voltage V.

In the issue period, if one of the switches SW1 . SW2 is brought to the ON state during the 1/4 period of the drive cycle, reaches an excitation current ILM about zero, and those in a transformer Tr accumulated magnetic energy reaches about zero.

Further, when switching from the stop period to the output period (a time T22 ) one of the switches SW1 . SW2 during the 1/4 period of the drive cycle brought into the ON state, and the other of the switches SW1 . SW2 is brought into the OFF state. That is, upon transition from the stop period to the output period, the ON time (duty) of the switch becomes SW1 . SW2 decreased from about 50% to about 25%. With this configuration, the maximum value of the level of the excitation current ILM are set substantially immediately after the beginning of the output period in accordance with the maximum value in a stable output period, and a magnetic saturation of the transformer Tr can be reduced.

Third Embodiment

14 illustrates an electrical embodiment of a third embodiment. In the embodiment of the present embodiment, there is no third switch SW3 , In addition, the design is such that a fourth switch SW4 is present as a semiconductor switching element connected between a connection point of a primary coil L1 and a first switch SW1 and a connection point of the primary coil L1 and a second switch SW2 connected is. More precisely, the fourth switch is SW4 designed so that two MOSFETs (switch SW4a . SW4b ) are connected in series. Furthermore, body diodes (diodes D4a . d4b ), each connected in parallel with these two MOSFETs, are connected in opposite directions. That is, the body diodes are connected such that anodes or cathodes are connected together. It should be noted that an IGBT can be used as the fourth switch.

In an output period, an excitation current flows ILM in the primary coil L1 , If a DC voltage source 10 and the primary coil L1 In a stop period, a locked state causes magnetic energy to flow in a transformer Tr through the excitation current ILM accumulated to a secondary site. In the stop period, when the output period is resumed in a state in which the excitation current ILM flows on the secondary side, the excitation current increases ILM depending on the time, and for this reason, it is feared that the transformer Tr becomes magnetically saturated. Thus, the fourth switch is used SW4 the purpose of reducing the magnetic saturation at the beginning of the output period.

More specifically, a control device brings 40 as a "driving unit" both the first switch SW1 as well as the second switch SW2 during the stop period in an OFF state and thus blocks the current in the primary coil L1 from the DC voltage source 10 flows, and brings the fourth switch SW4 in an ON state. In addition, the control device brings 40 , during the issue period, the fourth switch SW4 in an OFF state and brings in alternation the first switch SW1 and the second switch SW2 in an ON state.

In the stop period, both switches will turn on SW1 . SW2 brought into the OFF state, so that the power output is stopped, and the fourth switch SW4 is brought into the ON state. In this way, a short circuit of both terminals of the primary coil L1 brought about. Accordingly, the excitation current flows ILM to a primary side, and the flow of the excitation current ILM to the secondary side of the transformer Tr can be reduced. In addition, an increase in the amplitude of the excitation current ILM due to a reduction in the frequency of the excitation current ILM be reduced. Furthermore, the fourth switch SW4 in the output period is brought into the OFF state, and therefore, the power output from the primary side to the secondary side can be carried out in the normal way.

Fourth Embodiment

15 illustrates an electrical embodiment of a fourth embodiment. The embodiment of the present embodiment is an embodiment obtained by adding an LC filter circuit 22 to the embodiment of in 1 illustrated first embodiment.

As in the configuration of the first embodiment, in the configuration of the fourth embodiment, a path that is a connection point of a third switch SW3 and a positive terminal of a DC voltage source 10 and a connection point of a first switch SW1 and a second switch SW2 connects, present, and a smoothing capacitor Cin is located in the path. With the smoothing capacitor Cin will be in an inverter circuit 21 supplied voltage smoothed (stabilized).

Furthermore, in the embodiment of the present embodiment, the LC filter circuit is 22 between the smoothing capacitor Cin and the DC voltage source 10 arranged. An induction coil Lf containing the LC filter circuit 22 is arranged in a path which the positive terminal of the DC voltage source 10 and the third switch SW3 combines. A capacitor Cf that the LC filter circuit 22 is arranged in a path having the positive terminal and a negative terminal of the DC power source 10 closer to the DC voltage source 10 connects, as the induction coil Lf located. The LC filter circuit 22 is designed to inject high frequency noise into the DC power source 10 due to the operation of the inverter circuit 21 to reduce.

When switching from the output period to the stop period, the third switch SW3 brought into an OFF state, so that the DC voltage source 10 and the inverter circuit 21 be brought into a locked state. At this point, the current flowing from the induction coil flows Lf to the inverter circuit 21 (a center tap CT ) flows, ie in the induction coil Lf accumulated energy, in the smoothing capacitor Cin , Due to the flow of current from the induction coil Lf in the smoothing capacitor Cin increases the inter-terminal voltage of the smoothing capacitor Cin , Therefore, the withstand voltage of the smoothing capacitor must be Cin be increased, causing a problem such as an increase of the smoothing capacitor Cin ,

Based on 16 will be a change in the inter-terminal voltage of the smoothing capacitor Cin when switching from the output period to the stop period described above. In 16 is a time T40 the timing of switching from the output period to the stop period. An input current Iin is a current supplied from a power source and a center tap current ict is a current that is over the third switch SW3 to the center tap CT flows.

In the issue period before the time T40 there is a drive signal GSW3 (not shown) constant in a HIGH state, and accordingly, the switch SW3 constant in an ON state. control signals GSW1 . GSW2 are alternately brought into a HIGH state, and accordingly, the switches SW1 . SW2 alternately brought into an ON state. In addition, the input current Iin due to the LC filter circuit 22 a direct current. Furthermore, the input current changes Iin periodically in a drive cycle to drive the switch SW1 . SW2 ,

At the time T40 brings a control device 40 both drive signals GSW1 . GSW2 in the HIGH state, and accordingly both switches SW1 , 2 brought into the ON state. In addition, the drive signal GSW3 (not shown) constant in a LOW state, and therefore the third switch SW3 in the ON state. Thus, a power source device goes 20 from the issue period to the stop period via. At the time T40 becomes an electrical connection between the induction coil Lf and the inverter circuit 21 separated, ie a closed circuit, the induction coil Lf and the primary coil L1 includes, no longer exists. Thus, the center tap current reaches ict that of the induction coil Lf to the center tap CT flows, zero. In addition, the induction coil current flowing from the induction coil flows Lf to the smoothing capacitor Cin and the center tap CT flows into the smoothing capacitor Cin ,

That is, at the time T40 An LC resonance occurs between the induction coil Lf and the smoothing capacitor Cin through the induction coil Lf accumulated energy. The value of the maximum amount ΔVc the change of the inter-terminal voltage Vc of the smoothing capacitor Cin due to the LC resonance can be represented as ΔVc = √ {(Lf / Cin) (Iin0-Ict0) ^ 2}, wherein the capacitance value of the smoothing capacitor Cin is, the inductance value of the induction coil Lf is, the input current Iin at the time T40 Iin0 is, and the center tap current ict at the time T40 IctO is. That is, the peak value of the inter-terminal voltage Vc of the smoothing capacitor Cin is proportional to the input current Iin0 at the time of switching from the output period to the stop period.

Thus, the control device controls 40 as a "driving unit" of the present embodiment in the output period alternately the first switch SW1 and the second switch SW2 with a predetermined drive frequency sw and a predetermined duty cycle of a maximum of 50%. Furthermore, the changes control device 40 the duty ratio in a decreasing direction in a predetermined time period including, in the output period, the timing of switching to the stop period. At the time of switching from the output period to the stop period, the above-described control may be that in the induction coil Lf reduce accumulated energy and may increase the inter-terminal voltage of the smoothing capacitor Cin reduce.

In addition, the control device performs 40 in the inverter circuit 21 the burst output of outputting an output current lout in the output period and stopping the output current lout in the stop period. That is, the output current lout the inverter circuit 21 changes periodically taking the total period of the single issue period and the single stop period as a single cycle (a burst cycle). Thus, the output current has lout the inverter circuit 21 a frequency component corresponding to the inverse of the burst cycle and a frequency component of the nth harmonic thereof. The frequency components due to the burst cycle have a lower frequency than, for example, a resonant frequency Fri. , and therefore it is feared that such components have frequencies in an audible range. A negative effect due to the frequency components of the output current lout which result from the burst cycle and occur in the audible range, such as the occurrence of noise due to the bias magnetization, becomes a problem.

For this reason, the control device 40 is configured to change the duty ratio so that the duty ratio changes in an increasing direction from the time of starting the dispensing period to a predetermined time during such dispensing period that the duty ratio in the decreasing direction from the predetermined time to the time of Ending of the output period changes, and that the amplitude of an output voltage Vout in the output period changes in a cycle that is twice as long as the output period. More specifically, it is designed to match the on-time of the switch SW1 . SW2 so changes that the amplitude (the width of the envelope of the output voltage Vout from top to bottom) of the output voltage Vout of the inverter circuit 21 sinusoidally changes, as in 17 , More specifically, it is designed to increase the on-time of the switch SW1 . SW2 changes so that the absolute value (the modulation factor) of the amplitude of the output voltage Vout changes in a half-rectified waveform of a sine wave. That is, the control device 40 Brings the amplitude of the output voltage Vout at the time of starting the output period substantially to zero, and then increases the amplitude of the output voltage Vout sinusoidally. At an intermediate time between the beginning and the end of the output period, the amplitude of the output voltage Vout is made the maximum value, and then the amplitude of the output voltage Vout is reduced sinusoidally. Then, the amplitude of the output voltage Vout is made substantially zero at the end of the output period. With the present embodiment, each frequency component of the output voltage Vout due to the burst cycle can be attenuated, and the negative effect due to the frequency components of the output current lout that belong to the audible range can be reduced.

In the embodiment, in which the duty ratio is changed in the increasing direction from the time of starting the output period to the predetermined time during the output period, and the duty ratio is changed in the decreasing direction from the predetermined time to the time of the completion of the output period , the duty ratio (the percentage of ON time in the drive cycle) of the switch changes SW1 . SW2 in the decreasing direction in the predetermined period, which, in the output period, includes the timing of switching to the stop period. That is, at the time of switching from the output period to the stop period, the energy accumulated in an induction component can be reduced, and an increase in the inter-terminal voltage Vc of the smoothing capacitor Cin can be reduced.

When the control of the present embodiment is carried out, the duty ratio of the switch includes SW1 . SW2 in the output period, a duty ratio of less than 50%, and for this reason, the output voltage Vout is lower than in the case of setting the duty of the switch SW1 . SW2 to 50%. Therefore, it is feared that one of a discharge load 31 supplied energy decreases. For this reason, the control device 40 in the case of reducing the on-time of the switch SW1 . SW2 a longer output period to reduce the output power Pout to be considered in conjunction with a reduction of the duty cycle.

Based on 18 will be a change in the inter-terminal voltage of the smoothing capacitor Cin in a case of changing the duty ratio so that the amplitude of the Output voltage in the output period changes sinusoidally described.

In a period before the date T50 during the issuing period (ie, a period from when the issue period is started to a given time T50 during the output period), the duty cycle of each switch changes SW1 . SW2 (each drive signal GSW1 . GSW2 ) in the increasing direction. At the time T50 reaches the duty cycle of each switch SW1 . SW2 the maximum value (50%). In the period before the date T50 during the output period, the amplitude (the width of the envelope from top to bottom) of the output voltage Vout changes in the increasing direction, the amplitude (the peak value) of the center tap current ict the inverter circuit 21 changes in the increasing direction, and the input current Iin changes in the increasing direction.

After the time T50 the duty cycle of each switch changes SW1 . SW2 in the decreasing direction over a period from the time T50 until one time T51 as the time of the completion of the issue period. In the period from the date T50 until that time T51 That is, the amplitude (the width of the envelope from top to bottom) of the output voltage Vout changes in the decreasing direction, the amplitude (the peak value) of the center tap current ict changes in the decreasing direction, and the input current Iin changes in the decreasing direction.

At the time T51 Both are control signals GSW1 . GSW2 put in the HIGH state, and therefore both switches SW1 . SW2 brought into the ON state. In addition, the drive signal GSW3 (not shown) brought into the LOW state, and therefore the switch SW3 brought into the off state. In this way, the switching from the output period to the stop period is executed. When switching from the output period to the stop period, the input current becomes Iin decreases, and therefore becomes in the induction coil Lf accumulated energy decreases. Thus, an increase in the inter-terminal voltage of the smoothing capacitor Cin in conjunction with the flow of current from the induction coil Lf in the smoothing capacitor Cin be reduced.

Furthermore, the discharge load 31 , which is designed for that of the inverter circuit 21 to receive applied energy, a non-linear element designed so that the voltage and the current are not in a proportional relationship. Thus, the duty of the switch SW1 . SW2 adjusted so that the amplitude of the output voltage Vout sinusoidally changes, but the amplitude of the output voltage Vout actually changes in a distorted sinusoidal waveform.

19 shows the magnitude of the frequency component of the noise voltage of the inverter circuit 21 due to the burst cycle. The frequency component of the noise voltage in a case of constantly setting the on-time of the switch SW1 . SW2 to 50% in the issue period is indicated by the color black. Moreover, in the case of the sinusoidal change, the frequency component of the noise voltage is the duty ratio of the switch SW1 . SW2 indicated in the present embodiment by the color gray. As in 19 As shown, the control of the present embodiment is carried out so that the n-th harmonic component of the burst frequency can be reduced.

It should be noted that above the embodiment in which the LC filter circuit 22 between the DC voltage source 10 and the smoothing capacitor Cin is arranged, but can also be omitted. Even in the embodiment without the LC filter circuit 22 The flow of current from a parasitic induction coil, which is located between the DC voltage source 10 and the smoothing capacitor Cin located in the smoothing capacitor Cin instead of. Thus, even in the case where the configuration of reducing the duty ratio of the switch SW1 . SW2 in the predetermined period including, in the output period, the timing of switching to the stop period, to the embodiment without the LC filter circuit 22 is applied, an increase in the inter-terminal voltage of the smoothing capacitor Cin also be reduced.

Modifications of the embodiment for changing the duty cycle of the switch SW1 . SW2 in the increasing direction from the time of starting the output period to the predetermined time during the output period and changing the on-time of the switch SW1 . SW2 in the decreasing direction from the predetermined time to the time of the completion of the output period may include a configuration in which the control device 40 the duty cycle of each switch SW1 . SW2 so adjusts that the output voltage Vout changes in a triangle waveform. In this case, the adjustment can be made so that the on-time of the switch SW1 . SW2 between times is the same.

The modifications of the configuration for changing the duty in the decreasing direction in the predetermined period, which, in the output period, the timing of switching to the stop period, may include a configuration in which the control device 40 the duty cycle of each switch SW1 . SW2 at the specified time during the output period and the duty cycle of each switch SW1 . SW2 shortened after the given time.

In the description of the present embodiment, the electrical configuration of the first embodiment is assumed; however, instead of such a configuration, the electrical configuration of the third embodiment may be adopted. On the basis of such assumption of the electrical configuration of the third embodiment, the configuration may be made such that in the output period, the duty ratio of the switch SW1 . SW2 is changed in the increasing direction from the time of starting the output period to the predetermined time during the output period, and is changed in the decreasing direction from the predetermined time to the time of the completion of the output period. In addition, the embodiment can be made such that the fourth switch SW4 is turned off in the output period. Furthermore, in the stop period, both switches SW1 . SW2 be turned off, and the fourth switch SW4 can be brought into the ON state.

Other Embodiments

It may be a configuration without smoothing capacitor Cin to be provided.

In the first, second and fourth embodiments, the configuration is such that the switch SW3 between the DC voltage source 10 and the center tap CT is arranged. However, instead of such a configuration, the configuration may also be such that the switch SW3 between the connection point of the first switch SW1 and the second switch SW2 and the DC voltage source 10 is arranged (a connection point of an emitter of the first switch SW1 and an emitter of the second switch SW2 ). It should be noted that in the embodiment with the smoothing capacitor Cin the configuration can be made such that the switch SW3 closer to the connection point of the first switch SW1 and the second switch SW2 is arranged as the smoothing capacitor Cin ,

In the second embodiment, the configuration may be such that a reflux diode DT , in addition to the electrical design of in 1 illustrated first embodiment, closer to the primary coil L1 is arranged as it is the third switch SW3 in a path that is the center tap CT and connecting the connection point of the first switch SW and the second switch SW, as in 20 illustrated.

In the present embodiment, the output period goes to the stop period as soon as one of the switches SW1 . SW2 during the 1/4 period of the drive cycle is brought into the ON state. In this embodiment, the switch SW3 put in the off state while the power in the switch SW3 flows, and the surge voltage is at the switch SW3 caused. Thus, the embodiment is made such that the reflux diode DT is present, and therefore that can be at the switch SW3 caused surge voltage can be reduced.

In addition, even in the embodiment in which the switch SW3 between the connection point of the first switch SW1 and the second switch SW2 and the DC voltage source 10 is arranged, the configuration also be made so that the reflux diode DT closer to the primary coil L1 is arranged as the third switch SW3 on the path that the center tap CT and connects the connection point of the first switch SW and the second switch SW.

In the first embodiment, the configuration is such that one of the switches SW1 . SW2 is turned ON with a duty of 50% just before switching from the output period to the stop period and the other of the switches SW1 . SW2 is turned ON with a duty of 50% just before the subsequent switching from the stop period to the issue period; however, this configuration can be changed. For example, the embodiment may be such that one of the switches SW1 . SW2 is turned ON with a predetermined duty ratio (A%) immediately before switching from the output period to the stop period, and the other of the switches SW1 . SW2 is turned ON with the predetermined duty ratio (A%) immediately before the subsequent switching from the stop period to the output period (A is an optional value from 0 to 50).

The embodiment may be such that a coil in series with the discharge load 31 inserted on the secondary side. In this embodiment, the resonance frequency Fri. by the secondary-side corresponding value lsb the separate leakage inductance of the primary and the secondary side of the transformer Tr , the inductance of the coil and a capacity component of the discharge load 31 certainly.

The desk SW1 . SW2 does not need to be an N-channel MOSFET. For example, an IGBT can be used. It should be noted that in the case of using the IGBT as the switch SW1 . SW2 the embodiment can be made so that a reflux diode is present.

In the embodiments described above, the configuration is made such that the power output is stopped in such a manner that the switches SW1 . SW2 Be turned ON and the switch SW3 is turned off in the stop period. Instead, the switch can SW3 be omitted, and the configuration can be made so that SW1 . SW2 be turned off in the stop period.

Furthermore, the embodiment in the embodiment without the switch SW3 such that the stop period at the time passes to the output period at which the excitation current ILM becomes essentially zero. In this case, the excitation current gets ILM during the stop period in a resonant cycle resonating, which is the excitation inductance LM , the pre-discharge replacement capacity cb the discharge load 31 and the secondary side parasitic capacitance. Thus, the output period at the time passes to the stop period at which the excitation current ILM becomes substantially zero, and the stop period goes to the output period at the time point after kx of the resonance cycle has elapsed (k is an optional natural number). Thus, the stop period at the time may transition to the output period at which the excitation current ILM becomes essentially zero.

21 shows a timing diagram of a temporal change of the excitation current ILM when performing an intermittent output in the present modification. At a time T31 at which the excitation current ILM reaches substantially zero, the switching from the output period to the stop period is executed. That is, at the time T31 becomes the switch SW2 in the ON state brought into the OFF state, and in this way both switches SW1 . SW2 brought into the off state. Subsequently, at a time T32 at which the excitation current ILM achieved essentially zero after a period of 7 x the resonant cycle at the time T31 has elapsed, the switching from the stop period to the issuing period is executed. This can be an excessively high excitation current ILM reduce.

The excitation current ILM has a correlation with the secondary side current that is in the secondary coil L2 flows, and the secondary side voltage in the secondary coil L2 is generated. The control device 40 as a "detection value detection unit" may be the detection value of the output current lout as a detection value of the secondary-side current, that in the secondary coil L2 flows. In addition, the control device 40 as the "detection value detection unit", the detection value of the output voltage Vout as a detection value of the secondary side voltage, that in the secondary coil L2 is generated.

Thus, the control device performs 40 on the basis of the secondary side current detection value or the secondary side voltage detection value, switching from the stop period to the output period if the exciting current ILM who is in the transformer Tr flows, is less than a predetermined value.

More specifically, as in 22 is shown switching from the stop period to the output period is executed in the case that the absolute value of the detection value (the detection value of the output voltage Vout ) of the secondary side voltage is substantially the maximum value. The secondary side voltage and the excitation current ILM have a phase difference of about 90 degrees, and therefore reaches the excitation current ILM substantially zero in the case that the absolute value of the secondary side voltage is substantially the maximum value. Thus, the switching from the stop period to the output period can be performed at the time when the excitation current ILM essentially goes to zero, and as a result, the magnetic saturation in the transformer Tr be reduced.

In addition, when switching from the stop period to the output period, a ratio of the time period with respect to the drive cycle is one in which the switch SW2 ) of the first switch SW1 and the second switch SW2 is brought into the ON state and the other (the switch SW1 ) of the first switch SW1 and the second switch SW2 is brought to the OFF state, half of a target ratio (for example 1/2), as in 22 illustrated. Subsequently, the ratio of the period - with respect to the drive cycle - in which the other (the switch SW2 ) of the first switch SW1 and the second switch SW2 is brought into the ON state and one (the switch SW1 ) of the first switch SW1 and the second switch SW2 brought into the OFF state, brought to the target ratio. With this configuration, an excessively high excitation current ILM be reduced immediately after the transition from the stop period to the output period.

In this case, the configuration may be such that when switching from the stop period to the output period, the ratio of the time period with respect to the drive cycle in which one of the first switch SW1 and the second switch SW2 is brought into the ON state and the other of the first switch SW1 and the second switch SW2 is set to the OFF state, set to a predetermined value smaller than the target ratio (for example, 1/2). Furthermore, the configuration may be such that after the elapse of a predetermined period of time, the ratio of the time period with respect to the drive cycle, in which one of the first switch SW1 and the second switch SW2 is brought into the ON state and the other of the first switch SW1 and the second switch SW2 is brought into the OFF state, then increased to the target ratio. In this case, the configuration may be such that the ratio of the time period with respect to the drive cycle in which one of the first switch SW1 and the second switch SW2 is brought into the ON state and the other of the first switch SW1 and the second switch SW2 is brought into the OFF state, is gradually increased. With such a configuration, an excessively high excitation current ILM be reduced immediately after the transition from the stop period to the output period.

The present disclosure has been described according to the embodiments. However, it should be understood that the present disclosure is not limited to these embodiments and structures. The present disclosure also includes a variety of variations and variations within an equivalent scope. In addition, various combinations and shapes as well as other combinations and shapes that include these various combinations and shapes with only a single component, more or less, also fall within the spirit and scope of the present disclosure.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• JP 2016077264 [0001]
• JP 2016200351 [0001]
• JP 5681943 [0005]

Claims (15)

A power source device (20), comprising: a push-pull inverter circuit (21) configured to receive a DC power supplied from a DC power source (10) and to output an AC power to a capacitive load (31), the inverter circuit comprising: a transformer (Tr) having a primary coil (L1) with a center tap (CT) and a secondary coil (L2) magnetically coupled to the primary coil, a first switch (SW1) and a second switch (SW2) as semiconductor switching elements respectively connected to both ends of the primary coil, and a first diode (D1) and a second diode (D2) each connected in parallel with the first and second switches in the reverse direction, the center tap being connected to one terminal of the DC voltage source and the first and second switches being connected to the other terminal the DC voltage source are connected; a drive unit (40) configured to drive the first switch and the second switch in alternation with a drive frequency that is at most equal to a resonance frequency of a resonance circuit (30) having a secondary side corresponding value (Lsb) of the separate leakage inductance the primary and the secondary side of the transformer and a capacitance of the capacitive load and which is close to the resonant frequency; and a calculation unit configured to calculate a ratio between a dispersible power of the inverter circuit determined according to an output voltage of the inverter circuit and the drive frequency and a target power as a target value for a supply power supplied to the capacitive load calculate, where the driving unit sets, in a predetermined period of time, a time corresponding to a product of the predetermined time period and the ratio calculated by the calculating unit as an output period to change the first switch and the second switch to an ON state during the output period, and the driving unit is set in the predetermined period of time other than the output period as a stop period to block a current flowing from the DC voltage source to the primary coil during the stop period. Power source device according to Claim 1 wherein the power source device further comprises a third switch (SW3) as a semiconductor switching element connected between the center tap and the DC power source or between a connection point of the first and second switches and the DC power source. Power source device according to Claim 2 wherein the drive unit holds the third switch in an ON state during the output period, and the drive unit holds the third switch in an OFF state during the stop period, thereby disabling the current flowing from the DC voltage source to the primary coil and the first switch and the second switch are brought into the ON state. Power source device according to Claim 3 wherein the current source device further comprises a return diode (DT) arranged in a path connecting the center tap and the connection point of the first and second switches closer to the primary coil than the third switch. Power source device according to Claim 1 wherein the power source device further comprises a fourth switch (SW4) as a semiconductor switching element connected between a connection point of the primary coil and the first switch and a connection point of the primary coil and the second switch. Power source device according to Claim 5 wherein the drive unit holds the fourth switch in an OFF state during the output period, and the drive unit holds the first and second switches in an OFF state during the stop period, whereby the current flowing from the DC voltage source to the primary coil , is disabled and the fourth switch is brought into an ON state. Power source device according to one of Claims 3 to 6 wherein when the output period is switched to the stop period, and when one of the first switch or the second switch is in the ON state and the other of the first switch and the second switch is in the OFF state, the drive unit in the subsequent switching of one of the first switch and the second switch, which is not the switch in the OFF state in the output period, brings the OFF-state to the stop period at the output period, and the other switch of the first switch and the second switch, not the switch is in the ON state in the issue period, bringing into the ON state. Power source device according to one of Claims 3 to 6 wherein when the output period is switched to the stop period after, during a ¼ period of a drive cycle as a reversal of the drive frequency, the first switch is turned ON and the second switch is turned OFF, the drive unit both the first and switches the second switch to the ON state to switch the output period to the stop period. Power source device according to Claim 8 wherein when the stop period is switched to the output period, the drive unit, over the ¼ period of the drive cycle as the reversal of the drive frequency, puts one of the first switch and the second switch in the ON state and the other of the first switch and the first switch second switch brings into the off state. Power source device according to Claim 1 wherein the power source device further comprises a detection value detection unit configured to detect a detection value of a secondary side current flowing in the secondary coil, or to detect a detection value of a secondary side voltage generated in the secondary coil, and when switching from the output period to the stop period, the drive unit puts both the first and second switches in an OFF state to switch the output period to the stop period, and, based on the detection value detected by the detection value detection unit, stops the stop Period switches to the output period when an excitation current flowing in the transformer is smaller than a predetermined value. Power source device according to Claim 10 wherein the detection value detecting unit detects the detection value of the secondary side voltage generated in the secondary coil, and when an absolute value of the detection value detected by the detection value detecting unit is substantially a maximum value, the driving unit sets the stop period to the output period switches. Power source device according to Claim 10 or 11 wherein, when the stop period is switched to the output period, the driving unit is a ratio of a period with respect to a driving cycle as a reversal of the driving frequency in which one of the first switch and the second switch is brought into the ON state and the other of the first switch and the second switch is brought into the OFF state, changes to one half of the target ratio, and then a ratio of a period in which the other of the first switch and the second switch is brought into the ON state and the one of the first switch and the second switch is brought into the OFF state, changes to the target ratio. Power source device according to Claim 10 or 11 wherein, when the stop period is switched to the output period, the driving unit sets the ratio of the period with respect to a driving cycle as a reversal of the driving frequency in which one of the first switch and the second switch is turned ON another of the first switch and the second switch is brought into the OFF state, set to a predetermined value smaller than the target ratio, and after the lapse of a predetermined period, the ratio of the period in which one of the first switch and the first switch second switch is brought into the ON state and the other of the first switch and the second switch is brought into the OFF state, increased to the target ratio. Power source device according to one of Claims 1 to 13 wherein the power source device further comprises a smoothing capacitor in the path connecting the center tap and the connection point of the first and second switches, the drive unit alternately driving the first switch and the second switch at the drive frequency and a predetermined duty in the output period; and the driving unit changes the duty ratio in a decreasing direction in a predetermined time period including, in the output period, a timing of switching to the stop time period. Power source device according to one of Claims 1 to 14 wherein the drive unit alternately drives the first switch and the second switch at the drive frequency and a predetermined duty in the output period, and the drive unit changes the duty in an increasing direction from a time of starting the output period to a predetermined time during the output period and the duty in the decreasing direction from the predetermined time to a time of completion of the issue period changes.

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