JP6340517B2 - Gaming machine - Google Patents

Description

About the gaming machine comprising a plurality of group units control means for controlling the effect device which is divided into groups, and the group supervisory controlling means for controlling a plurality of group units control means.

As a gaming machine capable of simplifying the wiring between the sub relay board and the electric decoration board, the top LED central board disposed in the center of the top electric decoration area is serially connected to the sub relay board,
A gaming machine is known in which the top LED right substrate disposed on the right side of the top illumination area and the top LED left substrate disposed on the left side of the top illumination area are separated from the top LED central substrate and connected by wiring It is done. As a result, the number of wires from the sub relay board to the top illumination area can be reduced to simplify the wires (see, for example, Patent Document 1).

In addition, as a gaming machine that can reduce the number of signal lines and easily detect fraudulent activity, it performs signal transmission between the main substrate and the sub substrate by the I ² C bus system, and Some substrates and sub substrates are provided with bidirectional bus buffers, respectively. This bi-directional bus buffer is for branching the two bi-directional serial lines (SDA, SCL) constituting the I ² C bus into two unidirectional serial lines, respectively. Between the bus buffer and the bidirectional bus buffer provided on the sub board, the signal transmission directions of the unidirectional serial lines branched by them are made to coincide with each other, and they are connected by four serial lines (see FIG. See, for example, Patent Document 2).

Japanese Patent Application Publication No. 2008-212271 Japanese Patent Application Publication No. 2006-15036

In conventional gaming machines, it was not possible to sufficiently reduce wiring.

The present invention aims to provide a game machine that can of reducing the wiring between the group supervisory controlling means and the group-unit control unit.

The present invention divides a plurality of rendering devices into a plurality of groups, and comprises group unit control means for controlling the rendering devices belonging to the divided groups for each group, and supervising each of the group unit control means And an arithmetic processing means for controlling the group general control means, and an initialization signal line capable of transmitting an initialization signal between the arithmetic processing means and the group general control means. And a timing signal line for transmitting a timing signal between the group general control means and the group unit control means while enabling initialization of the group general control means by the arithmetic processing means. A harness including a data line transmitting a data signal, and a power supply line supplying a power supply voltage to the group unit control means. And capable of sending data including a plurality of control data from said group supervisory controlling means by connecting via the connector to the group-unit control unit allows the data to which the group supervisory controlling means sends, the group-unit control unit Address update information that can specify an upper limit address and a return address when updating an address within the range of the storage area, address information indicating a predetermined address among storage areas provided in the storage area, the plurality of control data, And the group unit control means includes initialization means for initializing the group unit control means itself based on the voltage rise due to the power supply when the power supply to the group unit control means is started. , as the starting address the address where the address information indicating the transmission than the group supervisory controlling means Stores the control data has a function to sequentially update the storage destination address for each for storing control data, when storing the control data in the storage area in which the upper address indicates, like back to the return address The address of the storage destination is updated, and the group general control means can designate, as the address update information, any one of a plurality of address update information different in the upper limit address or the return address .

It is possible to reduce wiring between the I lever, the group supervisory controlling means and the group-unit control unit to the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS It is explanatory drawing of the game machine of 1st Embodiment of this invention. It is a front view of the game board of 1st Embodiment of this invention. It is a block diagram showing composition of a game machine of a 1st embodiment of the present invention. It is a block diagram which shows the structure of the presentation control apparatus of 1st Embodiment of this invention. It is an explanatory view of connection of a decoration control device of a 1st embodiment of the present invention. It is a block diagram of a decoration control device of a 1st embodiment of the present invention. It is a block diagram of a I ² CI / O expander of the first embodiment of the present invention. It is a circuit diagram of a I ² CI / O expander neighborhood decorative control device for controlling the decoration apparatus of the first embodiment of the present invention. It is a circuit diagram of a I ² CI / O expander near decoration controller for controlling the character object driving MOT and character object drive SOL of the first embodiment of the present invention. It is a circuit diagram of the connection line regarding the input and output of the relay substrate of a 1st embodiment of the present invention. It is a circuit diagram of the connection line regarding input and output of a decoration control device of a 1st embodiment of the present invention. It is explanatory drawing of the slave address contained in the data output to a decoration control apparatus from the presentation control apparatus of 1st Embodiment of this invention. It is an explanatory view of I ² CI / O expander address table of the first embodiment of the present invention. It is a diagram for explaining the I ² CI / O Aix work register assigned to the output setting register provided in expander of the first embodiment of the present invention. FIG. 7 is an explanatory diagram of start conditions and stop conditions of data output by the master IC of the first embodiment of the present invention via the connection line SDA and the connection line SCL. It is a timing chart in which a decoration control device to which data output from a master IC of the first embodiment of the present invention is input outputs a response signal. It is a timing chart of the signal level of connecting line SDA and connecting line SCL in case master IC of a 1st embodiment of the present invention outputs presentation control data. The master IC according to the first embodiment of the present invention is exchanged between the master IC and the I ² CI / O expander when the effect control data is set in the decoration control device by designating the individual address of the slave. It is a figure explaining the format of data. The master IC according to the first embodiment of the present invention is exchanged between the master IC and the I ² CI / O expander when the effect control data is set in the decoration control device by designating the individual address of the slave. A concrete numerical value is applied to the effect control data. It is a figure explaining another form of presentation control data of a 1st embodiment of the present invention. FIG master IC of the first embodiment is to initialize the I ² CI / O expander, illustrating the data format of the initialization instruction data transmitted to I ² CI / O expander from the master IC of the present invention It is. It is a figure explaining the abnormality determination table of 1st Embodiment of this invention. It is a flowchart of the process by the presentation control apparatus of 1st Embodiment of this invention. It is a flow chart of I ² C initial reset processing of a first embodiment of the present invention. It is a flowchart of the slave reset process of 1st Embodiment of this invention. It is a flowchart of the light emission control slave output processing of 1st Embodiment of this invention. It is a flowchart of the slave continuous processing of 1st Embodiment of this invention. It is a flow chart of I ² C occasional reset processing of a first embodiment of the present invention. It is a flowchart of the timer interruption process performed when the timer interruption of 1st Embodiment of this invention generate | occur | produces. It is a flow chart of slave single output processing of a 1st embodiment of the present invention. It is a figure which shows the connection form of the decoration control apparatus provided in the whole game machine of 1st Embodiment of this invention. It is an explanatory view of connection of a plurality of master ICs and an I ² CI / O expander according to a second embodiment of the present invention. It is explanatory drawing of the abnormality determination table of 2nd Embodiment of this invention. It is a flowchart of I ² C initial reset processing of a second embodiment of the present invention. It is a flowchart of I ² C occasional reset processing of a second embodiment of the present invention.

First Embodiment
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is an explanatory view of a gaming machine 1 according to a first embodiment of the present invention.

The front frame (game frame) 3 of the gaming machine 1 is assembled to the front of the gaming machine 1 so as to be able to open and close and pivot on the main frame (outer frame) 2 via the hinge 4. On the front side of the front frame 3, the game board 10 (see FIG. 2) is accommodated. Further, a glass frame 18 provided with a cover glass (transparent member) covering the front of the game board 10 is attached to the front frame 3.

A decorative member 9 for emitting decorative light is provided around the cover glass of the glass frame 18. A decoration device 620 (see FIG. 3) comprising a lamp, an LED, etc. inside the decoration member 9
Is equipped. When the decoration device 620 emits light in a predetermined light emission mode, the decoration member 9 emits light in a predetermined light emission mode.

At the left and right of the glass frame 18, speakers 30 for emitting sound (for example, sound effects) are provided. Further, a lighting unit 11 is provided above the glass frame 18. Inside the lighting unit 11, the above-described decoration device 620 is provided.

An abnormality notification LED 29 is provided on the right side of the lighting unit 11 to notify that an abnormality has occurred in the gaming machine 1.

An upper tray 21 for supplying gaming balls to a hitting launch device (not shown) is provided at the lower opening and closing panel 20 of the front frame 3, and the fixed tray 22 is provided with an ashtray 15, a lower tray 23 and an operating unit 24 of the hitting launcher. . The lower plate 23 has a lower plate ball removing mechanism 16 for discharging the gaming balls stored in the lower plate 23.
Is provided. A key 25 for locking the glass frame 18 is provided on the lower right side of the front frame 3.

In addition, when the player rotates the operation unit 24, the ball hitting and launching device shoots the game ball supplied from the upper tray 21.

In addition, at the upper edge of the upper tray 21, an effect button 1 for receiving an operation input from the player
7 are provided.

The display device 5 provided on the game board 10 by the player operating the effect button 17
The effect contents of the special view variation display game in 3 (refer to FIG. 2) can be selected, and the special view variation display game in the display device 53 can be performed by causing the player's operation to intervene.

In the special view variation display game, the first starting winning opening 45 (see FIG. 2) or the second starting winning opening of the normal variation winning device 36 (see FIG. 2) provided on the game board 10 with the launched game ball It will be started if you In the special view variable display game, a plurality of identification information is variably displayed on the display device 53. Then, when the identification information which has been variably displayed is stopped, and the result mode of the stopped identification information is a specific result mode, the state of the gaming machine 1 is advantageous to the player (the state in which a bonus is given) Transition to the special game state that is.

In the upper right portion of the upper tray 21, there are provided a ball lending button 26 operated when the player borrows a game ball, and a discharge button 27 operated to eject a prepaid card from a card unit (not shown). . A balance display unit 28 is provided between the buttons 26 and 27 to display the balance of the prepaid card.

  FIG. 2 is a front view of the game board 10 according to the first embodiment of the present invention.

The gaming machine 1 shown in FIG. 1 is to play a game by firing a gaming ball into the internal gaming area 10a (playing a ball), and on the back side of the cover glass of the glass frame 18, the gaming area 10a is The game board 10 which comprises is installed.

The game board 10 includes a flat game board body 10b (made of wood or synthetic resin) serving as a mounting base for various members, and the game area 10 surrounded by the guide rails 32 on the front of the game board body 10b.
have a. In addition, on the front of the game board main body 10b and outside the guide rail 32,
The front components 33, 33, ... are attached. Then, a game ball (ball: game medium) is fired from the launch device into the game area 10a surrounded by the guide rails 32 to play a game.

At the approximate center of the game area 10a, a center case 51 is attached, which forms a window 52 serving as a display area of the special view variable display game. Behind the window portion 52 formed in the center case 51, a display device 53 as an effect display device capable of executing an effect of a special view fluctuation display game in which a plurality of identification information are variably displayed is disposed. ing. This display device 53 is
For example, a liquid crystal display is provided, and a display unit 53a whose display content can be changed is arranged so as to be visible from the front side of the game board 10 through the window 52 of the center case 51. The display device 53 is not limited to one provided with a liquid crystal display, but may be provided with a display such as an EL, a CRT or the like.

In the vicinity of the upper end of the window portion 52 of the center case 51, a movable role object 60 operable based on the gaming state is attached.

Further, the game board 10 is provided with a common drawing start gate 34, a common drawing memory display 47 for displaying the number of unprocessed times of the common drawing change display game, and a common drawing display 35 for displaying the common drawing change display game. ing. In addition, in the game area 10a, there is a first start winning opening 45 which forms a first start winning area,
A normal fluctuation winning device 36 having a second starting winning opening that constitutes a second starting winning area is provided. Then, when the gaming ball wins the first start winning opening 45, the first special view fluctuation display game is executed as an auxiliary game, and when the gaming ball wins the normal fluctuation winning device 36, the second auxiliary game. A special figure variation display game is to be executed.

In addition, the game board 10 is provided with a first special view display 38 for displaying a first special view fluctuation display game and a second special view display 39 for displaying a second special view fluctuation display game. There is. Also, the first
First special view memory display 4 for displaying the number of times the special view variation display game has not been processed (first special view start memory)
A second special view storage display 49 is provided to display the number 8 and the number of unprocessed times (second special view start storage) of the second special view variation display game. The common view storage display 47, the common view display 35, the first special view display 38, the second special view display 39, the first special view storage display 48, and the second special view storage display 49 It is integrally provided as a segment LED together with a game state display LED (not shown) indicating a game state.

Furthermore, in the game area 10a, there is an open / close door 42a of the attacker type that can be opened by turning in the direction in which the upper end side falls to the front side, and the first special view change display game, the second special view change display game As a result, the special variation winning device 42, which converts the large winning opening closed (a disadvantage for the player) to the open condition (a favorable condition for the player), the gaming ball that did not win the winning opening etc. An out hole 43 for collecting is provided. Besides, in the game area 10a, general winning openings 44, 44,..., A windmill 46 as a hitting direction changing member, a large number of obstacle nails (not shown), etc. are disposed.

In the drawing start gate 34, a gate SW 34a (see FIG. 3) for detecting the gaming ball having passed through the drawing start gate 34 is provided. Then, when the gaming ball driven into the gaming area 10a passes through the common drawing start gate 34, a common drawing variation display game is performed.

In addition, when the game ball passes the common drawing start gate 34 while the common drawing fluctuation display game can not be started, if the common drawing start memory number is less than the upper limit number, the common drawing start memory number is incremented by one. ,
A random number indicating whether or not the common drawing variation display game is hit is stored as one common drawing start memory.

The state in which the common drawing fluctuation display game can not be started means, for example, a state in which the common drawing fluctuation display game has already been played and the common drawing fluctuation display game has not ended, or the common drawing fluctuation display game hits 36 refers to a state in which it is converted to the open state.

In addition, the starting memory number of the common drawing variation display game is displayed on the common drawing storage display 47 provided with an LED.

The common drawing variation display game is to be executed by the common drawing indicator 35 provided on the game board 10. It should be noted that a common drawing variation display game may be displayed in a part of the display area of the display device 53. In this case, for example, numbers, symbols, character symbols etc. are used as identification symbols, and the identification symbols are specified. It is made to carry out by making it stop display, after displaying time variation.

If the stop display of the common drawing fluctuation display game is a special result mode, the common drawing fluctuation display game becomes a hit, and the opening / closing members 36a and 36a of the normal fluctuation winning apparatus 36 are set for a predetermined time (for example, 0
Open for .5 seconds) Thereby, the game ball easily wins the normal fluctuation winning device 36, and the start of the second special view fluctuation display game becomes easy.

The normal fluctuation winning device 36 has a pair of left and right opening and closing members 36 a, 36 a and is disposed below the first start winning opening 45. Although the opening and closing members 36a and 36a normally maintain a closed state (a disadvantageous state for the player) with an interval of about the diameter of the gaming ball, the result of the common drawing fluctuation display game is a predetermined stop display When it becomes an aspect (when a common drawing fluctuation display game is hit), it is opened in a reverse "C" shape by a solenoid (Pu SOL 36b, see FIG. 3) as a driving device and a normal fluctuation winning The game ball can be changed to a state in which the game ball can easily flow into the device 36 (a state advantageous to the player).

In addition, the gaming machine 1 of the present embodiment shortens the fluctuation display time of the special view fluctuation display game on the display device 53 as the gaming state based on the result mode of the special drawing fluctuation display game (second operation state (second operation state ) Can be generated. At this time, the short operating state (second operating state) is a state in which the operating state of the normal fluctuation winning device 36 is more likely to be open than the normal operating state (first operating state).

At this time, in the short operation state, the execution time of the above-mentioned common view variation display game is controlled to be shorter than the long execution time in the normal operation state (for example, 10 seconds is one second), whereby The number of opening of the normal fluctuation winning device 36 is controlled to be substantially increased. Further, in the time-saving operation state, when the regular drawing fluctuation display game is hit and the normal fluctuation winning apparatus 36 is opened, the opening time is controlled to be longer than the opening time for which the normal operation state is short. (For example, 0.3 seconds is 1.8 seconds). Also, in the short-time operation state,
The normal fluctuation winning device 36 is not one time per hit result of the common drawing fluctuation display game,
It is opened multiple times (for example, twice). Furthermore, in the short-time operation state, the probability of being a hit result of the common view variation display game is controlled to be higher than that in the normal operation state. That is, the number of times the normal fluctuation winning device 36 is opened is increased more than in the normal operation state, the gaming ball easily wins the normal fluctuation winning device 36, and the start of the second special view fluctuation display game becomes easy.

A first starting opening SW 45a (see FIG. 3) is provided inside the first starting winning opening 45, and based on the detection of the game ball by the first starting opening SW 45a, a first special view variation display as an auxiliary game The right to start the game is to be generated. Further, a second starting opening SW 36 d (see FIG. 3) is provided inside the normal fluctuation winning device 36, and this second starting opening SW 3
Based on the detection of the game ball by 6d, a start right to start a second special view variation display game as an auxiliary game is generated.

The right to start the first special view variable display game is stored as a first start storage (special view 1 start storage) within a predetermined upper limit number (for example, 4). Then, the first start memory number is displayed on the first special view memory display 48. The right to start the second special view variable display game is stored as a second start storage (special view 2 start storage) within a predetermined upper limit number (for example, 4). Then, the second start memory number is displayed on the second special view memory display 49.

Then, when the gaming ball is won in the first start winning opening 45 in a state where the first special view variation display game can be started (the first start memory number and the second start memory number are 0), the start right is generated. The random number extracted along with is stored as the first starting memory, and the first starting memory number is incremented by one, and the first special view fluctuation display game is started immediately based on the first starting memory, At this time, the first starting memory number is decremented by one.

Further, since the second special view variation display game is executed prior to the first special view variation display game, even if the first start storage number is not zero, if the second start storage number is zero, When the game ball wins in the normal variation winning device 36 forming the second starting winning opening, the random number extracted with the occurrence of the starting right is stored as the second starting memory, and the second starting memory number is incremented by one. At the same time, the second special view variable display game is started based on the second start memory immediately after the end of the first special view variable display game being executed, and at this time, the second start memory number is decremented by one.

On the other hand, the first special view variation display game or the second special view variation display game can not be started immediately, for example, the first special view variation display game or the second special view variation display game is already played, and the special view variation display game is performed. If the game ball does not end the game or is in the special game state, and the game ball is won in the first start winning opening 45, if the first start memory number is less than the upper limit number (for example, less than 4) The first start memory number is incremented by one, and one random number extracted at the timing when the gaming ball has won in the first start winning opening 45 is stored as a first start memory.

Similarly, in this case, if the game ball wins in the normal variation winning device 36 forming the second starting winning opening, if the second starting memory number is less than the upper limit number (for example, less than four), the second starting memory number is One is added, and one random number extracted at the timing when the gaming ball has won in the second starting winning opening is stored as a second starting memory.

Then, when the first special view variation display game or the second special view variation display game can be started, the first special view variation display game or the second special view variation display is based on the first start storage or the second start storage. The game is started. At this time, the first special view change display game and the second special view change display game are not simultaneously executed, and the second special view change display game is executed with priority over the first special view change display game. It is supposed to be.

That is, when there is the first start storage and the second start storage, the second special view variation display game is executed.

The first special view variation display game and the second special view variation display game as auxiliary games are to be executed by the first special view display 38 and the second special view display 39 provided on the game board 10. After a plurality of identification information are variably displayed, the predetermined result mode is displayed in a stopped state. In addition, a special figure variation display game in which a plurality of types of identification information (for example, numbers, symbols, character patterns, etc.) are variably displayed corresponding to the respective special figure variation display games on the display device 53 is executed. Then, as a result of the special view variation display game, the first special view display 38 or the second special view display 39
When the display mode of is a special result mode, it becomes a jackpot and becomes a special gaming state (a so-called jackpot state). In addition, in response to this, the display mode of the display device 53 is also a special result mode (for example, any of Zoro's numeral such as "7, 7, 7"). The special view variation display game may be executed only by the display device 53 without providing the first special view display 38 and the second special view display 39 in the gaming machine.

In addition, the gaming machine 1 of the present embodiment is capable of generating a probability change state (second probability state) as the game state based on the result mode of the special figure change display game. This probability change state (second probability state)
Is a state in which the probability of being a hit result in the special figure variation display game is higher than that in the normal probability state (first probability state). Note that the first special view fluctuation display game and the second special view fluctuation even if it becomes a definite change state based on the result form of the special view fluctuation display game of the first special view fluctuation display game and the second special view fluctuation display game Both display games are in a state of probability variation. Also, the probability variation state and the above-mentioned short time operation state can be generated independently of each other, and both can be generated simultaneously,
It is also possible to generate only one.

  FIG. 3 is a block diagram showing the configuration of the gaming machine 1 according to the first embodiment of the present invention.

The gaming machine 1 includes a game control device 500 for controlling the game in an integrated manner, a presentation control device 550 for controlling the display device 53 and the speaker 30 to perform various effects, and a payout motor (not shown) to pay out the gaming ball. It has a payout control device 580 to control.

First, the game control device 500 will be described. The effect control device 550 will be described with reference to FIG.

The gaming control device 500 includes a gaming microcomputer 501 and an input I / F (Interface) 5.
05, an output I / F (Interface) 506, and an external communication terminal 507.

The gaming microcomputer 501 has a CPU 502 and a ROM (Read Only Memory).
And a random access memory (RAM) 504.

The CPU 502 is a main control device that controls the game in an integrated manner, and controls the game control. RO
M 503 stores invariable information (program, data, etc.) for game control. R
AM 504 is used as a work area at the time of game control.

The external communication terminal 507 connects the game control device 500 to an external device such as an inspection device that inspects setting information and the like of the game control device 500.

The CPU 502 can input various input devices (a first start port SW 45 a, a second start port SW 36 d, a general winning port SW 44 a, a gate SW 34 a, a count SW 42 d) via the input I / F 505.
In response to detection signals from the glass frame opening switch 18a, the front frame opening switch 3a, the ball breakage switch 54, the vibration sensor 55, and the magnetic sensor 56), various processes such as a big hit lottery are performed.

The first starting opening SW 45 a is a switch for detecting that the gaming ball has won the first starting winning opening 45. The second starting opening SW 36 d is a switch for detecting that the gaming ball has won the second starting winning opening of the normal variation winning device 36.

The general winning openings SWa 44a to 44n are switches for detecting that the gaming ball has won the general winning openings 44. The gate SW 34 a is a switch for detecting that the gaming ball has passed through the common view starting gate 34.

The count SW 42 d is a switch for detecting that the gaming ball has won the special winning opening of the special variation winning device 42.

The glass frame opening switch 18a is a switch for detecting that the glass frame 18 has been opened. The front frame opening switch 3a is a switch that detects that the front frame 3 has been opened.

The out-of-ball SW 54 is a switch that is stored inside the gaming machine 1 and detects that the number of gaming balls used for payout has become equal to or less than a predetermined number.

The vibration sensor 55 is a sensor that detects the vibration given to the gaming machine 1 and gives a vibration to the gaming machine 1 to detect an injustice that illegally acquires the gaming ball. The magnetic sensor 56 includes a first start winning opening 45, a second starting winning opening of the normal fluctuation winning device 36, a general winning opening 44, and the special fluctuation winning device 4.
A sensor for detecting the magnetic force is provided near the winning opening 2 of FIG.
The magnetic sensor 93 brings a magnet close to each winning opening, and detects an injustice leading the gaming balls fired to the game area 10a to each winning opening.

In addition, the CPU 502, through the output I / F 506, the first special view display 38, the first special view storage display 48, the second special view display 39, the second special view storage display 49, a generic view display Unit 35, Puden S
A command signal is transmitted to the OL 36b, the special winning opening SOL 42b, the payout control device 580, and the effect control device 550 to control the game in an integrated manner.

On the first special view display 38, a first special view variation display game to be executed as an auxiliary game when the gaming ball has won in the first start winning opening 45 is displayed. The first special view storage display 48 displays a first start storage number which is a start right to start the first special view variation display game stored within a predetermined upper limit number range.

On the second special view display 39, a second special view variation display game to be executed as an auxiliary game is displayed when the gaming ball is won in the large winning opening of the normal variation winning device 36. Second special view memory display 4
A second start memory number, which is a start right to start a second special view variation display game stored within a predetermined upper limit number, is displayed on the 9.

The common drawing indicator 35 displays a common drawing fluctuation display game to be performed when the gaming ball passes the common drawing start gate 34.

When the stop display of the common drawing fluctuation display game executed by the common drawing indicator 35 becomes a special result mode, the common electric switch SOL 36b opens the opening and closing members 36a, 36a, and the normal fluctuation winning apparatus 36
The game ball makes it easy to win the second start winning opening of the game.

In the special winning opening SOL42b, when the result of the first special view variation display game or the second special view variation display game becomes a special result mode, and the special game state is obtained, the open / close door 42a of the special variation winning device 42 is opened. Then, the big winning opening is converted to a state in which the game ball is easy to win.

Further, the game control device 500 outputs the game machine data to the game arcade management device (not shown) through the information collecting terminal device (not shown) through the external information terminal 508. The game arcade management device is a computer that collects and manages game data of the game machine 1 installed in the game arcade.

Further, the payout control device 580 pays out the game balls of the number corresponding to the winning opening that has won, or the ball lending button 26 is operated, when the gaming ball has won the general winning opening 44 or the large winning opening. When a payout command for payout of a predetermined number of gaming balls is received from the game control device 500, a payout motor (not shown) is controlled based on the received payout command. The payout command includes the number of gaming balls to be paid out.

The game control device 500, through the output I / F 506, as a game data indicating the status of the game, such as a change start command, a customer wait demo command, a fanfare command, a probability information command, and an error designation command. Send to

FIG. 4 is a block diagram showing the configuration of the effect control device 550 of the first embodiment of the present invention.

The effect control device 550 determines the effect contents based on the game data (display control command) input from the game control device 500 and controls the display device 53 and the speaker 30, and also via the decoration control device 610. Decoration device 620, product drive SOL 560 (solenoid)
, And controls the accessory drive MOT (motor) 561. Although the details will be described later, the decoration device 620, the feature drive SOL 560, and the feature drive MOT 561 (collectively referred to as a rendering device)
An effect of the game is performed. Further, the effect control device 550 receives a signal indicating that the effect button 17 has been operated from the effect button 17.

The effect control device 550 includes a CPU 551, a control ROM 552, a RAM 553 and an image ROM.
A sound ROM 555, a VDP 556, a sound LSI 557, an input / output I / F 558, a power on detection circuit 559, a master IC 570, and a NOR gate circuit 590 are provided.

The CPU 551 is a main control device that is connected to the game control device 500, receives a command signal from the game control device 500 as an interrupt signal (INT), and controls various effects based on the input command signal. Further, to the CPU 551, an interrupt signal is input from a controller, which will be described later, of the master IC 570, and an interrupt signal is input from the VDP 556.

When an interrupt signal is input to the CPU 551, the CPU 551 interrupts the process currently being executed and executes the process corresponding to the input interrupt signal.

The control ROM 552 stores invariable information (program, data, etc.) for effect control. The RAM 553 is used as a work area at the time of effect control.

The image ROM 554 stores image data to be displayed on the display device 53.
554 is connected to the VDP 556. The sound ROM 555 stores sound data output from the speaker 30, and the sound ROM 555 is connected to the sound LSI 557.

The VDP 556 is a processor that controls image output to the display device 53. Sound LSI 5
Reference numeral 57 denotes a circuit for controlling an audio output from the speaker 30.

The VDP 556 includes synchronization signal generating means for generating a synchronization signal synchronized with a cycle (33 ms cycle) for updating the image displayed on the display device 53. The synchronization signal generation means inputs the generated synchronization signal as an interrupt signal to the CPU 551 each time the synchronization signal is generated.

The input / output I / F 558 is an interface connected to the effect button 17, the motor position detection sensor 510, and the NOR gate circuit 590, and the operation signal from the effect button 17 and the motor position detection signal from the motor position detection sensor 510. And the reset signal from the CPU 551 to the NOR gate circuit 590.

The effect button 17 is provided on the upper edge of the upper tray 21 and is operated by the player in the effect in the first special view variation display game or the second special view variation display game executed by the display device 53. .

The motor position detection sensor 510 is a sensor that outputs a motor position detection signal when it is detected that the rotation axis of the accessory driving MOT 561 has reached the initial position.

NOR gate circuit 590 is a reset circuit provided in the controller of master IC 570.
It is connected to the T terminal and other circuits that require initialization. The other circuits requiring initialization are, for example, the VDP 556 and the sound LSI 557. These are effect control devices 550
When the power is turned on to start up, the CPU 551 initializes it.

The CPU 551, VDP 556, RAM 553, control ROM 552, sound LSI 557, and input / output I / F 558 are connected to one another via a bus 563.

The power on detection circuit 559 operates as a master I when the effect control device 550 is powered on.
A reset signal for initializing a register (not shown) of C 570 to a default state (all 0s) is generated, and the generated reset signal is output to NOR gate circuit 590.

Further, when a predetermined condition is satisfied, the CPU 551 outputs a reset signal to the input / output I / F 558 through the bus 563 and the input / output I / F 558 outputs the reset signal input NO
R gate circuit 590 is output.

The reset signal input from the power on detection circuit 559 to the NOR gate circuit 590 and the reset signal input from the CPU 551 to the NOR gate circuit 590 via the input / output I / F 558 are in the low level state in either case. Functions as a signal instructing reset. Therefore, when at least one of the power on detection circuit 559 and the CPU 551 outputs a reset signal to the NOR gate circuit 590, the reset signal is input to the master IC 570 via the NOR gate circuit 590.

As described above, since the NOR gate circuit 590 is connected to the master IC 570 and other circuits requiring initialization, when the reset is input to the NOR gate circuit 590, the master IC 570 and the NOR gate circuit 590 are reset. Other circuits requiring initialization to be connected are initialized.

If there is no other circuit requiring initialization, NOR gate circuit 590 is connected only to master IC 570.

  Next, master IC 570 will be described.

The master IC 570 designates the address of the decoration control device 610 of the rendering device to be controlled, and outputs the control content of the rendering device to the decoration control device 610 of the designated address.

Master IC 570 includes connection line Vcc, connection line Vact, connection line SDA, connection line SCL,
And the relay substrate (decorative control device) 60 via five connection lines of the connection line GND (see FIG. 5).
Connected to 0.

The connection line Vcc is a connection line for supplying a power supply for logic to the relay substrate 600 and the decoration control device 610. The connection line Vact is a connection line for supplying a power source for driving the rendering device (for example, a power source for emitting an LED). The connection line SDA is a connection line for communicating data between the effect control device 550 and the decoration control device 610,
It functions as a data line in the present embodiment. The connection line SCL is a connection line for inputting and outputting a clock signal used for data communication in the connection line SDA, and functions as a timing signal line in the present embodiment. Connection line GND shown in FIG. 5 is formed of connection line Vcc and connection line V.
It is the ground of the power supplied by act.

Similar to the connection between the master IC 570 and the relay substrate 600, the relay substrate 600 and the decoration control device 610 are connected via the connection line Vcc, the connection line Vact, the connection line SDA, the connection line SCL, and the connection line GND. Ru.

Master IC 570 and decoration control device 610 are connected by connection line SDA and connection SCL.
Perform line bi-directional communication.

When transmitting data to relay board 600 and decoration control device 610, master IC 570 first changes the signal level of connection line SDA from HIGH to LOW while maintaining the signal level of connection line SCL at HIGH. Thus, the start condition for starting data output to the decoration control device 610 is satisfied (a start condition is issued to the decoration control device 610).

After this, master IC 570 changes the signal level of connection line SCL to LOW, and connection line S
While the signal level of CL is LOW, the signal level of the connection line SDA is set to the level of the first bit of the transmission data, and after a predetermined time, the signal level of the connection line SCL changes from LOW to HIGH. When the signal level of the connection line SCL changes to HIGH, the decoration control device 610 takes in the signal level of the connection line SDA and recognizes it as the first bit of the transmission data. Next, the master IC 570 returns the signal level of the connection line SCL from HIGH to LOW.

When this procedure is executed once, one bit of data is transmitted from the master IC 570 to the decoration control device 610, and by repeating this procedure eight times finally, all eight bits which are unit bits of the transmission data become the master. It is transmitted from IC 570 to decoration control unit 610 (one byte of data is transmitted).

Then, master IC 570 completes transmission of the last eighth bit data, and connection line SC
When the signal level of L is returned from HIGH to LOW, the connection line SDA is released to be in a reception standby state to wait to receive a response signal from the decoration control device 610.

When in the reception standby state, the decoration control device 610 returns a 1-bit response signal (ACK or NACK described later) to the master IC 570 via the connection line SDA. Then, master IC 5
70 changes the signal level of the connection line SCL from LOW to HIGH to capture the level of the response signal, and changes the signal level of the connection line SCL from HIGH to LOW after a predetermined time, the decoration control device 610 detects the connection line SDA. Release

Master IC 570 alternately repeats such 1-byte data transmission and 1-bit response reception, and continues until all data to be output to decoration control device 610 is output. When output of data to be output is completed, master IC 570
The signal level of the connection line SDA is changed from LOW to H while keeping the signal level of CL HIGH.
By changing to IGH, a stop condition for ending data output to the decoration control device 610 is satisfied (a stop condition is issued to the decoration control device 610).

The input BUF 571 is a storage device for temporarily storing data input from the decoration control device 610 via the connection line SDA.

Specifically, when the master IC 570 is set to the input mode, the data transmitted from the decoration control device 610 to the master IC 570 is temporarily stored in the input BUF 511 with the noise removed by the filter 575A.

The output BUF 572 temporarily stores data to be output to the decoration control device 610 via the connection line SDA.

The reset REG 573 functions as an initialization instruction data storage area in the present embodiment, is connected to the bus 563, receives a command from the CPU 551, and outputs a reset signal to the controller. The controller generally controls the master IC 570 to execute various processes.

The transmission mode REG 574 is a register for selecting whether to set the mode for transmitting data to the I ² CI / O expander 615 to the byte mode or the buffer mode.

In byte mode, the master IC 570 transfers data to the I ² CI / O expander 615
In this mode, an ACK or NACK is received from the I ² CI / O expander 615 each time a byte is transmitted, and the master IC 570 outputs an interrupt signal to the CPU 551 regardless of whether the ACK or NACK is received.

In the buffer mode, the master IC 570 transmits a plurality of bytes of data stored in the output BUF 572 to the I ² CI / O expander 615 for each 1 byte, each time the transmission is performed, I ²
In addition to receiving an ACK or NACK from the CI / O expander 615, this mode is a mode in which an interrupt signal is output to the CPU 551 at that time when a NACK is received.

However, in the buffer mode, when ACK is received, an interrupt signal is output to the CPU 551 only when transmission of all data stored in the output BUF 572 is completed,
Master IC 570 can not perform I ² CI with unsent data remaining in output BUF 572.
When an ACK is received from the / O expander 615, the control for taking out the next data to be transmitted from the output BUF 572 without outputting an interrupt signal to the CPU 551 and outputting it to the I ² CI / O expander 615 is Repeated.

The byte mode is used when the master IC 570 outputs initialization instruction data and movable control data to be described later to the I ² CI / O expander 615. The buffer mode is used when the master IC 570 outputs light emission control data to be described later to the I ² CI / O expander 615.

The status REG 579 is a register that identifies whether the response signal received by the master IC 570 from the I ² CI / O expander 615 is an ACK or a NACK. When outputting an interrupt signal to CPU 551, master IC 570 sets the value of status REG 579 in response to the response signal received from I ² CI / O expander 615.

The filter 575A removes noise of data input from the connection line SDA. When the driver 576A outputs data from the connection line SDA, the driver 576A applies a voltage at which the transistor 578A can operate to the transistor 578A.

As shown in FIG. 9, a predetermined voltage is applied to the connection line SDA by the pull-up resistor R, and the connection line SDA is connected to the filter 575A and the transistor 578A.

Transistor 578A uses a field effect transistor (FET) to reduce power consumption, the gate of transistor 578A is connected to driver 576A, and the drain is a connection line SDA to which a predetermined voltage is applied by a pull-up resistor R. And the source is grounded.

If the voltage applied to the gate of transistor 578A is smaller than the predetermined value for operating transistor 578A, no current flows between the drain and the source.
The applied voltage does not drop, and as a result, the connection line SDA goes high. on the other hand,
If the voltage applied to the gate of the transistor 578A is equal to or higher than the predetermined value for operating the transistor 578A, the current flows from the drain to which the voltage of the predetermined value is applied to the source grounded, whereby the voltage of the connection line SDA As a result, connecting line SDA is LOW.
It becomes a level.

Note that the transistor 578A has a specification that is not damaged even when a current of about 10 milliamperes flows from the drain to the source. For this reason, the connection line SDA is normally I ²
A current of about 10 milliamperes which is much larger than the current value used in the C bus use can be supplied, and data transmission between the presentation control device 550 and the decoration control device 610 can withstand noise interference. It has become.

When driver 576A outputs data from connection line SDA, transistor 578
In order to cause current to flow between the drain and the source in A, a voltage with an operable value of the transistor 578A is applied to the gate of the transistor 578A. Then, the driver 576A outputs data from the connection line SDA by setting the voltage of the connection line SDA to the HIGH level or the LOW level.

In addition, the filter 575B removes noise of data input from the connection line SCL.
When driver 576 B outputs data from connection line SCL, transistor 578 B
Apply an operable voltage to the transistor 578B.

As shown in FIG. 9, a predetermined voltage is applied to the connection line SCL by the pull-up resistor R, and the connection line SDA is connected to the filter 575B and the transistor 578B.

The transistor 578B uses a field effect transistor (FET) to reduce power consumption, the gate of the transistor 578B is connected to the driver 576B, and the drain is a connection line SCL to which a predetermined voltage is applied by the pull-up resistor R. And the source is grounded.

If the voltage applied to the gate of transistor 578B is smaller than the predetermined value for operating transistor 578B, no current flows between the drain and the source.
The applied voltage does not drop, as a result, the connection line SCL goes high. on the other hand,
If the voltage applied to the gate of the transistor 578B is equal to or higher than the predetermined value for operating the transistor 578B, a current flows from the drain to which the voltage of the predetermined value is applied to the source grounded, whereby the voltage of the connection line SCL As a result, connecting line SCL is LOW.
It becomes a level.

Note that the transistor 578B has a specification which is not damaged even when a current of about 10 milliamperes flows from the drain to the source. Therefore, the connection line SCL is usually I ²
A current of about 10 milliamperes which is much larger than the current value used in the C bus use can be supplied, and data transmission between the presentation control device 550 and the decoration control device 610 can withstand noise interference. It has become.

When the driver 576B outputs a clock signal from the connection line SCL, the driver 576B applies a voltage with an operable value to the gate of the transistor 578B in order to flow a current between the drain and the source in the transistor 578B. And driver 576B is
A clock signal is output from the connection line SCL by repeatedly changing the voltage of the connection line SCL between the high level and the low level.

When the master IC 570 is powered on and the voltage in the power-on reset circuit 577 reaches a predetermined value, the power-on reset circuit 577 receives the input BUF 571 and the output BUF.
A reset signal for setting a storage area such as 572 to a default state is output to the controller.

  Next, the relay substrate 600 and the decoration control device 610 will be described.

The relay substrate 600 is directly connected to the master IC 570 in the decoration control device 610, that is, located on the most upstream side.

The decoration device 620 is a light emitting device that is controlled by an I ² CI / O expander 615 (described later in FIG. 6) provided in the decoration control device 610, and produces light by flashing light when current flows. And so on. The accessory driving solenoid (SOL) 560 is a device that reciprocates when a current flows, and moves an accessory for decoration (not shown) disposed on the game board 10 to perform rendering. The accessory driving motor (MOT) 561 is a device that rotates when a current flows, and causes the movable antenna 60 to move for effect. Feature drive solenoid (SOL
) 560 and the character drive motor (MOT) 561 are also provided in the decoration control device 610 with I ² CI.
/ O expander 615 controls.

In addition, the bonus drive SOL 560 may move the movable bonus 60, or the bonus drive MOT 5
61 may move an unillustrated accessory.

A method of connecting the effect control device 550 and the relay substrate 600, and the relay substrate 600 and the relay substrate 6
The connection method with the decoration control device 610 other than 00 will be described in detail with reference to FIG. Decoration control device 6
10 will be described in detail with reference to FIGS.

FIG. 5 is an explanatory diagram of connection of the decoration control devices 610A to 610F according to the first embodiment of this invention. Although one relay board 600 and six decoration control devices 610A to 610F are illustrated as the decoration control device 610 for convenience of explanation, in actuality, it is necessary to correspond to the specification of the gaming machine. A number of decoration control devices 610 are connected.

The effect control device 550 includes a connection line Vcc, a connection line Vact, a connection line SDA, and a connection line SCL.
And the connection line GND (hereinafter, these five connection lines are referred to as one harness) and are connected to the effect control device 550.

Two decoration control devices 610A and 610D are connected to the relay substrate 600 in parallel by harnesses, respectively.

A decoration control device 610B is connected to the decoration control device 610A via a harness, and a decoration control device 610C is connected to the decoration control device 610B via a harness.

On the other hand, the decoration control device 610E is connected to the decoration control device 610D via a harness,
A decoration control device 610F is connected to the decoration control device 610E via a harness.

Each decoration control device 610 is provided with a connector serving as a mounting port for connecting the harness to itself. Since this connector is common to each decoration control device 610, it is possible to prevent incorrect wiring of the connection lines in the connection order.

Here, the I ² CI / O expander 615 (described later in FIG. 6) provided in the decoration control device 610
The method of controlling the decoration apparatus 620 is described.

Based on the game data input from game control device 500, effect control device 550 determines the output mode of the effect device. Then, the effect control device 550 includes effect control data (effect control) including the individual address of the decoration control device 610 to be controlled (the individual address of the I ² CI / O expander 615) such that the determined output mode is obtained. Information) is output to the relay board 600. At this time, the effect control data is output from the connection line SDA to all the decoration control devices 610 connected to the effect control device 550 via the relay substrate 600. For this reason,
The master IC 570 can control all the decoration control devices 610 connected to the master IC 570.

In the present embodiment, a light emitting device such as an LED is illustrated as a rendering device, so the LED
The light emission aspect of corresponds to the output aspect of the effect device. In this case, the effect control data causes LE to
The lighting / blinking / lighting out of D is instructed, and at the same time, the blinking cycle of the LED and the lighting luminance are also instructed.

Since unique individual addresses are set in advance in each decoration control device 610, when the effect control data is input, the address included in the input effect control data matches the individual address set. It is determined whether or not. When it is determined that the address included in the input effect control data matches the set individual address, the I ² CI / O expander 615 of the decoration control device 610 takes in the effect control data. Then, while controlling the output mode of the corresponding decoration device 620, immediately after the data of the 8th bit is input, the reply signal is output to the master IC 570.

In addition, in each decoration control device 610, the I ^{2 of the} decoration control device 610 is also available in addition to the individual address.
A reset address for initializing the CI / O expander 615 is set.
This reset address is an address commonly provided to all the I ² CI / O expanders 615, and can not be used as an individual address. Also,
The value of this reset address can not be changed (the details will be described later).

The presentation control device 550 is a decoration control device 610 (more precisely, I ² C of the decoration control device 610).
When the I / O expander 615) is initialized, initialization instruction data including the common address for this reset is output to the relay substrate 600. At this time, the initialization instruction data presentation control data is output from the connection line SDA to all the decoration control devices 610 connected to the presentation control device 550 via the relay substrate 600.

Since a reset common address is preset in each decoration control device 610, it is determined whether the address included in the input data matches the preset reset common address. Do. If it is determined that the address included in the input data matches the preset reset common address, the decoration control device 610
The I ² CI / O expander 615 outputs a response signal to the master IC 570, and takes in input data as initialization instruction data, and the I ² CI / O expander 61
5 Initialize itself.

Incidentally, the I ² CI / O expander 615 is initialized, the initialized I ² CI /
The rendering device controlled by the O expander 615 is turned off.

Thus, since the decoration control device 610 performs control based on a command from the effect control device 550, the master IC 570 of the effect control device 550 is the master in the relationship between the effect control device 550 and the decoration control device 610, I ² CI / O Expander 615 of Decoration Controller 610
Is the slave.

Although FIG. 5 describes the case where the control target of the decoration control device 610 is the decoration device 620, the control target of the decoration control device 610 may be the gift driving SOL 560 or the gift driving MOT 561. In this case, the effect device is a drive source such as a motor or a solenoid.
The operation mode of these drive sources corresponds to the output mode of the rendering device. In this case, the effect control data instructs the operation / stop of the drive source and at the same time the operation speed.

  FIG. 6 is a block diagram of the decoration control device 610 according to the first embodiment of this invention.

In FIG. 6, the decoration control device 610 (the decoration control device 610 at the lower side of FIG. 6) including the LED that is the decoration device 620 inside the decoration control device 610 and the decoration control device 610 connected to the external decoration device 620 (The decoration control device 610 at the center of FIG. 6) will be described.

First, the decoration control device 610 including the LED inside the decoration control device 610 will be described.

The decoration control device 610 on the lower side of FIG. 6 includes an I ² CI / O expander 615 and an LED (decorative device 20). The connection line SDA and the connection line SCL are branched into two in the decoration control device 610, and one is output to the next decoration control device 610 as it is. The other is I ² CI /
O expander 615 is connected.

In addition, on the output side of the I ² CI / O expander 615, the decoration device 620 to be controlled
Is connected. The output side of the I ² CI / O expander 615 is connected to the port 0 described in FIG.
It is comprised by 15. Furthermore, all ports of the decoration control device 610 are connected to the internal LEDs via current limiting resistors R0 to R15 described later in FIG. 8A. The current limiting resistors R0 to R15 are also included in the decoration control device 610.

As described above, the I ² CI / O expander 615 includes the address included in the effect control data input from the effect control device 550 and the individual address set in the I ² CI / O expander 615. Only when it matches, the decoration device 620 connected to the I ² CI / O expander 615 is controlled based on the decoration data included in the presentation control data.

Note that the power supply Vled in the figure is a power supply supplied by the connection line Vact described above with reference to FIG.
It corresponds to the power supply for making LED light-emit).

  Next, the decoration control device 610 connected to the external decoration device 620 will be described.

The decoration control device 610 in the center of FIG. 6 includes an I ² CI / O expander 615 and an LED (decorative device 20), and supplies current to the LED provided on the decorative device substrate 625 connected to the outside of the decoration control device 610. The decoration control device 610 and the decoration device substrate 625 are connected via the connection line for supplying the power supply voltage Vled to the LED of the decoration device substrate 625 and the connection line grounded to the ground.

The decoration device substrate 625 is a substrate that does not include the I ² CI / O expander 615 but has only LEDs. In this case, although a current limiting resistor (FIG. 8A) connected to the LED provided on the decoration device substrate 625 is provided on the decoration device substrate 625, the decoration control device provided with the I ² CI / O expander 615 It may be provided at 610.

It should be noted that the number of connection lines for causing current to flow to the decoration device substrate 625 is determined corresponding to the number of LEDs provided on the decoration device substrate 625. . For example, if the decor substrate 625 is equipped with two LEDs, then I ² CI
Two control lines for connecting the port of the / O expander 615 to the corresponding LED,
At least one power supply line for supplying Vled is required.

And, the I ² CI / O expander 615 provided in the central decoration control device 610 is also
An address included in the effect control data input from the effect control device 550 and the I ² CI
Controls the decoration device 620 connected to the I ² CI / O expander 615 based on the decoration data included in the presentation control data only when the individual address set in the / O expander 615 matches. Do. In this case, both the decoration device 620 provided in the central decoration control device 610 and the decoration device 620 provided in the decoration device substrate 625 are I ² CI /
It is controlled by O expander 615.

Thus, the decoration device substrate 625 is provided to
Even if the LEDs are placed at a distant place by separating the LEDs), the common I ² C
It can be controlled by the I / O expander 615.

Note that the decoration control device 610 may connect and control the gift drive SOL 560 and the gift drive MOT 561 instead of the decoration device 620, but the details will be described later with reference to FIG. 8B.

FIG. 7 is a block diagram of the I ² CI / O expander 615 of the first embodiment of the present invention.

The I ² CI / O expander 615 includes a transistor 630 connected to the connection line SDA.
Filter 631 connected to connection line SDA, driver 632 connected to connection line SDA,
A filter 633 connected to the connection line SCL, a bus controller 634, an output setting register 635, an output controller 636, a driver 637 connected to each port 0 to 15 on the output side of the I ² CI / O expander 615, each port 0 Transistor 63 connected to
8A to 638P and a reset signal generation circuit 639.

The filter 631 is connected to the connection line SDA, removes noise of the data input from the connection line SDA, and outputs the data from which the noise is removed to the bus controller 634. When the driver 632 outputs a response signal from the connection line SDA, the driver 632 applies a voltage at which the transistor 630 can operate to the transistor 630.

When the driver 632 outputs data (a response signal) from the connection line SDA, the driver 632 applies a voltage at which the transistor 630 can operate to the transistor 630.

The transistor 630 uses a field effect transistor (FET) to reduce power consumption, the gate of the transistor 630 is connected to the driver 632 and the drain is applied with a predetermined voltage by the pull-up resistor R (see FIG. 4). And the source is grounded.

If the voltage applied to the gate of the transistor 630 is smaller than the predetermined value for operating the transistor 630, no current flows between the drain and the source. Meanwhile, transistor 6
If the voltage applied to the gate of 30 is equal to or greater than the predetermined value for operating the transistor 630,
When a current flows from the drain to which the voltage of a predetermined value is applied to the source grounded, the voltage of the connection line SDA decreases. Note that the transistor 630 has a specification which is not broken even when a current of about 10 milliamperes flows from the drain to the source.

The driver 632 applies a voltage having an operable value of the transistor 630 to the gate of the transistor 630 in order to flow current between the drain and the source in the transistor 630 when outputting data (a response signal) from the connection line SDA. Do. Then, the driver 632 outputs data from the connection line SDA by repeatedly changing the voltage of the connection line SDA from HIGH to LOW.

The filter 633 is connected to the connection line SCL, removes noise of data input from the connection line SCL, and outputs the data from which the noise is removed to the bus controller 634.

In addition, the I ² CI / O expander 615, is set a unique address by the address setting terminals A0~A3 provided in the I ² CI / O expander 615 is input to the bus controller 634. Furthermore, an address for resetting the I ² CI / O expander 615 is also preset.

The bus controller 634 sets the address of the data input from the connection line SDA to I ² CI.
It is determined whether or not the address matches the unique address set in the / O expander 615. If the address matches, the data is taken as effect control data.

Also, the bus controller 634 sets the address of the data input from the connection line SDA to I.
^{2 It} is determined whether or not the address matches with the address for resetting preset in the CI / O expander 615, and the address of the input data and the address for resetting preset in the I ² CI / O expander 615 DOO takes in the data as initialization instruction data if they match, it initializes the I ² CI / O expander 615.

In addition, when the signal level of the SCL connection line changes from HIGH to LOW after the bus controller 634 changes the signal level of the SCL connection line from LOW to HIGH 8 times and captures the eighth bit data, A response signal is output from connection line SDA to master IC 570. Furthermore, when it is confirmed that the signal level of the SCL connection line changes from LOW to HIGH, and when the signal level of the SCL connection line changes from HIGH to LOW again, the connection line SDA
Open In other words, the number of times the signal level of the SCL connection line changes from LOW to HIGH is 9
Outputs a response signal at the same timing.

In the output setting register 635, the operation mode of the I ² CI / O expander 615 and the output state of the ports 0 to 15 are set. When the bus controller 634 takes in initialization instruction data from the connection line SDA and the I ² CI / O expander 615 is initialized, the output setting register 635 causes current to flow to all the ports 0-15. It is set to the initial state so as not to.

Output controller 636 sets data based on the data set in output setting register 635.
By supplying current to the rendering devices connected to the ports 0 to 15 via the port driver 637, the output state of the rendering device is actually controlled. When the bus controller 634 takes in the effect control data from the connection line SDA, this output state is updated to the contents specified in the taken effect control data.

The driver 637 applies a voltage to which the transistors 638A to 638P, which are connected to the port through which current flows, can operate when the current flows through the port.

The gates of the transistors 638A to 638P are connected to the driver 637, the drain is connected to the port terminal connected to the connection line to which the voltage for operating the rendering device is applied as shown in FIGS. 8A and 8B, and the source is grounded It is done.

The voltage applied to the gates of the transistors 638A to 638P
If it is smaller than the predetermined value for operating 638P, no current flows between the drain and the source. On the other hand, if the voltage applied to the gates of 638A to 638P is equal to or higher than the predetermined value for operating the transistor 638, the predetermined voltage applied to the gate from the power supply Vled shown in FIG. 8A or the power supply Vmot shown in FIG. When the voltage of the current flows through the drain of the transistor 638 to the grounded source, the output state of the rendering device connected to the port terminal can be controlled.

In addition, since the I ² CI / O expander 615 of the decoration control device 610 can simultaneously control all the rendering devices connected to the port terminals of the I ² CI / O expander 615, I I One rendering device connected to the port terminal of the ² CI / O expander 615 can be controlled as one group.

And since I ² CI / O expanders 615 provided in each decoration control device 610 are assigned different individual addresses, the rendering device is divided into a plurality of groups. That is, the I ² CI / O expander 6 provided in each decoration control device 610
Reference numeral 15 is configured as group unit control means capable of controlling the rendering device in group units.

Therefore, the effect control device 550 that controls the decoration control device 610 functions as a group general control device that controls the group unit control device.

The reset signal generation circuit 639 receives a reset terminal Vcc connected to the connection line Vcc for supplying power to the I ² CI / O expander 615, and an external reset signal RES.
ET terminal is connected.

The reset signal generation circuit 639 supplies power to the I ² CI / O expander 615,
When the voltage rises to a predetermined value, a reset signal is generated, and the generated reset signal is input to the bus controller 634, the output setting register 635, and the output controller 636.

Since the reset signal generation circuit 639 outputs a reset signal when a low level reset signal is externally input, the CPU 551 of the effect control device 550 outputs N.
A reset signal may be input from the RESET terminal via the OR gate circuit 590. When the RESET terminal is not used, RESE as shown in FIGS. 8A and 8B.
The T terminal may be pulled up to HIGH.

FIG. 8A is a circuit diagram around the I ² CI / O expander 615 of the decoration control device 610 that controls the decoration device 620 according to the first embodiment of this invention.

I ² CI / O Expander 615 has NC terminal, RESET terminal, SC as input terminal
An L terminal, an SDA terminal, a Vcc terminal, an A0 to A3 terminal, and a GND terminal are provided, and PORT0 to PORT15 are provided as output terminals.

The power supply supplied to the I ² CI / O expander 615 via the pull-up resistor R is connected to the RESET terminal. Therefore, the voltage applied to the reset terminal is always HIG.
H is maintained.

  The SCL terminal is connected to the connection line SCL, and the SDA terminal is connected to the connection line SDA.

The power supply supplied to the I ² CI / O expander 615 is connected to the Vcc terminal. Further, a capacitor CP for removing power supply noise is connected to the Vcc terminal.

Terminals A0 to A3 are terminals for setting an address unique to the I ² CI / O expander 615. The address of the I ² CI / O expander 615 is usually expressed by 4 bits, and when the power of the I ² CI / O expander 615 is applied to this terminal, “1” is given to the bus controller 634. When set, if this terminal is connected to ground, the bus controller 634 is set to "0".

Therefore, the address of the I ² CI / O expander 615 shown in FIG. 8A is “0100”.
The address of the I ² CI / O expander 615 shown in FIG. 8B is “0110”. The GND terminal is a terminal for grounding a voltage.

The PORT0 to PORT15 terminals are connected to the LEDs via the current limiting resistors R0 to R15.
It is connected to a decoration device 620 consisting of 0 to 15 LEDs. As in PORT0, one LED may be connected to one port, but as in PORT 1-15, port 1
A plurality of LEDs may be connected to each.

If one LED is provided for every port, one I ² CI / O expander 61
5 will allow up to 16 LEDs to be controlled. In addition, when the number of LEDs connected to each port is different, if all LEDs connected in series to one port are one type of LED, one I ² CI / O expander With 615, up to 16 types of LEDs can be controlled.

When a voltage is applied from the driver 637 to the gates of the transistors 638A to 638P (see FIG. 7) connected to the PORT0 terminal to the PORT15 terminal, a current flows from the drain to the source of the transistors 638A to 638P to which the voltage is applied. Becomes possible,
A current flows through the LEDs 0 to 15 connected to the PORT 0 terminal to the PORT 15 terminal, and the LEDs 0 to 15 are turned on.

On the other hand, if the driver 637 does not apply a voltage to the gates of the transistors 638A to 638P, no current flows in the LEDs 0 to 15 and the LEDs 0 to 15 do not light.

Note that the PORT0 to PORT15 terminals of the I ² CI / O expander 615 are L
Since a motor or a solenoid can be connected instead of the ED, a case where the motor or the solenoid is driven using the I ² CI / O expander 615 will be described.

FIG. 8B shows the item driving MOT 561 and the item driving SOL 560 according to the first embodiment of this invention.
FIG. 16 is a circuit diagram of the periphery of the I ² CI / O expander 615 of the decoration control device 610 which controls

The accessory driving MOT 561 is configured by a stepping motor, and rotates by sequentially applying a predetermined voltage to signal terminals of respective phases that drive the stepping motor. In the present embodiment,
The signal terminals of each phase of the bonus drive MOT 561 are connected to the PORT0 terminal to the PORT3 terminal.

When a voltage is applied from the driver 637 to any gate of the transistors 638A to 638D connected to the PORT0 terminal to the PORT3 terminal connected to the product driving MOT 561, the voltage applied to the transistors 638A to 638D The current can flow from the drain to the source, and the current flows to the accessory driving MOT 561 connected to the PORT0 terminal to the PORT3 terminal, and the accessory driving MOT 561 is driven.

The connection line connecting the PORT0 terminals to the PORT3 terminals to the accessory drive MOT 561 is branched, and one of the branched connection lines is connected to the accessory drive MOT 561 through the diode D and the Zener diode ZD. Connected

In addition, the PORT terminal 15 is connected to the bonus drive SOL 560. Feature drive SOL 56
When a voltage is applied from the driver 637 to the gate of the transistor 638P connected to the PORT 15 terminal connected to 0, a current can flow from the drain to the source of the transistor 638P to which the voltage is applied, A current flows in the item drive SOL 560 connected to the PORT 15 terminal, and the item drive SOL 560 is driven.

In FIG. 8B, with respect to I ² CI / O Aix although both character object drive MOT561 and character object drive SOL560 Panda 615 are connected, one I ² CI / O expander 615, the character object drive A configuration in which only at least one of the MOT 561 and the item drive SOL 560 is connected may be used.

For example, the I ² CI / O expander 615 as a group controlling only a stepping motor may be provided exclusively, or the I ² CI / O expander 615 as a group controlling only a solenoid may be provided exclusively. . With such a configuration, it is possible to control the rendering devices belonging to the same group at the same timing, and it is also possible to group only the rendering devices that require high-speed processing for efficient control.

FIG. 9 is a circuit diagram of connection lines related to input and output of the relay substrate 600 according to the first embodiment of the present invention.

The relay substrate 600 includes an upstream connector 601, two downstream connectors 602A and 602B, and an I ² CI / O expander 615.

The upstream connector 601 is a connector connected to the master IC 570 upstream of the relay substrate 600, and the connectors 602 A and 602 B are connected to the decoration control device 610 downstream of the relay substrate 600.

In order to connect the connection line SDA to the two downstream connectors 602A and 602B, the internal connection line SDA911 extending from the upstream connector 601 branches into a first connection line SDA921 and a second connection line SDA931 at a branch 901. The first connection line SDA 921 is connected to the downstream connector 602A, and the second connection line SDA 931 is connected to the downstream connector 602B.

Similarly, the internal connection line SCL 912 extending from the upstream connector 601 branches at a branch 902 into a first connection line SCL 922 and a second connection line SCL 932. The first connection line SCL 922 is connected to the downstream connector 602A, and the second connection line SCL 932 is connected to the downstream connector 602B.

In order to connect the connection line SDA to the I ² CI / O expander 615, the second connection line SDA
The branch 931 branches at a branch 903, and the branched second connection line SDA 931 is connected to the SDA terminal shown in FIGS. 8A and 8 of the I ² CI / O expander 615. Also, I ²
In order to connect to the CI / O expander 615, the second connection line SCL 932 branches at branch 904, and the branched second connection line SCL 932 is the SCL terminal shown in FIGS. 8A and 8B of the I ² CI / O expander 615. Connected to

The I ² CI / O expander 615 is supplied with a voltage Vcc which is a power supply voltage of the I ² CI / O expander 615. Also, although not shown in FIG. 9, I ² CI /
The O expander 615 outputs signal lines (see FIG. 8A) of ports 0 to 15 for driving the LEDs (decorative device 200) provided on the relay substrate 600.

In addition, the I ² CI / O expander 615 includes the second connection line SDA 931 and the second connection line S.
Although it is assumed that the CL 932 is connected, the first connection line SDA 921 and the first connection line SCL 922
It may be connected to

A signal that the I ² CI / O expander 615 outputs to the upstream master IC 570 via the connection line SDA, and an input from the upstream master IC 570 to the I ² CI / O expander 615 of the relay substrate 600 via the connection line SDA The Zener diode ZD 941 is connected to the internal connection line SDA 911 in order to remove the noise of the input signal.

Specifically, internal connection line SDA 911 is branched at branch 905 and branched internal connection line SD.
A 911 is connected to the cathode side of zener diode ZD 941 and zener diode ZD
The anode side of 941 is grounded.

Therefore, a voltage (for example, a pulse noise signal) higher than a predetermined voltage applied to the internal connection line SDA 911 is released by the Zener diode ZD 941.

Also, the I ² CI / O expander 615 of the relay board 600 from the master IC 570 upstream
In order to eliminate noise on the signal input through connection line SCL, internal connection line SCL9
The zener diode ZD 942 is connected to the terminal 12.

Specifically, internal connection line SCL 912 branches at branch 906, and branched internal connection line SC.
L 912 is connected to the cathode side of zener diode ZD 942, and zener diode Z D
The anode side of 942 is grounded.

For this reason, a voltage (for example, a pulse noise signal) higher than a predetermined voltage applied to the internal connection line SCL912 is released by the Zener diode ZD942.

A signal output from the I ² CI / O expander 615 of the relay substrate 600 to the decoration control device 610 connected to the downstream connector 602A via the connection line SDA, and the downstream connector 602A
The I ² CI / O expander 615 of the relay board 600 from the decoration control device 610 connected to
In order to remove noise of the signal input through connection line SDA, first connection line SDA9
The Zener diode ZD943 is connected to the reference numeral 21.

Specifically, the first connection line SDA 921 branches at a branch 907, and the branched first connection line SD
A 921 is connected to the cathode side of zener diode ZD943, zener diode ZD
The anode side of 943 is grounded.

Therefore, a voltage (for example, a pulse noise signal) higher than a predetermined voltage applied to the internal connection line SDA 921 is released by the Zener diode ZD 943.

Further, similarly to the Zener diode ZD943 connected to the first connection line SDA921, the Zener diode 945 is also connected to the second connection line SDA931.

In addition, in order to remove noise of a signal input from the I ² CI / O expander 615 of the relay substrate 600 to the decoration control device 610 connected to the downstream connector 602A via the connection line SCL, the first connection line SCL922 Zener diode ZD 944 is connected to.

Specifically, the first connection line SCL 922 branches at a branch 908, and the branched first connection line SC
L 922 is connected to the cathode side of zener diode ZD 944, and zener diode Z D is
The anode side of 944 is grounded.

Therefore, a voltage (for example, a pulse noise signal) higher than a predetermined voltage applied to the internal connection line SCL 922 is dissipated by the Zener diode ZD 944.

Further, similarly to the Zener diode ZD 944 connected to the first connection line SCL 922, the Zener diode ZD 946 is also connected to the second connection line SCL 932.

Also, the upstream connection line SDA connected to the master IC 570, and the decoration control device 610
Pull-up resistor R95 for pulling up the voltage of the downstream connection line SDA connected to
1 is connected to the first connection line SDA 921. Similarly, a pull-up resistor R952 for pulling up the voltage of the upstream connection line SCL connected to the master IC 570 and the downstream connection line SCL connected to the decoration control device 610 is connected to the first connection line SDA922. Connected

Specifically, the first connection line SDA 921 branches at a branch 909, and the branched first connection line SD
A 921 is connected to pull-up resistor R 951. Similarly, the first connection line SCL922 branches at a branch 910, and the branched first connection line SCL922 is connected to a pull-up resistor R952.

Note that a pull-up resistor 951 pulls up the voltage of the connection line SDA and the connection line SCL,
The relay substrate 600 may not be provided 952, but may be provided in the master IC 570, or may be provided in the decoration control device 610 other than the relay substrate 600. In short, it may be anywhere as long as the voltage Vcc can be supplied to the terminal of the drain of the transistor driving the connection line SDA and the connection line SCL.

Connection line Vcc that supplies power supply voltage to I ² CI / O expander 615 of relay board 600
The internal connection line Vcc 971 extending from the Vcc terminal of the upstream connector 601 connected to and the internal connection line GND 972 extending from the GND terminal of the upstream connector 601 and grounded are:
It is connected via the smoothing capacitor C 961 and the bypass capacitor 962.

The smoothing capacitor C961 is a capacitor for smoothing the voltage waveform of the power supply,
The bypass capacitor CP962 is a capacitor for removing noise of the voltage of the power supply.

For this reason, the power supply voltage supplied to the I ² CI / O expander 615 of the relay substrate 600 is smoothed by the smoothing capacitor C 961 and the noise is removed by the bypass capacitor 962 to obtain the I ² CI / O expander. It is supplied to 615.

Similarly, internal connection line Vcc9 extending from the Vcc terminal of downstream connectors 602A and 602B.
73 and the internal connection line GND 974 extending from the GND terminal are connected via the smoothing capacitor C 961 and the bypass capacitor 962. Thereby, the smoothed and denoised voltage is applied to the connection line Vcc connected to the decoration control device 610 downstream.

FIG. 10 is a circuit diagram of connection lines regarding input and output of the decoration control device 610 according to the first embodiment of the present invention.

The decoration control device 610 includes an upstream connector 611, an I ² CI / O expander 615, and a downstream connector 612.

A bus is connected to the upstream connector 611 from the relay substrate 600 or the decoration control device 610 on the upstream side. The downstream connector 612 is connected to a bus connected to the decoration control device 610 on the downstream side.

The SDA terminal of the upstream connector 611 and the SDA terminal of the downstream connector 612 are connected by an internal connection line SDA1011. The SCL terminal of the upstream connector 611 and the SCL terminal of the downstream connector 612 are connected by an internal connection line SCL1012.

In order to connect connection line SDA to I ² CI / O expander 615, internal connection line SDA
1011 is branched at branch 1001, and the branched internal connection line SDA 1011 is connected to the SDA terminal shown in FIGS. 8A and 8 of the I ² CI / O expander 615. Also, connection line SCL
In order to connect the I ² CI / O expander 615, the internal connection line SCL1012 branches at a branch 1002, and the branched internal connection line SCL1012 is a I ² CI / O expander 61.
5 is connected to the SCL terminal shown in FIGS. 8A and 8B.

The I ² CI / O expander 615 is supplied with a voltage Vcc which is a power supply voltage of the I ² CI / O expander 615. Although not shown in FIG. 10, I ² CI
LED relating to the decoration control device 610 (decorative device 20)
Signal lines (see FIG. 8A) of ports 0 to 15 for driving 0) are output.

The I ² CI / O expander 615 of the decoration control device 610 shown in FIG.
A signal shown in FIG. 10 from an upstream decoration control device 610 or relay board 600 connected to the upstream connector 611 and a signal output via the connection line SDA to the upstream decoration control device 610 or relay board 600 connected to 11. In order to remove noise of a signal input to I ² CI / O expander 615 of control device 610 through connection line SDA, internal connection line SDA 101.
The Zener diode ZD1041 is connected to 1.

Specifically, the internal connection line SDA1011 branches at a branch 1003, the branched internal connection line SDA1011 is connected to the cathode side of the Zener diode ZD1041, and the anode side of the Zener diode ZD1041 is grounded.

For this reason, a voltage (for example, a pulsating noise signal) applied to the internal connection line SDA1011 is exceeded by the Zener diode ZD1041.

Also, the upstream decoration control device 610 or relay board 600 connected to the upstream connector 611
10 to the I ² CI / O expander 615 of the decoration controller 610 shown in FIG.
The Zener diode ZD942 is connected to the internal connection line SCL1012 in order to remove noise of the signal input via the.

Specifically, the internal connection line SCL1012 branches at a branch 1004, the branched internal connection line SCL1012 is connected to the cathode side of the Zener diode ZD1042, and the anode side of the Zener diode ZD1042 is grounded.

Therefore, a voltage (for example, a pulse noise signal) higher than a predetermined voltage applied to the internal connection line SCL1012 is released by the Zener diode ZD1042.

The I ² CI / O expander 615 of the decoration control device 610 shown in FIG.
A signal output to the downstream decoration control device 610 connected to 12 via the connection line SDA, and I ² CI / O of the decoration control device shown in FIG. 10 from the downstream decoration control device 610 connected to the downstream connector 612 In order to remove noise of a signal input to the expander 615 via the connection line SDA, a Zener diode ZD1043 is connected to the internal connection line SDA1011.

Specifically, the internal connection line SDA1011 branches at a branch 1005, the branched internal connection line SDA1011 is connected to the cathode side of the Zener diode ZD1043, and the anode side of the Zener diode ZD1043 is grounded.

Therefore, a voltage (for example, a pulse noise signal) higher than a predetermined voltage applied to the internal connection line SDA1011 is released by the Zener diode ZD1043.

Also, in order to remove noise of a signal input via connection line SCL from I ² CI / O expander 615 of decoration control device 610 shown in FIG. 10 to decoration control device 610 downstream connected to downstream connector 612. In the internal connection line SCL1012, the Zener diode ZD1
044 is connected.

Specifically, the internal connection line SCL1012 branches at a branch 1006, the branched internal connection line SCL1012 is connected to the cathode side of the Zener diode ZD1044, and the anode side of the Zener diode ZD1044 is grounded.

Therefore, a voltage (for example, a pulse noise signal) higher than a predetermined voltage applied to the internal connection line SCL1012 is released by the Zener diode ZD1044.

Connection V for supplying power supply voltage to the I ² CI / O expander 615 of the decoration control device 610
Internal connection line Vcc1071 extending from the Vcc terminal of the upstream connector 611 connected to cc
And the internal connection line GND 107 extending from the GND terminal of the upstream connector 611 and grounded
2 is connected via the smoothing capacitor C1061 and the bypass capacitor 1062.

The smoothing capacitor C1061 is the same as the smoothing capacitor C961 shown in FIG. 9, and the bypass capacitor CP1062 is the same as the bypass capacitor 962 shown in FIG.

Also, an internal connection line Vcc 1073 extending from the Vcc terminal of the downstream connector 612, GN
The internal connection line GND 1074 extending from the D terminal is connected via the smoothing capacitor C 1061 and the bypass capacitor 1062.

FIG. 11 is an explanatory diagram of a slave address 1100 included in data output from the effect control device 550 of the first embodiment of the present invention to the decoration control device 610.

The slave address 1100 includes a fixed address portion 1101 consisting of upper 3 bits and a variable address portion 1102 consisting of lower 5 bits.

The fixed address portion 1101 is an address in which “110” is set in advance and the I ² CI / O expander 615 can not change.

Variable address portion 1102 is a configurable address I ² CI / O expander 615, corresponding to a pattern that is set to A0~A3 terminal of I ² CI / O expander 615 to be controlled 4 A bit I ² CI / O expander address 1103 and 1-bit R / W identification data 1104 indicating whether the data is a read request or a write request are included.

Since the effect control data output from the effect control device 550 to the decoration control device 610 is a write request, “0” is normally registered in the R / W identification data 1104.

FIG. 12 shows the I ² CI / O expander address table 12 according to the first embodiment of this invention.
FIG.

The I ² CI / O expander address table 1200 is a table managed by the master IC 570. The I ² CI / O expander address table 1200 shows the correspondence between the slave address 1201 and the I ² CI / O expander address 1202.

The slave address 1201 stores a slave address of the decoration control device 610 designated as a target of transmission and reception by the effect control device 550. The slave address is, as described above with reference to FIG. 13, a fixed address portion consisting of upper 3 bits and a 4-bit I ² CI /
It is configured by combining the O expander address and 1-bit R / W identification data.

As described above with reference to FIGS. 8A and 8B, the I ² CI / O expander address 1202
A 4-bit I ² CI / O expander address corresponding to each slave address is registered.

However, among the I ² CI / O expander addresses, the address “1000” and the address “1011” can not be used as unique addresses for mutually identifying the respective I ² CI / O expanders 615.

“1000” is used as a power-on default value of an address (all call address) specified when outputting a command to all the decoration control devices 610. "
1011 "is a common address used when software unconditionally resets all decoration control devices 610 connected to the master IC 570.

Thus, since there are 14 unique addresses that can be set in the I ² CI / O expander 615 of the decoration control device 610, the presentation control device 550 controls the 14 I ² CI / O expander 615. it can. In addition, one decoration control device 610 includes PORT0 to PORT1.
Since 5 is provided, 16 (16 in other words) LEDs can be controlled. Thus, the effect control device 550 can control 224 LEDs (in other words, 224 types).

FIG. 13 is a diagram for describing a work register assigned to the output setting register 635 (see FIG. 7) provided in the I ² CI / O expander 615 according to the first embodiment of this invention.

A work register (device register) and a control register (control register) are assigned to the output setting register 635 of the I ² CI / O expander 615.
Work register, and information for setting the predefined relative I ² CI / O Expander 615, the output of the effect device connected to the I ² CI / O expander 615 (e.g., LED) It stores information for specifying an aspect. The control register also stores information that defines the procedure for writing data to the work register.

As shown in FIG. 13, the work register is configured to distribute and store a plurality of pieces of information in different storage areas, and different register numbers are assigned to the respective storage areas.

A register name "MODE1" is assigned to the storage area where the register number is "00h", and a register name "MODE2" is assigned to the storage area where the register number is "01h" There is. When values are written to the storage areas of register numbers “00h” and “01h”, initialization of the I ² CI / O expander 615 is performed based on the written values.

In the storage area where the register number is “02h” to “11h”, “PWM 0” to “PWM”
The register name "15" is given. When a value is written to any of the storage areas of register numbers “02h” to “11h”, the value is written out of the 16 LEDs constituting the light emitting device connected to I ² CI / O expander 615 LE corresponding to the registered register number
The brightness of D is adjusted based on the written value. For example, when a value is written to the storage area of the register number “02h”, the brightness of the LED 0 connected to the port 0 shown in FIG. 8A is adjusted.

When the accessory drive SOL 560 is connected to the I ² CI / O expander 615, the accessory drive SOL 560 is energized in the storage area of the register number corresponding to the port to which the accessory drive SOL 560 is connected. A value is written that indicates whether to operate or not to operate without energizing.

When the accessory driving MOT 561 is connected to the I ² CI / O expander 615, the target rotation number of the accessory driving MOT 561 is stored in the storage area of the register number corresponding to the port to which the accessory driving MOT 561 is connected. A value indicating the position is written.

A register name "GRPPWM" is given to the storage area having the register number "12h", and a register name "GRPFREQ" is given to the storage area having the register number "13h". When values are written in the storage areas of the register numbers “12h” and “13h”, the blinking patterns of the entire LEDs (16 LEDs) are set based on the written values.

Specifically, when a value is written in the storage area of the register number "12h", the duty cycle which is the on / off ratio of the entire LED is set, and the register number "13h"
When a value is written to the storage area of the above, the blinking cycle of the entire LED is set.

The register name "LEDOUT0" is assigned to the storage area where the register number is "14h". When a value is written to the storage area of the register number "14h", the output states of LED0 to LED3 are set based on the written value.

The register name "LEDOUT1" is assigned to the storage area where the register number is "15h". When a value is written to the storage area of the register number "15h", the output states of the LED4 to LED7 are set based on the written value.

The register name "LEDOUT2" is assigned to the storage area where the register number is "16h". When a value is written to the storage area of the register number "16h", the output states of the LEDs 8 to 11 are set based on the written value.

The register name "LEDOUT3" is assigned to the storage area where the register number is "17h". When a value is written to the storage area of the register number "17h", the output states of the LEDs 12 to 15 are set based on the written value.

In the storage area where the register number is “18h” to “1Ah”, “SUBADR1” to
The register name "SUBADR3" is given. Register number “18h” to “1A
When a value is written to the storage area “h”, the first sub-address
The third subaddress is set.

The register name "ALLCALLADR" is assigned to the storage area where the register number is "1 Bh". When the value is written to the storage area of the register number "1Bh", the all-call address is set based on the written value.

FIG. 14 shows that the master IC 570 according to the first embodiment of the present invention has the connection line SDA and the connection line SC.
It is explanatory drawing of the start condition and stop condition of the data output via L. FIG.

Connection line SCL has a signal level of HIGH when data is not transmitted, and the master IC
570 outputs the signal level of connection line SCL to L when outputting data to decoration control device 610.
It changes from OW to HIGH, and the decoration controller 610 acts as a strobe signal for capturing data on the connection line SDA.

Connection line SDA has a signal level HIGH when data is not transmitted, and connection line SC
Data is output from the connection line SDA in accordance with the L clock signal.

Master IC 570 keeps connection signal S high while keeping the signal level at connection line S high.
By changing the signal level of DA from HIGH to LOW, a signal serving as a start condition indicating that data output starts is output.

The I ² CI / O expander 615 of the decoration control device 610 has a connection line SDA and a connection line S.
When a signal serving as a start condition is input from CL, it is understood that data output starts.

Master IC 570 keeps connection signal S high while keeping the signal level at connection line S high.
By changing the signal level of DA from LOW to HIGH, a signal indicating a stop condition indicating that the output of data ends is output.

When the stop condition is input, the I ² CI / O expander 615 of the decoration control device 610 recognizes that the output of data ends.

FIG. 15 is a timing chart in which the decoration control device 610 to which data output from the master IC 570 according to the first embodiment of this invention is input outputs a response signal.

The decoration control device 610 counts the number of changes in the signal level of the connection line SCL after the start condition is satisfied, and takes in data input from the connection line SDA in accordance with the clock signal of the connection line SCL.

Then, the decoration control device 610 outputs a response signal to the master IC 570 via the connection line SDA immediately before the start condition is satisfied and immediately before the number of times of change in the signal level of the connection line SCL reaches nine. In other words, the decoration control device 610 receives the data of the 8th bit from the connection line SDA, and then, when the signal level of the connection line SCL changes from HIGH to LOW, a response signal is sent via the connection line SDA. Output.

As shown in the figure, a response signal (ACK response signal) indicating that data reception was successful is indicated by a LOW level, and a response signal (NA) indicates that data reception failed.
The CK response signal (corresponding to no ACK output in the figure) is indicated by the HIGH level.

Further, when the signal level of the connection line SCL changes eight times after the start condition is satisfied, the master IC 570 waits for the input of the response signal from the decoration control device 610 by releasing the connection line SDA. Then, while releasing connection line SDA, master IC 570 changes the signal level of connection line SCL, and takes in the response signal from decoration control device 610.

FIG. 16 is a timing chart of signal levels of the connection line SDA and the connection line SCL when the master IC 570 according to the first embodiment of the present invention outputs effect control data.

First, when starting to output data, master IC 570 changes the signal level of connection line SDA from HIGH to LOW while maintaining the signal level of connection line SCL to a signal indicating a start condition. And notify the decoration control device 610 that data is to be output from this.

Next, the master IC 570 controls the decoration control device 610 to be controlled, which consists of 7 bits in total.
Output slave address of Next, the master IC 570 outputs data indicating whether it is a write request, which is a read request, to the eighth bit.

Then, the master IC 570 receives a response signal from the decoration control device 610 when the signal level of the connection line SCL goes high for the ninth time, so if it is an ACK response signal, the signal level of the connection line SDA is LOW. If the response signal is NACK, the signal level of the connection line SDA changes to HIGH.

Next, after the output of the address data, the master IC 570 outputs the data as a multiple of eight bits. After outputting the 8th bit of data, the master IC 570 waits for an ACK response signal to be input, and outputs the 9th bit of data. Thereafter, when data of bits corresponding to multiples of 8 is output, after confirming that an ACK response signal is input,
Output a multiple of 8 plus 1) th bit and repeat until all data is output.

Note that after the master IC 570 outputs a bit that is a multiple of eight of the data, if the ACK response signal is not input even after a predetermined time has elapsed, it is regarded as having failed data transmission, and is restarted. Send the condition. Then, the address data is output again through the connection line SDA, and the data is output from the first bit again while confirming the ACK reply signal.

Further, after outputting the data of the last bit of data, the master IC 570 waits for an ACK response signal to be input, and outputs a signal indicating a stop condition.

Note that, in FIG. 16, a total of 24 bits (slave address 8 bits, data 16 bits) from the output of the signal indicating the start condition to the output of the signal indicating the stop condition
However, the data may be 24 bits or more, or 24 bits or less.

FIG. 17 shows a case where the master IC 570 according to the first embodiment of the present invention sets effect control data in the decoration control device 610 by designating an individual address of a slave.
FIG. 10 is a diagram for explaining the format of data exchanged between 0 and the I ² CI / O expander 615.

The 8-bit data 1801 to be output first includes the address “A0 to A6” of the decoration control device 610 to be subjected to data transmission and a 1-bit R indicating whether the data is a read request or a write request. / W identification data is included. This address “A0
Of A6, "A4 to A6" is a fixed address portion having a value "110", and "A0 to A
“3” corresponds to the address set to the terminals A0 to A3 of the I ² CI / O expander 615 (see FIG. 8). This data 1801 corresponds to "ADRESS" in FIG.
And “R / W”.

Next, 8-bit data 1802 to be output includes setting data to the control register assigned to the output setting register 635 (see FIG. 7) of the I ² CI / O expander 615. This data 1802 is transmitted first in FIG.
Corresponds to “TA”.

Here, the control register will be described. The control register consists of 8 bits, and the upper 3 bits "AI0 to AI2" are automatic write parameters that specify the method of writing to or reading from the work register of the output setting register 635. The lower 5 bits "D0"
".About.D4" is a register address specifying the access start position (the start position to start writing or the start position to start reading) in the work register.

The automatic writing parameter is accessed by the master IC 570 including access to only the area of the access start position designated by the register address (prohibiting auto-increment) or an area adjacent to the area of the access start position to be designated (auto increment Is a parameter that specifies whether to allow or not, specifically, “000”, “100”, “101
“110” or “111” can be set.

When the value of "000" is set to the automatic writing parameter, auto-increment is inhibited, only the area of the access start position designated by the register address is accessed, and the area other than the start position is not accessed. For example, if the register address is "10100", only the storage area whose register number is "14h" is accessed, and other storage areas are not accessed.

When the value of "100" is set in the automatic write parameter, auto-increment is permitted, and after accessing the area of the access start position specified by the register address, the area is moved in the direction of increasing the register number and accessed in order repeat. Then, after accessing the last storage area where the register number is “1 Bh”, the storage area where the register number is “00 h” is accessed, and the area is moved again in the direction in which the register number increases. repeat. For example, if the register address is "10100", after accessing the storage area where the register number is "14h", the register number is "15h" → "16".
h "→ to ·· →" 1Bh "→" 00h "→" 01h "→ ·· and a region (that is, all of the area), repeatedly access.

When the value of "101" is set in the automatic writing parameter, "100" is set in the automatic writing parameter.
As in the case where the value of is set, after accessing the area of the access start position designated by the register address, the access is repeated in order while moving the area in the direction of increasing the register number. However, once the storage area having the register number “11h” is accessed, the storage area having the register number “02h” is accessed, and thereafter, the register number “02h” to
The recording area (area related to the brightness adjustment of the LED) of the section to be “11h” is repeatedly accessed. For example, if the register address is "10100", the register number is "14h"
Register number is “15h” → “16h” →.
The areas are sequentially accessed as follows: 1Bh → 00h → 01h →. Then, after accessing the storage area where the register number is "11h", the register number is "02h"
→ Repeatedly access the area where "03h" → · · · "11h" → "02h" → "03h" →.

When the value of "110" is set in the automatic writing parameter, "100" in the automatic writing parameter
As in the case where the value of is set, after accessing the area of the access start position designated by the register address, the access is repeated in order while moving the area in the direction of increasing the register number. However, once the storage area having the register number “13h” is accessed, the storage area having the register number “12h” is accessed, and thereafter, the register number “12h” to
The recording area (area related to the blinking cycle of the LED) of the section of “13h” is repeatedly accessed. For example, if the register address is "10100", the register number is "14h"
Register number is “15h” → “16h” →.
The areas are sequentially accessed as follows: 1Bh → 00h → 01h →. Then, after accessing the storage area where the register number is "13h", the register number is "12h"
→ Repeatedly access the area where “13h” → “12h” → “13h” →.

When the value of "111" is set to the automatic writing parameter, "100" to the automatic writing parameter
As in the case where the value of is set, after accessing the area of the access start position designated by the register address, the access is repeated in order while moving the area in the direction of increasing the register number. However, once the storage area having the register number “13h” is accessed, the storage area having the register number “02h” is accessed, and thereafter, the register number “02h” to
The recording area (area related to the brightness of the LED and the blinking cycle) of the section “13h” is repeatedly accessed. For example, if the register address is "10100", the register number is "
After accessing the storage area of 14h, the register number is “15h” → “16h” →
·· → "1Bh" → to "00h" → the "01h" → ·· area, in order to access. Then, after accessing the storage area where the register number is "13h", the register number is "
02h ”→“ 03h ”→... →“ 13h ”→“ 02h ”→“ 03h ”→...

Referring back to FIG. 17, following the setting data 1802 to the control register, the setting data 1803 to the work register is output. This setting data 1803 is two in FIG.
Corresponds to “DATA” transmitted after the

When the automatic writing parameter is set to "000", the setting data 1803 is 8-bit data necessary to update one storage area designated by the register address. When the automatic writing parameter is set to a value other than "000", the setting data 1803 is a multiple of 8 necessary to repeatedly update a plurality of areas starting from the storage area designated by the register address. It will be bit data.

FIG. 18 shows a case where the master IC 570 according to the first embodiment of the present invention specifies the slave's individual address and sets presentation control data in the decoration control device 610;
A specific numerical value is applied to effect control data exchanged between 0 and the I ² CI / O expander 615. This figure exemplifies presentation control data in which only one storage area of the work register is updated by inhibiting auto-increment, and is connected to the PORT0 to PORT3 terminals of the I ² CI / O expander 615. It is assumed that the light emission state of the LED is updated.

First, the decoration control device 61 of the transmission destination is used for the 8-bit data 1901 output first.
“1101100” is assigned to indicate the slave address of the 0 I ² CI / O expander 615.

The next output 8-bit data 1902 is set in the control register of the output setting register 635 of the I ² CI / O expander 615 assigned to set the automatic writing parameter and the LED output data. Value is included.

Here, since the light emission state of the LED connected to the PORT0 terminal to the PORT3 terminal of the I ² CI / O expander 615 is set, LEDOUT0 (address = 10100) is designated as the register address.

Note that "000" is designated as the automatic writing parameter in order to inhibit auto-increment.

Next, the output 8-bit data 1903 includes data for setting the light emission mode of the decoration device 620 controlled by the decoration control device 610 of the transmission destination. Specifically, LE
Data to be set in the DOUT0 register is allocated. This makes I ² CI /
The light emission state (on, off, blink, etc.) of the LED connected to the PORT0 terminal to the PORT3 terminal of the O expander 615 is designated, and the LED emits light in the designated state.

In this way, the light emission state of the LED PORT0 terminal ~PORT3 terminal I ² CI / O expander 615 is controlled, the other PORT terminal I ² CI / O expander 615 (PORT4~PORT15) also Control is possible by specifying the value of data 1902 to be written in the control register and setting output data 1903. In the PORT terminal,
Even if a motor or solenoid is connected, it is similarly controlled.

FIG. 19 is a diagram for explaining another form of effect control data according to the first embodiment of the present invention.
In this figure, it is assumed that auto-increment is permitted and all storage areas of the work register are updated, and the transmission order of each data included in the effect control data is defined.

First, master IC 570 transmits 8-bit data (data having the same format as data 1901 in FIG. 18) that can specify the individual address of decoration control device 610 to be controlled.

Next, master IC 570 transmits data (data in the same format as data 1902 in FIG. 18) set in the control register of output setting register 635 of I ² CI / O expander 615 to be controlled. In this figure, "100" is set as the automatic write parameter to allow auto-increment to update all storage areas of the work register.
Is designated, and "00h" which is the head area of the work register is designated as the register address which designates the write destination or the start position of the read.

Therefore, the decoration control device 6 to be controlled after receiving the control register set value
In the 10 I ² CI / O expander 615, the storage area (MODE 1 register) whose register number is “00h” is updated first.

Next, after transmitting the control register set value, the master IC 570 transmits a value (8 bits in total) to be written to the MODE 1 register. When receiving the write value, the I ² CI / O expander 615 updates the value of the MODE 1 register, increments the register number, and prepares to update the next “01h” storage area (MODE 2 register) .

Next, master IC 570 transmits the value (total 8 bits) to be written to the MODE 2 register, and subsequently transmits the set values to the registers of the remaining storage areas whose register numbers are “02h” to “1 Bh”. . The I ² CI / O expander 615 updates the value of the corresponding register each time the write value is received, increments the register number, and repeats the preparation for updating the next storage area, thereby the work register Assigned to "00
The values of all the registers h "to" 1 Bh "are updated.

When the I ² CI / O expander 615 updates the last “1 Bh” storage area of the work register, the I ² CI / O expander 615 changes the register number to “00 h” and waits for update of the MODE 1 register.

FIG. 20 shows the master IC 570 according to the first embodiment of the present invention as the I ² CI / O expander 6.
15 is a diagram for explaining a data format of initialization instruction data transmitted from a master IC 570 to an I ² CI / O expander 615 when initializing 15. FIG.

When the CPU 551 of the effect control device 550 instructs the master IC 570 to initialize the decoration control device 610, the master IC 570 transmits initialization instruction data to all the decoration control devices 610 connected thereunder. .

The 8-bit data 2001 output first has the fixed address “11” shown in FIG.
0 "and a reset address" 1011 "(see FIG. 12) which is a common address. Note that this data 2001 corresponds to "ADRESS" in FIG. 16, and "0" representing writing is set to the bit of "R / W".

Next, in the 8-bit data 2002 to be output, the first predetermined value “10100101” is output, and in the 8-bit data 2003 to be output next, the second predetermined value “01011010” is output.
"Is output. Note that this data 2002 is transmitted first in FIG.
The data 2003 corresponds to “ATA”, and the data 2003 is transmitted second in FIG.
Corresponds to

When all the I ² CI / O expanders 615 connected to master IC 570 receive initialization instruction data including the reset address, the first predetermined value, and the second predetermined value,
Initialize itself.

The first predetermined value and the second predetermined value are outputted after the output of the reset address.
Even though the master IC 570 does not transmit the reset address "1011", the I ² CI / O expander 615 erroneously resets the address "101" due to noise or the like.
This is to prevent the initialization process from being performed at an incorrect timing.

Also, unlike the individual addresses, the reset addresses are all (in other words, plural) I
^{2 This} is an address common to the CI / O expander 615. Therefore, only transmit once initialization instruction data including the reset address, it means that initialize Select I ² CI / O expander 615 all (plural), I ² CI / O Aix As compared with the method of individually selecting the pandas 615 and instructing initialization, initialization can be instructed at high speed.

In FIG. 20, although the first predetermined value and the second predetermined value are different values, they may be the same value. Alternatively, one of the first predetermined value and the second predetermined value may be transmitted once.

  FIG. 21 is a diagram for explaining the abnormality determination table 2100 according to the first embodiment of this invention.

The abnormality determination table 2100 is stored in the RAM 553 of the effect control device 550. The abnormality determination table 2100 includes the master IC 570 of the effect control device 550 and the master IC 57.
It monitors the connection status with the I ² CI / O expander 615 connected to 0, and the error described later corresponding to the corresponding I ² CI / O expander 615 according to the confirmation result of the connection status. The flag 2105 is set.

The abnormality determination table 2100 includes an I / O expander address 2101, a slave address 2102, an error counter 2103, a comparison value 2104, and an error flag 2105.

The I / O expander address 2101 is I ² CI / O connected to the master IC 570
It corresponds to the address (see FIG. 8) set to the terminals A0 to A3 of the expander 615.

The slave address registered in the I ² CI / O expander address table 1200 shown in FIG. 12 is registered in the slave address 2102.

When the error counter 2103 monitors whether the ACK from the I ² CI / O expander 615 can be received with respect to the transmission of presentation control data from the master IC 570 to the I ² CI / O expander 615, It is incremented when two consecutive unsuccessful receptions of this ACK occur.

A predetermined value is registered as the comparison value 2104. The error flag 2105 registers an error flag indicating whether or not an abnormality has occurred in the connection state of the entry with the I ² CI / O expander 615.

Specifically, when the value of the incremented error counter 2103 reaches a predetermined value registered in the comparison value 2104, the error flag 2105 is set ON, and the I ² CI / O expander 615 of the entry That an abnormality has occurred is registered.

In addition, the I ² CI / O of “0110” registered in the I / O expander address 2101
The expander 615 is, as shown in FIG. 8B, a feature drive SOL 560 or a feature drive MOT 5
It controls mobile devices such as 61. Therefore, the decoration control device 610 including the I ² CI / O expander 615 will be referred to as a movable control device (movable group unit control means).

On the other hand, I ² CIs other than “0110” registered in the I / O expander address 2101
The / O expander 615 controls a light emitting device such as an LED as shown in FIG. 8A.
Therefore, the decoration control device 610 including the I ² CI / O expander 615 will be referred to as a light emission control device (light emission group unit control means) in order to distinguish it from the movable control device described above.

In FIG. 21, the value registered in the movable control device (I / O expander address 2101
There is no entry of “0110”, and only the entry of the light emission control device is registered.

If an abnormality occurs in the movable control device, the gift drive MOT 561 rotates too much.
In order to prevent the movable character 60 from moving beyond the operable range and damaging the movable character 60 and members in the vicinity of the movable character, the abnormality is judged in a shorter time than the light emission control device. There is a need. Therefore, since the connection monitoring timing of the movable control device and the connection monitoring timing of the light emission control device are different, in other words, the connection monitoring configuration of the movable control device and the connection monitoring configuration of the light emission control device are different. The entry of the movable control device is excluded from 2100.

Specifically, in the present embodiment, as described later, data output processing of the light emission control device (FIG.
2) is to be executed in synchronization with the VDP interrupt (about 33.3 ms cycle) and to execute data output processing of the mobile control device in synchronization with the timer interrupt (2 ms cycle) There is.

As described above, in response to the second transmission of presentation control data from the master IC 570 to the I ² CI / O expander 615 included in the light emission control device, the ACK from the I ² CI / O expander 615 is If not received, the error counter 2103 is incremented.

Therefore, when an abnormality occurs in the light emission control device, the execution period of data output processing is 33 ms, and the comparison value 2104 is "300", so 33.3 ms x 300 ≒ 10 s.
Detects that an abnormality has occurred in the light emission control device.

When an abnormality occurs in the movable control device, the execution cycle of data output processing is 2 m
s, and as described later, since occurrence of abnormality is detected without waiting for the next execution cycle, occurrence of abnormality in the movable control device can be detected in a very short time (a time of about 2 ms). .

For this reason, the error determination of the movable control device is performed more frequently than the error determination of the light emission control device, and the occurrence of an abnormality in the movable control device can be detected earlier than the occurrence of an abnormality in the light emission control device. Therefore, it is possible to prevent the movable part 60 from moving beyond the operable range and damaging the movable part 60 and the members near the movable part.

On the other hand, since the light emitting device such as the LED is less likely to be damaged due to a malfunction, the problem does not occur even if it takes time to determine the abnormality regarding the light emission control device.

Therefore, the cycle of determination is shortened by limiting to the decoration control device 610 which needs to perform the abnormality determination in a short time, and the abnormality determination of the other decoration control device 610 is performed in a period with a margin. It becomes possible to execute the abnormality judgment processing considered.

Further, “0111” is not registered in the I / O expander address 2101. Although it is possible to assign the address “0111” to the decoration control device 610, in the present embodiment, since the address “0111” is not used, the I / O expander address 210 is used.
Not registered in 1.

Although 14 I ² CI / O expanders 615 can be connected to one master IC 570, all 14 I ² CI / O expanders 615 may not be connected to one master IC 570. . For example, in the present embodiment, as described above, thirteen I ² CI / O expanders 615 are connected to the master IC 570 corresponding to the abnormality determination table 2100 shown in FIG.

Thus, the I ² CI / O expander 615 to which an address is given is a master IC 5
An I ² CI / O expander 615 can be connected to 70, and I ² CI / O expander 615 decoration controller 610 for controlling the decoration device 620 that may perform rendering of the game
It is.

Therefore, the I / O expander address 2101 of the abnormality determination table 2100 is the I ² CI / O expander 615 connectable to the master IC 570, and a decoration device 620 having the possibility of performing a game effect. The address of the I ² CI / O expander 615 of the decoration control device 610 controlling the is registered.

The I ² CIs of all the addresses registered in the I / O expander address 2101
The / O expander 615 is not actually connected to the master IC 570, and only the I ² CI / O expander 615 of some addresses is connected to the master IC 570.

In FIG. 21, for example, the I ² CI / O expander 61 whose address is “0000”.
It is assumed that 5 is not connected to the master IC 570, and the I ² CI / O expander 615 of the other address is connected to the master IC 570.

As described in FIG. 25, master IC 570 has I / O expander address 2101.
Since the decoration control data is transmitted to all the addresses registered in, if it is the I ² CI / O expander 615 of the address registered in the I / O expander address 2101, it is connected to the master IC 570. Even if not connected, the same control program can control the I ² CI / O expander 615 connected to the master IC 570.

In addition, if there are 14 I ² CI / O expanders 615 of the decoration control device 610 that controls the decoration device 620 that may perform a game presentation, the 14 I ² CI / O expanders 615 An address may be assigned, and 14 I ² CI / O expanders 615 may be connected to the master IC 570.

FIG. 22 is a flowchart of processing by the effect control device 550 of the first embodiment of the present invention.

The processing of the effect control device 550 shown in FIG. 22 is executed by the CPU 551 of the effect control device 550.

When the presentation control device 550 is powered on, the presentation control device 550 first performs step 22.
After the processes of 01 to 2210 are executed, the process waits until a synchronization signal (for example, a synchronization signal having a cycle of 33 ms seconds) synchronized with the image update cycle is input to the CPU 551 from the VDP 556. Thereafter, every time a synchronization signal synchronized with the image update cycle is input from the VDP 556 to the CPU 551, the processing of steps 2204 to 2210 is repeatedly executed.

First, the effect control device 550 initializes the RAM 553 of the effect control device 550 (22
01). At this time, with the power on to the effect control device 550 as a base point, the CPU 551
The first control data to be output to the VDP 556 and the sound LSI 557 are also generated.

Next, the effect control device 550 executes an I ² C initial reset process for initializing the master IC 570 and the decoration control device 610 connected to the master IC 570 (2202). I ²
The C initial reset process will be described in detail with reference to FIG. When this I ² C initial reset process is executed, initialization operations of the gift drive MOT 561 and the gift drive SOL 560 are also started.

Then, the effect control device 550 receives from the VDP 556 a synchronization signal synchronized with the image update cycle (
VDP interrupt) and timer interrupt acceptance are permitted (2203).

Then, the effect control device 550 causes the VDP 556 to display an image on the display device 53.
The sound control data is output to the sound LSI 557 in order to output the data to be an instruction to display the image on the screen (2204), and to output the sound from the speaker 30 according to the game state.
7 makes the speaker 30 output a sound based on the sound control data (2205).

Next, the effect control device 550 executes a light emission control slave output process of outputting the effect control data from the master IC 570 to the light emission control device (2206). The light emission control slave output process will be described in detail with reference to FIG.

Then, the effect control device 550 edits the data to be output next to the VDP 556 (22
07) Edit the sound control data to be output next to the sound LSI 557 (2208), and edit the effect control data to be output next to the light emission control device of each group (2209).

Next, referring to the abnormality determination table 2100, the effect control device 550 determines that the reset condition is satisfied when the error flags 2105 of all the light emission control devices are ON, and the master IC 570, the bonus drive MOT 561. , I ² C random reset processing instructing initialization of all I ² CI / O expanders 615 connected to the master IC 570 and the symbol drive SOL 560 (2210), and then the synchronization signal from the VDP 556 is the CPU 55
Wait until 1 is entered. The I ² C random reset process will be described in detail with reference to FIG.

In the process according to FIG. 22, in synchronization with the cycle of updating the image of the display device 53, presentation control data is transmitted from the master IC 570 of the presentation control device 550 to the I ² CI / O expander 615 of the decoration control device 610. ^{2 Since the} CI / O expander 615 controls the decoration device 620 based on the received effect control data, the effect on the display device 53 and the effect on the decoration device 620 are in harmony, and the player does not feel discomfort Can be enhanced.

Also, each time the decoration control device 610 receives presentation control data transmitted from the master IC 570 in synchronization with the cycle of updating the image of the display device 53, the I ² CI / O expander 615 The value is updated. Therefore, since the value of the work register is updated to the latest state every time, even if the value of the work register is destroyed due to noise or the like, it is possible to return to the normal value.

Further, since the error determination process executed in the process of step 2211 is performed in synchronization with the cycle of updating the image of the display device 53, the execution frequency of the error determination can be made appropriate, that is,
If the execution frequency of the error judgment processing is too high (the number of executions per unit time is too high), the processing load of the CPU 551 of the effect control device 550 increases, and conversely, the execution frequency of the error judgment processing is too low ( If the number of executions per unit time is too small), the occurrence of an abnormality can not be properly detected. Therefore, by performing the error determination with an appropriate frequency, it is possible to prevent processing defects.

FIG. 23 is a flowchart of I ² C initial reset processing according to the first embodiment of this invention.

The I ² C initial reset process is performed immediately after the presentation control device 550 is powered on.
70, processing for instructing initialization of all the I ² CI / O expanders 615 connected to the master IC 570, which is executed in the processing of step 2202 shown in FIG. During the processing, the start of the initialization operation of the bonus drive MOT 561 and the bonus drive SOL 560 is instructed.

First, the CPU 551 of the effect control device 550 sets a reset request flag indicating that initialization is in progress (2301), and inputs a reset pulse to the master IC 570 via the input / output I / F 558 and the NOR gate circuit 590. , And initialize (hard reset) the master IC 570 in hardware (2302).

The hard reset refers to the master IC 570 as a reset circuit (not shown) of the master IC 570.
The RESET terminal is connected, and the reset circuit of the master IC 570 resets the master IC 570 itself by holding the voltage applied to the RESET terminal at the low level for a predetermined time. The RESET terminal functions as an initialization signal input instruction terminal in the present embodiment.

In the present embodiment, the reset signal applied to the RESET terminal is, as described above,
It is also connected to other circuits provided in the presentation control device 550. The other circuits are, for example, the VDP 556, the sound LSI 557, etc., and are initialized by the CPU 551 when the effect control device 550 is powered on and activated. Therefore, when the power is turned on, these circuits can be initialized together with the master IC 570 by the hard reset, so that the processing speed can be expected.

Next, the effect control device 550 controls all the decoration control devices 6 connected to the master IC 570.
In order to initialize the 10 I ² CI / O expanders 615, slave reset processing for outputting initialization instruction data from the master IC 570 is executed (2303). The slave reset process will be described in detail with reference to FIG.

Next, since the initialization of the master IC 570 and the I ² CI / O expander 615 is completed by the processing of step 2302 and the processing of step 2303, the effect control device 550 clears the reset request flag (2304). Then, the effect control device 550 is a feature driving MO.
A motor initialization flag indicating that T561 is being initialized is set (2305). The initialization of the bonus drive MOT 561 is a process of returning the rotation axis of the bonus drive MOT 561 to the initial position, and is performed by the timer interrupt process shown in FIG.

Next, when the effect control device 550 initializes the bonus drive MOT 561, the bonus drive MO
The motor output data output to T561 is set in the RAM 553 (2306). Then, the effect control device 550 causes the feature drive SOL 5 to initialize the feature drive SOL 560.
Output OFF data to turn off the 60 energized states to the non-energized state to the bonus drive SOL 560 (230
7) Go to the processing of step 2203 shown in FIG. Note that the initialization of the bonus drive SOL 560 is to de-energize the bonus drive SOL 560.

Although the CPU 551 inputs the reset pulse to the master IC 570 via the input / output I / F 558 and the NOR gate circuit 590 to reset the master IC 570 in hardware, the CPU 551 resets the register 573 via the bus 563. The master IC 570 may be softly reset by writing information to the

  FIG. 24 is a flowchart of slave reset processing according to the first embodiment of this invention.

Slave reset process is a process of transmitting an initialization instruction data for initializing the I ² CI / O expander 615 to I ² CI / O expander 615, the process of step 2303 shown in FIG. 23, and FIG. It is executed in the process of step 2706 shown in FIG.

The initialization instruction data is transmitted from master IC 570 in byte mode. In byte mode, the master IC570, every time one byte transmit data to I ² CI / O expander 615 receives the ACK or NACK from the I ² CI / O expander 615, receiving either an ACK or NACK Even in this case, the interrupt signal is output to the CPU 551. That is, when it is completed to transmit 1-byte data from master IC 570 to I ² CI / O expander 615, master IC 570 to CPU 55 always transmit, regardless of ACK / NACK reception.
An interrupt signal is output to 1.

First, the master IC 570 changes the signal levels of the connection line SDA and the connection line SCL to a signal level indicating a start condition (2401).

Next, the CPU 551 sets 1 byte of data indicating the reset address (see FIG. 20) in the output BUF 572 (2402).

Then, from the time when the CPU 551 instructs the master IC 570 to start data transmission,
In order to monitor the time until master IC 570 transmits an interrupt signal to CPU 551,
The start of the monitoring timer for the byte mode is started (2403). Hereinafter, this monitoring time will be referred to as a byte mode monitoring time.

If the CPU 551 does not receive an interrupt signal from the master IC 570 even after a predetermined time has elapsed since the start of monitoring of the byte mode time, it is assumed that a timeout has occurred,
In order to interrupt data transmission, the master IC 570 outputs a stop condition (2415)
After that, the process returns to step 2401 to make the master IC 570 output the start condition again, and then transmit initialization instruction data from the first data.

Next, the master IC 570 outputs the reset address set in the output buffer 572 in the process of step 2402 to the I ² CI / O expander 615 (2404). When outputting the reset address, master IC 570 temporarily turns off driver 576A to release connection line SDA (change it to a high level). Then, when the connection line SDA is not released (when the connection line SDA does not become high level and is maintained at low level even when the driver 576A is turned off), the output of this reset address is Wait until line SDA is released (connection line SDA goes high).

Next, the master IC 570 determines whether an ACK response signal is input to the master IC 570 within a predetermined time (a monitoring time shorter than the above-described byte mode monitoring time) after completion of data output for one byte. Check (2405).

Then, based on the confirmation result of the process of step 2405, master IC 570 determines whether or not an ACK response signal is input within a predetermined time after the data is output (
2406).

If it is determined in the process of step 2406 that the ACK response signal is not input within a predetermined time after the data is output, the master IC 570 sets information indicating that the response signal is NACK in the status REG 579. And generate an interrupt signal. As a result, the reception of the NACK response signal from the I ² CI / O expander 615 is
It is notified to U551. At this time, the CPU 551 ends the byte mode time monitoring (
2407).

Next, the CPU causes the master IC 570 to output a stop condition to interrupt data transmission (2415), and then returns to the process of step 2401 and again performs the master IC 570.
After making the start condition output, the initialization instruction data is output again.

If it is determined in the process of step 2406 that the ACK response signal has been input within a predetermined time after the data is output, the master IC 570 sets information indicating that the response signal is ACK in status REG 579. Generates an interrupt signal. This makes I
^The CPU 551 is notified that the response signal of ACK has been received from the ² CI / O expander 615. At this time, the CPU 551 ends the time monitoring in the byte mode (2408).
.

Then, CPU 551 outputs all three types of data (initial data shown in FIG. 20 including reset address 2001, data 2002 of the first predetermined value, and data 2003 of the second predetermined value) shown in FIG. It is determined whether or not (2409). Since the output order of these data is determined in advance, in the process of step 2409, it may be determined whether or not the data 2003 of the second predetermined value has just been output.

If it is determined in the process of step 2409 that all the data constituting the initialization instruction data has been output, that is, if the data indicating the second predetermined value shown in FIG. 20 is output, the master IC 570 is connected The signal level of the line SDA and the connection line SCL is changed to the signal level indicating the stop condition (2410), and the slave reset process is ended.

If it is determined in the process of step 2409 that not all data constituting the initialization instruction data has been output, the CPU 551 outputs the 1-byte data to be transmitted next as the output BU
It sets to F572 (2411). In the process of step 2411 executed immediately after outputting the reset address, the output BUF 572 has data 20 of the first predetermined value shown in FIG.
In the process of step 2411 executed immediately after the data 02 having the first predetermined value is set, data 2002 having the second predetermined value shown in FIG. 20 is set in the output BUF 572.

Then, from the time when the CPU 551 instructs the master IC 570 to start data transmission,
In order to monitor the time until master IC 570 transmits an interrupt signal to CPU 551,
The start of the monitoring timer for the byte mode is started (2412).

Next, master IC 570 monitors the voltage level of connection line SDA and confirms that connection line SDA is released (2413), and then outputs 1 byte of data set in output BUF 572 ( 2414), Go to the processing of step 2405. In the process of step 2413, since the connection line SDA is occupied by the reply signal until the output of the reply signal from the group unit controller is completed, the master IC 570 outputs the reply signal from the group unit controller. It is processing to end and wait until the connection line SDA is released.

From the above, each time the initialization instruction data outputs 1 byte of data (that is, while sending 3 bytes of initialization instruction data), it indicates whether the response signal to the 1 byte data that has been output indicates no or not. It is transmitted in a byte mode to monitor whether or not a load signal is output.

In the process of step 2403 and the process of step 2412, monitoring of the time from transmission of 1-byte data to the output of an interrupt signal from master IC 570 is C
Although performed by the PU 551, the master IC 570 itself may monitor the time from the transmission of 1-byte data to the output of an interrupt signal from the master IC 570.

FIG. 25 is a flowchart of light emission control slave output processing according to the first embodiment of this invention.

Light emission control slave output processing, I ² CI / O expander 615 connected to light emitting device
22 is a process of transmitting issue control data to the (light emission control device), and step 220 shown in FIG.
It is executed in the process of 6.

First, the effect control device 550 increments the time division counter (2501). The time division counter is a counter that counts integers from 0 to 3.

As described later, in the gaming machine of this embodiment, the I ² CI / O expander 61 determined to be connected to the master IC 570 by the abnormality determination table 2100 shown in FIG.
5, the master IC 570 transmits data from the master IC 570 at regular intervals, as well as periodically transmitting data from the master IC 570, as well as to the I ² CI / O expander 615 not connected to the master IC 570. ing.

This is because it is assumed that the I ² CI / O expander 615, which is not connected at this time, has resumed connection with the master IC 570 during the operation of the game arcade. However,
In order to make the data transmission frequency lower than that of the I ² CI / O expander 615 whose connection is established, data transmission is performed from the master IC 570 only when the time division counter is zero.

Next, the effect control device 550 determines whether the value of the time division counter incremented in the process of step 2501 is larger than the maximum value (2502).

If it is determined in the process of step 2502 that the value of the time division counter is larger than the maximum value, the value of the time division counter is set to 0 (2503).

Here, since the maximum value of the time division counter is set to 3, when the value of the time division counter becomes larger than 3, that is, when the value of the time division counter becomes 4, the value of the time division counter is set to 0 Be done. Therefore, the time division counter is incremented each time the light emission control device slave process is executed, and changes as 0 → 1 → 2 → 3 → 0 →...

If it is determined in the process of step 2502 that the value of the time division counter is equal to or less than the maximum value, or after the process of step 2503 is executed, the effect control device 550 executes one of the abnormality determination tables 2100 shown in FIG. An address is selected, and an I ² CI / O expander 615 to be a transmission destination is selected (2504).

Specifically, the effect control device 550 controls the I / O of the abnormality determination table 2100 shown in FIG.
One address is selected from the addresses registered in the expander address 2101. The I ² CI / O expander 615 of the address selected in the process of step 2504 becomes the destination I ² CI / O expander 615.

Next, the effect control device 550 determines whether or not the I ² CI / O expander 615 selected in the process of step 2504 is connected to the master IC 570, as shown in FIG.
It is determined whether the error flag 2105 included in the entry of the address selected in the process of step 2504 is ON, referring to the abnormality determination table 2100 shown in FIG.
505).

Error flag 21 included in the entry of the address selected in the process of step 2504
If 05 is determined in the processing in step 2505 If it is on, because the data transmission to the address is failed continuously until value registered in the comparison value 2104, of the address I ² CI / It is determined that the O expander 615 is not connected to the master IC 570.
Then, the effect control device 550 sets 0 to RP (2506).

The RP will be described in detail with reference to FIG. 26, but I ² CI / O from the master IC 570 to the destination
If data transmission to the expander 615 fails (if the master IC 570 can not receive an ACK response signal from the I ² CI / O expander 615), or if a predetermined time has elapsed from the start of data transmission to the CPU 551, the master In the case where an interrupt signal is not input from the IC 570, the number of retransmissions of the data is determined.

Therefore, in the process of step 2506, since 0 is set to RP, the master IC 57
When the I ² CI / O expander 615 is not connected to 0, even if data transmission to the I ² CI / O expander 615 fails, retransmission is not performed.

Next, the effect control device 550 determines whether the value of the time division counter is 0 (25
07).

If it is determined in the process of step 2507 that the value of the time division counter is 0, the effect control device 550 executes slave continuous output processing, and the data is sent to the I ² CI / O expander 615 as the transmission destination. Is sent (2508).

On the other hand, if it is determined in the process of step 2507 that the value of the time division counter is not 0,
The process proceeds to step 2509 without executing the slave continuous output process.

Therefore, data transmission to the I ² CI / O expander 615 not connected to the master IC 570 is performed once when the light emission control slave output process is performed four times.

  The slave continuous output processing will be described in detail with reference to FIG.

When the slave continuous process executed in the process of step 2508 is completed, or when it is determined in the process of step 2507 that the time division counter is not 0, the effect control device 550
It is determined whether data transmission has ended for all addresses registered in the abnormality determination table 2100 shown in FIG. 21 (2509).

If it is determined in the process of step 2509 that data transmission has not ended for all the addresses registered in the abnormality determination table 2100 shown in FIG.
0 selects an address for which data transmission has not been performed yet among addresses registered in the abnormality determination table 2100 shown in FIG. 21 (2510), and returns to the process of step 2505. If it is determined in the process of step 2509 that data transmission has ended for all addresses registered in the abnormality determination table 2100 shown in FIG. 21, the stop condition is output (2512), and the calling source Return to the processing of

On the other hand, when it is determined in the process of step 2505 that the error flag 2105 included in the entry of the address selected in the process of step 2504 is off, the I ² CI / O expander 615 of the address is the master IC 570. It is determined that it is connected to Then, the effect control device 550 sets 2 in RP (2511), and proceeds to the processing of step 2508.

In the process of step 2511, since 2 is set to RP, the master IC 570 is set to I ² CI.
If the I / O expander 615 is connected, the I ² CI / O expander 61
If data transmission to 5 fails, the number of retransmissions is two.

In the process of FIG. 25, the master IC 570 transmits data to the I ² CI / O expander 615 of all the addresses registered in the abnormality determination table 2100 shown in FIG.
That is, data transmission is performed on the addresses of all the I ² CI / O expanders 615 connectable to the master IC 570.

Here, in the present embodiment, a part of the I ² CI / O expander 6 among the I ² CI / O expanders 615 of all the addresses registered in the abnormality determination table 2100 shown in FIG. 21.
Only 15 is connected to the master IC 570.

Therefore, if the address is registered in the abnormality determination table 2100 shown in FIG.
² Master IC 5 even if CI / O Expander 615 is not connected to Master IC 570
70 sends data.

Accordingly, the abnormality determination if I ² CI / O expander 615 addresses registered in the table 2100, any I ² CI / O expander 615 master IC address
Even when connected to 570, the connected I ² CI / O expander 615 can be accurately controlled.

For example, it is assumed that a game machine of the first specification and a game machine of the second specification (both described later) having different types of effect devices to be provided are developed. If the type of rendering device provided differs, the type of I / O expander 615 inevitably provided will also differ. Even in this case, all the I ² CI / O expanders 615 registered in the abnormality determination table 2100
The present invention can be applied to both the first specification gaming machine and the second specification gaming machine by creating only one type of program for transmitting data to the address of. Therefore, it is not necessary to create the program for the gaming machine of the first specification and the program for the gaming machine of the second specification, respectively, and the manufacturing cost of the gaming machine can be reduced.

In the process of FIG. 25, data is output to the I ² CI / O expander 615 determined to be connected to the master IC 570 each time the light emission control slave output process is performed, while the master When the light emission control slave output process is performed four times, data is output to the I ² CI / O expander 615 determined not to be connected to the IC 570 at a rate of once.

Thus, I ² of the data transmission frequency to the I ² CI / O expander 615 where it is determined not to be connected to the master IC570, is determined to be connected to the master IC570
Since the frequency of data transmission to the CI / O expander 615 is lower (the number of transmissions per unit time is reduced), the overall amount of data communication between the master IC 570 and the I ² CI / O expander 615 is It can be reduced.

Also, the I ² CI / O expander 6 determined not to be connected to the master IC 570
15, because it is I ² CI / O expander 615 a predetermined number of times continuously transmitting data is determined to have failed, the abnormality (in the gaming facility serves temporarily the I ² CI / O expander 615 There may be a possibility that a communication failure has occurred. Also I ² CI / O
In an abnormality that occurs in the expander 615, the abnormality may be resolved after a lapse of time under some circumstances (such as when the communication state is restored by replacing the broken I ² CI / O expander 615) .

Here, in the present embodiment, the I ² CI determined not to be connected to the master IC 570
The data transmission to the / O expander 615 is not stopped, but the data transmission is performed once every four times. For this reason, data transmission is also performed to the I ² CI / O expander 615 in which an abnormality has occurred.

As described above, when the I ² CI / O expander 615 receives the 1-byte data, the I ² CI / O expander 615 outputs the response signal to the master IC 570. When the master IC 570 receives the response signal, data transmission is normally performed between the master IC 570 and the I ² CI / O expander 615. Therefore, among the entries of the abnormality determination table 2100 shown in FIG. An initial value is set to the error counter 2103 included in the entry of the address of the I ² CI / O expander 615 (step 26 shown in FIG. 26).
20) and “off” is registered in the error flag 2106 included in the entry.

Therefore, it does not stop sending data to I ² CI / O expander 615 where it is determined not to be connected to the master IC570, the I ² CI / O expander 615 where it is determined not to be connected to the master IC570 Even if an abnormality has occurred, the I ²
When the abnormality of the CI / O expander 615 disappears, the I ² CI / O expander 615
Control can be performed quickly.

  FIG. 26 is a flowchart of slave continuous processing according to the first embodiment of this invention.

The slave continuous process is a process of transmitting light emission control data, which is effect control data, to the I ² CI / O expander 615 connected to the light emitting device, and is executed in the process of step 2508 shown in FIG.

The light emission control data is transmitted from the master IC 570 in the buffer mode. In the buffer mode, the master IC 570 transmits a plurality of bytes of data stored in the output BUF 572 to the I ² CI / O expander 615 for each 1 byte, and each time the transmission is performed, the I ² CI /
The ACK or NACK is received from the O expander 615. When a NACK is received, an interrupt signal is output to the CPU 551 at that time.

However, when an ACK is received, an interrupt signal is output to the CPU 551 only when transmission of all data stored in the output BUF 572 is completed. Master IC 570 is the I ² CI / O expander 6 with unsent data remaining in BUF 572 for output.
When an ACK is received from No. 15, the output BU is not output without outputting an interrupt signal to the CPU 551.
The next data to be transmitted is taken out from F 572 and output to the I ² CI / O expander 615.

That is, in the buffer mode, the master IC 570 transmits I ² CI until all the data stored in the output BUF 572 is transmitted to the I ² CI / O expander 615.
As long as the ACK is continuously received from the / O expander 615, the processing is continued without handing over the processing to the CPU 551.

Returning to FIG. 26, first, the CPU 551 sets 0 in an ACK counter that counts failure in reception of an ACK response signal (2601).

Next, the CPU 551 generates data to be output to the selected decoration control device 610 (2602).

Then, the CPU 551 outputs the data generated in the process of step 2602 to the BUF for output.
The buffer setting process set to 572 is executed (2603). The data to be set is shown in Figure 1
The format of the effect control data shown in FIG. 9 is 1 according to the transmission order shown in the figure.
The data is sent to the I ² CI / O expander 615 while being separated into bytes.

Then, the master IC 570 changes the signal levels of the connection line SDA and the connection line SCL to a signal level indicating the start condition (2604).

Specifically, the master IC 570 outputs a signal indicating a start condition by changing the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH.

After outputting a signal indicating the start condition, the master IC 570 changes the level of the connection line SCL to LOW in order to send data to the decoration control device 610 to be controlled.

Next, CPU 551 starts activation of a buffer mode monitoring timer to monitor the time until master IC 570 transmits an interrupt signal to CPU 551 from the time when master IC 570 is instructed to start data transmission. (2605). Hereinafter, this monitoring time will be referred to as a buffer mode monitoring time.

The master IC 570 then acquires 8-bit data corresponding to the slave address of the decoration control device 610 to be controlled from the beginning of the data set in the output BUF 572, and the value of this address is used as a connection line. Connection line S while changing the signal level of SCL
Output via DA (2606).

Since the address data output in the process of step 2606 is a data string of 8 bits, the address data is output in one output process (output while the connection line SCL changes to HIGH eight times).

When the master IC 570 outputs the slave address, the driver
An operation is performed to turn off the connection 76A and release the connection line SDA (change it to a high level). When the connection line SDA is not released, the output of the slave address waits until the connection line SDA is released.

The address data output in the process of step 2606 is the I ² CI / O expander 61
When it is input to 5, the I ² CI / O expander 615 determines whether or not the input address data matches the address set in itself.

The I ² CI / O expander 615, for which an address matching the input address data is set, is immediately after the eighth number of times that the connection line SCL changes from LOW to HIGH, and The response signal is output from the connection line SDA to the master IC 570 in response to the change of the connection line SCL, which has been set, to the LOW level.

Next, the master IC 570 confirms whether or not an ACK response signal is input to the master IC 570 within a predetermined time after the address data is output in the process of step 2605 (
2607).

Next, based on the confirmation result of the process of step 2606, master IC 570 determines whether or not an ACK response signal is input within a predetermined time after the address data is output in the process of step 2602 (2608). ).

If it is determined in the process of step 2608 that the ACK response signal is not input within a predetermined time after the address data is output in the process of step 2605, the master I
C 570 sets the status REG 579 to the information that the response signal is NACK, and then generates an interrupt signal. This allows the I ² CI / O expander 615 to NA
The CPU 551 is notified that the CK response signal has been received. At this time, the CPU 551
Ends the time monitoring in byte mode (2609).

When the CPU 551 receives the interrupt signal at step 2609, the instructed master IC 570 controls the signal levels of the connection line SDA and the connection line SCL and issues a stop condition to the master IC 570 (2610). Thereafter, it is determined whether or not the ACK counter is equal to or greater than RP (2611).

If it is determined in the process of step 2611 that the ACK counter is smaller than RP, then A
The ACK counter is updated by +1 to count the failure to receive the CK reply signal (2
612), to send the same data again to the decoration controller 610, step 260
Return to processing of 2.

On the other hand, if it is determined in the process of step 2611 that the ACK counter is equal to or greater than RP, the CPU 551 selects the I / O expander address 2101 from the entries registered in the abnormality determination table 2100. Select an entry that matches the address of the 610 I ² CI / O expander 615, and select the error counter 2 for the selected entry.
103 is incremented (2613).

Here, a value of 0 or 2 may be set to RP. When it is determined that the I ² CI / O expander 615 is not connected to the master IC 570, 0 is set to RP,
In the process of step 2611, it is not determined that the ACK counter is smaller than RP.
Therefore, the I ² CI / O expander 6 determined not to be connected to the master IC 570
Even if the data transmission to 15 fails, the data is not retransmitted to the I ² CI / O expander 615.

On the other hand, when it is determined that the I ² CI / O expander 615 is not connected to the master IC 570, 2 is set in the RP, and therefore, retransmission of data to the I ² CI / O expander 615 is maximum. Do it twice.

In this embodiment, when it is determined that the I ² CI / O expander 615 is not connected to the master IC 570, data is not retransmitted to the I ² CI / O expander 615. data retransmissions of data to the I ² CI / O expander 615 where it is determined not to be connected to the master IC570 is, the I ² CI / O expander 615 where it is determined to be connected to the master IC570 The number should be less than the number of retransmissions of

Thus, in the process of FIG. 26, it is determined that I is not connected to master IC 570.
^{2 Since the} number of times of data retransmission to the CI / O expander 615 is smaller than the number of times of data retransmission to the I ² CI / O expander 615 determined to be connected to the master IC 570, the master IC 570 And the I ² CI / O expander 615 can be reduced overall.

After executing the processing of step 2612, the CPU 551 determines whether the value of the error counter 2103 incremented in the processing of step 2612 has reached the comparison value 2104 (2614).

If it is determined in the process of step 2614 that the value of the error counter 2103 incremented in the process of step 2613 has reached the comparison value 2104, the CPU 551:
The decoration control device 610 selected from the entries registered in the abnormality determination table 2100
The error flag of the entry is set to ON (2615), and the slave continuous output processing is ended.

On the other hand, if it is determined in the process of step 2613 that the value of the error counter 2103 incremented in the process of step 2613 does not reach the comparison value 2104, the slave continuous output process is ended.

On the other hand, within the predetermined time after the address data is output in the process of step 2602, the AC
If it is determined in the process of step 2608 that the response signal of K is input, the master I
The C 570 determines whether all the data stored in the output BUF 572 has been output (2616).

If it is determined in the process of step 2616 that all the data stored in output BUF 572 has been output, master IC 570 sets in status REG 579 information indicating that the response signal is ACK. , Generate an interrupt signal. This makes I ²
Having completed the transmission of all byte data to CI / O expander 615, CPU 551
Will be notified. At this time, the CPU 551 ends the monitoring of the buffer mode time (26
19).

Then, after execution of the processing of step 2619, the CPU 551 determines the abnormality determination table 21.
Among the entries registered in 00, select the entry that matches the address of the I ² CI / O expander 615 of the decoration control device 610 where the I / O expander address 2101 is selected, and the error counter of the selected entry 2103 is initialized to zero (2620), the error flag 2105 of the entry is set to off (2621), and the slave continuous output processing is ended.

On the other hand, when it is determined in the process of step 2616 that not all the data stored in output BUF 572 is output, master IC 570 monitors the voltage level of connection line SDA, and connection line SDA After confirming that it is released (2617), it transmits one byte of data to be transmitted next among the data stored in the output BUF 572 (26
18) Go to the processing of step 2607.

As described above, the light emission control data is monitored to receive the reply signal every time 1 byte of data is output (that is, while the light emission control data is transmitted), but the master IC 570 is
As long as the CK response signal is input, all data stored in the output BUF 572 is transmitted in a buffer mode in which processing is not handed over from the master IC 570 to the CPU 551 until transmission is completed.

Here, the initialization instruction data including the common address is transmitted in the byte mode, and as shown in FIG. 24, each time one byte of data transmission is started, the master IC 57 is used each time.
The time from 0 to the return of the interrupt signal to the CPU 551 (byte mode monitoring time) is monitored.

On the other hand, the light emission control data including the slave address serving as the individual address is transmitted in the buffer mode, and as shown in FIG. 26, from the start of data transmission of the first byte stored in the output BUF 572 to the final byte The time until the end of data transmission (buffer mode monitoring time) is monitored.

In the present embodiment, when data is transmitted from the effect control device 550 to the decoration control device 610, either the byte mode or the buffer mode described above is selected. Here, the features of the byte mode and the buffer mode will be described.

In the byte mode, an interrupt signal is immediately transmitted from the master IC 570 to the CPU 551 regardless of any response signal (both ACK and NACK) input from the decoration control device 610 to 1-byte data transmitted from the master IC 570. Ru. At this time, as the byte mode monitoring time, a time value is set in accordance with the time required to transmit one byte of data and receive a reply signal.

When a response signal of ACK is transmitted from the decoration control device 610 to the master IC 570, the CPU 551 determines that 1-byte data transmission has succeeded, and performs the following processing. While
The CPU 551 determines that an error has occurred in data transmission when the NACK response signal is transmitted from the decoration control device 610 to the master IC 570, or when the byte mode monitoring time has timed out, and the necessary processing is performed. I do.

On the other hand, in the buffer mode, an interrupt signal is sent immediately from the master IC 570 to the CPU 551 only when the NACK response signal is input from the decoration control device 610 to the 1-byte data transmitted from the master IC 570. It is transmitted. However, when the response signal of ACK is input from the decoration control device 610, the interrupt signal is output from the master IC 570 if it is not the timing when all the data stored in the output BUF 572 is transmitted.
The master IC 570 transmits the data stored in the output BUF 572 one after another without being transmitted to the PU 551.

Therefore, in the data transmission in the buffer mode, the number of times the interrupt signal is transmitted from the master IC 570 to the CPU 551 is smaller than that in the byte mode, so the number of times of transfer of processing from the master IC 570 to the CPU 551 is reduced. It is possible to reduce the overall transmission time when transmitting byte data.

On the other hand, in the buffer mode, as long as the response signal of ACK continues to be input from decoration control device 610, until all the data to be transmitted has been completely transmitted,
Processing is not delivered to PU551. Therefore, during data transmission, if a state where data transmission can not be performed using connection line SDA occurs for any reason, master IC 570
May interrupt the data transmission, and the time taken for the processing to be handed over from the master IC 570 to the CPU 551 may become very long.

In addition, in order to monitor the time until the process is handed over from the master IC 570 to the CPU 551, the above-mentioned buffer mode monitoring time has a time value matched to the time required for data transmission of all bytes to be transmitted and reception of the reply signal. It is set. Inevitably, this buffer mode monitoring time is set to be longer than the aforementioned byte mode monitoring time.

When a response signal of ACK is transmitted from the decoration control device 610 to the master IC 570, the CPU 551 determines that data transmission of all the bytes to be transmitted has succeeded, and performs the following processing. On the other hand, when the NACK response signal is transmitted from decoration control device 610 to master IC 570, or when the buffer mode monitoring time has timed out, CPU 551:
It is determined that an error has occurred in data transmission, and necessary processing is performed.

From the above, if it is premised that no abnormality occurs in data transmission, multi-byte data (the data will inevitably be data with a bit number longer than 8 bits which is the transmission unit)
In the case of transmitting data, it is true that data transmission using buffer mode can perform processing faster than data transmission using byte mode. However, in consideration of the possibility of occurrence of an abnormality at the time of data transmission, byte mode has the advantage that processing can be performed while confirming completion of data transmission in units of one byte, so which mode is superior is simple It can not be compared to

In this embodiment, the initialization instruction data is transmitted in the byte mode, and the light emission control data is transmitted in the buffer mode, and the effects achieved by such a configuration will be described.

First, in response to the initialization instruction data including the common address, ACK response signals are output from all the decoration control devices 610 to which the common address is previously assigned. On the other hand, for the light emission control data including the individual address, an ACK response signal is output from one decoration control device 610 to which the individual address is previously assigned.

For this reason, when initialization instruction data is transmitted, since a plurality of decoration control devices 610 output response signals, connection line SDA after transmitting 1-byte data of initialization instruction data
The waiting time until the release of the second function depends on the time until all the plurality of decoration control devices 610 release the connection line SDA. On the other hand, the waiting time until the connection line SDA is released after transmitting 1-byte data of the light emission control data is the time until only one decoration control device 610 to be transmitted releases the connection line SDA. It depends on the time. Therefore, the former has a longer waiting time until the connection line SDA is released.

The initialization instruction data is data 2001 of the common address and data 20 of the first predetermined value.
The data is transmitted in three steps such as 02 and second predetermined value data 2003. further,
If the three types of initialization instruction data are not correctly transmitted to decoration control device 610, in order to initialize decoration control device 610 reliably, processing for repeating transmission of initialization instruction data is performed many times. .

Here, the case where the initialization instruction data is transmitted using the buffer mode and the case where the initialization instruction data is transmitted using the byte mode are compared. In each mode, after transmission of the data 2001 of the first common address or transmission of the data 2002 of the first predetermined value next, it is assumed that an abnormal state occurs in which the connection line SDA is not released for any reason. Explain.

When the initialization instruction data is transmitted in the buffer mode, the buffer mode monitoring time starts with the transmission of the data 2001 of the common address and the transmission of the data 2003 of the second predetermined value.
The time required for data transmission of at least 3 bytes must be set until reception of CK. Therefore, when the initialization instruction data is transmitted in the buffer mode, if an abnormality that the connection line SDA is not released occurs, the CPU 551 waits for the buffer mode monitoring time to increase.

On the other hand, if initialization instruction data is sent in byte mode, byte mode monitoring time is
The time required to transmit at least one byte of data must be set. Therefore, when the initialization instruction data is transmitted in the byte mode, if an abnormality that the connection line SDA is not released occurs, the CPU 551 waits for the time-up of the byte mode monitoring time.

Therefore, when the initialization instruction data is transmitted in the buffer mode, if an abnormality that the connection line SDA is not released occurs, the CPU 551 waits for a long time-up time to elapse and then cancels the abnormality. As a result, inefficient data transmission will be performed.

On the other hand, when the initialization instruction data is transmitted in the byte mode, connection line SDA is
Even if an abnormality occurs that is not released, the CPU 551 waits for the elapse of a short time-up time and then cancels the abnormality, so unnecessary time can be suppressed and efficient data transmission can be performed.

Therefore, in the present embodiment, the initialization instruction data is transmitted in the byte mode, so that the abnormality that the connection line SDA is not released can be detected promptly, and as a result, the data transmission time can be shortened.

In particular, as described above, since initialization instruction data is transmitted to a plurality of decoration control devices 610 and it is monitored that all the reply signals are output from these decoration control devices 610, connection line SDA is released. It is preferable to perform time monitoring using the byte mode, since the waiting time tends to be long and the monitoring time itself needs to be set longer.

On the other hand, in the present embodiment, the light emission control data is transmitted in the buffer mode. This is because, as described above, in data transmission in buffer mode, as compared with byte mode,
Since the number of times the interrupt signal is transmitted from the master IC 570 to the CPU 551 is reduced, the number of times of transfer of processing from the master IC 570 to the CPU 551 is reduced, thereby shortening the overall transmission time when transmitting multiple bytes of data. It is because it can.

In addition, the light emission control data is transmitted in the buffer mode, and for some reason, the connection line SD
When an abnormal state in which A is not released occurs, the abnormal state is canceled after the buffer mode monitoring time is up and the light emission control data is retransmitted to the decoration control device 610 only once. If transmission abnormality of the light emission control data occurs twice in a row, the transmission of the light emission control data is stopped.

Therefore, in the case of transmitting the light emission control data, the number of times the interrupt signal is output can be reduced by reducing the time required to detect an abnormality that the connection line SDA is not released.
Since the data transmission time can be shortened by reducing the processing load on the PU 551, the light emission control data is transmitted in a buffer mode in which the number of times the interrupt signal is output is smaller than that in the byte mode.

Also, as shown in FIG. 24, in the initialization instruction data, when the connection line SDA is not released and a timeout occurs, or a response signal for 1 byte data is the master IC5.
If it is not input to 70, re-transmission is performed from the first data (data 2001 including the common address) of the initialization instruction data, and the initialization instruction data is the I ² CI / O expander 6
Since the retransmitted until received is repeatedly performed by 15, since the initialization command data is correctly received I ² CI / O expander 615 can be accurately initialize the I ² CI / O expander 615 . Further, as shown in FIG. 26, in the light emission control data, light emission occurs when the connection line SDA is not released and a time-out occurs, or when a reply signal to 1 byte data is not input to the master IC 570. Since retransmission is performed only once from the first data of control data, high-speed data transmission becomes possible.

Since initialization of the I ² CI / O expander 615 is a process performed to eliminate the abnormality that has occurred at the time of abnormality occurrence, the initialization instruction data is I ² so that the initialization is surely performed.
Retransmission is repeated until it is received by the CI / O expander 615 reliably. On the other hand, even if the light emission control data is not received by the I ² CI / O expander 615, the output mode of the light emitting device is only stopped in the previous output mode, so the high speed of data transmission is emphasized. It is designed to retransmit only once.

FIG. 27 is a flowchart of I ² C occasional reset processing according to the first embodiment of this invention.

I ² C occasional reset processing, master IC 570, character product drive MOT 561, master IC 5
All I ² CI / O Expanders 615 connected to 70, and Feature Drive SOL 560
Is a process of instructing initialization of the process, and is a process of step 2210 shown in FIG.

First, the effect control device 550 determines whether the reset request flag is on (2
701).

If it is determined in the process of step 2701 that the reset request flag is not on, the effect control device 550 refers to the abnormality determination table 2100 to determine whether the condition for instructing reset is established. Whether an ACK response signal could not be received continuously a predetermined number of times from all the I ² CI / O expanders 615 to which the decoration device is connected among the I ² CI / O expanders 615 connected to the master IC 570 Check (2702).

Specifically, the effect control device 550 determines whether ON is registered in the error flags 2105 of all the entries registered in the abnormality determination table 2100.

Next, the effect control device 550 determines whether the reset condition is satisfied based on the confirmation result of the process of step 2702 (2703).

Specifically, when all the error flags 2105 are ON at the time of the process of step 2702 (when there is no light emission control device in which the error flag 2105 is OFF), the process of step 2703 is performed. It is considered that the reset condition is satisfied. Otherwise, it is considered that the reset condition is not satisfied in the process of step 2703.

If it is determined in the processing of step 2703 that the reset condition is satisfied, the effect control device 550 sets a reset request flag indicating that initialization is in progress (2704).

Then, the effect control device 550 performs soft reset on the master IC 570 (2705).
. Specifically, the CPU 551 writes a predetermined value to the reset REG 573 provided in the master IC 570 via the data bus. When a predetermined value is written to reset REG 573 provided in master IC 570, the controller of master IC 570 inputs BUF 571 for input,
The values of the output BUF 572, reset REG 573, and transmission mode REG 574 are set to initial values, and the master IC 570 is initialized. The CPU 551 receives the master I via the data bus
By writing a predetermined value to the reset REG 573 provided in C570, the master IC
Initializing the 570 is called soft reset.

In the present embodiment, when the master IC 570 is hard reset, as described above, other circuits (circuits initialized at power on such as the VDP 556 and the sound LSI 557) provided in the effect control device 550 are also initialized. If it is determined that an abnormality has occurred in master IC 570, such soft reset is performed to reset only the master IC in which the abnormality has occurred, and even to a circuit not directly related to master IC 570. Prevent reset.

Next, the effect control device 550 controls all the decoration control devices 6 connected to the master IC 570.
In order to initialize the 10 I ² CI / O expanders 615, a slave reset process shown in FIG. 24 is executed to output a reset signal from the master IC 570 (2706).

In this manner, when the master IC 570 is initialized, initialization instruction data is transmitted to all the I ² CI / O expanders 615 connected to the master IC 570, so that the gaming machine 1 can be reliably initialized. can do.

Then, the effect control device 550 sets a motor initialization flag indicating that the accessory drive MOT 561 is being initialized (2707), and is output to the accessory drive MOT 561 when initializing the accessory drive MOT 561 Set motor output data to RAM 553 (2708)
. Then, in order to initialize the bonus drive SOL 560, the effect control device 550 sets, in the RAM 553, off data for switching the energized state of the bonus drive SOL 560 into the non-energized state (270
9) The reset request flag is released (2710), and the I ² C arbitrary reset processing is ended.

If it is determined in the process of step 2701 that the reset request flag is set, the initialization must be performed immediately, so it is not determined whether the reset condition is satisfied or not. Proceed to processing of 2705.

If it is determined in the process of step 2704 that the reset condition is not satisfied,
Since it is not necessary to perform initialization, the process proceeds to step 2710, the reset request flag is released, and the I ² C arbitrary reset process is ended.

As described above, when it is determined that the reset condition is satisfied, the process of step 2706 is performed on all the I ² CI / O expanders 615 connected to the master IC 570.
Since initialization is simultaneously instructed, in other words, all the I ² CI / O expanders 615
Since the I ² CI / O expander 615 can be individually selected to instruct initialization since initialization can be performed simultaneously by selecting L ² simultaneously, the I ² CI can be initialized at a high speed.
The / O expander 615 can be quickly returned to the normal state.

Note that the RESET terminal (see FIG. 7) input to all the I ² CI / O expanders 615 is electrically connected to the CPU 551, and all the I ² CI / Os are simultaneously transmitted from the CPU 551.
Even when the reset signal is transmitted to the RESET terminal of expander 615, all I
It is possible to simultaneously select and initialize the ² CI / O expander 615.

If it is determined in step 2702 that the reset condition is satisfied, the master IC 5 is
Since it is conceivable that an abnormality occurs at 70, the master IC 570 is also initialized in the process of step 2705.

Master IC 570 receives connection line SDA and connection line SC according to a command from CPU 551.
Since it functions as a signal level control means for controlling the signal level of L, when an abnormality related to data transmission occurs in all the light emission control devices, an abnormality may also occur in the master IC 570 itself. Conceivable.

Therefore, when an abnormality related to data transmission occurs in all the decoration control devices 610, the master IC 570 is initialized by the CPU 551 (calculation processing means) just in case. Thus, even when an abnormality occurs in master IC 570, master IC 570 can be reliably controlled.

Further, as shown in FIG. 22, in synchronization with the cycle of updating the image of the display device 53, and transmits the light emission control data from the master IC570 of the effect control device 550 to the I ² CI / O expander 615, I ² CI Since the / O expander 615 controls the light emitting device based on the received light emission control, the effect on the display device 53 and the effect on the light emitting device are harmonized and the player does not feel discomfort, so the interest can be enhanced. .

In addition, whenever the light emission control data transmitted from the master IC 570 is received by the decoration control device 610 in synchronization with the cycle of updating the image of the display device 53, the I ² CI / O expander 615 The value is updated. Therefore, since the value of the work register is updated to the latest state every time, even if the value of the work register is destroyed due to noise or the like, it is possible to return to the normal value.

Moreover, since the error determination process is performed in synchronization with the cycle of updating the image of the display device 53, the execution frequency of the error determination can be made appropriate, that is, the execution frequency of the error determination process is too high (per unit time If the number of executions is too high), the processing load of the CPU 551 of the effect control device 550 will increase, and conversely, if the frequency of execution of the error judgment processing is too low (the number of executions per unit time is too low), an abnormality will occur. Since the occurrence can not be properly detected, it is possible to prevent the processing failure by performing the error determination with an appropriate frequency.

FIG. 28 is a flowchart of timer interrupt processing executed when a timer interrupt occurs according to the first embodiment of this invention.

The timer interrupt is executed in a form of interrupting the process shown in FIG. 22 when the CPU 551 receives a timer interrupt that occurs in a 2 ms cycle under the condition that the timer interrupt is permitted.

The timer interrupt process is a process of outputting control data to the I ² CI / O expander 615 (movable control device) connected to the product driven MOT 561 and the product driven SOL 560 (movable object) to control the movable object. is there.

First, the effect control device 550 determines whether a reset request flag is set (2801).

If it is determined in the process of step 2801 that the reset request flag is set, it is in a state of waiting for the reset process of the decoration control device 600 including the movable control device to start, so the timer allocation is Finish the loading process.

On the other hand, if it is determined in the process of step 2801 that the reset request flag is not set, the movable control device to be controlled is selected (2802), and to the movable control device selected in the process of step 2802 A slave single output process of transmitting movable control data which is effect control data is executed (2803). The slave single output processing will be described in detail with reference to FIG.

Next, the effect control device 550 determines whether the slave single output processing executed in the processing of step 2803 has ended normally (2804). In slave single output processing, the first data output to the movable control device selected in the processing of step 2802 fails, and two more
If the second data output also fails, it terminates abnormally.

If it is determined in the process of step 2804 that the slave single-shot output process has not ended normally, that is, if it is determined that the slave single-shot output process has ended abnormally, the effect control device 550 determines A motor initialization flag indicating that initialization is in progress is set (2805), and a reset request flag is set to start reset processing of the decoration control device 600 (2806).

Then, the effect control device 550 sets, in the RAM 553, motor output data to be output to the movable control device when initializing the product drive MOT 561 (2807), and the product drive SOL
The off data, which is output to the movable control device when initializing 560, is set in the RAM 553 to turn off the conductive state of the accessory driving SOL 560 (2808), and ends the timer interrupt process.

On the other hand, when it is determined in the processing of step 2804 that the slave single output processing has ended normally, the motor initialization flag is set in order to determine whether or not initialization of the bonus drive MOT 561 is to be performed. It is determined whether or not there is (2809).

If it is determined in the process of step 2809 that the motor initialization flag is set, it is determined whether or not the motor position detection sensor 510 detects that the rotation axis of the bonus drive MOT 561 has returned to the initial position. The determination (2810).

If it is determined in the process of step 2810 that the motor position detection sensor 510 does not detect that the rotary shaft of the accessory driving MOT 561 has returned to the initial position, the process proceeds to step 2807 to initialize the accessory driving MOT 561 The motor output data to be output to the movable control device is set in the RAM 553 in the case of conversion.

On the other hand, in the process of step 2810, the motor position detection sensor 510 is operated as the bonus drive MOT 56.
If it is determined that it has detected that the rotation axis of 1 has returned to the initial position, the feature drive MOT 561
In order to output stop data to stop the rotation of the motor to the movable control device, it is set in the RAM 553 (2811), and initialization of the product drive MOT 561 is completed, so the motor initialization flag is cleared (2812). Finish the loading process.

If it is determined in the process of step 2809 that the motor initialization flag is not set, the effect control device 550 determines whether or not an operation abnormality is detected in the bonus drive MOT 561 (2813).

If it is determined in the process of step 2813 that the accessory driving MOT 561 detects an operation abnormality, the process proceeds to step 2805 to initialize the bonus driving MOT 561.

On the other hand, if it is determined in the process of step 2813 that no operation abnormality is detected in the accessory driving MOT 561, the effect control device 550 controls the rotation axis of the accessory driving MOT 561 to rotate to the target value. In order to output data to the movable control device, in order to output data to the movable control device, in order to output data to the movable control device (2814) and to output solenoid output data indicating whether the accessory drive SOL 560 is to be energized or de-energized, Set in the RAM 553
5) End the timer interrupt process.

  FIG. 29 is a flowchart of slave single output processing of the first embodiment of the present invention.

The slave single-shot output process is a process of transmitting movable control data to the movable control device, as shown in FIG.
It is executed in the process of step 2803 shown in FIG.

The movable control data is transmitted from the master IC 570 in a byte mode. In byte mode, the master IC570, every time one byte transmit data to I ² CI / O expander 615 receives the ACK or NACK from the I ² CI / O expander 615, ACK and N
The interrupt signal is output to the CPU 551 regardless of which of the ACKs is received. That is, when it is completed to transmit 1-byte data from the master IC 570 to the I ² CI / O expander 615, the master IC 570 to the CPU 551 are always required regardless of ACK / NACK reception.
Interrupt signal is output.

First, the CPU 551 sets 0 in an ACK counter that counts the failure to receive an ACK response signal (2901).

Then, the master IC 570 changes the signal levels of the connection line SDA and the connection line SCL to a signal level indicating the start condition (2902).

Specifically, the master IC 570 outputs a signal indicating a start condition by changing the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH.

After outputting a signal indicating the start condition, the master IC 570 changes the level of the connection line SCL to LOW in order to send data to the decoration control device 610 to be controlled.

Next, the CPU 551 sets the address data of the movable control device selected as the transmission target in the output BUF 572 (2903).

Then, from the time when the CPU 551 instructs the master IC 570 to start data transmission,
In order to monitor the time until master IC 570 transmits an interrupt signal to CPU 551,
The start of the monitoring timer for the byte mode is started (2904).

The CPU 551 causes the master IC 570 to output a stop condition to interrupt data transmission when no interrupt signal is received even if a predetermined time has elapsed since the start of monitoring of the byte mode time (2912) Then, add 1 to the value of the ACK counter, return to the process of step 2902, send the start condition to the master IC 570 again, and then transmit the movable control data from the first data (address of the movable control device) . However, if the value of the ACK counter is a predetermined value (for example, "1") at the time of step 2913,
End the process.

Then, CPU 551 outputs to master IC 57 a command to transmit the address data set in output BUF 572 in the processing of step 2902. When master IC 570 receives the command, it is set to output BUF 572 in the processing of step 2902. Address data, while changing the signal level of connection line SCL, via I ² CI via connection line SDA
It transmits to the / O expander 615 (2905). When outputting the address data, master IC 570 temporarily turns off driver 576A to release connection line SDA (change it to a high level). Then, when the connection line SDA is not released (when the connection line SDA is not changed to the high level and maintained at the low level even when the driver 576A is turned off), the output of this address data is connected Wait until line SDA is released (connection line SDA goes high).

Since the address data output in the process of step 2905 is a data string of 8 bits, the address data is output in one output process (output while the connection line SCL changes to HIGH eight times).

The address data output in the process of step 2905 is the I ² CI / O expander 61
When it is input to 5, the I ² CI / O expander 615 determines whether or not the input address data matches the address set in itself.

The I ² CI / O expander 615, for which an address matching the input address data is set, is immediately after the eighth number of times that the connection line SCL changes from LOW to HIGH, and The response signal is output from the connection line SDA to the master IC 570 in response to the change of the connection line SCL, which has been set, to the LOW level.

Next, the master IC 570 determines whether an ACK response signal is input to the master IC 570 within a predetermined time (a monitoring time shorter than the above-described byte mode monitoring time) after completion of data output for one byte. Check (2906).

Next, the master IC 570 determines whether or not an ACK response signal is input within a predetermined time after the address data is output in the process of step 2905 based on the confirmation result of the process of step 2906 (2907). ).

If it is determined in the process of step 2907 that the ACK response signal is not input within a predetermined time after the address data is output in the process of step 2905, the master I
C 570 sets the status REG 579 to the information that the response signal is NACK, and then generates an interrupt signal. This allows the I ² CI / O expander 615 to NA
The CPU 551 is notified that the CK response signal has been received. At this time, the CPU 551
Ends the time monitoring of the byte mode (2911).

Subsequently, the CPU 551 causes the master IC 570 to output a stop condition to interrupt data transmission (2912), and determines whether the ACK counter has a predetermined value (291).
3).

If it is determined in the process of step 2912 that the ACK counter has a predetermined value, the slave single output process ends abnormally.

On the other hand, when it is determined in the process of step 2913 that the ACK counter is not the predetermined value,
The ACK counter is incremented, and the process returns to step 2902 and the master IC 5 is again processed.
After the start condition is output to 70, the same movable control data is output again (re-output from the address of the movable control device).

On the other hand, if it is determined in the process of step 2907 that the response signal of ACK is input within a predetermined time after completion of data output for one byte in the process of step 2905, master IC 570 responds to status REG579. An interrupt signal is generated after setting information indicating that the signal is an ACK. Thus, the I ² CI / O expander 615 to A
The CPU 551 is notified that the CK response signal has been received. At this time, the CPU 551
Ends the time monitoring in byte mode (2908).

Next, the CPU 551 determines whether or not all data to be output to the movable control device has been output (2909).

If it is determined in the process of step 2909 that all data to be output to the movable control device is output, the signal levels of the connection line SDA and the connection line SCL are changed to the signal level indicating the stop condition (2910), The slave single output processing ends normally.

On the other hand, if it is determined in the process of step 2909 that the data to be output to the movable control device has not been output yet, the CPU 551 sets the next 1 byte of data to be output to the movable control device to the output BUF 572 Set (2915).

Next, CPU 551 starts starting the monitoring timer for the byte mode in order to monitor the time until master IC 570 transmits an interrupt signal to CPU 551 from the time when master IC 570 is instructed to start data transmission. (2916).

Monitoring of time (byte mode time) from transmission of 1-byte data to issuance of an interrupt for notifying whether or not a reply signal which is an ACK to the 1-byte data is input from master IC 570 Start (2916).

As described above, when the CPU 551 does not receive an interrupt signal even if a predetermined time has elapsed since the start of monitoring of the byte mode time, the master IC 570 is given a stop condition to interrupt data transmission. Then, the value of the ACK counter is incremented by one, and the process returns to the processing of step 2902. After the start condition is output to the master IC 570 again, the movable control data is used as the first data (of the movable controller Send from address).
However, if the value of the ACK counter is a predetermined value at the time of step 2913, then
End the process.

Next, the master IC 570 monitors the voltage level of the connection line SDA and confirms that the connection line SDA is released (2917), and then outputs 1 byte of data set in the output BUF 572 ( 2918), Go to the processing of step 2906. In the process of step 2917, since the connection line SDA is occupied by the reply signal until the output of the reply signal from the group unit controller is completed, the master IC 570 outputs the reply signal from the group unit controller. It is processing to end and wait until the connection line SDA is released. I ² C
Thereafter, the movable control data is sequentially transmitted, and when the transmission of all the movable control data is completed, the processing of step 2910 is performed and the processing ends normally as described above.

The order of the movable movement control data to be transmitted is in the format shown in FIG. 19 as in the case of the light emission control data, but since the movable movement control data is transmitted in the byte mode, all the data in the format shown in FIG. Instead of setting the output BUF 572 at a time, data is transmitted while being divided into 1 byte each from the head and set in the output BUF 572. Therefore, all the data in the format shown in FIG. 19 (including control data of the motor and the solenoid) is temporarily stored in the RAM 553.

Thus, the product driving MOT 561 and the product driving SOL controlled by the I ² C movable control device
In 560, if the movable control data is output in synchronization with the VDP interrupt (about 33.3 ms cycle), it is not possible to control the movable member according to the effect, so the timer interrupt (2 ms) whose cycle is shorter than the VDP interrupt The movement control data is output in synchronization with the cycle). As a result, it is possible to produce effects by the movable members adapted to the gaming state.

The movable control data is transmitted in byte mode as shown in FIG. this is,
If an abnormality occurs in which the connection line SDA is not released, the mobile control device can not be controlled,
Since there is a possibility that the movable member can be moved beyond the movable range of the movable member set in advance by the bonus drive MOT 561, the time-up monitoring of a short time by the byte mode monitoring time is performed and the connection line SDA is released. It is for immediately detecting an abnormal condition.

In the processing according to FIGS. 26 and 29, after outputting 8-bit data, master IC 570 determines the success or failure of data transfer by taking in the response signal from decoration control device 610, and data transfer fails. In this case (that is, when the NACK response signal is input to the master IC 570), the output data is output again only once, so that data can be output to the decoration control device 610 as reliably as possible. Malfunction of can be prevented.

When master IC 570 transmits the start condition, connection line SDA needs to be HIGH, but there is a state where connection line SDA does not change with LOW due to the influence of noise or the like. There is.

In this embodiment, the slave address transmitted by the master IC 570 to the I ² CI / O expander 615 of the decoration control device 610 is only one whose R / W identification data is “0” (meaning writing). (See Figure 11), but due to the effects of noise etc
It may be transmitted to the I ² CI / O expander 615 with the / W identification data being “1” (meaning reading).

In this case, the I ² CI / O expander 615 is in the read mode and the master IC 57
In response to the change of the signal level of the connection line SCL due to 0, processing of transmitting data bit by bit via the connection line SDA from the I ² CI / O expander 615 to the master IC 570 is performed.

At this time, every time the I ² CI / O expander 615 transmits 8-bit data,
An acknowledge signal is received from master IC 570 via connection line SDA, and when the acknowledge signal is received, data transmission of 8 more bits is performed, and thereafter, the data transmission of 8 bits and confirmation of the acknowledge signal are repeated. The connection line SDA is I ² CI
/ O expander 615 is in a state of exclusive use.

On the other hand, the I ² CI / O expander 615 is a master IC after data transmission of 8 bits.
If the acknowledge signal can not be received from 570 through connection line SDA, connection line SDA
To release data transmission. The I ² CI / O expander 615 is a master I
When an acknowledge signal is received from C570 via connection line SDA, it is interpreted that an acknowledge signal is received if connection line SDA is at a LOW level, and that an acknowledge signal is not received if connection line SDA is at a HIGH level. Interpret.

Therefore, when the data from the master IC 570 changes due to the influence of noise etc. and the I ² CI / O expander 615 which receives the changed data freely and becomes the read mode is generated, the connection line SDA becomes It will not be released forever.

In such a case, the signal level of the connection line SDA remains LOW, and the master IC 570 and the I ² CI / O of the decoration control device 610 originally intended to perform transmission.
Communication with the expander 615 can not be performed via the connection line SDA.

Therefore, before the master IC 570 outputs a signal indicating the start condition, the connection line SDA is
It is determined whether the signal level of the connection line SDA is HIGH or not in order to determine whether or not the data can be output.

If it is determined that the signal level of the connection line SDA is not HIGH, data can not be output from the connection line SDA, and the driver 576A does not apply an operable voltage to the transistor 578A without turning on the transistor 578A (connection line Change the signal level of connection SCL at least nine times with SDA released).

By performing such processing, the I ² CI / O expander 61 that has become the read mode
5 outputs data to the connection line SDA in accordance with the change of the signal level of the connection SCL, but the master IC 570 is in the middle of at least nine times of the change of the signal level of the connection SCL being performed.
Timing to confirm the acknowledge signal from At this time, since the connection line SDA is released, it becomes high level, and the I ² CI / O expander 615 in the read mode determines that the acknowledge signal has not been received, so data transmission is stopped and the connection line SDA It will be released.

This process is not only performed before the signal indicating the start condition is output, but also the master IC 57.
0 may be performed before outputting actual data to the decoration control device 610.

In this manner, since the connection line SDA is forcibly released from the I ² CI / O expander 615 of the decoration control device 610 in the read mode, the signal level of the connection line SDA is H.
Be maintained in IGH.

FIG. 30 is a view showing a connection form of the decoration control device 610 provided in the entire game machine according to the first embodiment of the present invention, and in particular, a view for explaining the decoration control device 610 provided in the front frame 3.

The decoration control device 610 is mainly attached to the game board 10 and the front frame 3. The LEDs controlled by the decoration control device 610 attached to the front frame 3 irradiate the decoration member 9, the lighting unit 11, and the abnormality notification LED 29.

The game machine has a plurality of specifications, and the normal version game machine 1 (the first specification game machine) and the low price version game machine 1
(The game machine of the second specification). The normal version game machine 1 is provided with a front frame 3 (a normal version front frame, a first game frame) provided with a decorative member 9 of a standard specification. The low-priced game machine 1 has a front frame 3 (a low-priced front frame, provided with a decorative member 9 'configured at a cost lower than that of the standard specification decorative member 9).
The second game slot is provided.

The number of decoration control devices 610 attached for irradiating the decoration member 9 is different between the normal plate front frame 3 and the inexpensive plate front frame 3. Specifically, the decorative members 9 of the normal plate front frame 3 are irradiated by the four decoration control devices 610, and the decorative members 9 'of the inexpensive plate front frame 3 are irradiated by the two decoration control devices 610. The decorative member 9 is illuminated by at most 60 LEDs, while the decorative member 9 'is illuminated by at most 30 LEDs, so the decorative member 9 is brighter than the decorative member 9'. For this reason, the control of the decoration control device 610 when the normal version front frame 3 is attached and the control of the decoration control device 610 when the low price version front frame 3 is attached are different.

I ² CI / O Expander 61 of Decoration Controller 610 Attached to Normal Version Front Frame 3
If the address of No. 5 and the unique address of the I ² CI / O expander 615 of the decoration control device 610 attached to the low price version front frame 3 are the same, the control is performed when the normal version front frame 3 is attached A presentation control device 550 for the printing plate and a presentation control device 550 for the low-cost printing plate for controlling the case where the low-cost printing frame 3 is attached are prepared corresponding to the front frame 3 to be attached I have to replace 550. Therefore, when the manufacturer ships the gaming machine 1, the effect control device 550 for the normal version and the effect control device 55 for the bargain version
It is necessary to prepare 0, which increases the manufacturing cost.

For this reason, in this embodiment, different addresses are assigned to the individual addresses of the I ² CI / O expander 615 of the decoration control device 610 having different controls in the normal version front frame 3 and the low price version front frame 3. The effect control device 550 can perform control for the normal version and control for the inexpensive version. Thus, the presentation control device 550 for the normal version and the presentation control device 550 for the low price version
There is no need to prepare and manufacturing costs can be reduced.

Specifically, the I ² CI / O expander 6 of the four decoration control devices 610 (first specification dependent group unit control means) connected to the LEDs that irradiate the decorative member 9 of the normal version front frame 3
The 15 unique addresses are "1001", "1010", "1100", and "1101".
Is assigned.

On the other hand, the I ² CI / O expander 615 (second specification dependent group unit control means) of the two decoration control devices 610 connected to the LED irradiating the decoration member 9 ′ of the inexpensive front frame 3
Address different from the unique address of the I ² CI / O expander 615 of the four decoration control devices 610 connected to the LED that irradiates the decoration member 9 of the normal version front frame 3 “1110”
And "1111" are assigned.

And, even in the case of being used for any of the normal version front frame 3 and the low price version front frame 3, the effect control device 550 assigns it to the I ² CI / O expander 615 of the decorative members 9 and 9 ′. Unique addresses “1001”, “1010”, “1100”, “1101”, “
Effect control data including all of 1110 ”and“ 1111 ”is transmitted to the decoration control device 610.

Therefore, since one effect control device 550 capable of performing control for the normal version and control for the low price version can control the decoration control device 610 for the normal version front frame 3 and the decoration control device 610 for the low price version. , Can reduce the manufacturing cost.

In addition, the I ² CI / O expander 615 of the decoration control device 610 connected to the illumination unit 11 that performs the same control with the normal version front frame 3 and the low price version front frame 3 and the LED that emits the abnormality notification LED 29 It is not necessary to make the addresses of the normal version front frame 3 and the low price version front frame 3 different, and the same address is assigned.

In the low price front frame 3, the unique addresses are “1001”, “1010”, and “1100”.
, “1101” will not be used and the I ² CI / O expander 615 will not be used.
Then, the I ² CI / O expander 61 with unique addresses “1110” and “1111”.
5 is not used. Therefore, even if the front frame 3 of any specification, the abnormality determination table 21
At 00 (FIG. 21), there is an I ² CI / O expander 615 which is not connected, but as described above, with the I ² CI / O expander 615 registered in the abnormality determination table 2100 If data transmission / reception with the master IC 570 is performed, there is no problem because it is processed as a normal state.

Second Embodiment
A second embodiment of the present invention will be described with reference to FIGS.

The second embodiment of the present invention is an embodiment in which the effect control device 550 includes a plurality of master ICs 570.

FIG. 31 is an explanatory diagram of connection between a plurality of master ICs 570 and the I ² CI / O expander 615 according to the second embodiment of this invention.

  The presentation control device 550 includes two master ICs 570A and 570B.

To the master IC 570A, seven decoration control devices 610 (relay board 600A and decoration control devices 610A to 610F) for decoration the game board 10 are connected.

Since relay board 600A includes I ² CI / O expander 615, decoration control device 61
It is a type of 0, and is positioned most upstream in the decoration control device 610 attached to the game board 10. In the relay base 600A, decoration control devices 610A to 610C directly connected and decoration control devices 610D to 610F directly connected are connected in parallel.

In master IC 570 B, seven decoration control devices 600 attached to the normal version front frame 3
B and 610G to 610L, or four decoration control devices 600B and 610M to 610O attached to the low price plate front frame 3 are connected.

The decoration control device 600B is the decoration control device 610 positioned most upstream in the decoration control device 610 connected to the master IC 570B regardless of which of the normal version front frame 3 and the low price version front frame 3 is attached to the gaming machine 1 Therefore, it also functions as the relay board 600. For this reason, it is described as a decoration control device 600B.

The decoration control device 600B is an LED that illuminates the lighting unit 11 and the abnormality notification LED 29.
Control. The irradiation mode of the illumination unit 11 and the abnormality notification LED 29 is the same whether the normal plate front frame 3 or the low price plate front frame 3 is used. For this reason, the decoration control device 610B to which the same address is given is attached to the normal plate front frame 3 and the low price plate front frame 3.

When the normal version front frame 3 is attached to the gaming machine 1, the decoration control device 610B is connected to the decoration control devices 610G to 610I connected in series.
J to 610L are connected in parallel. On the other hand, when the low priced front frame 3 is attached to the gaming machine 1, the decoration control devices 610M to 610 connected in series to the decoration control device 600B.
O is connected.

The LEDs that illuminate the decoration member 9 of the normal version front frame 3 are six decoration control devices 610G to 61
It is controlled by 0L. The LEDs that illuminate the decorative member 9 'of the inexpensive front frame 3 are controlled by three decoration control devices 610M-610O.

Therefore, the decorative member 9 is brighter than the decorative member 9 '. For this reason, the control of the decoration control device 610 when the normal version front frame 3 is attached and the control of the decoration control device 610 when the low price version front frame 3 is attached are different.

The address of the I ² CI / O expander 615 of the decoration control device 610 connected to each master IC 570 is given so as to be unique within the connected master IC 570. As described in FIG. 30, the decoration control device 610G connected to the master IC 570B
Different addresses are given to 610L and decoration control devices 610M-610.

The I ² CI / O expander 6 of the decoration control device 610 that controls the LEDs that irradiate the decorative members 9 and 9 'regardless of which of the normal version front frame 3 and the low price version front frame 3 is attached to the game machine 1
The mastering control data is master IC 570 for all unique addresses assigned to 15.
Sent from B.

Therefore, since one effect control device 550 capable of performing control for the normal version and control for the low price version can control the decoration control device 610 for the normal version front frame 3 and the decoration control device 610 for the low price version. , Can reduce the manufacturing cost.

In addition, the I ² CI / O expander 6 of the decoration control device 610 attached to the game board 10
15 is connected to the master IC 570, and the decoration control device 6 attached to the normal version front frame 3
The master IC 570 to which the I ² CI / O expander 615 of the decoration control device 610 attached to the 10 I ² CI / O expander 615 or the inexpensive plate front frame 3 is connected is separated.

This allows the I ² CI / O expander 615 to be controlled by one master IC 570.
There is no limitation of the number of (14 as an upper limit as shown in FIG. 12), and it can be expected to enable a variety of effect control.

Also in this embodiment, the I ² CI / O registered in the abnormality determination table 2100 (see FIG. 32)
I ² CI / O Expander 615 and Master IC 570 of Expander 615
If the data transmission and reception are performed between them, the processing is performed as a normal state, but determination of abnormality,
Also, this embodiment differs from the first embodiment in that the process of initializing the I ² CI / O expander 615 and the master IC 570 is performed independently for each system.

In the present embodiment, as shown in FIG. 32, an abnormality determination table 2100 is prepared for each system. In other words, the abnormality determination table 2100 corresponding to each master IC 570 is stored in the RAM 553 of the effect control device 550.

These abnormality determination tables 2100 will be specifically described. FIG. 32 is an explanatory diagram of the abnormality determination table 2100 according to the second embodiment of this invention.

First abnormality determination table 2100A for determining, for each decoration control device, an abnormality in data transmission and reception performed between master IC 570A and relay board 600A and decoration control devices 610A to 610F
, And the decoration control device 600B attached to the master IC 570B and the normal version game slot 3,
610G to 610L, or the decoration control device 600B attached to the low price version play frame 3, 61
There are two types of tables of a second abnormality determination table 2100B that determines, for each decoration control device, an abnormality in data transmission and reception performed between 0M and 610O.

When it is determined in any of the abnormality determination tables that a data transmission / reception abnormality has occurred for all of the I ² CI / O expanders 615, all the decoration control devices 610 belonging to the abnormality determination table are initialized. At the same time, the corresponding master IC 570 is also initialized. However, the decoration control device 610 and the master IC 570 belonging to another abnormality determination table are not initialized.

For example, in the first abnormality determination table described above, all I ² CI / O expanders 61
If it is determined that a data transmission / reception abnormality has occurred with respect to No. 5, only the master IC 570A, the relay substrate 600A, and the decoration control devices 610A to 610F are initialized, and the other master IC
The 570 B, the decoration control device 600 B, and the decoration control devices 610 G to 610 O are not initialized.

Therefore, even if the master IC 570 in which the data transmission abnormality has occurred and the decoration control device 610 connected to the master IC 570 in which the data transmission abnormality has occurred are in process of initialization, the master IC 570 and the decoration control device 610 have no abnormality. Since the decoration control data can be transmitted and received between them, it is possible to prevent the presentation by the decoration device 620 from being suddenly stopped temporarily during the game.

There are soft reset and hard reset as a method of initializing each master IC 570A, 570B.

In soft reset, one of the master ICs 570A and 570B is initialized by the CPU 551.

Specifically, each master IC 570A, 570B is reset REG 573 (FIG. 4).
See). When the CPU 551 writes a specific value (initialization instruction information) to the reset register 573 via the bus 563, only the master IC 570 including the reset REG 573 to which the specific value is written is initialized. In this case, the reset REG 573 is an initialization instruction information storage area.

In hard reset, N connected to input / output I / F 558 and power on detection circuit 559
When the RESET terminal of each of the master ICs 570A and 570B is connected to the OR gate circuit 590 and the voltage applied to the NOR gate circuit 590 is held low for a predetermined time, RES
The voltage (initialization signal) applied to the ET terminal is also held low for a predetermined time, and all master ICs are
570A and 570B are initialized. In this case, the RESET terminal is an initialization signal input terminal.

The NOR gate circuit 590 is connected to the RESET terminal of all the master ICs 570, and when the voltage applied to the NOR gate circuit 590 is held low for a predetermined time, the voltage applied to the RESET terminals of all the master ICs 570 Also, it goes low for a predetermined time, and is taken into all the master ICs 570 as an initialization signal.

The line connecting the NOR gate circuit 590 and the RESET terminal of the master IC 570 is a line separate from the bus 563 (a signal line not passing through the bus).

In the present embodiment, when the power is turned on, all the master ICs 570 are reset by hard reset.
A, 570 B are initialized, and the corresponding decoration control device 610 is initialized. Then, if it is determined in any of the abnormality determination tables that a data transmission / reception abnormality has occurred for all of the I ² CI / O expanders 615, only the master IC belonging to the abnormality determination table is initially reset by soft reset. And the corresponding decoration control device 610 is initialized, but the other master ICs and decoration control device 610 are not reset.

As described above, when the effect control device 550 is provided with a plurality of master ICs 570, only the master IC in which the abnormality has occurred is reset, so the decoration of the entire gaming machine 1 does not temporarily stop, and the player feels uncomfortable. Can be suppressed. Also, all the master IC 570
If you want to reset at the same time fast, you can reset by hard reset.
Various aspects of the reset process can be implemented.

In the second embodiment, the same processing as that of the first embodiment is performed, but only processing different from that of the first embodiment will be described in detail with reference to FIGS. 33 and 34.

FIG. 33 is a flowchart of an I ² C initial reset process of the second embodiment of the present invention.
In FIG. 33, the same processes as the I ² C initial reset process shown in FIG. 23 carry the same reference numerals, and the description thereof is omitted.

I ² C initial reset process is a process executed when the power is turned, in I ² C initial reset process of the second embodiment transmits an initialization instruction data to the decoration control device 610 which is connected to each master IC570.

Specifically, after all the master ICs 570 are hard reset in the process of step 2302, the CPU 551 selects the first master IC 570A (3301), and is connected to the master IC 570A selected in the process of step 3301. Relay substrate 600A, slave reset processing for transmitting initialization instruction data to the decoration control devices 610A to 610F (2303), and the relay substrate 600A connected to the first master IC 570A and the decoration control devices 610A to 610F are initialized. Turn

Then, the CPU 551 selects the second master IC 570B (3302), and the decoration control device 610G to be connected to the master IC 570B selected in the process of step 3302
A slave reset process for transmitting initialization instruction data to 610L is executed (2303), and the decoration control device 600B connected to the master IC 570B, decoration control devices 610G to 610O
Initialize

FIG. 34 is a flowchart of I ² C occasional reset processing according to the second embodiment of this invention.
In FIG. 34, the same processing as the I ² C occasional reset processing shown in FIG. 27 is denoted by the same reference numeral, and the description will be omitted.

If it is determined that the reset request flag is set in the process of step 2701, or if it is determined that the reset condition is satisfied in the process of step 2703, the CPU 5
51 selects the master IC 570 for which the reset condition is satisfied (3401);
In the processing of 01, a predetermined value is written in the reset REG 573 provided in the master IC 570, and the master IC 570 is soft reset (3402).

Then, the CPU 551 executes a slave reset process of transmitting initialization instruction data to all the decoration control devices 610 connected to the master IC 570 selected in the process of step 3401 (2706).

Next, the CPU 551 determines whether or not the master IC 570 whose reset condition is satisfied is the master IC 570 connected to the movable control device (3403).

When it is determined in the process of step 3403 that the master IC 570 for which the reset condition is satisfied is the master IC 570 connected to the movable control device, the accessory drive MOT 561 and the accessory drive SOL 560 controlled by the movable control device are set to initial positions. Since the initialization process is performed back,
The process proceeds to step 2707.

On the other hand, if it is determined in step 3403 that the master IC 570 for which the reset condition is satisfied is not the master IC 570 connected to the movable control device, the process proceeds to step 2710.

As described above, in the present embodiment, since only the master IC 570 in which the abnormality is detected is soft reset, it is not necessary to initialize the master IC 570 in which the abnormality is not detected. Can be minimized, and the discomfort given to the player can be reduced.

In addition, when the master IC 570 is initialized by hard reset or soft reset, all the decoration control devices 610 connected to the master IC 570 to be initialized are also initialized, so that the abnormality can be reliably resolved.

The embodiment disclosed in this specification is naturally intended to be applicable not only to pachinko machines but also to other gaming machines such as pachislot machines.

Although a pachinko machine that generates a special gaming state corresponding to the result of the variable display game is disclosed as an embodiment, the present invention is not limited to the variable display game, but a special game corresponding to the results of other auxiliary games. It is naturally intended that the gaming machine may generate a state.

For example, the entrance of a specific winning device is opened (the movable member of the specific winning device is activated and the inlet is opened) when the predetermined condition is met, and the gaming ball taken into the winning device is provided inside the winning device. A game in which lottery is performed in which prize area (having a specific prize area and a general prize area) may be used as the auxiliary game. In this case, the special gaming state is generated by the game ball taken into the inside of the winning device winning in the specific winning area.

In addition, as an embodiment, a pachinko machine that generates a special gaming state corresponding to the result of the special figure fluctuation display game is disclosed, but in response to the result of the common drawing fluctuation display game (or Naturally, it is intended that the present invention is applicable even to a pachinko machine that generates a special game state) (due to the result of the display game). For example, even if it is a pachinko machine that generates a special gaming state when the entrance of a specific winning device is opened according to the result of the common view variation display game and the gaming ball taken into the winning device reaches a specific winning region. The invention is applicable.

Moreover, although the structure by which the game control apparatus and the presentation control apparatus were isolate | separated is disclosed as embodiment, the game control apparatus and the presentation control apparatus are unitedly, and one control apparatus is comprised, and Naturally, it is naturally intended that the game control device itself may be configured as a group general control means.

The embodiment disclosed this time is illustrative in all points and not restrictive. Further, the scope of the present invention is indicated not by the description of the invention described above but by the scope of claims, and is intended to include all modifications within the scope of meaning and contents equivalent to the scope of claims.

As described above, the present invention is applicable to a game machine in which the effect control device controls the decoration control device.

1 Game machine 2 Main unit frame (outer frame)
Reference Signs List 3 front frame 4 hinge 10 game board 11 lighting unit 17 effect button 18 glass frame 34 common drawing starting gate 36 ordinary fluctuation winning device 42 special fluctuation winning device 44 general winning opening 45 first starting winning opening 51 center case 52 window 53 display Device 55 Vibration sensor 60 Movable role 500 Game control device 550 Effect control device 560 Feature drive SOL
561 Feature Drive MOT
570 Master IC
573 reset REG
574 Send mode REG
580 Dispensing control device 600 Relay board (decorative control device)
610 decoration control device 620 decoration device 2100 abnormality determination table

Claims (1)

A group for dividing a plurality of effect devices into a plurality of groups and having group unit control means for controlling the effect devices belonging to the divided groups for each group, and collectively controlling each of the group unit control means Integrated control means, and arithmetic processing means for controlling the group integrated control means;
By providing an initialization signal line capable of transmitting an initialization signal between the arithmetic processing means and the group general control means, the arithmetic processing means enables initialization of the group general control means.
A timing signal line for transmitting a timing signal between the group general control means and the group unit control means, a data line for transmitting a data signal, and a power supply line for supplying a power supply voltage to the group unit control means; Connecting by means of a connector including a harness, and enabling transmission of data including a plurality of control data from the group general control means to the group unit control means,
The data transmitted by the group general control means includes address information indicating a predetermined address in the storage area provided in the group unit control means, the plurality of control data, and an address within the range of the storage area. Address update information that can specify the upper limit address and return address when updating the
The group unit control means
When power supply to the group unit control means is started, the group unit control means itself is initialized based on a voltage rise due to the power supply,
While storing the control data transmitted from the group general control means with the address indicated by the address information as a start address, it has a function of sequentially updating the storage destination address each time the control data is stored,
When control data is stored in the storage area indicated by the upper limit address, the address of the storage destination is updated to return to the return address,
A gaming machine characterized in that the group general control means can designate any one of a plurality of address update information different in the upper limit address or the return address as the address update information .

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