JPH0580889A - Unit initialization device for real time processor device - Google Patents

Abstract

PURPOSE:To initialize plural processing units under control simultaneously by outputting prescribed address information from a managing unit in a real time processor device used in a data collection/distribution system. CONSTITUTION:This processor device is the real time processor device consisting of the managing unit 1 and the plural processing units 2. The processing unit 2 consists of a setting device 3 capable of setting a value in common to each processing unit 2, a coincidence detecting part 4 which compares an address signal on a bus 6 with the value of the setting device 3 and outputs a coincidence signal when coincidence is obtained, and a self reset circuit 5 which judges the coincidence signal from the coincidence detecting part 4 and performs the initialization of its own unit and it is make up so that the plural processing units 2 under control can be initialized simultaneously by outputting the same address signal as the value of the setting device 3 from the managing unit 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a real-time processor device used in a data collection / distribution system.

[0002]

2. Description of the Related Art Recent real-time processor devices are
In addition to speeding up, flexibility in system construction is required. As a countermeasure against this, a multi-CPU type device, which can be configured with a single architecture from a small scale to a large scale, is currently being developed, and the acceleration of the speed of a multi-CPU type real-time processor device is being promoted.

In the conventional real-time processor device, the following method is known as a method for the management unit to initialize the subordinate processing unit. As a first method, as shown in FIG. 3, there is a method in which an initialization signal line 33 connected by multi-drop between a management unit 31 and a processing unit 32 under it is installed on a bus 34. As a second method, as shown in FIG. 4, a reset register 35 having a function of performing a self-reset is provided in a register of a subordinate processing unit 32, and the management unit 31 sequentially resets the reset register 35 of each processing unit 32. , There is a method of performing initialization by operating.

[0004]

However, when the real-time processor device is a multi-CPU type real-time processor device having a plurality of management units 31 on the same bus as shown in FIG. According to the conventional method as shown in FIG. 2, it is necessary to provide a plurality of initialization signal lines on the bus 34, the hardware scale of the device increases, and the hardware scale varies depending on the number of management units 31 ( The size of the backboard on which the bus is placed is different), so the system construction lacks flexibility.
For this reason, the method shown in FIG. 4 is generally used. However, according to this method, since it is necessary to operate the reset register 35 for each processing unit 32, a large number of processing units 32 are subordinate thereto. If there is such a problem, there is a problem that the time required for the initialization increases and the speed property of the device deteriorates.

The present invention has been made in consideration of such circumstances, and a plurality of subordinate processing units can be initialized all at once by outputting predetermined address information from the management unit. A unit initialization device for a processor device is provided.

[0006]

FIG. 1 is a structural explanatory view showing the structure of the present invention. As shown in the figure, the present invention is a real-time processor device comprising a management unit 1 and a plurality of processing units 2 connected to the management unit 1 by a bus 6 transmitting an address signal. The setter 3 capable of setting a common value to each processing unit 2 and the coincidence detection unit 4 which compares the address signal on the bus 6 with the value of the setter 3 and outputs a coincidence signal when they coincide.
And a self-resetting circuit 5 for judging the coincidence signal from the coincidence detecting section 4 and initializing the self unit, and the management unit 1 outputs the same address signal as the value of the setter 3 to allow a plurality of subordinate units to operate. Is a unit initialization device for a real-time processor device, wherein the processing units 2 are simultaneously initialized.

[0007]

According to the present invention, when the management unit 1 simultaneously initializes the subordinate processing units 2, the management unit 1 outputs the same address signal as the value of the setter 3 onto the bus 6. As a result, a coincidence signal is simultaneously output from the coincidence detection unit 4 of each of the subordinate processing units 2, the coincidence signal is determined, and the self reset circuit 5 initializes the self unit. Therefore, the management unit 1
Each processing unit 2 can be initialized by one control regardless of the number of processing units 2 under it.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on the embodiments shown in the drawings. The present invention is not limited to this.

FIG. 2 shows a multi C as an embodiment of the present invention.
It is a structure explanatory view which shows the structure of a PU type real-time processor apparatus. In this real-time processor device, the management unit A (1
2) and its subordinate processing units A _1, A _2, A _3, ...
-A _n (13) is connected and further management unit B
(14) and its subordinate processing units B _1, B _2, B _3,
... _Bn (15) is connected. In each processing unit (13), (15), setters A, B (16),
(17), the coincidence detection unit 23, the reset register 21, and the self-reset circuit 22 are provided.

Processing units A _1, A _2, A _3, ... A _n (1
The common value A is stored in the setter A (16) of ₃ ), and the setter B (17) of the processing units B _1, B _2, B _3, ... B _n (15), The common value B is stored.

When the management unit A (12) initializes the processing units A _1, A _2, A _3, ... A _n (13) belonging to it, the management unit A (12) , The same address signal as that of the setter A (16) is sent to the bus (1
1) and outputs the register write signal to the register write signal line (19) of the bus (11). At this time, the processing units A _1, A _2, A _3, ... A _n (1
The match detection unit (23) provided in 3) issues a match detection signal, and this match detection signal is latched in the reset register (21) by a register write signal. When the coincidence detection signal is latched in the reset register (21), the self-reset circuit (22) is activated, and the respective processing units A _1, A _2, A _3, ... A _n (13) are initialized simultaneously. Be converted. When the management unit B (14) initializes the subordinate processing units B _1, B _2, B _3, ... B _n (15), the same operation is performed as described above.

In this way, the management unit (12),
Processing units (13) and (1) subordinate to (14)
By outputting the same address signal as the contents of the setters A, B (16), (17) to 5), the plurality of subordinate processing units (13), (15) are simultaneously initialized. be able to.

[0013]

According to the present invention, the management unit can simultaneously initialize the subordinate processing units without affecting the subordinate processing units of other management units. It is a major contributor to the realization.

[Brief description of drawings]

FIG. 1 is a configuration explanatory view showing a configuration of the present invention.

FIG. 2 is a configuration explanatory diagram showing a configuration of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a configuration of a real-time processor device in which a conventional initialization signal line is installed.

FIG. 4 is a diagram illustrating the configuration of a conventional real-time processor device provided with a reset register.

FIG. 5 is an explanatory diagram of a configuration of a conventional multi-CPU type real-time processor device.

[Explanation of symbols]

11 bus 12 management unit A 13 processing unit A _1, A _2, A _3, ... A _n 14 management unit B 15 processing unit B _1, B _2, B _3, ... B _n 16 setting device A 17 setting Device B 19 Register write signal line 21 Reset register 22 Self-reset circuit 23 Match detection unit

Claims (1)

[Claims] 1. A real-time processor device comprising a management unit (1) and a plurality of processing units (2) connected to the management unit (1) by a bus (6) for transmitting an address signal, the processing unit comprising: Matches when (2) compares the value of the setter (3) capable of setting a common value for each processing unit (2) with the value of the address signal on the bus (6) and the setter (3), and if they match. Match detection unit (4) that outputs a signal, and match detection unit (4)
It consists of a self-reset circuit (5) that determines the coincidence signal from the unit and initializes its own unit, and the management unit (1) outputs the same address signal as the value of the setter (3), so that a plurality of subordinate units can operate. A unit initialization device for a real-time processor device, wherein all the processing units (2) are initialized at the same time.