JP5568731B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine including a plurality of group unit control means for controlling the effect devices divided into groups and a group overall control means for controlling the plurality of group unit control means, and more particularly to an initialization method for the group unit control means.

  As a gaming machine that can simplify the wiring between the sub-relay board and the illumination board, the top LED central board arranged in the center of the top illumination area is serially connected to the sub-relay board, and the top illumination A gaming machine having a configuration in which a top LED right substrate disposed on the right side of the region and a top LED left substrate disposed on the left side of the top illumination region are separated from the top LED central substrate and connected by wiring. . Thereby, the number of wirings from the sub relay board to the top illumination area can be reduced to simplify the wiring (for example, see Patent Document 1).

In addition, as a gaming machine that can reduce the number of signal lines and easily detect fraudulent activities, signal transmission between the main board and the sub board is performed by the I ² C bus method. Some boards and sub-boards are each provided with a bidirectional bus buffer. This bidirectional bus buffer is for bifurcating the two bidirectional serial lines (SDA, SCL) constituting the I ² C bus into two unidirectional serial lines, respectively. The bus buffer and the bidirectional bus buffer provided on the sub-board are connected by four serial lines so that the signal transmission directions of the one-way serial lines branched by them match each other ( For example, see Patent Document 2).

JP 2008-212271 A JP 2006-15036 A

In the game machine described in Patent Document 1, it is impossible to sufficiently reduce wiring.

The present invention aims to provide a game machine capable of reducing the number of connection lines connecting the integrated Batch control means and units of the control unit.

The present invention includes a game control unit for generally controlling the game, a plurality of rendering devices for performing an effect of the game, in response to an instruction from the game control means, presentation control means for controlling said plurality of rendering devices If the provided, dividing said plurality of rendering devices to a plurality of groups, a group-unit control unit for controlling the effect device belonging to the divided groups provided for each group, the performance control unit, before Symbol configured as a group supervisory controlling means for centrally controlling the respective group unit control means, by a data line for transmitting data between a pre-Symbol group overall control unit and the group-unit control unit, before Symbol group supervisory controlling means wherein the enabling data transfer between each group unit control means and the group supervisory controlling means is a signal corresponding to the signal level before Symbol data lines transmitting data level By setting, to Shin sequentially send the data to the group-unit control unit, the group-unit control unit, said common address as a common between each group unit control means, different in each group unit control means to each other Is determined in advance, and the content of the address included in the data transmitted from the group overall control unit is determined, and when it is determined that the address is an individual address addressed to itself, the address is transmitted. If the address is determined to be a common address and the output mode of the effect device is controlled based on the effect control information, and the transmitted data is initialized instruction data And initializing itself based on the initialization instruction data .

According to the present invention, the number of connection lines connecting the overall control unit and the unit control unit can be reduced.

It is explanatory drawing of the game machine of 1st Embodiment of this invention. It is a front view of the game board of a 1st embodiment of the present invention. It is a block diagram which shows the structure of the game machine of 1st Embodiment of this invention. It is a block diagram which shows the structure of the presentation control apparatus of 1st Embodiment of this invention. It is explanatory drawing of the connection of the decoration control apparatus of 1st Embodiment of this invention. It is a block diagram of the decoration control apparatus of 1st Embodiment of this invention. 1 is a block diagram of an I ² CI / O expander according to a first embodiment of this invention. It is a circuit diagram around the I ² CI / O expander of the decoration control device that controls the decoration device of the first embodiment of the present invention. It is a circuit diagram around the I ² CI / O expander of the decoration control device that controls the accessory driving MOT and the accessory driving SOL of the first embodiment of the present invention. It is a circuit diagram of the connection line regarding the input / output of the relay board | substrate of 1st Embodiment of this invention. It is a circuit diagram of the connecting line regarding the input / output of the decoration control apparatus of 1st Embodiment of this invention. It is explanatory drawing of the slave address contained in the data output to the decoration control apparatus from the presentation control apparatus of 1st Embodiment of this invention. It is an explanatory view of I ² CI / O expander address table of the first embodiment of the present invention. It is a diagram for explaining the I ² CI / O Aix work register assigned to the output setting register provided in expander of the first embodiment of the present invention. It is explanatory drawing of the start condition and stop condition of the data which the master IC of 1st Embodiment of this invention outputs via the connection line SDA and the connection line SCL. It is a timing chart which the decoration control apparatus into which the data output from the master IC of 1st Embodiment of this invention was input outputs a reply signal. It is a timing chart of the signal level of the connection line SDA and the connection line SCL when the master IC of the first embodiment of the present invention outputs effect control data. When the master IC according to the first embodiment of the present invention designates the individual address of the slave and sets the effect control data in the decoration control device, it is exchanged between the master IC and the I ² CI / O expander. It is a figure explaining the format of data. When the master IC according to the first embodiment of the present invention designates the individual address of the slave and sets the effect control data in the decoration control device, it is exchanged between the master IC and the I ² CI / O expander. Specific numerical values are applied to the production control data. It is a figure explaining another form of presentation control data of a 1st embodiment of the present invention. FIG master IC of the first embodiment is to initialize the I ² CI / O expander, illustrating the data format of the initialization instruction data transmitted to I ² CI / O expander from the master IC of the present invention It is. It is a figure explaining the abnormality determination table of 1st Embodiment of this invention. It is a flowchart of the process by the presentation control apparatus of 1st Embodiment of this invention. It is a flowchart of the I ² C initial reset process of the first embodiment of the present invention. It is a flowchart of the slave reset process of 1st Embodiment of this invention. It is a flowchart of the light emission control slave output process of 1st Embodiment of this invention. It is a flowchart of the slave continuous processing of 1st Embodiment of this invention. It is a flowchart of an I ² C occasional reset process according to the first embodiment of the present invention. It is a flowchart of the timer interruption process performed when the timer interruption of 1st Embodiment of this invention generate | occur | produces. It is a flowchart of the slave single output process of 1st Embodiment of this invention. It is a figure which shows the connection form of the decoration control apparatus provided in the whole gaming machine of the 1st Embodiment of this invention. It is explanatory drawing of the connection of the presentation control apparatus and decoration control apparatus of 2nd Embodiment of this invention. It is explanatory drawing of the abnormality determination table of 2nd Embodiment of this invention. It is a flowchart of the I2C initial reset process of ^2nd Embodiment of this invention. It is a flowchart of an I ² C occasional reset process of the second embodiment of the present invention. It is a timing chart before and after initialization of the master IC by power-on according to the second embodiment of the present invention. It is a timing chart before and after initialization of the master IC in which the abnormality of the second embodiment of the present invention has occurred.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is an explanatory diagram of the gaming machine 1 according to the first embodiment of the present invention.

  A front frame (game frame) 3 of the gaming machine 1 is assembled to a main body frame (outer frame) 2 via a hinge 4 so as to be openable and closable on the front surface of the gaming machine 1. A game board 10 (see FIG. 2) is accommodated on the front side of the front frame 3. Further, a glass frame 18 having a cover glass (transparent member) covering the front surface of the game board 10 is attached to the front frame 3.

  A decorative member 9 that emits decorative light is provided around the cover glass of the glass frame 18. The decoration member 9 is provided with a decoration device 620 (see FIG. 3) made of a lamp, an LED, or the like. The decoration device 620 emits light in a predetermined light emission mode, so that the decoration member 9 emits light in a predetermined light emission mode.

  Speakers 30 that emit sound (for example, sound effects) are provided on the left and right sides of the glass frame 18. An illumination unit 11 is provided above the glass frame 18. Inside the lighting unit 11, the above-described decoration device 620 is provided.

  On the right side of the lighting unit 11, an abnormality notification LED 29 for notifying that an abnormality has occurred in the gaming machine 1 is provided.

  The open / close panel 20 below the front frame 3 is provided with an upper tray 21 for supplying game balls to a not-shown ball hitting device, and the fixed panel 22 is provided with an ashtray 15, a lower plate 23, an operation unit 24 of the hit ball launching device and the like. . The lower tray 23 is provided with a lower tray ball removing mechanism 16 for discharging the game balls stored in the lower tray 23. A key 25 for locking the glass frame 18 is provided on the lower right side of the front frame 3.

  Further, when the player turns the operation unit 24, the hitting ball launching device launches a game ball supplied from the upper plate 21.

  In addition, the upper edge portion of the upper plate 21 is provided with an effect button 17 for receiving an operation input from the player.

  When the player operates the effect button 17, the effect content of the special figure variation display game on the display device 53 (see FIG. 2) provided on the game board 10 is selected, and the special figure variation display game on the display device 53 is selected. In addition, it is possible to perform an effect in which the player's operation is intervened.

  In addition, in the special figure variation display game, the launched game ball is awarded to the first start winning opening 45 (see FIG. 2) provided in the game board 10 or the second starting winning opening of the normal variation winning apparatus 36 (see FIG. 2). It starts when you do. In the special figure fluctuation display game, a plurality of pieces of identification information are variably displayed on the display device 53. Then, when the identification information that has been variably displayed is stopped and the result mode of the stopped identification information is a specific result mode, the state of the gaming machine 1 is advantageous to the player (a state where a privilege is granted) Transition to a special gaming state.

  In the upper right portion of the upper plate 21, a ball lending button 26 that is operated when a player borrows a game ball and a discharge button 27 that is operated to discharge a prepaid card from a card unit (not shown) are provided. . Between these buttons 26 and 27, a balance display unit 28 for displaying the balance of the prepaid card is provided.

  FIG. 2 is a front view of the game board 10 according to the first embodiment of the present invention.

  The gaming machine 1 shown in FIG. 1 fires a game ball in an internal game area 10a (bounces it) to play a game, and a game area 10a is provided on the back side of the cover glass of the glass frame 18. The game board 10 which comprises is installed.

  The game board 10 includes a flat game board main body 10b (made of wood or synthetic resin) as a mounting base for various members, and has a game area 10a surrounded by a guide rail 32 on the front surface of the game board main body 10b. ing. Further, front structural members 33, 33,... Are attached to the front surface of the game board main body 10b and outside the guide rail 32. Then, a game ball (hit ball; game medium) is launched from the launching device into the game area 10a surrounded by the guide rail 32 to play a game.

  A center case 51 that forms a window 52 serving as a display area for a special figure variation display game is attached to the approximate center of the game area 10a. Behind the window portion 52 formed in the center case 51, a display device 53 is provided as an effect display device capable of executing an effect of a special figure variable display game that displays a plurality of identification information in a variable manner. ing. The display device 53 includes, for example, a liquid crystal display, and is arranged so that a display portion 53 a whose display contents can be changed is visible from the front side of the game board 10 through the window portion 52 of the center case 51. . Note that the display device 53 is not limited to a device including a liquid crystal display, and may include a display such as an EL or a CRT.

  Near the upper end of the window 52 of the center case 51, a movable accessory 60 that can be operated based on the gaming state is attached.

  In addition, the game board 10 is provided with a general map start gate 34, a general map storage display 47 for displaying the number of unprocessed times of the general map change display game, and a general map display 35 for displaying the general map change display game. ing. Further, in the game area 10a, a first start winning opening 45 forming a first start winning area and a normal variable winning apparatus 36 having a second starting winning opening forming a second start winning area are provided. ing. When the game ball has won the first start winning opening 45, the first special figure variation display game is executed as an auxiliary game, and when the game ball has won the normal variation prize winning device 36, the second game is performed as an auxiliary game. A special figure variation display game is executed.

  Further, the game board 10 is provided with a first special figure display 38 for displaying the first special figure fluctuation display game, and a second special figure display 39 for displaying the second special figure fluctuation display game. Yes. In addition, the first special figure storage display 48 for displaying the number of unprocessed times of the first special figure variation display game (first special figure start memory), and the number of unprocessed times of the second special figure fluctuation display game (second special figure). A second special figure memory display 49 for displaying (starting memory) is provided. It should be noted that the common figure memory display 47, the universal figure display 35, the first special figure display 38, the second special figure display 39, the first special figure storage display 48, and the second special figure storage display 49 are: Together with a game state display LED (not shown) representing the game state, it is integrally provided as a segment LED.

  Furthermore, the game area 10a has an attacker-type opening / closing door 42a that can be opened by rotating in a direction in which the upper end side is tilted toward the front side, and the first special figure variation display game and the second special figure variation display game. As a result, the special variable winning device 42 for converting the closed state (a disadvantageous state for the player) from the closed state (a disadvantageous state for the player) to the open state (a state advantageous for the player), and the game balls that have not won the winning point etc. An out-hole 43 to be collected is provided. In addition, the game area 10a is provided with general winning holes 44, 44,..., A windmill 46 as a batting direction changing member, a number of obstacle nails (not shown), and the like.

  A gate SW 34a (see FIG. 3) for detecting a game ball that has passed through the general chart start gate 34 is provided in the general chart start gate 34. Then, when the game ball that has been driven into the game area 10a passes through the usual figure start gate 34, a usual figure change display game is performed.

  In addition, when the game ball passes through the general chart start gate 34 in a state in which the normal map change display game cannot be started, if the general chart start memory number is less than the upper limit number, the general chart start memory number is incremented by one. One random number indicating whether or not the normal figure change display game is a win is stored as the normal figure start memory.

  The state in which the normal map variable display game cannot be started is, for example, a state in which the normal map variable display game has already been executed and the normal map variable display game has not ended, or the normal variable display game has been hit and the normal variable prize winning device This is a state where 36 is converted to an open state.

  In addition, the starting memory | storage number of a common figure change display game is displayed on the common figure memory | storage display 47 provided with LED.

  The normal map display game is executed by a general map display 35 provided on the game board 10. In addition, you may make it display a common figure change display game in a part of display area of the display apparatus 53, In this case, for example, a number, a symbol, a character design etc. are used as an identification design, and this identification design is predetermined. After the time variation display, the display is stopped.

  If the stop display of the normal fluctuation display game becomes a special result mode, the normal fluctuation display game is won and the opening / closing members 36a and 36a of the normal fluctuation winning device 36 are set for a predetermined time (for example, 0.5 seconds). ) Opened. Thereby, it becomes easy to win a game ball in the normal variation winning device 36, and the start of the second special figure variation display game is facilitated.

  The normal variation winning device 36 includes a pair of left and right opening / closing members 36 a and 36 a and is disposed below the first start winning port 45. The open / close members 36a, 36a always maintain a closed state (an unfavorable state for the player) with an interval of about the diameter of the game ball. When it becomes a mode (when a normal fluctuation display game is a win), it is opened in a reverse “C” shape by a solenoid (Fuden SOL 36b, see FIG. 3) as a driving device, and a normal fluctuation prize is won. The device 36 can be changed to a state in which a game ball easily flows into the device 36 (a state advantageous to the player).

  In addition, the gaming machine 1 according to the present embodiment, based on the result form of the special figure variation display game, as a gaming state, a short-time operation state (second operation state) that shortens the variation display time of the special figure variation display game on the display device 53. ) Can be generated. At this time, the short operation state (second operation state) is a state in which the operation state of the normal variation winning device 36 is more likely to be an open state than the normal operation state (first operation state).

  At this time, in the short operation state, the execution time of the above-mentioned general-purpose variable display game is controlled to be shorter than the long execution time in the normal operation state (for example, 10 seconds is 1 second). The number of times of opening of the normal variation winning device 36 is controlled to be substantially increased. Further, in the short-time operation state, when the normal variation winning game 36 is released as a result of the normal variation display game being won, the release time is controlled to be longer than the short release time of the normal operation state. (For example, 0.3 seconds is 1.8 seconds). Also, in the short-time operation state, the normal variation winning device 36 is opened a plurality of times (for example, two times) instead of once for the result of one hit of the normal-variation display game. Further, in the short-time operation state, the probability that the hit result of the normal-variable display game is higher than that in the normal operation state is controlled. That is, the number of times of opening of the normal variation winning device 36 is increased as compared to the normal operation state, and it becomes easier for the game ball to win the normal variation winning device 36, and the second special figure variation display game can be easily started.

  A first start opening SW45a (see FIG. 3) is provided in the first start winning opening 45, and based on detecting a game ball by the first start opening SW45a, a first special figure variation display as an auxiliary game is provided. A starting right to start the game is generated. Further, the normal variation winning device 36 is provided with a second start opening SW36d (see FIG. 3), and based on the detection of the game ball by the second start opening SW36d, the second special figure change as an auxiliary game is performed. A start right to start the display game is generated.

  The right to start the first special figure variation display game is stored as a first start memory (special figure 1 start memory) within a predetermined upper limit number (for example, 4). The first start memory number is displayed on the first special figure memory display 48. The start right for starting the second special figure variation display game is stored as the second start memory (special figure 2 start memory) within a predetermined upper limit number (for example, 4). The second start memory number is displayed on the second special figure memory display 49.

  When the first special figure variation display game can be started (the first start memory number and the second start memory number are 0) and the game ball wins the first start winning opening 45, the start right is generated. The random number extracted with is stored as the first start memory, the first start memory number is incremented by 1, and the first special figure variation display game is immediately started based on the first start memory, At this time, 1 is subtracted from the first start memory number.

  In addition, since the second special figure fluctuation display game is executed in preference to the first special figure fluctuation display game, even if the first start memory number is not zero, if the second start memory number is zero, When the game ball wins the normal variation winning device 36 that forms the second start winning opening, the random number extracted with the start right is stored as the second start memory, and the second start memory number is incremented by one. At the same time, the second special figure variation display game is started based on the second start memory immediately after the execution of the first special figure variation display game being executed, and at this time, the second start memory number is decremented by one.

  On the other hand, a state in which the first special figure fluctuation display game or the second special figure fluctuation display game cannot be started immediately, for example, the first special figure fluctuation display game or the second special figure fluctuation display game has already been performed, and the special figure fluctuation display. If a game ball is won in the first start winning opening 45 when the game is not finished or in a special game state, if the first start memory number is less than the upper limit number (for example, less than four) The first start memory number is incremented by 1, and one random number extracted at the timing when the game ball is won in the first start winning opening 45 is stored as the first start memory.

  Similarly, in this case, when a game ball wins the normal variation winning device 36 that forms the second starting winning opening, if the second starting stored number is less than the upper limit number (for example, less than four), the second starting stored number is 1 is added, and one random number extracted at the timing when the game ball wins the second start winning opening is stored as the second start storage.

  When the first special figure fluctuation display game or the second special figure fluctuation display game is ready to start, the first special figure fluctuation display game or the second special figure fluctuation display is based on the first start memory or the second start memory. The game starts. At this time, the first special figure fluctuation display game and the second special figure fluctuation display game are not executed simultaneously, and the second special figure fluctuation display game is executed with priority over the first special figure fluctuation display game. It is like that.

  That is, when there is a first start memory and a second start memory, the second special figure variation display game is executed.

  The first special figure change display game and the second special figure change display game as the auxiliary game are executed by the first special figure display 38 and the second special figure display 39 provided on the game board 10. After a plurality of pieces of identification information are variably displayed, a predetermined result mode is stopped and displayed. In addition, a special figure fluctuation display game is executed in which a plurality of types of identification information (for example, numbers, symbols, character designs, etc.) are variably displayed on the display device 53 corresponding to each special figure fluctuation display game. And as a result of this special figure fluctuation display game, when the display mode of the first special figure display 38 or the second special figure display 39 becomes a special result mode, it becomes a big hit and a special game state (so-called , Jackpot state). Correspondingly, the display mode of the display device 53 is also a special result mode (for example, any one of the numbers in the flat order such as “7, 7, 7”). The game machine may not be provided with the first special figure display 38 and the second special figure display 39, and the special figure variation display game may be executed only by the display device 53.

  In addition, the gaming machine 1 of the present embodiment can generate a probability variation state (second probability state) as a gaming state based on the result mode of the special figure variation display game. This probability variation state (second probability state) is a state in which the probability of a hit result in the special figure variation display game is higher than the normal probability state (first probability state). It should be noted that the first special figure fluctuation display game and the second special figure fluctuation regardless of whether the first special figure fluctuation display game or the second special figure fluctuation display game results in the result mode of the special figure fluctuation display game. Both display games are in a probable state. Further, the probability variation state and the above-described short-time operation state can be generated independently, and both can be generated simultaneously, or only one can be generated.

  FIG. 3 is a block diagram showing a configuration of the gaming machine 1 according to the first embodiment of the present invention.

  The gaming machine 1 includes a game control device 500 that controls the game in an integrated manner, an effect control device 550 that controls the display device 53 and the speaker 30 to perform various effects, and a payout motor (not shown) for paying out game balls. A payout control device 580 for controlling is provided.

  First, the game control device 500 will be described. In FIG. 4, the effect control device 550 will be described.

  The game control device 500 includes a game microcomputer 501, an input I / F (Interface) 505, an output I / F (Interface) 506, and an external communication terminal 507.

  The gaming microcomputer 501 includes a CPU 502, a ROM (Read Only Memory) 503, and a RAM (Random Access Memory) 504.

  The CPU 502 is a main control device that controls the game in an integrated manner, and controls the game. The ROM 503 stores invariant information (programs, data, etc.) for game control. The RAM 504 is used as a work area during game control.

  The external communication terminal 507 connects the game control device 500 to an external device such as an inspection device that inspects the setting information of the game control device 500.

  The CPU 502 receives various input devices (first start port SW45a, second start port SW36d, general winning port SW44a, gate SW34a, count SW42d, glass frame open SW18a, front frame open SW3a, and out of ball SW54 via the input I / F 505. In response to the detection signals from the vibration sensor 55 and the magnetic sensor 56), various processes such as a big hit lottery are performed.

  The first start port SW 45 a is a switch that detects that a game ball has won the first start winning port 45. The second start port SW 36 d is a switch that detects that a game ball has won a second start winning port of the normal variation winning device 36.

  The general winning openings SWa 44 a to 44 n are switches that detect that a game ball has won the general winning opening 44. The gate SW 34a is a switch that detects that a game ball has passed through the usual start gate 34.

  The count SW 42d is a switch that detects that a game ball has won a special winning opening of the special variable winning device 42.

  The glass frame opening SW 18a is a switch that detects that the glass frame 18 has been opened. The front frame opening SW 3a is a switch for detecting that the front frame 3 is opened.

  The ball cut SW 54 is a switch that detects that the number of game balls stored in the gaming machine 1 and used for payout has become a predetermined number or less.

  The vibration sensor 55 is a sensor that detects a vibration applied to the gaming machine 1 and detects a fraud that improperly acquires a gaming ball by applying a vibration to the gaming machine 1. The magnetic sensor 56 is provided in the vicinity of the first start winning opening 45, the second starting winning opening of the normal variation winning apparatus 36, the general winning opening 44, the large winning opening of the special variable winning apparatus 42, and the normal start starting gate 34. It is a sensor that detects magnetic force. The magnetic sensor 93 detects a fraud that brings a magnet close to each winning hole and guides a game ball launched to the gaming area 10a to each winning hole.

  In addition, the CPU 502 receives the first special figure display 38, the first special figure storage display 48, the second special figure display 39, the second special figure storage display 49, and the common figure display via the output I / F 506. A command signal is transmitted to the device 35, the ordinary electric power SOL 36b, the special winning opening SOL 42b, the payout control device 580, and the effect control device 550 to control the game in an integrated manner.

  The first special figure display 38 displays a first special figure fluctuation display game that is executed as an auxiliary game when a game ball wins the first start winning opening 45. The first special figure memory display 48 displays a first start memory number that is a right to start the first special figure variable display game stored within a predetermined upper limit number range.

  The second special figure display 39 displays a second special figure fluctuation display game that is executed as an auxiliary game when a game ball wins a big winning opening of the normal fluctuation winning device 36. The second special figure memory display 49 displays a second start memory number that is a right to start the second special figure variable display game stored within a range of a predetermined upper limit number.

  The general map display 35 displays a general map change display game that is performed when the game ball passes the general map start gate 34.

  The general electric power SOL 36b opens the opening and closing members 36a, 36a when the stop display of the general variable display game executed on the general signal display 35 becomes a special result mode. Make the starting winning opening easy for the game ball to win.

  The special winning opening SOL42b opens the open / close door 42a of the special variable winning device 42 when the result of the first special figure fluctuation display game or the second special figure fluctuation display game becomes a special result mode and becomes a special game state. Then, the big winning opening is converted into a state in which the game ball is easy to win.

  In addition, the game control device 500 outputs the gaming machine data to a game hall management device (not shown) via an external information terminal 508 and an information collection terminal device (not shown). The gaming hall management device is a computer that collects and manages gaming data of the gaming machines 1 installed in the gaming hall.

  In addition, the payout control device 580 pays out the number of game balls corresponding to the winning winning opening when the gaming ball wins the general winning opening 44 or the big winning opening, or the ball lending button 26 is operated. When a payout command for paying out a predetermined number of game balls is received from the game control device 500, a payout motor (not shown) is controlled based on the received payout command. The payout command includes the number of game balls to be paid out.

  The game control device 500 uses a change start command, a customer waiting demo command, a fanfare command, a probability information command, an error designation command, and the like as game data indicating the game situation via the output I / F 506, and the effect control device 550. Send to.

  FIG. 4 is a block diagram showing a configuration of the effect control device 550 according to the first embodiment of the present invention.

  The effect control device 550 determines the contents of the effect based on the game data (display control command) input from the game control device 500, controls the display device 53 and the speaker 30, and via the decoration control device 610. The decoration device 620, the accessory driving SOL 560 (solenoid), and the accessory driving MOT (motor) 561 are controlled. Although the details will be described later, a game effect is performed by the decoration device 620, the accessory driving SOL 560, and the accessory driving MOT 561 (generally referred to as an effect device). The effect control device 550 receives a signal indicating that the effect button 17 has been operated from the effect button 17.

  The effect control device 550 includes a CPU 551, a control ROM 552, a RAM 553, an image ROM 554, a sound ROM 555, a VDP 556, a sound LSI 557, an input / output I / F 558, a power-on detection circuit 559, a master IC 570, and a NOR gate circuit 590.

  The CPU 551 is connected to the game control device 500, receives a command signal from the game control device 500 as an interrupt signal (INT), and is a main control device that controls various effects based on the input command signal. In addition, an interrupt signal is input to the CPU 551 from a controller of the master IC 570 which will be described later, and an interrupt signal is input from the VDP 556.

  When an interrupt signal is input to the CPU 551, the CPU 551 interrupts the process currently being executed and executes a process corresponding to the input interrupt signal.

  The control ROM 552 stores invariant information (program, data, etc.) for effect control. The RAM 553 is used as a work area during production control.

  The image ROM 554 stores image data to be displayed on the display device 53, and the image ROM 554 is connected to the VDP 556. The sound ROM 555 stores sound data output from the speaker 30, and the sound ROM 555 is connected to the sound LSI 557.

  The VDP 556 is a processor that controls image output to the display device 53. The sound LSI 557 is a circuit that controls the sound output from the speaker 30.

  Note that the VDP 556 includes synchronization signal generation means for generating a synchronization signal that is synchronized with a cycle (33 ms cycle) for updating an image displayed on the display device 53. Every time the synchronization signal is generated, the synchronization signal generation means inputs the generated synchronization signal to the CPU 551 as an interrupt signal.

  The input / output I / F 558 is an interface connected to the effect button 17, the motor position detection sensor 510, and the NOR gate circuit 590, an operation signal from the effect button 17, and a motor position detection signal from the motor position detection sensor 510. Is transmitted to the CPU 551 and a reset signal from the CPU 551 is transmitted to the NOR gate circuit 590.

  The effect button 17 is provided on the upper edge portion of the upper plate 21 and is operated by the player in an effect in the first special figure fluctuation display game or the second special figure fluctuation display game executed on the display device 53. .

  The motor position detection sensor 510 outputs a motor position detection signal when it is detected that the rotation shaft of the accessory driving MOT 561 has rotated to the initial position.

  Note that the NOR gate circuit 590 is connected to a RESET terminal provided in the controller of the master IC 570 and other circuits that require initialization. Other circuits that require initialization include, for example, the VDP 556 and the sound LSI 557. These are initialized by the CPU 551 when the production control device 550 is powered on and activated.

  The CPU 551, VDP 556, RAM 553, control ROM 552, sound LSI 557, and input / output I / F 558 are connected via a bus 563.

  The power-on detection circuit 559 generates a reset signal that initializes a register (not shown) of the master IC 570 to a default state (all 0) when the presentation control device 550 is powered on, and the generated reset signal is NORed. Output to the gate circuit 590.

  The CPU 551 outputs a reset signal to the input / output I / F 558 via the bus 563 when a predetermined condition is satisfied, and the input / output I / F 558 outputs the input reset signal to the NOR gate circuit 590. .

  Note that the reset signal input from the power-on detection circuit 559 to the NOR gate circuit 590 and the reset signal input from the CPU 551 to the NOR gate circuit 590 via the input / output I / F 558 are in a low level state in any case. Function as a signal to command resetting. Therefore, if at least one of the power-on detection circuit 559 and the CPU 551 outputs a reset signal to the NOR gate circuit 590, the reset signal is input to the master IC 570 via the NOR gate circuit 590.

  As described above, since the NOR gate circuit 590 is connected to the master IC 570 and other circuits that require initialization, when a reset is input to the NOR gate circuit 590, the master IC 570 and the NOR gate circuit 590 are input to the NOR gate circuit 590. Other circuits that require initialization to be connected are initialized.

  Note that when there is no other circuit that requires initialization, the NOR gate circuit 590 is connected only to the master IC 570.

  Next, the master IC 570 will be described.

  Master IC 570 designates the address of decoration control device 610 of the rendering device to be controlled, and outputs the control content of the rendering device to decoration control device 610 at the designated address.

  The master IC 570 is connected to the relay board (decoration control device) 600 through five connection lines of the connection line Vcc, the connection line Vact, the connection line SDA, the connection line SCL, and the connection line GND (see FIG. 5). The

  The connection line Vcc is a connection line for supplying logic power to the relay board 600 and the decoration control device 610. The connection line Vact is a connection line for supplying a power source for driving the effect device (for example, a power source for causing the LED to emit light). The connection line SDA is a connection line for communicating data between the effect control device 550 and the decoration control device 610, and functions as a data line in the present embodiment. The connection line SCL is a connection line for inputting and outputting a clock signal used for data communication through the connection line SDA, and functions as a timing signal line in the present embodiment. The connection line GND shown in FIG. 5 is the ground of the power supplied by the connection line Vcc and the connection line Vact.

  The relay board 600 and the decoration control device 610 are connected to each other through the connection line Vcc, the connection line Vact, the connection line SDA, the connection line SCL, and the connection line GND, similarly to the master IC 570 and the relay board 600. The

  The master IC 570 and the decoration control device 610 perform two-line bidirectional communication using the connection line SDA and the connection SCL.

  When transmitting data to the relay board 600 and the decoration control device 610, the master IC 570 first changes the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH. Thus, a start condition for starting data output to the decoration control device 610 is established (a start condition is issued to the decoration control device 610).

  Thereafter, the master IC 570 changes the signal level of the connection line SCL to LOW, sets the signal level of the connection line SDA to the level of the first bit of the transmission data while the signal level of the connection line SCL is LOW, After a predetermined time, the signal level of the connection line SCL is changed from LOW to HIGH. When the signal level of the connection line SCL changes to HIGH, the decoration control device 610 takes in the signal level of the connection line SDA and recognizes it as the first bit of the transmission data. Next, the master IC 570 returns the signal level of the connection line SCL from HIGH to LOW.

  When this procedure is executed once, 1-bit data is transmitted from the master IC 570 to the decoration control device 610. Finally, this procedure is repeated 8 times, so that all 8 bits, which are unit bits of transmission data, are master. The data is transmitted from the IC 570 to the decoration control device 610 (1 byte of data is transmitted).

  The master IC 570 releases the connection line SDA and returns the response signal from the decoration control device 610 when the signal level of the connection line SCL is returned from HIGH to LOW after the transmission of the last 8-bit data. It will be in the reception waiting state which waits to receive.

  In the reception standby state, the decoration control device 610 returns a 1-bit response signal (ACK or NACK described later) to the master IC 570 via the connection line SDA. Next, when the master IC 570 changes the signal level of the connection line SCL from LOW to HIGH to capture the level of the response signal, and after a predetermined time, changes the signal level of the connection line SCL from HIGH to LOW, the decoration control device 610 Release the connection line SDA.

  The master IC 570 alternately repeats the data transmission for 1 byte and the reception of the response signal for 1 bit, and continues until all the data to be output to the decoration control device 610 is output. When the output of the data to be output is completed, the master IC 570 changes the signal level of the connection line SDA from LOW to HIGH while maintaining the signal level of the connection line SCL at HIGH, thereby controlling the decoration control device 610. A stop condition for ending the data output to is established (a stop condition is issued to the decoration control device 610).

  The input BUF 571 is a storage device that temporarily stores data input from the decoration control device 610 via the connection line SDA.

  Specifically, when the master IC 570 is set to the input mode, the data transmitted from the decoration control device 610 to the master IC 570 is temporarily stored in the input BUF 571 with noise removed by the filter 575A.

  The output BUF 572 temporarily stores data to be output to the decoration control device 610 via the connection line SDA.

  The reset REG 573 functions as an initialization instruction data storage area of this embodiment, and is connected to the bus 563 and receives a command from the CPU 551 and outputs a reset signal to the controller. The controller comprehensively controls the master IC 570 and executes various processes.

The transmission mode REG574 is a register for selecting whether the mode for transmitting data to the I ² CI / O expander 615 is the byte mode or the buffer mode.

In the byte mode, every time the master IC 570 transmits 1 byte of data to the I ² CI / O expander 615, the master IC 570 receives ACK or NACK from the I ² CI / O expander 615, and receives either ACK or NACK. Even in this case, an interrupt signal is output from the master IC 570 to the CPU 551.

Buffer mode, master IC570 is, data of a plurality of bytes stored in the output BUF572, sends each byte to I ² CI / O expander 615, each of the transmission, from the I ² CI / O expander 615 When ACK or NACK is received and NACK is received, an interrupt signal is output to the CPU 551 at that time.

However, in the buffer mode, when ACK is received, an interrupt signal is output to the CPU 551 only when transmission of all data stored in the output BUF 572 is completed, and the master IC 570 outputs the BUF 572 for output. When ACK is received from the I ² CI / O expander 615 with untransmitted data remaining in the memory, the next signal to be transmitted is extracted from the output BUF 572 without outputting an interrupt signal to the CPU 551. , The control to output to the I ² CI / O expander 615 is repeated.

The byte mode is used when the master IC 570 outputs initialization instruction data and movable control data described later to the I ² CI / O expander 615. The buffer mode is used when the master IC 570 outputs light emission control data to be described later to the I ² CI / O expander 615.

The status REG 579 is a register that identifies whether the response signal received by the master IC 570 from the I ² CI / O expander 615 is ACK or NACK. When the master IC 570 outputs an interrupt signal to the CPU 551, the master IC 570 sets the value of the status REG 579 corresponding to the response signal received from the I ² CI / O expander 615.
The filter 575A removes noise from data input from the connection line SDA. When the driver 576A outputs data from the connection line SDA, the driver 576A applies a voltage at which the transistor 578A can operate to the transistor 578A.

  As shown in FIG. 9, a predetermined voltage is applied to the connection line SDA by the pull-up resistor R, and the connection line SDA is connected to the filter 575A and the transistor 578A.

  The transistor 578A uses a field effect transistor (FET) to reduce power consumption. The gate of the transistor 578A is connected to the driver 576A, and the drain is a connection line SDA to which a predetermined voltage is applied by the pull-up resistor R. And the source is grounded.

  If the voltage applied to the gate of the transistor 578A is smaller than a predetermined value for operating the transistor 578A, no current flows between the drain and the source, so that the voltage applied to the connection line SDA does not drop, and as a result The connection line SDA becomes HIGH level. On the other hand, if the voltage applied to the gate of the transistor 578A is equal to or higher than a predetermined value for operating the transistor 578A, a current flows from the drain to which the voltage of the predetermined value is applied to the grounded source. As a result, the connection line SDA becomes LOW level.

Note that the transistor 578A has a specification that does not break even when a current of about 10 milliamperes flows from the drain to the source. For this reason, it is possible to flow a current of about 10 milliamperes, which is much larger than the current value used when using a normal I ² C bus, to the connection line SDA, and the effect control device 550 and the decoration control device 610 The data transmission between them is configured to withstand failures due to noise.

  When the driver 576A outputs data from the connection line SDA, the driver 576A applies a voltage of a value that allows the transistor 578A to operate to the gate of the transistor 578A in order to pass a current between the drain and source of the transistor 578A. Then, the driver 576A outputs data from the connection line SDA by setting the voltage of the connection line SDA to HIGH level or LOW level.

  The filter 575B removes noise from data input from the connection line SCL. When the driver 576B outputs data from the connection line SCL, the driver 576B applies a voltage with which the transistor 578B can operate to the transistor 578B.

  As shown in FIG. 9, a predetermined voltage is applied to the connection line SCL by the pull-up resistor R, and the connection line SDA is connected to the filter 575B and the transistor 578B.

  The transistor 578B uses a field effect transistor (FET) to suppress power consumption, the gate of the transistor 578B is connected to the driver 576B, and the drain is a connection line SCL to which a predetermined voltage is applied by the pull-up resistor R. And the source is grounded.

  If the voltage applied to the gate of the transistor 578B is smaller than a predetermined value for operating the transistor 578B, no current flows between the drain and the source, so that the voltage applied to the connection line SCL does not drop, and as a result The connection line SCL becomes HIGH level. On the other hand, when the voltage applied to the gate of the transistor 578B is equal to or higher than a predetermined value for operating the transistor 578B, a current flows from the drain to which the predetermined voltage is applied to the grounded source, whereby the connection line SCL As a result, the connection line SCL becomes the LOW level.

Note that the transistor 578B has a specification that does not break even when a current of about 10 milliamperes flows from the drain to the source. Therefore, a current of about 10 milliamperes, which is much larger than the current value used when using the normal I ² C bus, can be passed through the connection line SCL, and between the effect control device 550 and the decoration control device 610. The data transmission is configured to withstand failures due to noise.

  When the driver 576B outputs a clock signal from the connection line SCL, the driver 576B applies a voltage with a value that allows the transistor 578B to operate to the gate of the transistor 578B in order to cause a current to flow between the drain and the source of the transistor 578B. Then, the driver 576B outputs a clock signal from the connection line SCL by repeatedly changing the voltage of the connection line SCL between a HIGH level and a LOW level.

  The power-on reset circuit 577 is used to set storage areas such as the input BUF 571 and the output BUF 572 to a default state when the master IC 570 is powered on and the voltage in the power-on reset circuit 577 reaches a predetermined value. The reset signal is output to the controller.

  Next, the relay board 600 and the decoration control device 610 will be described.

  The relay board 600 is directly connected to the master IC 570 in the decoration control device 610, that is, located on the most upstream side.

The decoration device 620 is a light-emitting device that is controlled by an I ² CI / O expander 615 (described later in FIG. 6) provided in the decoration control device 610 and flashes light when an electric current is passed. Etc. The accessory driving solenoid (SOL) 560 is a device that reciprocates when an electric current flows. The accessory driving solenoid (SOL) 560 moves an accessory for decoration (not shown) arranged on the game board 10 to produce an effect. The accessory driving motor (MOT) 561 is a device that rotates when an electric current flows, and produces an effect by moving the movable accessory 60. The accessory driving solenoid (SOL) 560 and the accessory driving motor (MOT) 561 are also controlled by the I ² CI / O expander 615 provided in the decoration control device 610.

  Note that the accessory driving SOL 560 may move the movable accessory 60, or the accessory driving MOT 561 may move an accessory not shown.

  The connection method between the effect control device 550 and the relay board 600 and the connection method between the relay board 600 and the decoration control device 610 other than the relay board 600 will be described in detail with reference to FIG. Details of the decoration control device 610 will be described with reference to FIGS.

  FIG. 5 is an explanatory diagram of connections of the decoration control devices 610A to 610F according to the first embodiment of this invention. In addition, for convenience of explanation, one relay board 600 and six decoration control devices 610A to 610F are illustrated as the decoration control device 610, but actually, it is necessary to correspond to the specifications of the gaming machine. A large number of decoration control devices 610 are connected.

  The effect control device 550 is connected to the effect control device 550 via the connection line Vcc, the connection line Vact, the connection line SDA, the connection line SCL, and the connection line GND (hereinafter, these five connection lines are referred to as one harness). Is done.

  Two decoration control devices 610A and 610D are connected to the relay board 600 in parallel by harnesses.

  The decoration control device 610B is connected to the decoration control device 610A via a harness, and the decoration control device 610C is connected to the decoration control device 610B via a harness.

  On the other hand, a decoration control device 610E is connected to the decoration control device 610D via a harness, and a decoration control device 610F is connected to the decoration control device 610E via a harness.

  Each decoration control device 610 includes a connector serving as an attachment port for connecting the harness to itself. Since this connector is common to each decoration control device 610, it is possible to prevent erroneous wiring in the connection order of the connection lines.

Here, a method of controlling the decoration device 620 by the I ² CI / O expander 615 (described later in FIG. 6) provided in the decoration control device 610 will be described.

The effect control device 550 determines the output mode of the effect device based on the game data input from the game control device 500. Then, the production control device 550 produces production control data (production control) including the individual address of the decoration control device 610 to be controlled (the individual address of the I ² CI / O expander 615) so that the determined output mode is obtained. Information) is output to the relay board 600. At this time, the effect control data is output from the connection line SDA to all the decoration control devices 610 connected to the effect control device 550 via the relay board 600. Therefore, the master IC 570 can control all the decoration control devices 610 connected to the master IC 570.

  In the present embodiment, a light emitting device such as an LED is exemplified as the effect device, and the light emission mode of the LED corresponds to the output mode of the effect device. In this case, lighting / flashing / extinguishing of the LED is instructed by the effect control data, and at the same time, the flashing cycle and the lighting brightness of the LED are also instructed.

Each decoration control device 610 has a unique individual address set in advance, so that when the effect control data is input, the address included in the input effect control data matches the set individual address. It is determined whether or not. If it is determined that the address included in the input effect control data matches the set individual address, the I ² CI / O expander 615 of the decoration control device 610 captures the effect control data. Thus, the output mode of the corresponding decoration device 620 is controlled, and a response signal is output to the master IC 570 immediately after the 8th bit data is input.

Each decoration control device 610 is set with a reset address for initializing the I ² CI / O expander 615 of the decoration control device 610 in addition to the individual address. This reset address is an address provided in common to all the I ² CI / O expanders 615 and cannot be used as an individual address. Further, the value of the reset address cannot be changed (details will be described later).

When the effect control device 550 initializes the decoration control device 610 (more precisely, the I ² CI / O expander 615 of the decoration control device 610), the effect control device 550 receives the initialization instruction data including the common address for resetting. , Output to the relay board 600. At this time, the initialization instruction data effect control data is output from the connection line SDA to all the decoration control devices 610 connected to the effect control device 550 via the relay board 600.

Each decoration control device 610 has a preset common address for resetting, so it is determined whether or not the address included in the input data matches the preset common address for resetting. To do. When it is determined that the address included in the input data matches a preset common address for resetting, the I ² CI / O expander 615 of the decoration control device 610 transmits a response signal as a master. In addition to outputting to the IC 570, the input data is fetched as initialization instruction data, and the I ² CI / O expander 615 itself is initialized.

When the I ² CI / O expander 615 is initialized, the rendering device controlled by the initialized I ² CI / O expander 615 is turned off.

As described above, the decoration control device 610 performs control based on a command from the effect control device 550, and therefore, the master IC 570 of the effect control device 550 is the master of the relationship between the effect control device 550 and the decoration control device 610. The I ² CI / O expander 615 of the decoration control device 610 is a slave.

  Although the case where the decoration target of the decoration control device 610 is the decoration device 620 has been described with reference to FIG. 5, the control target of the decoration control device 610 may be the accessory driving SOL 560 or the accessory driving MOT 561. In this case, since the rendering device serves as a drive source such as a motor or a solenoid, the operation mode of these drive sources corresponds to the output mode of the rendering device. In this case, activation / deactivation of the drive source is instructed by the effect control data, and the operation speed is also instructed at the same time.

  FIG. 6 is a block diagram of the decoration control device 610 according to the first embodiment of this invention.

  In FIG. 6, the decoration control device 610 (the decoration control device 610 on the lower side in FIG. 6) including the decoration device 620 LED inside the decoration control device 610 and the decoration control device 610 connected to the external decoration device 620. (The decoration control device 610 in the center of FIG. 6) will be described.

  First, the decoration control device 610 provided with LEDs inside the decoration control device 610 will be described.

The decoration control device 610 on the lower side of FIG. 6 includes an I ² CI / O expander 615 and LEDs (decoration device 20). The connection line SDA and the connection line SCL are branched into two in the decoration control device 610, and one is output to the next decoration control device 610 as it is. The other is connected to the I ² CI / O expander 615.

A decoration device 620 to be controlled is connected to the output side of the I ² CI / O expander 615. The output side of the I ² CI / O expander 615 includes ports 0 to 15 described with reference to FIG. Furthermore, all the ports of the decoration control device 610 are connected to the internal LEDs via current limiting resistors R0 to R15 described later with reference to FIG. 8A. Note that the current control resistors R0 to R15 are also provided in the decoration control device 610.

As described above, the I ² CI / O expander 615 has an address included in the effect control data input from the effect control device 550 and an individual address set in the I ² CI / O expander 615. Only when they match, the decoration device 620 connected to the I ² CI / O expander 615 is controlled based on the decoration data included in the effect control data.

  The power source Vled in the figure corresponds to the power source (power source for causing the LED to emit light) supplied by the connection line Vact described above with reference to FIG.

  Next, the decoration control device 610 connected to the external decoration device 620 will be described.

The central decoration control device 610 in FIG. 6 includes an I ² CI / O expander 615 and an LED (decoration device 20), and allows current to flow through the LEDs provided on the decoration device substrate 625 connected to the outside of the decoration control device 610. The decoration control device 610 and the decoration device substrate 625 are connected to each other through a connection line for connecting the power supply voltage Vled to the LED of the decoration device substrate 625 and a connection wire grounded to the ground.

The decoration device substrate 625 does not include the I ² CI / O expander 615 but is a substrate including only LEDs. In this case, the current limiting resistor (FIG. 8A) connected to the LED provided on the decoration device board 625 is provided on the decoration device board 625, but the decoration control device provided with the I ² CI / O expander 615. 610 may be provided.

It should be noted that the number of connection lines for passing current to these LEDs to be passed from the decoration control device 610 to the decoration device substrate 625 is determined in accordance with the number of LEDs provided on the decoration device substrate 625. . For example, when the decoration device substrate 625 includes two LEDs, two control lines for connecting the port of the I ² CI / O expander 615 and the corresponding LED, and a power supply line for supplying Vled Is required at least.

The I ² CI / O expander 615 provided in the central decoration control device 610 is also set in the address included in the effect control data input from the effect control device 550 and the I ² CI / O expander 615. The decoration device 620 connected to the I ² CI / O expander 615 is controlled based on the decoration data included in the effect control data only when the individual address matches. In this case, both the decoration device 620 provided in the central decoration control device 610 and the decoration device 620 provided on the decoration device substrate 625 are controlled by the I ² CI / O expander 615.

In this way, by providing the decoration device substrate 625 and separating a part of the decoration devices (LEDs) from the decoration control device 610, even if the LEDs are arranged at remote locations, a common I ² CI / It can be controlled by the O expander 615.

  Note that the decoration control device 610 may connect and control the accessory driving SOL 560 and the accessory driving MOT 561 in place of the decoration device 620, but details will be described later with reference to FIG. 8B.

FIG. 7 is a block diagram of the I ² CI / O expander 615 according to the first embodiment of this invention.

The I ² CI / O expander 615 includes a transistor 630 connected to the connection line SDA, a filter 631 connected to the connection line SDA, a driver 632 connected to the connection line SDA, a filter 633 connected to the connection line SCL, Bus controller 634, output setting register 635, output controller 636, driver 637 connected to ports 0-15 on the output side of I ² CI / O expander 615, transistors 638A-638P connected to ports 0-15 , And a reset signal generation circuit 639.

  The filter 631 is connected to the connection line SDA, removes noise of data input from the connection line SDA, and outputs the data from which noise has been removed to the bus controller 634. When the driver 632 outputs a response signal from the connection line SDA, the driver 632 applies a voltage at which the transistor 630 can operate to the transistor 630.

  When the driver 632 outputs data (response signal) from the connection line SDA, the driver 632 applies a voltage at which the transistor 630 can operate to the transistor 630.

  The transistor 630 uses a field effect transistor (FET) to suppress power consumption, the gate of the transistor 630 is connected to the driver 632, and a predetermined voltage is applied to the drain by a pull-up resistor R (see FIG. 4). Connected to the connected connection line SDA, and the source is grounded.

  If the voltage applied to the gate of the transistor 630 is smaller than a predetermined value for operating the transistor 630, no current flows between the drain and the source. On the other hand, if the voltage applied to the gate of the transistor 630 is greater than or equal to a predetermined value that causes the transistor 630 to operate, a current flows from the drain to which the voltage of the predetermined value is applied to the grounded source. The voltage drops. Note that the transistor 630 has a specification that does not break even when a current of about 10 milliamperes flows from the drain to the source.

  When the driver 632 outputs data (response signal) from the connection line SDA, the driver 632 applies a voltage of a value that allows the transistor 630 to operate to the gate of the transistor 630 so that a current flows between the drain and the source. To do. The driver 632 outputs data from the connection line SDA by repeatedly changing the voltage of the connection line SDA from HIGH to LOW.

  The filter 633 is connected to the connection line SCL, removes noise of data input from the connection line SCL, and outputs the data from which noise has been removed to the bus controller 634.

In addition, the I ² CI / O expander 615, is set a unique address by the address setting terminals A0~A3 provided in the I ² CI / O expander 615 is input to the bus controller 634. Further, an address for resetting the I ² CI / O expander 615 is also set in advance.

The bus controller 634 determines whether or not the address of the data input from the connection line SDA matches the unique address set in the I ² CI / O expander 615. Capture as production control data.

Also, the bus controller 634 determines whether the address of the data input from the connection line SDA matches the reset address preset in the I ² CI / O expander 615, and determines whether the input data When the address and the reset address preset in the I ² CI / O expander 615 match, the data is fetched as initialization instruction data, and the I ² CI / O expander 615 is initialized. .

  In addition, the bus controller 634 changes the signal level of the SCL connection line from LOW to HIGH and takes in the 8th bit data, and then changes the signal level of the SCL connection line from HIGH to LOW. A response signal is output from the connection line SDA to the master IC 570. Further, it is confirmed that the signal level of the SCL connection line changes from LOW to HIGH, and when the signal level of the SCL connection line changes from HIGH to LOW again, the connection line SDA is released. That is, a response signal is output at a timing when the number of changes in the signal level of the SCL connection line from LOW to HIGH becomes nine.

In the output setting register 635, the operation mode of the I ² CI / O expander 615 and the output state of the ports 0 to 15 are set. When the bus controller 634 fetches the initialization instruction data from the connection line SDA and the I ² CI / O expander 615 is initialized, the output setting register 635 causes a current to flow to all the ports 0 to 15. The initial state is set so that there is no.

  Based on the data set in the output setting register 635, the output controller 636 causes the directing device connected to each of the ports 0 to 15 to actually output the output state of the directing device through the port driver 637. To control. When the bus controller 634 fetches the effect control data from the connection line SDA, this output state is updated to the contents specified in the fetched effect control data.

  When a current flows through a port, the driver 637 applies a voltage at which the transistors 638A to 638P connected to the port through which the current flows can operate.

  The gates of the transistors 638A to 638P are connected to the driver 637, the drain is connected to the port terminal connected to the connection line to which the voltage for operating the rendering device is applied as shown in FIGS. 8A and 8B, and the source is grounded Has been.

  If the voltage applied to the gates of the transistors 638A to 638P is smaller than a predetermined value for operating the transistors 638A to 638P, no current flows between the drain and the source. On the other hand, if the voltage applied to the gates of 638A to 638P is equal to or higher than a predetermined value for operating the transistor 638, the power supply Vled shown in FIG. 8A or the power supply Vmot or the power supply Vsol shown in FIG. Current flows to the source grounded through the drain of the transistor 638, so that the output state of the effect device connected to the port terminal can be controlled.

Further, the I ² CI / O expander 615 of the decoration control device 610 can control all the rendering devices connected to the port terminals of the I ² CI / O expander 615 at the same time. ² One rendering device connected to the port terminal of the CI / O expander 615 can be controlled as one group.

Since the I ² CI / O expanders 615 included in each decoration control device 610 are assigned different individual addresses, the rendering device is divided into a plurality of groups. In other words, the I ² CI / O expander 615 included in each decoration control device 610 is configured as a group unit control unit that can control the effect device in units of groups.

  Therefore, the effect control device 550 that controls the decoration control device 610 functions as a group control unit that controls the group unit control unit.

The reset signal generation circuit 639 is connected to a Vcc terminal connected to a connection line Vcc that supplies power to the I ² CI / O expander 615 and a RESET terminal that receives an external reset signal.

The reset signal generation circuit 639 generates a reset signal when the I ² CI / O expander 615 is turned on and the voltage rises to a predetermined value, and the generated reset signal is sent to the bus controller 634 and the output setting register 635. , And the output controller 636.

  Note that when a LOW level reset signal is input from the outside, the reset signal generation circuit 639 outputs a reset signal, and therefore, from the CPU 551 of the effect control device 550 via the NOR gate circuit 590, from the RESET terminal. A reset signal may be input. When the RESET terminal is not used, the RESET terminal may be pulled up to HIGH as shown in FIGS. 8A and 8B.

FIG. 8A is a circuit diagram around the I ² CI / O expander 615 of the decoration control device 610 that controls the decoration device 620 according to the first embodiment of the present invention.

The I ² CI / O expander 615 includes an NC terminal, a RESET terminal, an SCL terminal, an SDA terminal, a Vcc terminal, an A0 to A3 terminal, and a GND terminal as input terminals, and includes PORT0 to PORT15 as output terminals.

A power source supplied to the I ² CI / O expander 615 is connected to the RESET terminal via a pull-up resistor R. For this reason, the voltage applied to the reset terminal is always maintained HIGH.

  The SCL terminal is connected to the connection line SCL, and the SDA terminal is connected to the connection line SDA.

A power supply supplied to the I ² CI / O expander 615 is connected to the Vcc terminal. Further, a capacitor CP for removing power supply noise is connected to the Vcc terminal.

The A0 to A3 terminals are terminals for setting unique addresses for the I ² CI / O expander 615. Note that the address of the normal I ² CI / O expander 615 is represented by 4 bits. When the power of the I ² CI / O expander 615 is applied to this terminal, “1” is displayed in the bus controller 634. When this terminal is connected to the ground, “0” is set in the bus controller 634.

Therefore, the address of the I ² CI / O expander 615 shown in FIG. 8A is “0100”, and the address of the I ² CI / O expander 615 shown in FIG. 8B is “0110”. The GND terminal is a terminal for grounding a voltage.

  Each PORT0 terminal to PORT15 terminal is connected to a decoration device 620 including each LED0 to LED15 via current limiting resistors R0 to R15. Note that one LED may be connected to one port as in PORT0, but a plurality of LEDs may be connected to one port as in PORT1-15.

When one LED is provided for all the ports, a maximum of 16 LEDs can be controlled by one I ² CI / O expander 615. If the number of LEDs connected to each port is different, assuming that all LEDs connected in series to one port are one type of LED, one I ² CI / O expander is used. By 615, up to 16 kinds of LEDs can be controlled.

  When a voltage is applied from the driver 637 to the gates of the transistors 638A to 638P (see FIG. 7) connected to the PORT0 terminal to the PORT15 terminal, a current flows from the drain to the source of the transistors 638A to 638P to which the voltage is applied. Thus, a current flows through the LED0 to LED15 connected to the PORT0 terminal to the PORT15 terminal, and each of the LED0 to LED15 lights up.

  On the other hand, if the driver 637 does not apply a voltage to the gates of the transistors 638A to 638P, no current flows through each LED0 to LED15, and each LED0 to LED15 is not lit.

In addition, since it is possible to connect a motor or a solenoid to the PORT0 terminal to the PORT15 terminal of the I ² CI / O expander 615 instead of the LED, the motor is used by using the I ² CI / O expander 615. A case where a solenoid is driven will be described.

FIG. 8B is a circuit diagram around the I ² CI / O expander 615 of the decoration control device 610 that controls the accessory driving MOT 561 and the accessory driving SOL 560 according to the first embodiment of this invention.

  The accessory driving MOT 561 is composed of a stepping motor, and rotates by sequentially applying a predetermined voltage to signal terminals of respective phases that drive the stepping motor. In the present embodiment, the signal terminals of the respective phases of the accessory driving MOT 561 are connected to the PORT0 terminal to the PORT3 terminal.

  When a voltage is applied from the driver 637 to any one of the gates of the transistors 638A to 638D connected to the PORT0 terminal to the PORT3 terminal connected to the accessory driving MOT561, the transistors 638A to 638D to which the voltage is applied are applied. The current can flow from the drain to the source, the current flows to the accessory driving MOT 561 connected to the PORT0 terminal to the PORT3 terminal, and the accessory driving MOT561 is driven.

  The connection lines connecting the PORT0 terminal to the PORT3 terminal and the accessory driving MOT 561 are branched, and one of the branched connection lines is connected to the power supplied to the accessory driving MOT 561 via the diode D and the Zener diode ZD. Connected.

  The PORT terminal 15 is connected to the accessory driving SOL 560. When a voltage is applied from the driver 637 to the gate of the transistor 638P connected to the PORT15 terminal connected to the accessory drive SOL560, a current can flow from the drain to the source of the transistor 638P to which the voltage is applied. Thus, a current flows through the accessory driving SOL 560 connected to the PORT 15 terminal, and the accessory driving SOL 560 is driven.

In FIG. 8B, with respect to I ² CI / O Aix although both character object drive MOT561 and character object drive SOL560 Panda 615 are connected, one I ² CI / O expander 615, the character object drive A configuration in which at least one of the MOT 561 and the accessory driving SOL 560 is connected may be used.

For example, an I ² CI / O expander 615 as a group that controls only the stepping motor may be provided exclusively, or an I ² CI / O expander 615 as a group that controls only the solenoid may be provided exclusively. . With such a configuration, it is possible to control the rendering devices belonging to the same group at the same timing, and therefore it becomes possible to group and control only the rendering devices that require high-speed processing.

  FIG. 9 is a circuit diagram of connection lines related to input / output of the relay board 600 according to the first embodiment of the present invention.

The relay board 600 includes an upstream connector 601, two downstream connectors 602A and 602B, and an I ² CI / O expander 615.

  The upstream connector 601 is a connector connected to the master IC 570 upstream of the relay board 600, and the connectors 602 A and 602 B are connected to the decoration control device 610 downstream of the relay board 600.

  In order to connect the connection line SDA to the two downstream connectors 602A and 602B, the internal connection line SDA911 extending from the upstream connector 601 branches at a branch 901 into a first connection line SDA921 and a second connection line SDA931. The first connection line SDA921 is connected to the downstream connector 602A, and the second connection line SDA931 is connected to the downstream connector 602B.

  Similarly, the internal connection line SCL912 extending from the upstream connector 601 branches at a branch 902 into a first connection line SCL922 and a second connection line SCL932. The first connection line SCL922 is connected to the downstream connector 602A, and the second connection line SCL932 is connected to the downstream connector 602B.

In order to connect the connection line SDA to the I ² CI / O expander 615, the second connection line SDA931 branches at the branch 903, and the branched second connection line SDA931 is the I ² CI / O expander 615 in FIG. It is connected to the SDA terminal shown in FIG. Further, in order to connect the connection line SCL to the I ² CI / O expander 615, the second connection line SCL 932 branches at the branch 904, and the branched second connection line SCL 932 is a diagram of the I ² CI / O expander 615. 8A and the SCL terminal shown in FIG. 8B.

Note that the I ² CI / O expander 615 is supplied with a voltage Vcc that is a power supply voltage of the I ² CI / O expander 615. Although not shown in FIG. 9, from the I ² CI / O expander 615, signal lines of ports 0 to 15 for driving LEDs (decoration device 200) provided on the relay board 600 (see FIG. 8A). Is output.

Further, although the I ² CI / O expander 615 is connected to the second connection line SDA931 and the second connection line SCL932, it may be connected to the first connection line SDA921 and the first connection line SCL922.

I ² CI / O Aix input expander 615 via the connection line SDA signal is output via the connection line SDA upstream of the master IC570, and from the upstream of the master IC570 to I ² CI / O expander 615 of the relay board 600 The Zener diode ZD941 is connected to the internal connection line SDA911 in order to remove the noise of the generated signal.

  Specifically, the internal connection line SDA911 branches at the branch 905, the branched internal connection line SDA911 is connected to the cathode side of the Zener diode ZD941, and the anode side of the Zener diode ZD941 is grounded.

  For this reason, a voltage (for example, a pulsed noise signal) higher than a predetermined voltage applied to the internal connection line SDA911 is released by the Zener diode ZD941.

In addition, a Zener diode ZD942 is connected to the internal connection line SCL912 in order to remove noise of a signal input from the upstream master IC 570 to the I ² CI / O expander 615 of the relay board 600 via the connection line SCL. ing.

  Specifically, the internal connection line SCL912 branches at a branch 906, the branched internal connection line SCL912 is connected to the cathode side of the Zener diode ZD942, and the anode side of the Zener diode ZD942 is grounded.

  For this reason, a voltage (for example, a pulsed noise signal) applied to the internal connection line SCL912 is released by the Zener diode ZD942.

A signal output from the I ² CI / O expander 615 of the relay board 600 via the connection line SDA to the decoration control device 610 connected to the downstream connector 602A, and the relay board from the decoration control device 610 connected to the downstream connector 602A. A Zener diode ZD943 is connected to the first connection line SDA921 in order to remove noise of a signal input to the 600 I ² CI / O expander 615 via the connection line SDA.

  Specifically, the first connection line SDA921 branches at a branch 907, the branched first connection line SDA921 is connected to the cathode side of the Zener diode ZD943, and the anode side of the Zener diode ZD943 is grounded.

  Therefore, a voltage (for example, a pulsed noise signal) higher than a predetermined voltage applied to the internal connection line SDA921 is released by the Zener diode ZD943.

  Similarly to the Zener diode ZD943 connected to the first connection line SDA921, the Zener diode 945 is also connected to the second connection line SDA931.

The first connection line SCL922 is used to remove noise of a signal input from the I ² CI / O expander 615 of the relay board 600 to the decoration control device 610 connected to the downstream connector 602A via the connection line SCL. Is connected to a Zener diode ZD944.

  Specifically, the first connection line SCL922 branches at a branch 908, the branched first connection line SCL922 is connected to the cathode side of the Zener diode ZD944, and the anode side of the Zener diode ZD944 is grounded.

  For this reason, a voltage (for example, a pulse noise signal) of a predetermined level or higher applied to the internal connection line SCL922 is released by the Zener diode ZD944.

  Similarly to the Zener diode ZD944 connected to the first connection line SCL922, the Zener diode ZD946 is also connected to the second connection line SCL932.

  In addition, a pull-up resistor R951 for pulling up the voltage of the upstream connection line SDA connected to the master IC 570 and the downstream connection line SDA connected to the decoration control device 610 is provided in the first connection line SDA921. Connected. Similarly, a pull-up resistor R952 for pulling up the voltage of the upstream connection line SCL connected to the master IC 570 and the downstream connection line SCL connected to the decoration control device 610 is provided in the first connection line SDA922. Connected.

  Specifically, the first connection line SDA921 branches at the branch 909, and the branched first connection line SDA921 is connected to the pull-up resistor R951. Similarly, the first connection line SCL922 branches at a branch 910, and the branched first connection line SCL922 is connected to a pull-up resistor R952.

  Note that the pull-up resistors 951 and 952 for pulling up the voltages of the connection line SDA and the connection line SCL may not be included in the relay substrate 600, may be included in the master IC 570, or a decoration control device other than the relay substrate 600. 610 may be provided. In short, it may be anywhere as long as the voltage Vcc can be supplied to the drain terminals of the transistors that drive the connection line SDA and the connection line SCL.

The internal connection line Vcc971 extending from the Vcc terminal of the upstream connector 601 connected to the connection line Vcc for supplying the power supply voltage to the I ² CI / O expander 615 of the relay board 600 and the GND terminal of the upstream connector 601 are grounded. The internal connection line GND972 is connected via a smoothing capacitor C961 and a bypass capacitor 962.

  The smoothing capacitor C961 is a capacitor for smoothing the voltage waveform of the power supply, and the bypass capacitor CP962 is a capacitor for removing noise of the power supply voltage.

For this reason, the power supply voltage supplied to the I ² CI / O expander 615 of the relay board 600 is smoothed by the smoothing capacitor C961, and noise is removed by the bypass capacitor 962, so that the I ² CI / O expander is removed. 615 is supplied.

  Similarly, the internal connection line Vcc973 extending from the Vcc terminal of the downstream connectors 602A and 602B and the internal connection line GND974 extending from the GND terminal are connected via a smoothing capacitor C961 and a bypass capacitor 962. As a result, the smoothed and noise-free voltage is applied to the connection line Vcc connected to the downstream decoration control device 610.

  FIG. 10 is a circuit diagram of connection lines related to input / output of the decoration control device 610 according to the first embodiment of the present invention.

The decoration control device 610 includes an upstream connector 611, an I ² CI / O expander 615, and a downstream connector 612.

  A bus is connected to the upstream connector 611 from the relay board 600 or the decoration control device 610 on the upstream side. The downstream connector 612 is connected to a bus connected to the decoration control device 610 on the downstream side.

  The SDA terminal of the upstream connector 611 and the SDA terminal of the downstream connector 612 are connected by an internal connection line SDA1011. The SCL terminal of the upstream connector 611 and the SCL terminal of the downstream connector 612 are connected by an internal connection line SCL1012.

In order to connect the connection line SDA to the I ² CI / O expander 615, the internal connection line SDA1011 branches at the branch 1001, and the branched internal connection line SDA1011 is the I ² CI / O expander 615 shown in FIGS. To the SDA terminal shown in FIG. Further, in order to connect the connection line SCL to the I ² CI / O expander 615, the internal connection line SCL 1012 branches at the branch 1002, and the branched internal connection line SCL 1012 is the I ² CI / O expander 615 shown in FIG. It is connected to the SCL terminal shown in FIG. 8B.

Note that the I ² CI / O expander 615 is supplied with a voltage Vcc that is a power supply voltage of the I ² CI / O expander 615. Although not shown in FIG. 10, the I ² CI / O expander 615 provides signal lines for the ports 0 to 15 for driving the LEDs (decoration device 200) related to the decoration control device 610 (see FIG. 8A). ) Is output.

The signal output from the I ² CI / O expander 615 of the decoration control device 610 shown in FIG. 10 to the upstream decoration control device 610 connected to the upstream connector 611 or the relay board 600 via the connection line SDA, and the upstream connector 611 In order to remove the noise of the signal input via the connection line SDA from the upstream decoration control device 610 or relay board 600 connected to the I ² CI / O expander 615 of the decoration control device 610 shown in FIG. The zener diode ZD1041 is connected to the internal connection line SDA1011.

  Specifically, the internal connection line SDA1011 branches at a branch 1003, the branched internal connection line SDA1011 is connected to the cathode side of the Zener diode ZD1041, and the anode side of the Zener diode ZD1041 is grounded.

  For this reason, a voltage (for example, a pulsed noise signal) higher than a predetermined voltage applied to the internal connection line SDA1011 is released by the Zener diode ZD1041.

Further, noise of a signal input from the upstream decoration control device 610 or the relay board 600 connected to the upstream connector 611 to the I ² CI / O expander 615 of the decoration control device 610 shown in FIG. 10 via the connection line SCL. In order to eliminate this, a Zener diode ZD942 is connected to the internal connection line SCL1012.

  Specifically, the internal connection line SCL1012 branches at a branch 1004, the branched internal connection line SCL1012 is connected to the cathode side of the Zener diode ZD1042, and the anode side of the Zener diode ZD1042 is grounded.

  For this reason, a voltage (for example, a pulsed noise signal) applied to the internal connection line SCL 1012 at a predetermined level or more is released by the Zener diode ZD1042.

The I ² CI / O expander 615 of the decoration control device 610 shown in FIG. 10 is connected to the downstream decoration control device 610 connected to the downstream connector 612 via the connection line SDA and to the downstream connector 612. In order to remove noise from the signal input via the connection line SDA from the downstream decoration control device 610 to the I ² CI / O expander 615 of the decoration control device shown in FIG. ZD1043 is connected.

  Specifically, the internal connection line SDA1011 branches at a branch 1005, the branched internal connection line SDA1011 is connected to the cathode side of the Zener diode ZD1043, and the anode side of the Zener diode ZD1043 is grounded.

  For this reason, a voltage (for example, a pulse noise signal) of a predetermined level or more applied to the internal connection line SDA1011 is released by the Zener diode ZD1043.

Further, in order to remove noise of a signal input via the connection line SCL from the I ² CI / O expander 615 of the decoration control device 610 shown in FIG. 10 to the downstream decoration control device 610 connected to the downstream connector 612. In addition, a Zener diode ZD1044 is connected to the internal connection line SCL1012.

  Specifically, the internal connection line SCL1012 branches at a branch 1006, the branched internal connection line SCL1012 is connected to the cathode side of the Zener diode ZD1044, and the anode side of the Zener diode ZD1044 is grounded.

  For this reason, a voltage (for example, a pulse noise signal) applied to the internal connection line SCL 1012 is more than a predetermined voltage and is released by the Zener diode ZD1044.

The internal connection line Vcc1071 extending from the Vcc terminal of the upstream connector 611 connected to the connection line Vcc for supplying the power supply voltage to the I ² CI / O expander 615 of the decoration control device 610, and the GND terminal of the upstream connector 611 extending to the ground The internal connection line GND 1072 is connected via a smoothing capacitor C 1061 and a bypass capacitor 1062.

  The smoothing capacitor C1061 is the same capacitor as the smoothing capacitor C961 shown in FIG. 9, and the bypass capacitor CP1062 is the same capacitor as the bypass capacitor 962 shown in FIG.

  Further, the internal connection line Vcc 1073 extending from the Vcc terminal of the downstream connector 612 and the internal connection line GND 1074 extending from the GND terminal are connected via a smoothing capacitor C 1061 and a bypass capacitor 1062.

  FIG. 11 is an explanatory diagram of the slave address 1100 included in the data output from the presentation control device 550 to the decoration control device 610 according to the first embodiment of this invention.

  The slave address 1100 includes a fixed address part 1101 consisting of upper 3 bits and a variable address part 1102 consisting of lower 5 bits.

The fixed address portion 1101 is an address that is preset with “110” and cannot be changed by the I ² CI / O expander 615.

Variable address portion 1102 is a configurable address I ² CI / O expander 615, corresponding to a pattern that is set to A0~A3 terminal of I ² CI / O expander 615 to be controlled 4 A bit I ² CI / O expander address 1103 and 1-bit R / W identification data 1104 indicating whether the data is a read request or a write request are included.

  Since the effect control data output from the effect control device 550 to the decoration control device 610 is a write request, “0” is normally registered in the R / W identification data 1104.

FIG. 12 is an explanatory diagram of the I ² CI / O expander address table 1200 according to the first embodiment of this invention.

The I ² CI / O expander address table 1200 is a table managed by the master IC 570. The I ² CI / O expander address table 1200 shows the correspondence between the slave address 1201 and the I ² CI / O expander address 1202.

The slave address 1201 stores the slave address of the decoration control device 610 specified by the effect control device 550 as a transmission / reception target. As described above with reference to FIG. 13, the slave address is configured by combining a fixed address portion composed of upper 3 bits, a 4-bit I ² CI / O expander address, and 1-bit R / W identification data. .

In the I ² CI / O expander address 1202, a 4-bit I ² CI / O expander address corresponding to each slave address is registered as described above with reference to FIGS. 8A and 8B.

However, among the I ² CI / O expander addresses, the address “1000” and the address “1011” cannot be used as unique addresses for identifying the I ² CI / O expanders 615 from each other.

  “1000” is used as a default value at the time of power-on of an address (all call address) specified when outputting commands to all the decoration control devices 610. “1011” is a common address used when all the decoration control devices 610 connected to the master IC 570 are unconditionally reset by software.

As described above, since there are 14 unique addresses that can be set in the I ² CI / O expander 615 of the decoration control device 610, the effect control device 550 controls the 14 I ² CI / O expanders 615. it can. In addition, since one decoration control device 610 includes PORT0 to PORT15, it can control 16 (in other words, 16 types) LEDs. Therefore, the production control device 550 can control 224 (in other words, 224 types) LEDs.

FIG. 13 is a diagram for explaining a work register assigned to the output setting register 635 (see FIG. 7) included in the I ² CI / O expander 615 according to the first embodiment of this invention.

A work register (device register) and a control register (control register) are assigned to the output setting register 635 of the I ² CI / O expander 615. Work register, and information for setting the predefined relative I ² CI / O Expander 615, the output of the effect device connected to the I ² CI / O expander 615 (e.g., LED) Information for specifying an aspect is stored. The control register also stores information defining the procedure for writing data to the work register.

  As shown in FIG. 13, the work register has a configuration in which a plurality of pieces of information are distributed and stored in different storage areas, and different register numbers are assigned to the respective storage areas.

A register name “MODE1” is assigned to the storage area with the register number “00h”, and a register name “MODE2” is assigned to the storage area with the register number “01h”. Yes. When values are written in the storage areas of the register numbers “00h” and “01h”, the I ² CI / O expander 615 is initialized based on the written values.

Register names “PWM0” to “PWM15” are assigned to storage areas having register numbers “02h” to “11h”. When a value is written in any of the storage areas of register numbers “02h” to “11h”, the value is written out of the 16 LEDs constituting the light emitting device connected to the I ² CI / O expander 615. The luminance of the LED corresponding to the register number is adjusted based on the written value. For example, when a value is written in the storage area of the register number “02h”, the luminance of the LED 0 connected to the port 0 shown in FIG. 8A is adjusted.

When the accessory driving SOL 560 is connected to the I ² CI / O expander 615, the accessory driving SOL 560 is energized in the storage area of the register number corresponding to the port to which the accessory driving SOL 560 is connected. A value indicating whether to operate or not to energize is written.

When the accessory driving MOT 561 is connected to the I ² CI / O expander 615, the target rotation of the accessory driving MOT 561 is stored in the storage area of the register number corresponding to the port to which the accessory driving MOT 561 is connected. A value indicating the position is written.

  A register name “GRPPWM” is assigned to the storage area with the register number “12h”, and a register name “GRPFREQ” is assigned to the storage area with the register number “13h”. When a value is written in the storage areas of the register numbers “12h” and “13h”, a blinking pattern of all LEDs (16 LEDs) is set based on the written value.

  Specifically, when a value is written in the storage area of the register number “12h”, the duty cycle that is the on / off ratio of the entire LED is set, and the value is stored in the storage area of the register number “13h”. When written, the blinking cycle of the entire LED is set.

  A register name “LEDOUT0” is given to the storage area where the register number is “14h”. When a value is written in the storage area of the register number “14h”, the output states of the LEDs 0 to LED3 are set based on the written value.

  A register name “LEDOUT1” is given to the storage area where the register number is “15h”. When a value is written in the storage area of the register number “15h”, the output states of the LEDs 4 to 7 are set based on the written value.

  A register name “LEDOUT2” is assigned to the storage area where the register number is “16h”. When a value is written in the storage area of the register number “16h”, the output states of the LEDs 8 to 11 are set based on the written value.

  A register name “LEDOUT3” is given to the storage area where the register number is “17h”. When a value is written in the storage area of the register number “17h”, the output states of the LEDs 12 to 15 are set based on the written value.

  Register names “SUBADR1” to “SUBADR3” are assigned to storage areas having register numbers “18h” to “1Ah”. When values are written in the storage areas of the register numbers “18h” to “1Ah”, the first subaddress to the third subaddress are set based on the written values.

  A register name “ALLCALLADR” is given to the storage area whose register number is “1Bh”. When a value is written in the storage area of the register number “1Bh”, an all-call address is set based on the written value.

  FIG. 14 is an explanatory diagram of a start condition and a stop condition for data output from the master IC 570 according to the first embodiment of this invention via the connection line SDA and the connection line SCL.

  The signal level of the connection line SCL is HIGH when data is not transmitted, and the master IC 570 changes the signal level of the connection line SCL from LOW to HIGH when outputting data to the decoration control device 610. Control device 610 acts as a strobe signal for taking in data on connection line SDA.

  The signal level of the connection line SDA is HIGH when data is not transmitted, and data is output from the connection line SDA in accordance with the clock signal of the connection line SCL.

  Master IC 570 changes the signal level of connection line SDA from HIGH to LOW while maintaining the signal level of connection line SCL at HIGH, and outputs a signal that is a start condition indicating that data output starts. .

The I ² CI / O expander 615 of the decoration control device 610 recognizes that data output starts when a signal serving as a start condition is input from the connection line SDA and the connection line SCL.

  The master IC 570 changes the signal level of the connection line SDA from LOW to HIGH while maintaining the signal level of the connection line SCL at HIGH, and outputs a signal indicating a stop condition indicating that data output is completed. .

The I ² CI / O expander 615 of the decoration control device 610 grasps that the output of data ends when the stop condition is input.

  FIG. 15 is a timing chart at which the decoration control device 610 to which the data output from the master IC 570 according to the first embodiment of the present invention is input outputs a response signal.

  The decoration control device 610 counts the number of changes in the signal level of the connection line SCL after the start condition is satisfied, and takes in data input from the connection line SDA in accordance with the clock signal of the connection line SCL.

  Then, the decoration control device 610 outputs a response signal to the master IC 570 via the connection line SDA immediately after the start condition is satisfied and immediately before the signal line change number of the connection line SCL reaches nine. In other words, the decoration control device 610 receives a response signal via the connection line SDA when the signal level of the connection line SCL changes from HIGH to LOW after taking the 8th bit data from the connection line SDA. Output.

  As shown in the figure, a response signal (ACK response signal) indicating that the data has been successfully received is indicated by a LOW level, and a response signal (NACK response signal, FIG. (Corresponding to no ACK output) is indicated by a HIGH level.

  Further, when the signal level of the connection line SCL changes eight times after the start condition is satisfied, the master IC 570 waits for a response signal from the decoration control device 610 by releasing the connection line SDA. Then, the master IC 570 changes the signal level of the connection line SCL while releasing the connection line SDA, and takes in the response signal from the decoration control device 610.

  FIG. 16 is a timing chart of signal levels of the connection line SDA and the connection line SCL when the master IC 570 according to the first embodiment of the present invention outputs effect control data.

  First, when starting output of data, the master IC 570 changes the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH, thereby indicating a start condition signal. And the decoration control device 610 is notified that data will be output.

  Next, the master IC 570 outputs the slave address of the decoration control device 610 to be controlled consisting of 7 bits in total. Next, the master IC 570 outputs data indicating whether the write request is a read request to the eighth bit.

  The master IC 570 receives a response signal from the decoration control device 610 when the signal level of the connection line SCL becomes HIGH for the ninth time. Therefore, if the response signal is an ACK response signal, the signal level of the connection line SDA is LOW. If the response signal is NACK, the signal level of the connection line SDA changes to HIGH.

  Next, after outputting the address data, the master IC 570 outputs the data in the number of bits that is a multiple of 8. After outputting the eighth bit of data, master IC 570 outputs the ninth bit of data after waiting for an ACK response signal to be input. Thereafter, when data of a bit corresponding to a multiple of 8 is output, after confirming that an ACK response signal is input, a (multiple of 8 + 1) th bit is output and all data is output. Repeat until.

  If the master IC 570 outputs a bit that is a multiple of 8 after the data has been output and the ACK response signal is not received after a predetermined time, the master IC 570 assumes that the data transmission has failed and starts again. Send the condition. Next, the address data is output again via the connection line SDA, and the data is output again from the first bit while confirming the ACK response signal.

  The master IC 570 outputs the signal indicating the stop condition after outputting the data of the last bit of the data and waiting for the ACK response signal to be input.

  In FIG. 16, a total of 24 bits (slave address 8 bits, data 16 bits) are output from the time when the signal indicating the start condition is output until the time when the signal indicating the stop condition is output. , 24 bits or more, or 24 bits or less.

FIG. 17 shows the master IC 570 and the I ² CI / O expander 615 when the master IC 570 of the first embodiment of the present invention sets the effect control data in the decoration control device 610 by designating the slave individual address. It is a figure explaining the format of the data transmitted / received between.

The 8-bit data 1801 that is output first includes an address “A0 to A6” of the decoration control device 610 that is the target of data transmission, and a 1-bit R that indicates whether the data is a read request or a write request. / W identification data. Among the addresses “A0 to A6”, “A4 to A6” are fixed address portions having a value “110”, and “A0 to A3” are set to terminals A0 to A3 of the I ² CI / O expander 615. This corresponds to the address that has been set (see FIG. 8). The data 1801 corresponds to “ADDRESS” and “R / W” in FIG.

Next, the output 8-bit data 1802 includes setting data for the control register assigned to the output setting register 635 (see FIG. 7) of the I ² CI / O expander 615. This data 1802 corresponds to “DATA” transmitted first in FIG.

  Here, the control register will be described. The control register consists of 8 bits, and the upper 3 bits “AI0 to AI2” are automatic write parameters for designating the writing or reading method to the work register of the output setting register 635, and the lower 5 bits “D0 to D4” are the work. This is a register address that specifies an access start position (a start position at which writing starts or a start position at which reading starts) in the register.

  The automatic write parameter is accessed by the master IC 570 including only the area at the access start position specified by the register address (auto-increment is prohibited) or including the area adjacent to the area at the access start position specified. (Specifically, “000”, “100”, “101”, “110”, “111”) can be set.

  When a value of “000” is set in the automatic write parameter, auto-increment is prohibited, and only the area at the access start position specified by the register address is accessed, and the area other than the start position is not accessed. For example, if the register address is “10100”, only the storage area with the register number “14h” is accessed, and the other storage areas are not accessed.

  When the value of “100” is set in the auto-write parameter, auto-increment is permitted, and after accessing the area at the access start position specified by the register address, the area is accessed in order while moving the area in the direction of increasing register numbers repeat. Then, after accessing the storage area where the register number is “1Bh” at the end, the storage area where the register number is “00h” is accessed and accessed again sequentially while moving the area in the direction in which the register number increases. repeat. For example, if the register address is “10100”, after accessing the storage area where the register number is “14h”, the register number is “15h” → “16h” →→→ “1Bh” → “00h” → “01h” →... (Ie, all areas) are repeatedly accessed.

  When the value of “101” is set in the automatic write parameter, the register number is set after accessing the area of the access start position specified by the register address, as in the case of setting the value of “100” in the automatic write parameter Access is repeated in order while moving the area in the direction of increasing. However, once the storage area where the register number is “11h” is accessed, the storage area where the register number is “02h” is accessed, and thereafter the section where the register numbers are “02h” to “11h”. The recording area (area related to LED brightness adjustment) is repeatedly accessed. For example, if the register address is “10100”, after accessing the storage area where the register number is “14h”, the register number is “15h” → “16h” →→→ “1Bh” → “00h” → “01h” →... After accessing the storage area where the register number is “11h”, the area where the register number is “02h” → “03h” → ··· “11h” → “02h” → “03h” → ··· , Repeatedly access.

  When the value “110” is set in the automatic write parameter, the register number is set after accessing the area of the access start position specified by the register address, as in the case where the value “100” is set in the automatic write parameter. Access is repeated in order while moving the area in the direction of increasing. However, once the storage area where the register number is “13h” is accessed, the storage area where the register number is “12h” is accessed, and thereafter the section where the register numbers are “12h” to “13h”. The recording area (area related to the LED blinking cycle) is repeatedly accessed. For example, if the register address is “10100”, after accessing the storage area where the register number is “14h”, the register number is “15h” → “16h” →→→ “1Bh” → “00h” → “01h” →... Then, after accessing the storage area where the register number is “13h”, the area where the register number is “12h” → “13h” → “12h” → “13h” →.

  When the value of “111” is set in the automatic write parameter, the register number is set after accessing the area of the access start position specified by the register address, as in the case of setting the value of “100” in the automatic write parameter. Access is repeated in order while moving the area in the direction of increasing. However, once the storage area where the register number is “13h” is accessed, the storage area where the register number is “02h” is accessed, and thereafter the section where the register numbers are “02h” to “13h”. The recording area (area related to the LED brightness and blinking cycle) is repeatedly accessed. For example, if the register address is “10100”, after accessing the storage area where the register number is “14h”, the register number is “15h” → “16h” →→→ “1Bh” → “00h” → “01h” →... After accessing the storage area where the register number is “13h”, the area where the register number is “02h” → “03h” → ··· “13h” → “02h” → “03h” → ··· , Repeatedly access.

  Returning to FIG. 17, the setting data 1803 to the work register is output following the setting data 1802 to the control register. This setting data 1803 corresponds to “DATA” transmitted after the second in FIG.

  When the automatic writing parameter is “000”, the setting data 1803 is 8-bit data necessary for updating one storage area designated by the register address. When the automatic write parameter is set to a value other than “000”, the setting data 1803 is a multiple of 8 necessary for repeatedly updating a plurality of areas starting from the storage area specified by the register address. Bit data.

FIG. 18 shows the master IC 570 and the I ² CI / O expander 615 when the master IC 570 according to the first embodiment of the present invention designates the slave individual address and sets the effect control data in the decoration control device 610. Specific numerical values are applied to the production control data exchanged with the. This figure illustrates the presentation control data that prohibits auto-increment and updates only one storage area of the work register, and is connected to the PORT0 terminal to the PORT3 terminal of the I ² CI / O expander 615. The case where the light emission state of LED is updated is assumed.

First, “1101100” indicating the slave address of the I ² CI / O expander 615 of the destination decoration control device 610 is assigned to the 8-bit data 1901 output first.

The 8-bit data 1902 to be output next is set in the control register of the output setting register 635 of the I ² CI / O expander 615 assigned to set the automatic writing parameter and LED output data. Value to be included.

Here, since the light emission state of the LED connected to the PORT0 terminal to the PORT3 terminal of the I ² CI / O expander 615 is set, LEDOUT0 (address = 10100) is designated as the register address.

  Note that “000” is designated in the auto-write parameter to prohibit auto-increment.

Next, the output 8-bit data 1903 includes data for setting the light emission mode of the decoration device 620 controlled by the destination decoration control device 610. Specifically, data set in the LEDOUT0 register is assigned. As a result, the light emission state (lighted, extinguished, blinking, etc.) of the LEDs connected to the PORT0 to PORT3 terminals of the I ² CI / O expander 615 is designated, and the LEDs emit light in the designated state.

In this way, the light emission state of the LED PORT0 terminal ~PORT3 terminal I ² CI / O expander 615 is controlled, the other PORT terminal I ² CI / O expander 615 (PORT4~PORT15) also Control can be performed by specifying the value of data 1902 to be written to the control register and setting output data 1903. Even if a motor or solenoid is connected to the PORT terminal, the same control is performed.

  FIG. 19 is a diagram illustrating another form of effect control data according to the first embodiment of this invention. In this figure, it is assumed that auto-increment is permitted and all storage areas of the work register are updated, and the transmission order of each data included in the presentation control data is defined.

  First, the master IC 570 transmits 8-bit data (data having the same format as the data 1901 in FIG. 18) that can specify the individual address of the decoration control device 610 to be controlled.

Next, the master IC 570 transmits data (data having the same format as the data 1902 in FIG. 18) set in the control register of the output setting register 635 of the I ² CI / O expander 615 to be controlled. In this figure, since the auto-increment is permitted and all the storage areas of the work register are updated, “100” is designated as the automatic write parameter, and the register address that designates the write destination or the read start position is designated. “00h” which is the head area of the work register is designated.

For this reason, in the I ² CI / O expander 615 of the decoration control device 610 to be controlled after receiving the control register setting value, the storage area (MODE1 register) with the register number “00h” is updated first. Will be.

Next, after transmitting the control register set value, the master IC 570 transmits a value (total of 8 bits) to be written to the MODE1 register. When the I ² CI / O expander 615 receives the write value, it updates the value of the MODE 1 register, increments the register number, and prepares to update the next “01h” storage area (MODE 2 register). .

Next, the master IC 570 transmits values to be written to the MODE2 register (8 bits in total), and thereafter transmits the set values in order to the remaining storage area registers whose register numbers are “02h” to “1Bh”. . Each time the I ² CI / O expander 615 receives the write value, the I ² CI / O expander 615 updates the value of the corresponding register, increments the register number, and repeats the preparation for updating the next storage area. The values of all the registers “00h” to “1Bh” assigned to are updated.

When the I ² CI / O expander 615 updates the storage area of “1Bh”, which is the last of the work registers, the register number is changed to “00h” and waits for the update of the MODE1 register.

20, when the master IC570 of the first embodiment of the present invention initializes the I ² CI / O expander 615, initialization instruction data transmitted from the master IC570 to I ² CI / O expander 615 It is a figure explaining the data format of.

  When the CPU 551 of the effect control device 550 instructs the master IC 570 to initialize the decoration control device 610, the master IC 570 transmits initialization instruction data to all the decoration control devices 610 connected thereto. .

  First, the 8-bit data 2001 output includes a fixed address “110” shown in FIG. 18 and a reset address “1011” (see FIG. 12), which is a common address. This data 2001 corresponds to “ADDRESS” in FIG. 16, and “0” indicating writing is set in the bit of “R / W”.

  In the next 8-bit data 2002 to be output, the first predetermined value “10100101” is output, and in the next 8-bit data 2003 to be output, the second predetermined value “01011010” is output. The data 2002 corresponds to “DATA” transmitted first in FIG. 16, and the data 2003 corresponds to “DATA” transmitted second in FIG.

When all the I ² CI / O expanders 615 connected to the master IC 570 receive initialization instruction data including a reset address, a first predetermined value, and a second predetermined value, the I ² CI / O expander 615 initializes itself.

After the output of the reset address, to that outputs a first predetermined value and second predetermined value, even though the master IC570 is not sending a reset address "1011", the influence such as noise, I ² This is to prevent the CI / O expander 615 from erroneously fetching the reset address “1011” and performing initialization at an incorrect timing.

Further, the reset address is an address common to all (in other words, a plurality) I ² CI / O expanders 615, unlike the individual address. Therefore, only transmit once initialization instruction data including the reset address, it means that initialize Select I ² CI / O expander 615 all (plural), I ² CI / O Aix Compared with the method of individually selecting the panda 615 and instructing initialization, it is possible to instruct initialization at high speed.

  In FIG. 20, the first predetermined value and the second predetermined value are different from each other, but may be the same value. Further, either the first predetermined value or the second predetermined value may be transmitted once.

  FIG. 21 is a diagram illustrating the abnormality determination table 2100 according to the first embodiment of this invention.

The abnormality determination table 2100 is stored in the RAM 553 of the effect control device 550. The abnormality determination table 2100 monitors the connection state between the master IC 570 of the production control device 550 and the I ² CI / O expander 615 connected to the master IC 570, and corresponds to the connection state confirmation result, An error flag 2105 described later corresponding to the corresponding I ² CI / O expander 615 is set.

  The abnormality determination table 2100 includes an I / O expander address 2101, a slave address 2102, an error counter 2103, a comparison value 2104, and an error flag 2105.

The I / O expander address 2101 corresponds to the address (see FIG. 8) set at the terminals A0 to A3 of the I ² CI / O expander 615 connected to the master IC 570.

In the slave address 2102, the slave address registered in the I ² CI / O expander address table 1200 shown in FIG. 12 is registered.

When the error counter 2103 monitors whether or not the ACK from the I ² CI / O expander 615 has been received in response to the transmission of the effect control data from the master IC 570 to the I ² CI / O expander 615, It is incremented when it fails to receive this ACK twice in succession.

A predetermined value is registered in the comparison value 2104. In the error flag 2105, an error flag indicating whether or not an abnormality has occurred in the connection state of the entry with the I ² CI / O expander 615 is registered.

Specifically, when the incremented value of the error counter 2103 reaches a predetermined value registered in the comparison value 2104, the error flag 2105 is set to ON, and the I ² CI / O expander 615 of the entry. It is registered that an error has occurred.

Note that the “0110” I ² CI / O expander 615 registered in the I / O expander address 2101 controls movable devices such as the accessory driving SOL 560 and the accessory driving MOT 561 as shown in FIG. 8B. Yes. Therefore, the decoration control device 610 including the I ² CI / O expander 615 is referred to as a movable control device (movable group unit control means).

On the other hand, the I ² CI / O expander 615 other than “0110” registered in the I / O expander address 2101 controls a light emitting device such as an LED as shown in FIG. 8A. For this reason, the decoration control device 610 including the I ² CI / O expander 615 is referred to as a light emission control device (light emission group unit control means) in order to distinguish it from the aforementioned movable control device.

  In FIG. 21, there is no entry for the movable control device (the value registered in the I / O expander address 2101 is “0110”), and only the entry for the light emission control device is registered.

  When an abnormality occurs in the movable control device, the accessory driving MOT 561 rotates too much and the movable accessory 60 moves beyond the operable range, and the movable accessory 60 and the vicinity of the movable accessory In order to prevent the members from being damaged, it is necessary to determine the abnormality in a shorter time than the light emission control device. Therefore, since the connection monitoring timing of the movable control device and the connection monitoring timing of the light emission control device are different, in other words, the configuration of the connection monitoring of the movable control device is different from the configuration of the connection monitoring of the light emission control device. The entry of the movable control device is excluded from 2100.

  Specifically, in this embodiment, as will be described later, the data output process (see FIG. 22) of the light emission control device is executed in synchronization with the VDP interrupt (approximately 33.3 ms cycle), and is movable. The data output process of the control device is executed in synchronization with the timer interrupt (2 ms cycle).

As described above, in response to the second transmission of the effect control data from the master IC 570 to the I ² CI / O expander 615 provided in the light emission control device, an ACK from the I ² CI / O expander 615 is received. If not received, the error counter 2103 is incremented.

  Therefore, when an abnormality has occurred in the light emission control device, the execution period of the data output process is 33 ms and the comparison value 2104 is “300”, so the light emission control device is abnormal in 33.3 ms × 300≈10 s. Detect that occurred.

  When an abnormality has occurred in the movable control device, the data output processing execution cycle is 2 ms, and as will be described later, it is detected that an abnormality has occurred without waiting for the next execution cycle. It is possible to detect that an abnormality has occurred in the movable control device in a very short time (about 2 ms).

  For this reason, the error determination of the movable control device is performed more frequently than the error determination of the light emission control device, and it is possible to detect that an abnormality has occurred in the movable control device earlier than the abnormality has occurred in the light emission control device. Therefore, it is possible to prevent the movable accessory 60 from moving beyond the operable range and damaging the movable accessory 60 and members in the vicinity of the movable accessory.

  On the other hand, a light emitting device such as an LED is less likely to be damaged due to a malfunction, and therefore no problem occurs even if it takes time to determine an abnormality related to the light emission control device.

  Therefore, the determination cycle is limited to the decoration control device 610 that needs to perform the abnormality determination in a short time, and the abnormality determination of the other decoration control devices 610 is performed with a sufficient period, so that the processing load is balanced. It is possible to execute the abnormality determination process in consideration.

  FIG. 22 is a flowchart of processing by the effect control device 550 according to the first embodiment of the present invention.

  The processing of the effect control device 550 shown in FIG. 22 is executed by the CPU 551 of the effect control device 550.

  When the effect control device 550 is turned on, the effect control device 550 first executes the processing of steps 2201 to 2210 and then synchronizes with the image update cycle from the VDP 556 (for example, a sync signal with a 33 ms second cycle). Is input to the CPU 551. Thereafter, each time the synchronization signal synchronized with the image update cycle is input from the VDP 556 to the CPU 551, the processing of steps 2204 to 2210 is repeatedly executed.

  First, the effect control device 550 initializes the RAM 553 of the effect control device 550 (2201). At this time, the initial control data output from the CPU 551 to the VDP 556 and the sound LSI 557 is also generated from the time when the power to the production control device 550 is turned on.

Next, the effect control device 550 executes an I ² C initial reset process for initializing the master IC 570 and the decoration control device 610 connected to the master IC 570 (2202). Details of the I ² C initial reset processing will be described with reference to FIG. When this I ² C initial reset process is executed, initialization operations of the accessory driving MOT 561 and the accessory driving SOL 560 are also started.

  Then, the production control device 550 permits the reception of the synchronization signal (VDP interrupt) synchronized with the image update cycle and the timer interrupt from the VDP 556 (2203).

  Then, in order to display the image on the display device 53, the effect control device 550 outputs data serving as a command for displaying the image on the VDP 556 (2204), and outputs the sound from the speaker 30 according to the gaming state. The sound control data is output to the sound LSI 557, and the sound LSI 557 is caused to output sound from the speaker 30 based on the sound control data (2205).

  Next, the effect control device 550 executes light emission control slave output processing for outputting effect control data from the master IC 570 to the light emission control device (2206). Details of the light emission control slave output processing will be described with reference to FIG.

  Then, the production control device 550 edits the data output next to the VDP 556 (2207), edits the sound control data output next to the sound LSI 557 (2208), and then sends it to the light emission control device of each group. The production control data to be output is edited (2209).

Next, the effect control device 550 refers to the abnormality determination table 2100 and regards that the reset condition is satisfied when the error flags 2105 of all the light emission control devices are ON, and the master IC 570 and the accessory driving MOT 561 The I ² C ad hoc reset process instructing initialization of all the I ² CI / O expanders 615 and the accessory driving SOL 560 connected to the master IC 570 is executed (2210), and then a synchronization signal is sent from the VDP 556 to the CPU 551. Wait for input. Details of the I ² C occasional reset process will be described with reference to FIG.

In the process according to FIG. 22, in synchronization with the cycle of updating the image on the display device 53, the effect control data is transmitted from the master IC 570 of the effect control device 550 to the I ² CI / O expander 615 of the decoration control device 610. ^{2 Since the} CI / O expander 615 controls the decoration device 620 based on the received effect control data, the effect on the display device 53 and the effect on the decoration device 620 are harmonized, and the player does not feel uncomfortable. Can be increased.

Also, whenever the decoration control device 610 receives the effect control data transmitted from the master IC 570 in synchronization with the cycle of updating the image on the display device 53, the I ² CI / O expander 615 updates the work register. The value is updated. Therefore, since the value of the work register is updated to the latest state every time, even if the value of the work register is destroyed due to noise or the like, it can be restored to a normal value.

  In addition, since the error determination process executed in the process of step 2211 is executed in synchronization with the cycle of updating the image of the display device 53, the error determination execution frequency can be made appropriate, that is, the error determination process execution frequency. If there is too much, the processing load of the CPU 551 of the effect control device 550 increases, and conversely, if the error determination processing is executed too little, it will not be possible to properly detect that an abnormality has occurred. Therefore, processing errors can be prevented by performing error determination at an appropriate frequency.

FIG. 23 is a flowchart of the I ² C initial reset process according to the first embodiment of this invention.

The I ² C initial reset process is a process for instructing initialization of all the I ² CI / O expanders 615 connected to the master IC 570 and the master IC 570 immediately after the power to the effect control device 550 is turned on. This is executed in the process of step 2202 shown in FIG. During the process, the start of the initialization operation of the accessory driving MOT 561 and the accessory driving SOL 560 is instructed. First, the CPU 551 of the effect control device 550 displays a reset request flag indicating that initialization is in progress. Setting is performed (2301), a reset pulse is input to the master IC 570 via the input / output I / F 558 and the NOR gate circuit 590, and the master IC 570 is initialized (hard reset) in hardware (2302).

  In the hard reset, the reset circuit (not shown) of the master IC 570 is connected to the RESET terminal of the master IC 570, and the voltage applied to the RESET terminal is held at a low level for a predetermined time, so that the reset circuit of the master IC 570 becomes the master circuit. This means resetting the IC 570 itself. The RESET terminal functions as an initialization signal input instruction terminal in the present embodiment.

  In the present embodiment, the reset signal applied to the RESET terminal is also connected to other circuits provided in the effect control device 550 as described above. The other circuits are, for example, the VDP 556 and the sound LSI 557, and are initialized by the CPU 551 when the presentation control device 550 is powered on and activated. Therefore, when the power is turned on, these circuits can be initialized together with the master IC 570 by a hard reset, so that high-speed processing can be expected.

Next, the effect control device 550 outputs the initialization instruction data from the master IC 570 in order to initialize the I ² CI / O expander 615 of all the decoration control devices 610 connected to the master IC 570. Is executed (2303). The slave reset process will be described in detail with reference to FIG.

Next, since the initialization of the master IC 570 and the I ² CI / O expander 615 has been completed in the process of step 2302 and the process of step 2303, the effect control device 550 cancels the reset request flag (2304). Then, the effect control device 550 sets a motor initialization flag indicating that the accessory driving MOT 561 is being initialized (2305). The initialization of the accessory driving MOT 561 is a process of returning the rotation axis of the accessory driving MOT 561 to the initial position, and is performed by a timer interrupt process shown in FIG.

  Next, the effect control device 550 sets motor output data to be output to the accessory driving MOT 561 in the RAM 553 when initializing the accessory driving MOT 561 (2306). Then, in order to initialize the accessory driving SOL 560, the effect control device 550 outputs to the accessory driving SOL 560 off data that sets the energization state of the accessory driving SOL 560 to the non-energizing state (2307), which is shown in FIG. Proceed to step 2203. The initialization of the accessory driving SOL 560 is to change the energized state of the accessory driving SOL 560 to a non-energized state.

  The CPU 551 inputs a reset pulse to the master IC 570 via the input / output I / F 558 and the NOR gate circuit 590 to reset the master IC 570 in hardware. However, the CPU 551 resets the reset register 573 via the bus 563. The master IC 570 may be reset by software by writing information into the.

  FIG. 24 is a flowchart of slave reset processing according to the first embodiment of this invention.

Slave reset process is a process of transmitting an initialization instruction data for initializing the I ² CI / O expander 615 to I ² CI / O expander 615, the process of step 2303 shown in FIG. 23, and FIG. This is executed in the process of step 2706 shown in FIG.

The initialization instruction data is transmitted from the master IC 570 in the byte mode. In byte mode, the master IC570, every time one byte transmit data to I ² CI / O expander 615 receives the ACK or NACK from the I ² CI / O expander 615, receiving either an ACK or NACK Even in this case, an interrupt signal is output to the CPU 551. That is, if transmission of 1-byte data from the master IC 570 to the I ² CI / O expander 615 is completed, an interrupt signal is always output from the master IC 570 to the CPU 551 regardless of reception of ACK / NACK. .

  First, the master IC 570 changes the signal levels of the connection line SDA and the connection line SCL to a signal level indicating a start condition (2401).

  Next, the CPU 551 sets 1-byte data indicating the reset address (see FIG. 20) in the output BUF 572 (2402).

  Then, the CPU 551 starts activation of the monitoring timer for the byte mode in order to monitor the time from when the master IC 570 is instructed to start data transmission until the master IC 570 transmits the interrupt signal to the CPU 551 ( 2403). Hereinafter, this monitoring time is referred to as byte mode monitoring time.

  If the CPU 551 does not receive an interrupt signal from the master IC 570 even after a predetermined time has elapsed since the start of monitoring of the byte mode time, the CPU 551 determines that a timeout has occurred and interrupts data transmission in order to interrupt data transmission. Then, the stop condition is output (2415), and then the process returns to step 2401 to output the start condition to the master IC 570 again, and then the initialization instruction data is transmitted from the first data.

Next, the master IC 570 outputs the reset address set in the output buffer 572 in the process of step 2402 to the I ² CI / O expander 615 (2404). When outputting the reset address, the master IC 570 temporarily turns off the driver 576A to release the connection line SDA (change it to high level). If the connection line SDA is not released (even if the driver 576A is turned off, the connection line SDA remains at a low level instead of a high level), the reset address output is It waits until the line SDA is released (the connection line SDA becomes high level).

  Next, the master IC 570 determines whether or not an ACK response signal has been input to the master IC 570 within a predetermined time (a monitoring time shorter than the above-described byte mode monitoring time) from the completion of data output for one byte. Is confirmed (2405).

  The master IC 570 determines whether or not an ACK response signal is input within a predetermined time after the data is output based on the confirmation result of the processing in step 2405 (2406).

If it is determined in step 2406 that an ACK response signal has not been input within a predetermined time after data is output, master IC 570 sets information indicating that the response signal is NACK in status REG579. Then, generate an interrupt signal. As a result, the CPU 551 is notified that the NACK response signal has been received from the I ² CI / O expander 615. At this time, the CPU 551 ends the time monitoring in the byte mode (2407).

  Next, in order to interrupt data transmission, the CPU causes the master IC 570 to output a stop condition (2415), and then returns to the processing of step 2401, outputs the start condition to the master IC 570 again, and then initializes the instruction data. Is output again.

If it is determined in step 2406 that an ACK response signal is input within a predetermined time after the data is output, the master IC 570 sets information indicating that the response signal is ACK in the status REG579. Then, an interrupt signal is generated. As a result, the CPU 551 is notified that the ACK response signal has been received from the I ² CI / O expander 615. At this time, the CPU 551 ends the time monitoring in the byte mode (2408).

  The CPU 551 outputs all three types of data constituting the initialization instruction data (data 2001 including the reset address, data 2002 of the first predetermined value, and data 2003 of the second predetermined value shown in FIG. 20). It is determined whether or not (2409). Since the output order of these data is determined in advance, in the processing of step 2409, it may be determined whether or not it is immediately after the data 2003 of the second predetermined value is output.

  If it is determined in step 2409 that all the data constituting the initialization instruction data has been output, that is, if data indicating the second predetermined value shown in FIG. 20 has been output, the master IC 570 connects The signal levels of the line SDA and the connection line SCL are changed to signal levels indicating a stop condition (2410), and the slave reset process is terminated.

  If it is determined in step 2409 that all data constituting the initialization instruction data has not been output, the CPU 551 sets 1-byte data to be transmitted next in the output BUF 572 (2411). In the processing of step 2411 executed immediately after outputting the reset address, the output BUF 572 is set with the first predetermined value data 2002 shown in FIG. 20 and executed immediately after outputting the first predetermined value data. In step 2411, the output BUF 572 is set with the second predetermined value data 2002 shown in FIG.

  Then, the CPU 551 starts activation of the monitoring timer for the byte mode in order to monitor the time from when the master IC 570 is instructed to start data transmission until the master IC 570 transmits the interrupt signal to the CPU 551 ( 2412).

  Next, the master IC 570 monitors the voltage level of the connection line SDA, confirms that the connection line SDA is released (2413), and then outputs 1-byte data set in the output BUF 572 ( 2414), the process proceeds to step 2405. In the processing of step 2413, the connection line SDA is occupied by the response signal until the output of the response signal from the group unit control means is completed, so that the master IC 570 outputs the response signal from the group unit control means. This is a process of waiting until the connection line SDA is released.

  As described above, every time 1-byte data is output (that is, during the transmission of 3-byte initialization data), the initialization instruction data indicates whether or not there is a response signal for the output 1-byte data. Is transmitted in a byte mode for monitoring whether or not an output signal is output.

  In the processing of step 2403 and the processing of step 2412, the CPU 551 monitors the time from when the 1-byte data is transmitted until the interrupt signal is output from the master IC 570. However, the master IC 570 itself You may monitor the time after transmitting 1-byte data until it outputs an interrupt signal from master IC570.

  FIG. 25 is a flowchart of light emission control slave output processing according to the first embodiment of this invention.

The light emission control slave output process is a process of transmitting issuance control data to the I ² CI / O expander 615 (light emission control apparatus) connected to the light emitting apparatus, and is executed in the process of step 2206 shown in FIG.

  The effect control device 550 selects one light emission control device from a plurality of light emission control devices (2501), and executes slave continuous processing for outputting data from the master IC 570 to the light emission control device selected in the processing of step 2501. (2502). Details of the slave continuous processing will be described with reference to FIG.

  Then, the effect control device 550 determines whether data is output to all the light emission control devices (2503).

  If it is determined in step 2503 that data has not been output to all the light emission control devices, the next light emission decoration control device is selected (2504), and the light emission control device selected in step 2504 is mastered. Slave continuous processing for outputting data from the IC 570 is executed (2502).

  On the other hand, if it is determined in step 2503 that data has been output to all the light emission control devices, the CPU 551 causes the master IC 570 to output a stop condition to end the light emission control slave output processing (2505), and FIG. The process proceeds to step 2207 shown in FIG.

  FIG. 26 is a flowchart of slave continuous processing according to the first embodiment of this invention.

The slave continuous process is a process of transmitting the light emission control data, which is the effect control data, to the I ² CI / O expander 615 connected to the light emitting device, and is executed in the process of step 2502 shown in FIG.

The light emission control data is transmitted from the master IC 570 in the buffer mode. In buffered mode, the master IC570 is multiple bytes of data stored in the output BUF572, sends each byte to I ² CI / O expander 615, each of the transmission, from the I ² CI / O expander 615 Receive ACK or NACK. When a NACK is received, an interrupt signal is output to the CPU 551 at that time.

However, when ACK is received, an interrupt signal is output to the CPU 551 only when transmission of all data stored in the output BUF 572 is completed. When the master IC 570 receives an ACK from the I ² CI / O expander 615 in a state where untransmitted data remains in the output BUF 572, the master IC 570 does not output an interrupt signal to the CPU 551, but outputs the next signal from the output BUF 572. Data to be transmitted is taken out and output to the I ² CI / O expander 615.

That is, when the buffer mode, master IC570 may, until stored in the output BUF572 data is transmitted all I ² CI / O expander 615, ACK from I ² CI / O expander 615 As long as the message is continuously received, the process is continued without passing the process to the CPU 551.

  First, the CPU 551 sets 0 to an ACK counter that counts failure in receiving an ACK response signal (2601).

  Next, the CPU 551 generates data to be output to the selected decoration control device 610 (2602).

The CPU 551 executes a buffer setting process for setting the data generated in the process of step 2602 in the output BUF 572 (2603). The data to be set has the format of the effect control data shown in FIG. 19, and is transmitted to the I ² CI / O expander 615 while being divided for each byte according to the transmission order shown in FIG.

  Then, the master IC 570 changes the signal levels of the connection line SDA and the connection line SCL to a signal level indicating a start condition (2604).

  Specifically, the master IC 570 outputs a signal indicating a start condition by changing the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH.

  Note that, after outputting a signal indicating the start condition, the master IC 570 changes the level of the connection line SCL to LOW in order to send data to the decoration control device 610 to be controlled.

  Next, the CPU 551 starts activation of the monitoring timer for the buffer mode in order to monitor the time from when the master IC 570 is instructed to start data transmission until the master IC 570 transmits the interrupt signal to the CPU 551. (2605). Hereinafter, this monitoring time is referred to as buffer mode monitoring time.

  Then, the master IC 570 obtains data for 8 bits corresponding to the slave address of the decoration control device 610 to be controlled from the head of the data set in the output BUF 572, and uses the value of this address as the connection line SCL. The signal level is output via the connection line SDA while changing the signal level (2606).

  Since the address data output in the process of Step 2606 is an 8-bit data string, the address data is output in one output process (output while the connection line SCL changes to HIGH for 8 times).

  Note that, when outputting the slave address, the master IC 570 temporarily turns off the driver 576A to release the connection line SDA (change it to high level). If the connection line SDA is not released, the slave address output waits until the connection line SDA is released.

If the address data output by the processing in step 2606 is inputted to the I ² CI / O expander 615, I ² CI / O expander 615, and the address set in the address data itself entered It is determined whether or not they match.

The I ² CI / O expander 615 in which an address that matches the input address data is set immediately after the connection line SCL is changed from LOW to HIGH for the eighth time, A response signal is output from the connection line SDA to the master IC 570 when the connected connection line SCL changes to the LOW level.

  Next, the master IC 570 confirms whether or not an ACK response signal is input to the master IC 570 within a predetermined time after the address data is output in the processing of step 2605 (2607).

  Next, the master IC 570 determines whether or not an ACK response signal is input within a predetermined time after the address data is output in the process of step 2602 based on the confirmation result of the process of step 2606 (2608). ).

If it is determined in step 2608 that an ACK response signal has not been input within a predetermined time after the address data is output in step 2605, the master IC 570 determines that the response signal is NACK in status REG579. After setting the information to the effect, an interrupt signal is generated. As a result, the CPU 551 is notified that the NACK response signal has been received from the I ² CI / O expander 615. At this time, the CPU 551 ends the time monitoring in the byte mode (2609).

  When the CPU 551 receives an interrupt signal in step 2609, it instructs the master IC 570 to issue a stop condition. The master IC 570 instructed to issue the stop condition controls the signal levels of the connection line SDA and the connection line SCL, and issues a stop condition (2610). Thereafter, it is determined whether or not the ACK counter is 0 (2611).

  If it is determined in step 2611 that the ACK counter is 0, the ACK counter is updated by +1 to count that the reception of the ACK response signal has failed (2612), and the same data is again transmitted to the decoration control. Return to step 2602 for transmission to device 610.

On the other hand, if it is determined in step 2611 that the ACK counter is not 0, the CPU 551 selects the decoration control device 610 in which the I / O expander address 2101 is selected from the entries registered in the abnormality determination table 2100. The entry that matches the address of the I ² CI / O expander 615 is selected, and the error counter 2103 of the selected entry is incremented (2613).

  Then, the CPU 551 determines whether or not the value of the error counter 2103 incremented in step 2613 has reached the comparison value 2104 (2614).

  If it is determined in step 2614 that the value of the error counter 2103 incremented in step 2613 has reached the comparison value 2104, the CPU 551 selects the entry registered in the abnormality determination table 2100. Then, the error flag of the entry of the decoration control device 610 is set to ON (2615), and the slave continuous output process is terminated.

  On the other hand, if the error counter 2103 incremented in the process of step 2613 has not reached the comparison value 2104, if it is determined in the process of step 2614, the slave continuous output process is terminated.

  On the other hand, if it is determined in step 2608 that an ACK response signal has been input within a predetermined time, the master IC 570 determines whether all data stored in the output BUF 572 has been output. (2616).

If it is determined in step 2616 that all data stored in the output BUF 572 has been output, the master IC 570 sets information indicating that the response signal is ACK in the status REG 579. Generate an interrupt signal. Thereby, the CPU 551 is notified that the transmission of all the byte data to the I ² CI / O expander 615 is completed. At this time, the CPU 551 ends the buffer mode time monitoring (2619).

Then, after executing the processing of step 2619, the CPU 551 selects the I ² CI / O expander 615 of the decoration control device 610 in which the I / O expander address 2101 is selected from the entries registered in the abnormality determination table 2100. The entry that matches the address is selected, the error counter 2103 of the selected entry is initialized to zero (2620), the error flag 2105 of the entry is set to OFF (2621), the process proceeds to step 2615, and the master IC 570 To output a signal indicating the stop condition.

  On the other hand, if it is determined in step 2616 that all data stored in the output BUF 572 has not been output, the master IC 570 monitors the voltage level of the connection line SDA, and the connection line SDA After confirming that it has been released (2617), 1 byte of data to be transmitted next is transmitted among the data stored in the output BUF 572 (2618), and the process proceeds to step 2607.

  As described above, the emission control data is monitored every time 1-byte data is output (that is, while the emission control data is being transmitted), but the reception of the response signal is monitored. As long as all data stored in the output BUF 572 is transmitted, the data is transmitted in the buffer mode in which the processing is not transferred from the master IC 570 to the CPU 551 until transmission is completed.

  Here, the initialization instruction data including the common address is transmitted in the byte mode. As shown in FIG. 24, each time transmission of 1-byte data is started, an interrupt signal is sent from the master IC 570 to the CPU 551. The time until the return of (byte mode monitoring time) is monitored.

  On the other hand, the light emission control data including the slave address serving as the individual address is transmitted in the buffer mode. As shown in FIG. 26, the last byte is stored from the start of data transmission of the first byte stored in the output BUF572. The time until the end of data transmission (buffer mode monitoring time) is monitored.

  In the present embodiment, when data is transmitted from the effect control device 550 to the decoration control device 610, either the byte mode or the buffer mode described above is selected. Here, characteristics of the byte mode and the buffer mode will be described.

  In the byte mode, any response signal (either ACK or NACK) is input from the decoration control device 610 to 1-byte data transmitted from the master IC 570, and an interrupt signal is immediately transmitted from the master IC 570 to the CPU 551. The At this time, in the byte mode monitoring time, a time value is set in accordance with the time required for transmitting 1-byte data and receiving a response signal.

  When an ACK response signal is transmitted from the decoration control device 610 to the master IC 570, the CPU 551 determines that 1-byte data transmission has been successful and performs the following processing. On the other hand, when the NACK response signal is transmitted from the decoration control device 610 to the master IC 570, or when the byte mode monitoring time has timed out, the CPU 551 determines that an abnormality has occurred in data transmission, Perform the necessary processing.

  On the other hand, in the buffer mode, an interrupt signal is immediately sent from the master IC 570 to the CPU 551 only when a NACK response signal is input from the decoration control device 610 to 1-byte data transmitted from the master IC 570. Communicated. However, when an ACK response signal is input from the decoration control device 610, the interrupt signal is not transmitted from the master IC 570 to the CPU 551 unless all the data stored in the output BUF 572 is transmitted. The master IC 570 performs a process of transmitting data stored in the output BUF 572 one after another.

  Therefore, in the data transmission in the buffer mode, the number of times that the interrupt signal is transmitted from the master IC 570 to the CPU 551 is smaller than in the data transmission in the byte mode, and therefore, the number of times the processing is transferred from the master IC 570 to the CPU 551 is reduced. The overall transmission time when transmitting a plurality of bytes of data can be shortened.

  On the other hand, in the buffer mode, as long as the ACK response signal is continuously input from the decoration control device 610, the processing is not delivered from the master IC 570 to the CPU 551 until transmission of all data to be transmitted is completed. For this reason, during the data transmission, if a state in which data transmission cannot be performed using the connection line SDA occurs for some reason, the time until the data transmission is interrupted by the master IC 570 and the processing is handed over from the master IC 570 to the CPU 551 each time. However, it can be very long.

  In order to monitor the time until the process is transferred from the master IC 570 to the CPU 551, the above-mentioned buffer mode monitoring time has a time value that matches the time required for data transmission of all bytes to be transmitted and reception of the response signal. Is set. Inevitably, the buffer mode monitoring time is set longer than the byte mode monitoring time described above.

  When an ACK response signal is transmitted from the decoration control device 610 to the master IC 570, the CPU 551 determines that data transmission of all the bytes to be transmitted has been successful, and performs the following processing. On the other hand, when the NACK response signal is transmitted from the decoration control device 610 to the master IC 570 or when the buffer mode monitoring time has timed out, the CPU 551 determines that an abnormality has occurred in data transmission, Perform the necessary processing.

  From the above, if it is premised that no abnormality occurs with respect to data transmission, when transmitting data of a plurality of bytes (which inevitably becomes data having a bit number longer than 8 bits which is a transmission unit), Certainly, data transmission using the buffer mode can perform higher-speed processing than data transmission using the byte mode. However, considering the possibility of anomalies during data transmission, the byte mode has the advantage that processing can be performed while confirming the completion of data transmission for each byte, so which mode is superior Cannot be compared.

  In the present embodiment, initialization instruction data is transmitted in the byte mode, and the light emission control data is transmitted in the buffer mode. The effects achieved by such a configuration will be described.

  First, for initialization instruction data including a common address, an ACK response signal is output from all the decoration control devices 610 to which the common address is assigned in advance. On the other hand, for the light emission control data including the individual address, an ACK response signal is output from one decoration control device 610 to which the individual address is assigned in advance.

  For this reason, when the initialization instruction data is transmitted, response signals are output from the plurality of decoration control devices 610. Therefore, until the connection line SDA after the 1-byte data of the initialization instruction data is transmitted is released. The waiting time depends on the time until all of the plurality of decoration control devices 610 open the connection line SDA. On the other hand, the waiting time until the connection line SDA is released after the 1-byte data of the light emission control data is transmitted is the time until only one decoration control device 610 to be transmitted opens the connection line SDA. Depends on time. Therefore, the former has a longer waiting time until the connection line SDA is released.

  Note that the initialization instruction data is transmitted in three steps, such as common address data 2001, first predetermined value data 2002, and second predetermined value data 2003. Further, when the three types of initialization instruction data are not accurately transmitted to the decoration control device 610, a process of repeatedly transmitting the initialization instruction data as many times as possible is performed in order to reliably initialize the decoration control device 610. Done.

  Here, the case where the initialization instruction data is transmitted using the buffer mode is compared with the case where the initialization instruction data is transmitted using the byte mode. In each mode, what happens when an abnormal state occurs in which the connection line SDA is not released for some reason after the transmission of the first common address data 2001 or after the transmission of the next first predetermined value data 2002? Explain how.

  When the initialization instruction data is transmitted in the buffer mode, the buffer mode monitoring time includes at least 3 bytes from the start of transmission of the common address data 2001 to the reception of ACK by transmission of the second predetermined value data 2003. The time required for data transmission must be set. For this reason, when the initialization instruction data is transmitted in the buffer mode, if an abnormality occurs in which the connection line SDA is not released, the CPU 551 waits for the buffer mode monitoring time to expire.

  On the other hand, when the initialization instruction data is transmitted in the byte mode, the time required for transmitting at least one byte of data must be set as the byte mode monitoring time. For this reason, when the initialization instruction data is transmitted in the byte mode, if an abnormality occurs in which the connection line SDA is not released, the CPU 551 waits for the time-up of the byte mode monitoring time.

  For this reason, when the initialization instruction data is transmitted in the buffer mode, if an abnormality occurs in which the connection line SDA is not released, the CPU 551 waits for a long time-up time to elapse before canceling the abnormality. As a result, inefficient data transmission is performed.

  On the other hand, when the initialization instruction data is transmitted in the byte mode, even if an abnormality that the connection line SDA is not released occurs, the CPU 551 waits for a short time-up time to elapse before canceling the abnormality. Therefore, useless time can be suppressed and efficient data transmission can be performed.

  For this reason, in this embodiment, since the initialization instruction data is transmitted in the byte mode, an abnormality that the connection line SDA is not released can be detected quickly, and as a result, the data transmission time can be shortened.

  In particular, as described above, the initialization instruction data is transmitted to the plurality of decoration control devices 610, and since it is monitored that all response signals are output from these decoration control devices 610, the connection line SDA is released. Since it is necessary to set the monitoring time itself longer, it is preferable to perform time monitoring using the byte mode.

  On the other hand, in the present embodiment, the light emission control data is transmitted in the buffer mode. As described above, in the data transmission in the buffer mode, the number of times that the interrupt signal is transmitted from the master IC 570 to the CPU 551 is smaller than in the byte mode. Therefore, the processing is transferred from the master IC 570 to the CPU 551. This is because the number of times is reduced, and the overall transmission time when transmitting a plurality of bytes of data can be shortened.

  If the abnormal state where the connection line SDA is not released for some reason occurs when the emission control data is transmitted in the buffer mode, the abnormality is canceled after waiting for the buffer mode monitoring time to expire, and the decoration is performed only once. The light emission control data is retransmitted to the control device 610. If a transmission abnormality of the light emission control data occurs twice consecutively, the transmission of the light emission control data is stopped.

  Therefore, when the emission control data is transmitted, the processing load on the CPU 551 is reduced by reducing the number of times that an interrupt signal is output, rather than reducing wasted time until an abnormality in which the connection line SDA is not released is detected. Since the data transmission time can be shortened by reducing the number, the light emission control data is transmitted in the buffer mode in which the number of times the interrupt signal is output is smaller than that in the byte mode.

As shown in FIG. 24, in the initialization instruction data, when the connection line SDA is not released and a timeout occurs, or when a response signal for 1-byte data is not input to the master IC 570, Since retransmission is performed from the first data (data 2001 including the common address) of the initialization instruction data, and the retransmission is repeatedly performed until the initialization instruction data is received by the I ² CI / O expander 615. because of instruction data is received correctly to the I ² CI / O expander 615 can be accurately initialize the I ² CI / O expander 615. As shown in FIG. 26, in the light emission control data, if the connection line SDA is not released and a timeout occurs, or if a response signal for 1-byte data is not input to the master IC 570, the light emission is performed. Since re-transmission is performed only once from the first data of the control data, high-speed data transmission is possible.

Since the initialization of the I ² CI / O expander 615 is a process that is performed to eliminate an abnormality that has occurred when an abnormality has occurred, the initialization instruction data is stored in the I ² CI / O so that the initialization is performed reliably. Re-transmission is repeatedly performed until the expander 615 receives the data reliably. On the other hand, even if the emission control data is not received by the I ² CI / O expander 615, the output mode of the light emitting device only stops in the previous output mode. Re-transmission is performed only once.

FIG. 27 is a flowchart of the I ² C occasional reset process according to the first embodiment of this invention.

The I ² C occasional reset process is a process for instructing initialization of the master IC 570, the accessory driving MOT 561, all the I ² CI / O expanders 615 connected to the master IC 570, and the accessory driving SOL 560. Step 2210 shown in FIG.

  First, the effect control device 550 determines whether or not the reset request flag is on (2701).

If it is determined in step 2701 that the reset request flag is not on, the effect control device 550 refers to the abnormality determination table 2100 to determine whether or not a condition for instructing reset is satisfied. Whether or not an ACK response signal has been continuously received a predetermined number of times from all of the I ² CI / O expanders 615 to which the decoration device is connected among the I ² CI / O expanders 615 connected to the master IC 570 Is confirmed (2702).

  Specifically, the effect control device 550 determines whether or not “ON” is registered in the error flag 2105 of all entries registered in the abnormality determination table 2100.

  Next, the effect control device 550 determines whether or not a reset condition is satisfied based on the confirmation result of the processing in step 2702 (2703).

  Specifically, when all the error flags 2105 are ON at the time of the processing in step 2702 (when there is no light emission control device in which the error flag 2105 is OFF), the processing in step 2703 is performed. It is considered that the reset condition is satisfied. In other cases, it is considered that the reset condition is not satisfied in step 2703.

  If it is determined in step 2703 that the reset condition is satisfied, the effect control device 550 sets a reset request flag indicating that initialization is in progress (2704).

  Then, the effect control device 550 soft resets the master IC 570 (2705). Specifically, the CPU 551 writes a predetermined value to the reset REG 573 provided in the master IC 570 via the data bus. When a predetermined value is written to the reset REG 573 provided in the master IC 570, the controller of the master IC 570 sets the values of the input BUF 571, the output BUF 572, the reset REG 573, and the transmission mode REG 574 to the initial values, and initializes the master IC 570. To do. The initialization of the master IC 570 by writing a predetermined value to the reset REG 573 provided in the master IC 570 via the data bus by the CPU 551 is called soft reset.

  In this embodiment, when the master IC 570 is hard reset, as described above, other circuits (circuits initialized when the power such as the VDP 556 and the sound LSI 557 are turned on) provided in the effect control device 550 are also initialized. When it is determined that an abnormality has occurred in the master IC 570, by performing such a soft reset, only the master IC in which the abnormality has occurred is reset, and even a circuit that is not directly related to the master IC 570 Prevents resetting.

Next, the effect control device 550 outputs a reset signal from the master IC 570 to initialize the I ² CI / O expander 615 of all the decoration control devices 610 connected to the master IC 570. The slave shown in FIG. A reset process is executed (2706).

As described above, when the master IC 570 is initialized, the initialization instruction data is transmitted to all the I ² CI / O expanders 615 connected to the master IC 570, so that the gaming machine 1 is surely initialized. can do.

Then, the effect control device 550 sets a motor initialization flag indicating that the accessory driving MOT 561 is being initialized (2707), and is output to the accessory driving MOT 561 when initializing the accessory driving MOT 561. Motor output data is set in the RAM 553 (2708). Then, in order to initialize the accessory driving SOL 560, the effect control device 550 sets off data for turning off the energization state of the accessory driving SOL 560 in the RAM 553 (2709), and cancels the reset request flag. (2710), I ² C as needed reset processing is terminated.

  If it is determined in step 2701 that the reset request flag is set, the initialization must be executed immediately, so that it is not determined whether the reset condition is satisfied. The process proceeds to 2705.

If it is determined in step 2704 that the reset condition is not satisfied, it is not necessary to perform initialization. Therefore, the process proceeds to step 2710, the reset request flag is canceled, and the I ² C optional reset process is performed. Exit.

As described above, when it is determined that the reset condition is satisfied, in step 2706, all the I ² CI / O expanders 615 connected to the master IC 570 are instructed to initialize at the same time. In other words, since all the I ² CI / O expanders 615 are selected and initialized at the same time, the method is compared with the method of individually selecting the I ² CI / O expander 615 and instructing the initialization. Initialization can be performed at high speed, and the I ² CI / O expander 615 can be returned to a normal state at high speed.

Note that the RESET terminal (see FIG. 7) input to all the I ² CI / O expanders 615 is electrically connected to the CPU 551, and the RESET of all the I ² CI / O expanders 615 is performed simultaneously from the CPU 551. Even when the reset signal is transmitted to the terminal, it is possible to simultaneously select and initialize all the I ² CI / O expanders 615.

  If it is considered that the reset condition is satisfied in the process of step 2702, it is considered that an abnormality has occurred in the master IC 570. Therefore, the master IC 570 is also initialized in the process of step 2705.

  Since the master IC 570 functions as a signal level control means for controlling the signal levels of the connection line SDA and the connection line SCL according to a command from the CPU 551, an abnormality related to data transmission has occurred in all the light emission control devices. In this case, it may be considered that an abnormality has occurred in the master IC 570 itself.

  Therefore, when an abnormality relating to data transmission occurs in all the decoration control devices 610, the master IC 570 is initialized by the CPU 551 (arithmetic processing means) just in case. Accordingly, even if an abnormality occurs in the master IC 570, the master IC 570 can be reliably controlled.

Also, as shown in FIG. 22, in synchronization with the cycle of updating the image on the display device 53, the emission control data is transmitted from the master IC 570 of the effect control device 550 to the I ² CI / O expander 615, and the I ² CI Since the / O expander 615 controls the light-emitting device based on the received light-emission control, the effect on the display device 53 and the effect on the light-emitting device are harmonized and does not give the player a sense of incongruity. .

Further, whenever the decoration control device 610 receives the light emission control data transmitted from the master IC 570 in synchronization with the cycle of updating the image on the display device 53, the I ² CI / O expander 615 updates the work register. The value is updated. Therefore, since the value of the work register is updated to the latest state every time, even if the value of the work register is destroyed due to noise or the like, it can be restored to a normal value.

  In addition, since the error determination process is executed in synchronization with the cycle of updating the image on the display device 53, the error determination execution frequency can be made appropriate. That is, if the error determination process is executed too frequently, the effect control apparatus If the processing load of the CPU 551 of the 550 increases and, on the contrary, the frequency of execution of the error determination process is too low, it becomes impossible to properly detect that an abnormality has occurred. It is possible to prevent processing problems by performing the above.

  FIG. 28 is a flowchart of timer interrupt processing executed when a timer interrupt occurs according to the first embodiment of this invention.

  The timer interrupt is executed in a form of interrupting the process shown in FIG. 22 when the CPU 551 accepts a timer interrupt generated at a cycle of 2 ms under the condition that the timer interrupt is permitted.

The timer interruption process is a process for outputting control data to the I ² CI / O expander 615 (movable control device) connected to the accessory driving MOT 561 and the accessory driving SOL 560 (movable object) to control the movable object. is there.

  First, the effect control device 550 determines whether a reset request flag is set (2801).

  If it is determined in step 2801 that the reset request flag has been set, the process waits for the reset processing of the decoration control device 600 including the movable control device to start. Finish the process.

  On the other hand, if it is determined in step 2801 that the reset request flag is not set, the movable control device to be controlled is selected (2802), and the movable control device selected in step 2802 is selected. Then, a slave single output process for transmitting the movable control data which is the effect control data is executed (2803). The slave single output process will be described in detail with reference to FIG.

  Next, the effect control device 550 determines whether or not the slave single-shot output process executed in the process of step 2803 has ended normally (2804). In the slave single-shot output process, if the first data output fails to the movable control device selected in the process of step 2802, and the second data output also fails, the process ends abnormally.

  If it is determined in step 2804 that the slave single-shot output process has not ended normally, that is, if it is determined that the slave single-shot output process has ended abnormally, the effect control device 550 causes the accessory drive MOT 561 to A motor initialization flag indicating that initialization is in progress is set (2805), and a reset request flag is set to start the reset processing of the decoration control device 600 (2806).

  Then, the production control device 550 sets the motor output data output to the movable control device when initializing the accessory driving MOT 561 in the RAM 553 (2807), and initializes the accessory driving SOL 560. Is set in the RAM 553 (2808), and the timer interrupt process is terminated.

  On the other hand, if it is determined in step 2804 that the slave single-shot output processing has ended normally, the motor initialization flag is set to determine whether or not to initialize the accessory driving MOT 561. It is determined whether or not (2809).

  If it is determined in step 2809 that the motor initialization flag is set, it is determined whether or not the motor position detection sensor 510 has detected that the rotation axis of the accessory driving MOT 561 has returned to the initial position. Determine (2810).

  If it is determined in step 2810 that the motor position detection sensor 510 has not detected that the rotation axis of the accessory driving MOT 561 has returned to the initial position, the processing proceeds to step 2807 to initialize the accessory driving MOT 561. The motor output data that is output to the movable control device in the case of conversion is set in the RAM 553.

  On the other hand, if it is determined in step 2810 that the motor position detection sensor 510 has detected that the rotation axis of the accessory driving MOT 561 has returned to the initial position, stop data for stopping the rotation of the accessory driving MOT 561 is movable. In order to output to the control device, it is set in the RAM 553 (2811), and since the initialization of the accessory driving MOT 561 is completed, the motor initialization flag is canceled (2812), and the timer interruption process is terminated.

  If it is determined in step 2809 that the motor initialization flag has not been set, the effect control device 550 determines whether an operation abnormality has been detected in the accessory driving MOT 561 (2813).

  If it is determined in step 2813 that an abnormality has been detected in the accessory driving MOT 561, the process proceeds to step 2805 to initialize the accessory driving MOT 561.

  On the other hand, if it is determined in step 2813 that no abnormal operation is detected in the accessory driving MOT 561, the effect control device 550 performs control for rotating the rotation axis of the accessory driving MOT 561 to the target value. In order to output data to the movable control device, it is set in the RAM 553 (2814), and solenoid output data indicating whether the accessory driving SOL 560 is to be energized or de-energized is output to the movable control device. The RAM 553 is set (2815), and the timer interrupt process is terminated.

  FIG. 29 is a flowchart of slave single output processing according to the first embodiment of this invention.

  The slave single output process is a process of transmitting the movement control data to the movement control apparatus, and is executed in the process of step 2803 shown in FIG.

The movable control data is transmitted from the master IC 570 in the byte mode. In byte mode, the master IC570, every time one byte transmit data to I ² CI / O expander 615 receives the ACK or NACK from the I ² CI / O expander 615, receiving either an ACK or NACK Even in this case, an interrupt signal is output to the CPU 551. That is, if transmission of 1-byte data from the master IC 570 to the I ² CI / O expander 615 is completed, an interrupt signal is always output from the master IC 570 to the CPU 551 regardless of reception of ACK / NACK. .

  First, the CPU 551 sets 0 to an ACK counter that counts failure in receiving an ACK response signal (2901).

  Then, the master IC 570 changes the signal levels of the connection line SDA and the connection line SCL to a signal level indicating a start condition (2902).

  Specifically, the master IC 570 outputs a signal indicating a start condition by changing the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH.

  Note that, after outputting a signal indicating the start condition, the master IC 570 changes the level of the connection line SCL to LOW in order to send data to the decoration control device 610 to be controlled.

  Next, the CPU 551 sets the address data of the movable control device selected as the transmission target in the output BUF 572 (2903).

  Then, the CPU 551 starts activation of the monitoring timer for the byte mode in order to monitor the time from when the master IC 570 is instructed to start data transmission until the master IC 570 transmits the interrupt signal to the CPU 551 ( 2904).

  If the interrupt signal is not received even after a predetermined time has elapsed since the start of the monitoring of the byte mode time, the CPU 551 causes the master IC 570 to output a stop condition in order to interrupt the data transmission (2912). Thereafter, the value of the ACK counter is incremented by one, and the process returns to step 2902 to output the start condition again to the master IC 570, and then transmit the movable control data from the first data (address of the movable control device). . However, if the value of the ACK counter is a predetermined value (eg, “1”) at the time of step 2913, the process is terminated.

Then, the CPU 551 outputs a command for transmitting the address data set in the output BUF 572 in the process of step 2902 to the master IC 57, and when the master IC 570 receives the command, the CPU 551 sets the output BUF 572 in the process of step 2902. The address data thus transmitted is transmitted to the I ² CI / O expander 615 via the connection line SDA while changing the signal level of the connection line SCL (2905). When the master IC 570 outputs the address data, the master IC 570 temporarily turns off the driver 576A to release the connection line SDA (change it to high level). If the connection line SDA is not released (even if the driver 576A is turned off, the connection line SDA remains at a low level instead of a high level), the output of this address data is It waits until the line SDA is released (the connection line SDA becomes high level).

  Since the address data output in step 2905 is an 8-bit data string, the address data is output in one output process (output while the connection line SCL changes to HIGH eight times).

If the address data output by the processing in step 2905 is inputted to the I ² CI / O expander 615, I ² CI / O expander 615, and the address set in the input address data and its own It is determined whether or not they match.

The I ² CI / O expander 615 in which an address that matches the input address data is set immediately after the connection line SCL is changed from LOW to HIGH for the eighth time, A response signal is output from the connection line SDA to the master IC 570 when the connected connection line SCL changes to the LOW level.

  Next, the master IC 570 determines whether or not an ACK response signal has been input to the master IC 570 within a predetermined time (a monitoring time shorter than the above-described byte mode monitoring time) from the completion of data output for one byte. Is confirmed (2906).

  Next, the master IC 570 determines whether or not an ACK response signal is input within a predetermined time after the address data is output in the process of step 2905 based on the confirmation result of the process of step 2906 (2907). ).

If it is determined in step 2907 that an ACK response signal has not been input within a predetermined time after the address data is output in step 2905, the master IC 570 determines that the response signal is NACK in status REG579. After setting the information to the effect, an interrupt signal is generated. As a result, the CPU 551 is notified that the NACK response signal has been received from the I ² CI / O expander 615. At this time, the CPU 551 ends the time monitoring in the byte mode (2911).

  Next, in order to interrupt the data transmission, the CPU 551 causes the master IC 570 to output a stop condition (2912), and determines whether or not the ACK counter is a predetermined value (2913).

  If it is determined in step 2912 that the ACK counter is a predetermined value, the slave single output process is abnormally terminated.

  On the other hand, if it is determined in step 2913 that the ACK counter is not a predetermined value, the ACK counter is incremented, the process returns to step 2902, the master IC 570 is again output with the start condition, and then the same movable control data is returned. Is output (re-output from the address of the movable control device).

On the other hand, if it is determined in step 2907 that an ACK response signal has been input within a predetermined time after completion of outputting 1 byte of data in the processing of step 2905, the master IC 570 returns a response to status REG579. An interrupt signal is generated after setting information indicating that the signal is ACK. As a result, the CPU 551 is notified that the ACK response signal has been received from the I ² CI / O expander 615. At this time, the CPU 551 ends the time monitoring in the byte mode (2908).

  Next, the CPU 551 determines whether or not all data to be output to the movable control device has been output (2909).

  If it is determined in step 2909 that all data to be output to the movable control device has been output, the signal levels of the connection line SDA and the connection line SCL are changed to signal levels indicating a stop condition (2910). Complete the slave single output process normally.

  On the other hand, if it is determined in step 2909 that the data to be output to the movable control device has not yet been output, the CPU 551 supplies the next 1-byte data to be output to the movable control device to the output BUF 572. Set (2915).

  Next, in order to monitor the time from when the master IC 570 instructs the master IC 570 to start data transmission until the master IC 570 transmits the interrupt signal to the CPU 551, the CPU 551 starts to start the monitoring timer for the byte mode. (2916).

  Monitoring of the time (byte mode time) from when 1-byte data is transmitted until an interrupt is issued to notify whether or not a response signal that is an ACK for the 1-byte data is input from the master IC 570 Is started (2916).

  As described above, the CPU 551 sets a stop condition to the master IC 570 in order to interrupt data transmission when an interrupt signal is not received after a predetermined time has elapsed since the start of monitoring of the byte mode time. After that, the value of the ACK counter is incremented by one, and the process returns to the step 2902 to output the start condition to the master IC 570 again, and then the movable control data is set to the initial data (of the movable control device). Address). However, if the value of the ACK counter is a predetermined value at the time of step 2913, the processing is terminated.

  Next, the master IC 570 monitors the voltage level of the connection line SDA, confirms that the connection line SDA is released (2917), and then outputs 1-byte data set in the output BUF572 ( 2918), the process proceeds to Step 2906. In the process of step 2917, since the connection line SDA is occupied by the response signal until the output of the response signal from the group unit control means is completed, the master IC 570 outputs the response signal from the group unit control means. This is a process of waiting until the connection line SDA is released.

  Thereafter, the movable control data is sequentially transmitted, and when the transmission of all the movable control data is completed, the process ends normally through the process of step 2910 as described above.

  The order of the movable motion control data to be transmitted is in the format shown in FIG. 19 like the light emission control data. However, since the movable motion control data is transmitted in the byte mode, all data in the format shown in FIG. Instead of setting the output BUF 572 at a time, the data is transmitted while setting the output BUF 572 by dividing it by one byte from the beginning. Therefore, all data in the format shown in FIG. 19 (including motor and solenoid control data) is temporarily stored in the RAM 553.

As a result, the accessory driving MOT 561 and the accessory driving SOL 560 controlled by the I ² C movable control device output the movable control data in synchronization with the VDP interruption (approximately 33.3 ms cycle). Since the movable member cannot be controlled, the movable control data is output in synchronization with a timer interrupt (2 ms period) having a shorter period than the VDP interrupt. Thereby, it is possible to produce an effect by the movable member in accordance with the gaming state.

  The movable control data is transmitted in the byte mode as shown in FIG. This is because when the abnormality that the connection line SDA is not released occurs, the movable control device cannot be controlled, and the accessory driving MOT 561 may move the movable member beyond the movable range of the movable member set in advance. This is because a short time-up monitoring based on the byte mode monitoring time is performed to immediately detect an abnormality in which the connection line SDA is not released.

  In the processing according to FIGS. 26 and 29, the master IC 570 determines the success or failure of the data transfer by fetching the response signal from the decoration control device 610 after outputting the 8-bit data, and the data transfer has failed. In this case (that is, when a NACK response signal is input to the master IC 570), the output data is output again only once, so that the data can be output to the decoration control device 610 as reliably as possible. Can be prevented from malfunctioning.

  Note that when the master IC 570 transmits the start condition, the connection line SDA needs to be HIGH. However, due to the influence of noise or the like, the connection line SDA remains LOW and does not change. There is.

In the present embodiment, only the slave address that the master IC 570 transmits to the I ² CI / O expander 615 of the decoration control device 610 has R / W identification data “0” (means writing). (Refer to FIG. 11), but may be transmitted to the I ² CI / O expander 615 when the R / W identification data is “1” (meaning reading) due to the influence of noise or the like. is there.

In this case, the I ² CI / O expander 615 enters the read mode, and the connection line SDA is transferred from the I ² CI / O expander 615 to the master IC 570 in response to the signal level of the connection line SCL being changed by the master IC 570. A process for transmitting data bit by bit through the network is performed.

At this time, each time the I ² CI / O expander 615 transmits 8-bit data, the I ² CI / O expander 615 performs a process of receiving an acknowledge signal from the master IC 570 via the connection line SDA. Data transmission is performed, and thereafter, the 8-bit data transmission and acknowledgment signal confirmation are repeated. During this time, the connection line SDA is occupied by the I ² CI / O expander 615.

On the other hand, if the I ² CI / O expander 615 cannot receive an acknowledge signal from the master IC 570 via the connection line SDA after 8-bit data transmission, the I ² CI / O expander 615 releases the connection line SDA and stops data transmission. When the I ² CI / O expander 615 receives an acknowledge signal from the master IC 570 via the connection line SDA, the I ² CI / O expander 615 interprets that the acknowledge signal is received if the connection line SDA is at the LOW level. If SDA is HIGH, it is interpreted that no acknowledge signal is received.

Therefore, when the data from the master IC 570 changes due to the influence of noise or the like, and the I ² CI / O expander 615 that receives the changed data and enters the read mode is generated, the connection line SDA is changed. It will not be released forever.

In such a case, the signal level of the connection line SDA remains LOW, and the master IC 570 and the I ² CI / O expander 615 of the decoration control device 610 originally intended for transmission Cannot communicate with each other via the connection line SDA.

  Therefore, the master IC 570 determines whether or not the signal level of the connection line SDA is HIGH in order to determine whether or not data can be output from the connection line SDA before outputting a signal indicating the start condition. Determine.

  When it is determined that the signal level of the connection line SDA is not HIGH, data cannot be output from the connection line SDA. Therefore, the driver 576A does not apply an operable voltage to the transistor 578A without turning on the transistor 578A (connection line With the SDA released, the signal level of the connection SCL is changed at least nine times.

By performing such processing, the I ² CI / O expander 615 that has entered the read mode outputs data to the connection line SDA in accordance with the change in the signal level of the connection SCL. The timing for confirming the acknowledge signal from the master IC 570 is generated while the change is made at least nine times. At this time, since the connection line SDA is released, it becomes HIGH level, and the I ² CI / O expander 615 that has entered the read mode determines that it has not received an acknowledge signal. Will be released.

  Note that this process may be performed not only before the signal indicating the start condition is output but also before the master IC 570 outputs actual data to the decoration control device 610.

In this way, the connection line SDA is forcibly released from the I ² CI / O expander 615 of the decoration control device 610 in the read mode, so that the signal level of the connection line SDA is maintained at HIGH. .

  FIG. 30 is a diagram illustrating a connection form of the decoration control device 610 provided in the entire gaming machine according to the first embodiment of the present invention, and is a diagram illustrating the decoration control device 610 provided in the front frame 3 in particular.

  The decoration control device 610 is mainly attached to the game board 10 and the front frame 3. The LED controlled by the decoration control device 610 attached to the front frame 3 irradiates the decoration member 9, the illumination unit 11, and the abnormality notification LED 29.

  The gaming machine has a plurality of specifications, and there are a normal version gaming machine 1 and a low price gaming machine 1. The normal version gaming machine 1 includes a front frame 3 (normal version front frame) including a decorative member 9 of standard specifications. The low-priced gaming machine 1 includes a front frame 3 (low-priced front frame) including a decorative member 9 ′ configured at a lower cost than a standard decorative member 9.

  The number of the decoration control devices 610 attached to irradiate the decorative member 9 is different between the normal plate front frame 3 and the inexpensive plate front frame 3. Specifically, the decoration member 9 of the normal plate front frame 3 is irradiated by four decoration control devices 610, and the decoration member 9 ′ of the inexpensive plate front frame 3 is irradiated by two decoration control devices 610. The decoration member 9 is illuminated by a maximum of 60 LEDs, whereas the decoration member 9 'is illuminated by a maximum of 30 LEDs, so that the decoration member 9 is brighter than the decoration member 9'. For this reason, the control of the decoration control device 610 when the normal plate front frame 3 is attached is different from the control of the decoration control device 610 when the inexpensive plate front frame 3 is attached.

The address of the I ² CI / O expander 615 of the decoration control device 610 attached to the normal plate front frame 3 and the unique address of the I ² CI / O expander 615 of the decoration control device 610 attached to the inexpensive plate front frame 3 are If it is the same, the production control device 550 for the normal version that performs control when the front plate 3 is attached to the normal version, and the production control device for the low price version that performs control when the front plate 3 is attached to the low cost version. 550 and the production control device 550 must be replaced in accordance with the front frame 3 to be attached. Therefore, when the manufacturer ships the gaming machine 1, the production control device 550 for the normal version and the production control device 550 for the low-priced version must be prepared, which increases the manufacturing cost.

For this reason, in this embodiment, different addresses are assigned to the individual addresses of the I ² CI / O expander 615 of the decoration control device 610 whose control is different between the normal version front frame 3 and the inexpensive version front frame 3. The production control device 550 can perform control for the normal version and control for the inexpensive version. Thereby, it is not necessary to prepare the production control device 550 for the normal version and the production control device 550 for the inexpensive version, and the manufacturing cost can be reduced.

Specifically, the I ² CI / O expander 615 of the four decoration control devices 610 (first specification-dependent group unit control means) connected to the LEDs that irradiate the decoration member 9 of the normal plate front frame 3. “1001”, “1010”, “1100”, and “1101” are assigned to the unique addresses.

On the other hand, the address of the I ² CI / O expander 615 (second specification-dependent group unit control means) of the two decoration control devices 610 connected to the LEDs that irradiate the decoration member 9 ′ of the low-priced front frame 3 is used. Are assigned “1110” and “1111”, which are different from the unique addresses of the I ² CI / O expanders 615 of the four decoration control devices 610 connected to the LEDs that irradiate the decoration member 9 of the front plate 3 of the normal plate.

Then, regardless of whether it is used for the normal version front frame 3 or the cheap version front frame 3, the effect control device 550 assigns it to the I ² CI / O expander 615 of the decoration members 9, 9 ′. The effect control data including all the unique addresses “1001”, “1010”, “1100”, “1101”, “1110”, and “1111” are transmitted to the decoration control device 610.

  Therefore, the decoration control device 610 of the normal plate front frame 3 and the decoration control device 610 for the low cost version can be controlled by one production control device 550 that can perform the control for the normal version and the control for the low cost version. Manufacturing cost can be reduced.

In addition, the I ² CI / O expander 615 of the decoration control device 610 connected to the illumination unit 11 that performs the same control in the normal version front frame 3 and the inexpensive version front frame 3 and the LED that emits the abnormality notification LED 29 includes: It is not necessary to use different addresses for the normal version front frame 3 and the low cost version front frame 3, and the same address is assigned.

The low price front frame 3 does not use the I ² CI / O expander 615 with the unique addresses “1001”, “1010”, “1100”, “1101”. The I ² CI / O expander 615 with addresses “1110” and “1111” is not used. For this reason, there is an unconnected I ² CI / O expander 615 in the abnormality determination table 2100 (FIG. 21) regardless of the front frame 3 of any specification. If data transmission / reception is performed between one of the I ² CI / O expanders 615 registered in 2100 and the master IC 570, the data is processed as a normal state, and there is no problem.

(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIGS.

  The second embodiment of the present invention is an embodiment in the case where the effect control device 550 includes a plurality of master ICs 570.

As described above, the I ² CI / O expander 615 of the decoration control device 610 that can be connected to one master IC 570 has an upper limit on the number of unique addresses that can be set. If it is desired to place the decoration control device 610 beyond this upper limit, it is necessary to provide a plurality of master ICs 570.

  FIG. 31 is an explanatory diagram of the connection between the effect control device 550 and the decoration control device 610 according to the second embodiment of the present invention.

  In the second embodiment, the effect control device 550 includes a plurality of master ICs 570.

  In FIG. 31, the production control device 550 includes three master ICs 570A to 570C.

  The master IC 570A is connected to the relay board 600A, and the relay board 600A is connected in series to the decoration control devices 610A to 610C and is connected in series to the decoration control devices 610D to 610F.

  The master IC 570B is connected to the relay board 600B, and the relay board 600B is connected in series to the decoration control devices 610G to 610I and is connected in series to the decoration control devices 610J to 610L.

  The master IC 570C is connected to the relay board 600C. The relay board 600C is connected in series to the decoration control devices 610M to 610O, and is connected in series to the decoration control device 610P connected to the accessory driving SOL560 and the accessory driving MOT561. Connected.

  Here, the decoration control device 610 group connected to one master IC 570 is referred to as a system. Specifically, in the case of the master IC 570A, the system is the relay board 600A and the decoration control devices 610A to 610F.

  Since the master IC 570 can output data to the connected decoration control device 610, the master IC 570 can control the connected decoration control device 610.

With such a configuration, the number of I ² CI / O expanders 615 that can be controlled by one master IC 570 is eliminated (up to 14 as shown in FIG. 12), and a variety of presentation control is possible. Can be expected to do.

Also in this embodiment, data transmission / reception is performed between one I ² CI / O expander 615 and the master IC 570 among the I ² CI / O expanders 615 registered in the abnormality determination table 2100 (see FIG. 32). In this case, the process is performed in a normal state. However, the first point is that the determination of abnormality and the initialization process of the I ² CI / O expander 615 and the master IC 570 are performed independently for each system. This is different from the embodiment.

  In the present embodiment, as shown in FIG. 32, an abnormality determination table 2100 is prepared for each system. In other words, the abnormality determination table 2100 corresponding to each master IC 570 is stored in the RAM 553 of the effect control device 550.

  The abnormality determination table 2100 will be specifically described. FIG. 32 is an explanatory diagram of the abnormality determination table 2100 according to the second embodiment of this invention.

  A first abnormality determination table 2100A for determining an abnormality in data transmission / reception performed between the master IC 570A and the decoration control devices 610A to 610F for each decoration control device, and between the master IC 570B and the decoration control devices 610G to 610L. Second abnormality determination table 2100B for determining an abnormality in data transmission / reception for each decoration control device, and a third abnormality for determining an abnormality in data transmission / reception performed between master IC 570C and decoration control devices 610M to 610O for each decoration control device There are three types of tables, the determination table 2100C.

  An abnormality in data transmission / reception between the master IC 570 and the movable control device (decoration control device 610P) is not registered in the third abnormality determination table 2100C. The abnormality in data transmission between the master IC 570 and the movable control device is determined based on whether the process in FIG. 29 is completed normally or abnormally. If it is determined that the process ends abnormally, in the process in FIG. This is because the accessory driving SOL 560 is initialized.

If any abnormality determination table determines that a data transmission / reception abnormality has occurred with respect to all the I ² CI / O expanders 615, all the decoration control devices 610 belonging to the abnormality determination table are initialized. At the same time, the corresponding master IC 570 is also initialized. However, the decoration control device 610 and the master IC 570 belonging to other abnormality determination tables are not initialized.

For example, if it is determined in the first abnormality determination table described above that data transmission / reception abnormality has occurred with respect to all the I ² CI / O expanders 615, only the master IC 570A and the decoration control devices 610A to 610F are initialized. The other master ICs 570B and 570C and the decoration control devices 610G to 610P are not initialized.

  For this reason, even if the master IC 570 in which the data transmission abnormality has occurred and the decoration control device 610 connected to the master IC 570 in which the data transmission abnormality has occurred are being initialized, the master IC 570 and the decoration control device 610 in which no abnormality has occurred. Since the decoration control data can be transmitted / received between the two, the effect by the decoration device 620 can be prevented from being suddenly stopped during the game.

  As a method for initializing the master ICs 570A to 570C, there are a soft reset and a hard reset.

  In the soft reset, the CPU 551 initializes one of the master ICs 570A to 570C.

  Specifically, each of the master ICs 570A to 570C includes a reset REG 573 (see FIG. 4). When the CPU 551 writes a specific value (initialization instruction data) to the reset register via the bus 563, only the master IC 570 including the reset REG 573 written with the specific value is initialized.

  In the hard reset, the RESET terminals of the master ICs 570A to 570C are connected to the NOR gate circuit 590 connected to the input / output I / F 558 and the power-on detection circuit 559, and the voltage applied to the NOR gate circuit 590 is applied for a predetermined time. When held low, the voltage applied to the RESET terminal is also held low for a predetermined time and all master ICs 570A-570C are initialized.

  The NOR gate circuit 590 is connected to the RESET terminal of all the master ICs 570. When the voltage applied to the NOR gate circuit 590 is held low for a predetermined time, the voltage applied to the RESET terminals of all the master ICs 570. Also goes low for a predetermined time and is taken as an initialization signal by all the master ICs 570.

  Note that a line connecting the NOR gate circuit 590 and the RESET terminal of the master IC 570 is a separate line from the bus 563.

In this embodiment, when the power is turned on, all the master ICs 570A to 570C are initialized by hardware reset, and the corresponding decoration control device 610 is initialized. If any abnormality determination table determines that a data transmission / reception abnormality has occurred with respect to all the I ² CI / O expanders 615, only the master IC belonging to the abnormality determination table is initialized by a soft reset. At the same time, the corresponding decoration control device 610 is initialized, but the other master IC and decoration control device 610 are not reset.

  As described above, when the production control device 550 includes a plurality of master ICs 570, only the master IC in which an abnormality has occurred is reset, so that the decoration of the entire gaming machine 1 does not pause and the player feels uncomfortable. Can be suppressed. Further, when all the master ICs 570 are to be simultaneously reset at a high speed, the reset can be performed by a hard reset, so that various types of reset processing can be performed.

  In the second embodiment, the same processing as that of the first embodiment is executed, but only the processing different from that of the first embodiment will be described in detail with reference to FIGS. 33 and 34.

FIG. 33 is a flowchart of the I ² C initial reset process according to the second embodiment of this invention. In FIG. 33, the same process as the I ² C initial reset process shown in FIG.

I ² C initial reset process is a process executed when the power is turned, in I ² C initial reset process of the second embodiment transmits an initialization instruction data to the decoration control device 610 which is connected to each master IC570.

  Specifically, after all the master ICs 570 are hard reset in the process of step 2302, the CPU 551 selects the first master IC 570A (3301) and is connected to the master IC 570A selected in the process of step 3301. A slave reset process for transmitting initialization instruction data to the decoration control devices 610A to 610F is executed (2303), and the decoration control devices 610A to 610F connected to the master IC 570A are initialized.

  Then, the CPU 551 selects the second master IC 570B (3302), and performs slave reset processing for transmitting initialization instruction data to the decoration control devices 610G to 610L connected to the master IC 570B selected in step 3302. Execute (2303) and initialize the decoration control devices 610G to 610L connected to the master IC 570B.

  Then, the CPU 551 selects the third master IC 570C (3303), and performs a slave reset process of transmitting initialization instruction data to the decoration control devices 610M to 610P connected to the master IC 570C selected in the process of step 3303. Execute (2303) and initialize the decoration control devices 610M to 610P connected to the master IC 570C.

FIG. 34 is a flowchart of the I ² C optional reset process according to the second embodiment of this invention. In FIG. 34, the same processes as the I ² C occasional reset process shown in FIG.

  If it is determined in step 2701 that the reset request flag is set, or if it is determined in step 2703 that the reset condition is satisfied, the CPU 551 selects the master IC 570 that satisfies the reset condition. In step 3401, a predetermined value is written in the reset REG 573 provided in the master IC 570, and the master IC 570 is soft reset (3402).

  Then, the CPU 551 executes slave reset processing for transmitting initialization instruction data to all the decoration control devices 610 connected to the master IC 570 selected in step 3401 (2706).

  Next, the CPU 551 determines whether or not the master IC 570 for which the reset condition is satisfied is the master IC 570 (master IC 570C in FIG. 31) connected to the movable control device (3403).

  If it is determined in step 3403 that the master IC 570 for which the reset condition is satisfied is the master IC 570 connected to the movable control device, the accessory driving MOT 561 and the accessory driving SOL 560 controlled by the movable control device are set to the initial positions. Since the initialization process to be returned is executed, the process proceeds to step 2707.

  On the other hand, if it is determined in step 3403 that the master IC 570 for which the reset condition is satisfied is not the master IC 570 connected to the movable control device, the process proceeds to step 2710.

  Thus, in this embodiment, since only the master IC 570 in which an abnormality is detected is soft reset, it is not necessary to initialize the master IC 570 in which no abnormality is detected, so that the decoration device whose output is temporarily stopped during the game The number of players can be minimized, and the uncomfortable feeling given to the player can be reduced.

  Further, when the master IC 570 is initialized by a hard reset or a software reset, all the decoration control devices 610 connected to the master IC 570 to be initialized are also initialized, so that the abnormality can be reliably eliminated.

  FIG. 35 is a timing chart before and after initialization of the master IC 570 upon power-on according to the second embodiment of the present invention.

When the gaming machine 1 is powered on, the CPU 551 executes the process of FIG. 22 and executes the I ² C initial reset process shown in FIG. In the process of step 2302 shown in FIG. 33, the master IC 570 provided in the effect control device 550 is held low for a predetermined time applied to the RESET terminals of all the master ICs 570 provided in the effect control device 550, and all the master ICs 570 provided in the effect control device 550 are hard reset.

In step 3301, the first master IC 570A is selected, and initialization instruction data is transmitted to all the I ² CI / O expanders 615 connected to the first master IC 570A.

Next, the second master IC 570B is selected in the process of step 3302, and initialization instruction data is transmitted to all the I ² CI / O expanders 615 connected to the second master IC 570B.

Next, in step 3303, the third master IC 570C is selected, and initialization instruction data is transmitted to all the I ² CI / O expanders 615 connected to the third master IC 570C.

  When the movable control device (decoration control device 610P) receives the initialization instruction data from the third master IC 570, the motor initialization operation for returning the rotation axis of the accessory driving MOT 561 to the initial position is performed, which is shown in FIG. When the motor initialization flag is set in the process of step 2305 and the output data (movable control data) of the motor at the time of initialization is output in the process of step 2306, the rotating shaft of the accessory driving MOT 561 is returned to the initial position. A motor initialization operation is executed.

When the I ² C initial reset process shown in FIG. 33 is completed, the timer interrupt is permitted in the process of step 2203 shown in FIG. Thereafter, whenever the VDP interrupt shown in FIG. 22 is input to the CPU 551, the processing of steps 2204 to 2210 shown in FIG. 22 is repeatedly executed, and when the timer interrupt is input to the CPU 551 in a cycle of 2 ms, FIG. The indicated timer interrupt process is executed.

  Even during the motor initialization operation, the processing of step 2206 shown in FIG. 22 is executed, and the master ICs 570A and 570B to which only the light emission control device is connected transmit the light emission control data to the light emission control device.

  On the other hand, in the timer interruption process shown in FIG. 28 executed at a cycle of 2 ms, if the motor initialization operation is being performed, the fact that the rotation axis of the accessory driving MOT 561 has been returned to the initial position in the process of step 2810. The motor initialization operation is executed until detection.

  When it is detected in step 2810 that the rotation shaft of the accessory driving MOT 561 has been returned to the initial position and the motor initialization operation is completed, the normal motor output data is obtained in step 2814 shown in FIG. Since (movable control data) is transmitted, the decoration effect operation by the accessory driving MOT 561 becomes possible.

  As described above, the master IC 570 other than the master IC 570 connected to the movable control device that controls the accessory driving MOT 561 in the initialization operation, even if the accessory driving MOT 561 is in the initialization operation by turning on the power, Since the decoration control data is transmitted to the decoration control device 610, the time from when the power is turned on to when the light emitting device is turned on can be shortened, and the time required for the confirmation operation of the light emitting device immediately after the power is turned on can be shortened.

  FIG. 36 is a timing chart before and after initialization of the master IC 570 in which an abnormality has occurred according to the second embodiment of the present invention.

  FIG. 36 illustrates a case where a reset condition is established in the third master IC 570C connected to the movable control device, that is, a case where an abnormality is detected in the third master IC 570C.

  When an abnormality is detected in the third master IC 570, the third master IC 570 is selected in the process of step 3401 shown in FIG. 34, and the third master IC 570 is soft reset in the process of step 3402.

  In step 2706 shown in FIG. 34, initialization instruction data is transmitted to all the decoration devices 620 connected to the third master IC 570. Since an abnormality is detected in the movable control master IC 570C, a motor initialization flag is set in step 2707, and motor output data (movable control data) at initialization is output in step 2708. .

  Even during the motor initialization operation, the processing of step 2206 shown in FIG. 22 is executed, and master ICs 570A and 570B to which only the light emission control device is connected transmit the light emission control data to the light emission control device. .

  On the other hand, in the timer interruption process shown in FIG. 28 executed at a cycle of 2 ms, if the motor initialization operation is being performed, the fact that the rotation axis of the accessory driving MOT 561 has been returned to the initial position in the process of step 2810. The motor initialization operation is executed until detection.

  When it is detected in step 2810 that the rotation shaft of the accessory driving MOT 561 has been returned to the initial position and the motor initialization operation is completed, the normal motor output data is obtained in step 2814 shown in FIG. Since (movable control data) is transmitted, the decoration effect operation by the accessory driving MOT 561 becomes possible.

  As described above, a master other than the master IC 570 connected to the movable control device that controls the accessory driving MOT 561 during the initialization operation even if the accessory driving MOT 561 is in the initialization operation due to the occurrence of an abnormality. Since the IC 570 transmits the decoration control data to the decoration control device 610, the board surface of the gaming machine 1 can be prevented from becoming dark even if the accessory driving MOT 561 is frequently initialized.

  It should be noted that the embodiments disclosed in the present specification are naturally intended to be applicable not only to pachinko machines but also to other gaming machines such as pachislot machines.

  Also, as an embodiment, a pachinko machine that generates a special game state corresponding to the result of the variable display game is disclosed, but not limited to the variable display game, the special game corresponding to the result of other auxiliary games Of course, it may be a gaming machine that generates a state.

  For example, when a predetermined condition is satisfied, an entrance of a specific winning device is opened (the movable member of the specified winning device is actuated to open the entrance), and a game ball taken into the winning device is provided inside the winning device. A game in which lottery is selected for which winning area (there is a specific winning area or a general winning area) may be used as an auxiliary game. In this case, a special game state occurs when the game ball taken into the winning device wins a specific winning area.

  In addition, as an embodiment, a pachinko machine that generates a special game state corresponding to the result of the special figure variation display game is disclosed, but in response to the result of the general figure variation display game (or It is naturally intended that the present invention can be applied even to a pachinko machine that generates a special gaming state (due to the result of the display game). For example, even a pachinko machine that generates a special game state when the entrance of a specific winning device is opened according to the result of the normal game display game and a game ball taken into the winning device wins a specific winning area. The present invention is applicable.

  Further, as an embodiment, a configuration in which the game control device and the effect control device are separated is disclosed, but the game control device and the effect control device constitute a single control device. Of course, it is intended that the game control device itself may be configured as a group overall control means.

  The embodiment disclosed this time is illustrative in all points and is not restrictive. The scope of the present invention is shown not by the above description of the invention but by the scope of claims, and is intended to include all modifications within the scope and meaning equivalent to the scope of claims.

  As described above, the present invention can be applied to a gaming machine in which an effect control device controls a decoration control device.

1 gaming machine 2 body frame (outer frame)
3 Front frame 4 Hinge 10 Game board 11 Illumination unit 17 Production button 18 Glass frame 34 Regular start gate 36 Regular variation prize device 42 Special variation prize device 44 General prize opening 45 First start prize opening 51 Center case 52 Window 53 Display Device 55 Vibration sensor 60 Movable accessory 500 Game control device 550 Production control device 560 Actor drive SOL
561 Actor Drive MOT
570 Master IC
573 Reset REG
574 Transmission mode REG
579 Status REG
580 Dispensing control device 600 Relay board (decoration control device)
610 decoration device 620 decoration device 2100 abnormality determination table

Claims (1)

Game control means for overall control of the game;
A plurality of directing devices for directing games;
In response to a command from the game control means, an effect control means for controlling the plurality of effect devices,
Dividing the plurality of effect devices into a plurality of groups, and providing group unit control means for each group to control the effect devices belonging to the divided group,
It said presentation control means, constitutes a respective pre-SL group unit control means as a group supervisory controlling means for centrally controlling,
The data line for transmitting data between the previous SL group supervisory controlling means the group-unit control unit, and enables data transfer between the pre-SL group supervisory controlling means wherein each group unit control means,
The group overall control means is :
By setting the signal level before Symbol data line to a signal level corresponding to the transmission data, and signal sequentially send the data to the group-unit control unit,
The group unit control means includes:
A common address that is common among the group unit control means and an individual address that is different between the group unit control means are assigned in advance,
Determine the content of the address included in the data transmitted from the group overall control means,
When it is determined that the address is an individual address addressed to the address, the transmitted data is fetched as effect control information, and the output mode of the effect device is controlled based on the effect control information.
When it is determined that the address is a common address, the transmitted data is fetched as initialization instruction data, and the game machine is initialized based on the initialization instruction data .

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