JP6327513B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, thermal expansion between a semiconductor chip as a heating element having a low coefficient of thermal expansion and a heat exchange cooler that cools the semiconductor chip. The present invention relates to a semiconductor device capable of relieving thermal stress caused by a rate difference and efficiently releasing heat generated from a semiconductor chip as a heating element to a cooler and a method for manufacturing the same.
The semiconductor device and the manufacturing method thereof according to the present invention can be suitably applied to a power module for electric power such as a hybrid vehicle.

Conventionally, this type of power module includes an insulating substrate on which a semiconductor chip is installed in an insulated state, and a heat radiator and a cooler that radiate heat generated from the semiconductor chip.
The semiconductor chip is bonded and fixed to a metal layer such as copper or aluminum plate bonded to the upper surface of the insulating substrate using solder or the like, and the insulating substrate is formed from a ceramic insulating material such as aluminum nitride. ing. The metal layer and the heat dissipating body, which are similarly formed on the lower surface of the insulating substrate, are joined by solder. Moreover, the heat radiator and the cooler are joined with silicon grease, solder, or the like to constitute a semiconductor device.
Here, a plurality of fins are generally formed in the cooler, and a solder made of an alloy containing Sn as a main component is generally used as a joining solder.

In recent years, the amount of heat generated by semiconductors has been steadily increasing as electronic parts have higher functions and higher performance. Generally, in order to prevent performance degradation due to heat generation, a semiconductor is bonded to a cooler typified by a heat sink and cooled by utilizing its heat conduction.
However, when comparing the thermal expansion coefficient of the semiconductor and the insulating substrate directly bonded thereto, the thermal expansion coefficient of the material of the cooler to which the metal having high thermal conductivity is mainly applied is remarkably high. For example, the thermal expansion coefficient of a semiconductor chip is generally about 3 ppm, the thermal expansion coefficient of an insulating substrate is 4 to 5 ppm, and the thermal expansion coefficient of an aluminum cooler is about 23 ppm.
For this reason, if they are joined directly, the respective members will thermally expand due to the heat generation of the semiconductor and the increase in environmental temperature, resulting in a large thermal stress due to the difference in thermal expansion at the joining interface. There is a possibility that destruction of the bonding material (cracks, etc.) and destruction of the bonding interface (shear failure) may occur.

In order to solve this problem, a buffer material having a thermal expansion coefficient intermediate between both a semiconductor chip represented by silicon (Si) and a cooler represented by aluminum or copper is appropriately interposed to provide a thermal expansion coefficient. A way to mitigate the difference is taken.
Typical examples of the buffer material include a sintered alloy such as copper-molybdenum and copper-tungsten, and a clad material such as copper-invar and aluminum-invar. They can change the coefficient of thermal expansion arbitrarily by alloying or clading molybdenum, tungsten, invar, etc., which are low thermal expansion materials, with aluminum or copper, which are high thermal expansion materials, at a required ratio. Is possible. In addition, there is an example in which silicon grease or the like is used as a bonding material and the bonding material also serves as a stress buffer material.
In general, due to the matching of these thermal expansion coefficients, the power module structure becomes a multilayer structure. As a result, the overall thermal resistance becomes high, and the manufacturing process becomes complicated as the constituent layers become complicated, resulting in high product costs. It has become.

  Further, in Patent Document 1, as a basic configuration, a power module substrate is interposed between a semiconductor chip and a cooler, and this power module substrate has a metal layer laminated on top and bottom of a ceramic insulating substrate. In order to alleviate the difference in coefficient of thermal expansion in the metal layer, a laminated substrate in which three layers of copper-molybdenum-copper are laminated by brazing is used. In order to alleviate this, bonding is performed via a thermal stress relaxation layer.

JP 2007-335795 A

However, in the method described in Patent Document 1, the laminated structure becomes very complicated, the number of parts and the number of joints increase, the manufacturing process becomes complicated, and the product cost increases.
Moreover, since it is connected to the cooler via the stress relaxation layer, the heat transfer from the semiconductor chip is reduced and the heat generation is increased.

  The present invention has been made in view of the above-described problems of the prior art. The object of the present invention is to reduce the number of parts, to simplify the laminated structure, to reduce the number of junctions, and to improve thermal performance and reliability. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can improve the performance, simplify the manufacturing process, and can be manufactured easily and inexpensively.

  As a result of intensive studies to achieve the above object, the present inventor has found that the above object can be achieved by appropriately arranging a predetermined multilayer substrate layer that is easy to form, and completes the present invention. It came to.

That is, the semiconductor device of the present invention is a semiconductor device including a semiconductor, a cooler for cooling the semiconductor, an electrode, an insulator, and a stress buffer material.
Between the semiconductor and the cooler, a multilayer substrate layer formed by laminating a stress buffer layer, an insulator layer and an electrode layer in this order from the cooler side is interposed,
The semiconductor is disposed on the electrode layer;
The multilayer substrate layer is embedded in the cooler;
At least the insulator layer and the electrode layer of the multilayer substrate layer are partially exposed from the surface of the cooler, and the exposed portion has a multiple ring structure in which the diameter of the electrode layer and the insulator layer is increased in this order,
The buried portion of the multilayer substrate layer has a curved or bent cross-sectional shape.

The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device as described above.
The multilayer substrate layer is formed by sequentially and integrally stacking a stress buffer layer, an insulating layer, and an electrode layer on the cooler by cold spraying or spraying.

According to the present invention, since a predetermined multilayer substrate layer that is easy to form is appropriately arranged, the number of components is reduced, the laminated configuration is simple, the number of junctions is reduced, and thermal performance and reliability are reduced. has improved, can simplify the manufacturing process, Ru can provide easy semiconductor device and a manufacturing method thereof can be manufactured at low cost.

In the semiconductor device of the present invention, the multilayer substrate layer is embedded in the cooler, and at least the insulator layer and the electrode layer of the multilayer substrate layer are partially exposed from the surface of the cooler, and these exposed portions are electrodes. If the multi-ring structure is expanded in the order of the layer and the insulator layer, and the buried portion of the multilayer substrate layer has a curved or bent cross-sectional shape, the thermal expansion difference of each layer with respect to the thermal cycle is absorbed. In addition, the thermal stress can be alleviated, and a semiconductor device in which high conductivity as an electrode and insulation as an insulating layer are realized with a simple configuration can be obtained.

  In the semiconductor device of the present invention, the stress buffer layer and the electrode layer are made of a composite material including copper (Cu) or aluminum (Al) and an additive for reducing the thermal expansion coefficient of copper or aluminum. By doing so, it is possible to match the coefficient of thermal expansion with the semiconductor while ensuring high conductivity as an electrode, and to obtain a semiconductor device with high durability and reliability.

Further, in the semiconductor device of the present invention, the content of the additive contained in the stress slow collision layer, can be seen from the cooler side gradually increases toward the insulating layer side, also, stress buffer layer There comprises a plurality of layers laminated, the content of the additive in each layer may be so as gradually increases toward the layer of insulating layer side a layer of the cooler side.
In any case, with a simple laminated structure, thermal stress can be effectively reduced, and heat generated in the semiconductor chip can be efficiently transferred to the cooler to be cooled, and a small semiconductor device can be obtained. Can do.

Furthermore, in the semiconductor device of the present invention, the additive to the stress buffer layer is made of silicon carbide (SiC), alumina (Al ₂ O ₃ ), boron carbide (B ₄ C), tungsten, molybdenum, graphite, and carbon fiber. When the material is at least one material selected from the group consisting of, the thermal expansion coefficient of the stress buffer layer can be arbitrarily controlled, and the matching of the thermal expansion coefficient between the insulating layer and the cooler is set optimally Therefore, a thermal stress can be relieved and a semiconductor device with high thermal performance can be obtained.

In the semiconductor device of the present invention, if the additive in the electrode layer is at least one material selected from the group consisting of conductive diamond, graphite, carbon fiber, and carbon nanotube (CNT), the heat of the electrode layer A semiconductor device capable of ensuring high conductivity as an electrode while lowering the expansion coefficient can be obtained.
If the semiconductor device of the present invention has a configuration in which a plurality of multilayer substrate layers and semiconductors are formed for one cooler, the system can be reduced in size and cost.

Furthermore, according to the method for manufacturing a semiconductor device of the present invention, the semiconductor device can be manufactured easily and inexpensively by simplifying the manufacturing process and integrating the components.
Further, in the method for manufacturing a semiconductor device of the present invention, the junction of the cooler, the stress buffer layer, the insulator layer, and the electrode layer in the semiconductor device is formed as a stress concentration portion for eutectic reaction and destruction of the oxide film. If bonding is performed by a bonding method using a combination of fine grooves, it is possible to obtain a high-performance semiconductor device that is excellent in durability with little deterioration with time in the bonded portion and low in electrical resistance and thermal resistance at the bonding interface.

It is a schematic sectional drawing which shows one Embodiment of the semiconductor device of this invention. FIG. 2 is a schematic plan view of the semiconductor device shown in FIG. 1. It is a schematic sectional drawing which shows other embodiment of the semiconductor device of this invention. It is a schematic sectional drawing which shows other embodiment of the semiconductor device of this invention. It is a schematic sectional drawing which shows other embodiment of the semiconductor device of this invention. It is a schematic sectional drawing which shows the other form of a semiconductor device . It is a block diagram which shows the apparatus structure of the cold spray used for the manufacturing method of the semiconductor device of this invention.

  Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be specifically described with reference to the drawings.

(Embodiment 1)
FIG. 1 shows a semiconductor device according to an embodiment of the present invention, and is a schematic cross-sectional view showing a structure of a semiconductor device formed by mounting and bonding a semiconductor chip on a cooler integrated with a multilayer substrate layer. .

In FIG. 1, the semiconductor device is integrally formed in a cooler 15 and each of the stress buffer layer 14, the insulator layer 13 and the electrode layer 12 is formed from the cooler 15 side toward the semiconductor chip 10 side. A multilayer substrate layer 11 that is sequentially laminated and bonded is formed, and a semiconductor device 10 is mounted and bonded to the semiconductor chip 10 by a bonding layer 16 thereon.
Here, the stress buffer layer 14 has a three-layer structure as an example in the present embodiment, and the three layers have different thermal expansion coefficients, and the stress buffer layer 14 is directed from the cooler 15 side toward the semiconductor chip 10 side. The coefficient of thermal expansion decreases in the order of C (14c), stress buffer layer B (14b), and stress buffer layer A (14a).

The cooler 15 is made of an aluminum alloy, and a plurality of fins 15c are formed in the cooler 15 in order to improve the cooling performance. A concave portion is formed as the curved portion 17 inside the cooler 15, and the multilayer substrate layer 11 is integrally formed so as to be in close contact therewith.
The stress buffer layer 14 that is one layer constituting the multilayer substrate layer 11 is made of a composite material containing aluminum and SiC added as an additive for reducing the thermal expansion coefficient of aluminum.
SiC is preferably selected because it has a low coefficient of thermal expansion (about 3 ppm) and a relatively high thermal conductivity (150 W / m · K).

  In the present embodiment, the stress buffer layer 14 gradually increases the amount of SiC as an additive from the cooler 15 side toward the insulator layer 13 side. Here, the stress buffer layer is composed of 25% by mass of SiC. A layer C (14c), a stress buffer layer B (14b) with SiC of 50% by mass, and a stress buffer layer A (14a) with SiC of 70% by mass are also configured. In the present embodiment, these three layers are formed with substantially the same thickness.

An insulating layer 13 is similarly formed integrally on the stress buffer layer 14, and this insulating layer has an electrical insulating property, a low thermal expansion coefficient (about 5 ppm), and an appropriate thermal conductivity. As a constituent material, Al ₂ O ₃ is selected from ceramics as an example, considering the manufacturability in the thermal spraying method described later.

  An electrode layer 12 is also integrally formed on the insulating layer 13, and this electrode layer 12 contains aluminum, reduces the thermal expansion coefficient of aluminum, and also has thermal conductivity and electrical conductivity. As an additive for improving the above, it is composed of a composite material to which 70% by mass of conductive diamond is added.

The semiconductor device according to the present embodiment has a laminated configuration in which the above materials are selected, so that the coefficient of thermal expansion of each layer is the semiconductor chip 10 (3 ppm), the electrode layer 12 (6 ppm), and the insulator layer 13 ( 5 ppm), stress buffer layer 14 a (8 ppm), stress buffer layer 14 b (12 ppm), stress buffer layer 14 c (15 ppm), and cooler 15 (23 ppm). Therefore, the thermal expansion difference of each layer with respect to the thermal cycle can be absorbed, and the thermal stress can be effectively relaxed.
The material and thickness of each of these layers are not limited to the present embodiment, and the material that is a component, the material and thickness of the additive, and the like can be appropriately selected.

In addition, as the stress buffer layer 14 and the electrode layer 12, although the composite material containing aluminum was shown as an example, it is not limited to this, Similarly, copper which is a metal with high heat conductivity and electrical conductivity is used. It is good also as a main component.
Moreover, although SiC was shown as an additive to the stress buffer layer 14, other than this, alumina (Al ₂ O ₃₎ , boron carbide (B ₄ C), tungsten, molybdenum, graphite, carbon fiber, and the like are appropriately used. These can be selected, and more than one of these may be selected.
Similarly to the conductive diamond, the additive to the electrode layer 12 can be appropriately selected from graphite, carbon fiber, carbon nanotube (CNT), and the like.

FIG. 2A shows a schematic plan view of the semiconductor device of FIG.
In FIG. 2A, the multi-layer substrate layer 11 is formed in a substantially circular shape so as to surround the semiconductor chip 10 in plan view, and is integrated with the inside of the cooler 15 in such a form that its end is opened. The structure which was made is taken.

That is, in planar observation, in the multilayer substrate layer 11 formed by laminating the stress buffer layer 14, the insulator layer 13 and the electrode layer 12, the stress buffer layer 14, the insulator layer 13 and the electrode layer 12 are connected to the cooler 15. The exposed portions are partially exposed from the upper surface, and these exposed portions are expanded in diameter in the order of the stress buffer layer 14, the insulator layer 13, and the electrode layer 12, and are a multiple that surrounds the semiconductor chip 10 like an annual ring. It has a ring structure.
Further, most of the multilayer substrate layer 11 is buried in the cooler 15, but the whole is not buried but has an exposed portion as described above, and these exposed portions are: It is substantially flush with the upper surface of the cooler 15 (see FIG. 1).
Needless to say, the semiconductor chip 10 is disposed (mounted) on the electrode layer 12 via the bonding layer 16.

In the above-described multiple ring structure, the planar shape of the exposed portion of each layer is not limited to a circle, and may be a rectangle having a curvature at a corner as shown in FIG.
In this example, each layer of the multilayer substrate layer 11 is formed in a rectangular shape having R portions 18 at the corners so as to surround the semiconductor chip 10, and the cooler in a form in which the end portions are opened (exposed). 15 is integrated (embedded).
In the present invention, the curvature of the R portion 18 and the open shape of the end portion of the multilayer substrate layer 11 are important conditions for relieving stress concentration caused by thermal expansion and contraction.

Next, an embodiment of a method for manufacturing a semiconductor device of the present invention will be described in detail with reference to the drawings.
In the present embodiment, basically, the three layers of the stress buffer layer, the insulating layer, and the electrode layer as described above are sequentially applied to the concave portion that is the curved portion 17 formed in the cooler 15 by using the cold spray method. The multi-layer substrate layer 11 is formed by stacking together.

FIG. 7 shows an apparatus configuration of a cold spray used in the method for manufacturing a semiconductor device of the present invention.
The cold spray process is as follows.
Cold spraying is a method of forming a film by colliding with a base material in a solid state at an ultra high speed together with a carrier gas without melting or gasifying the raw material powder.
First, a method of laminating a composite material containing aluminum as a main component of the stress buffer layer 14 and the electrode layer 12 in the cooler 15 is shown.

Any gas can be used as the carrier gas. In order to obtain better material characteristics, it is preferable to use an inert gas such as Ar (argon), He (helium), or N ₂ (nitrogen) that does not deteriorate the material characteristics due to oxidation.
Nitrogen has the advantage that nitride decomposition is less likely to occur and the advantage that the gas is inexpensive. He has the advantage that the molecular weight is small, a high gas velocity is easily obtained even at low pressure, and the equipment cost can be reduced. In particular, hydrogen may be included to prevent oxidation.

In this embodiment, spraying was performed using He gas.
The carrier gas temperature was adjusted to 300 ° C. The carrier gas temperature is a temperature obtained by mixing both the primary carrier gas heated by the heater and the raw material input gas (see FIG. 7). This temperature adjustment can be adjusted by the gas pressure ratio between the primary carrier gas and the raw material input gas. In the present embodiment, the heater temperature is 600 ° C. Moreover, the particle size of the used powder was 5-30 micrometers.
In addition, lamination | stacking of the ceramic material which is the insulator layer 13 was performed using plasma spraying in this embodiment.

For the lamination of each layer of stress buffer layer, insulator layer, electrode layer, in addition to cold spray, it can be applied as long as it is a method of spraying and laminating powder at high speed, such as aerosol deposition method, spraying method, etc. Since a plurality of layers having high adhesion can be formed with relatively high productivity and an arbitrary mixing ratio, a semiconductor device having high durability against thermal cycling can be obtained.
Moreover, according to the method of the present embodiment, the cooler, the stress buffer layer, the insulator layer, and the electrode layer can be handled as a single component, and the number of components and the number of joints are greatly reduced. Since the structure can be realized, the manufacturing process can be simplified and the cost of the semiconductor device can be reduced.

According to this cold spray method, it is relatively easy and inexpensive to combine aluminum or copper with tungsten or molybdenum, which has been difficult to combine with conventional casting methods. It is a feature.
Further, according to this method, although the stress buffer layer 14 and the three-layer structure in the embodiment shown in FIG. 1, changing which two or more layers of multilayer, or a gradual mixing ratio of the additive material steplessly In this way, it is also possible to manufacture a functionally gradient material having a gradually increased coefficient of thermal expansion, thereby realizing a small and highly functional power module. If this functionally gradient material is used, the effect of mitigating thermal stress is further increased.

In the embodiment shown in FIG. 1, the curved portion 17 is formed in the multilayer substrate layer 11. However, the curved portion 17 is not limited to the curved shape, and may be a bent shape as shown in FIGS. 3 and 4, for example.
3 and 4 show an embodiment relating to a bent shape.

(Embodiment 2)
FIG. 3 is a schematic cross-sectional view showing another embodiment of the semiconductor device of the present invention.
The semiconductor device shown in FIG. 3 has the same configuration as that of the embodiment shown in FIG. 1 except for the multilayer substrate layer 21 in which the bent portion 27 is formed. In other words, the stress buffer layer 24, the insulating layer 23, and the electrode layer 22 are sequentially laminated and bonded to each other from the cooler 25 side toward the semiconductor chip 10 side. A multi-layer substrate layer 21 is formed, and the semiconductor chip 10 is mounted and bonded by the bonding layer 16 thereon.
Further, the stress buffer layer 24 has a three-layer structure, and the three layers have different thermal expansion coefficients, and the thermal expansion coefficients are in the order of 24c, 24b, and 24a from the cooler 25 side toward the semiconductor chip 10 side. It is getting smaller.

(Embodiment 3)
FIG. 4 shows still another embodiment.
The semiconductor device shown in FIG. 4 has the same configuration as that of the above-described embodiment except for the multilayer substrate layer 31 in which the bent portion 37 is formed. A plurality of layers in which the stress buffer layer 34, the insulating layer 33, and the electrode layer 32 are sequentially laminated and bonded to each other from the cooler 35 side toward the semiconductor chip 10 side. A layer substrate layer 31 is formed, on which a semiconductor device 10 is mounted and bonded by a bonding layer 16.
The stress buffer layer 34 has a three-layer configuration, and each of the three layers has a different coefficient of thermal expansion, and the coefficient of thermal expansion decreases in the order of 34c, 34b, and 34a from the cooler 35 side toward the semiconductor chip 10 side. ing.
Even in the embodiment shown in FIG. 3 or FIG. 4, the same effect as that of the embodiment shown in FIG. 1 can be obtained.

  Furthermore, in the above embodiment, the semiconductor device in which each of the semiconductor chip, the multilayer substrate layer, and the cooler is configured has been described. However, the present invention is not limited to this, as shown in FIG. A plurality of multilayer substrate layers and semiconductor chips can be mounted on one cooler.

In FIG. 5, a plurality of recesses 47a and 47b are formed in the cooler 45, and multilayer substrate layers 41a and 41b are laminated by cold spray or the like to form an integral part, respectively, and further on the semiconductor chip 40a. , 40b are mounted via a bonding layer.
With such a configuration, the semiconductor device can be miniaturized and can be manufactured at low cost.

  In the embodiment shown so far, the stress buffer layer, the insulating layer, and the electrode layer constituting the multilayer substrate layer are all integrated in the cooler, and only the end thereof is opened. If at least the insulating layer is insulated, it is necessary to release the end, and the electrode layer on the outermost surface also needs to be released. However, the stress buffer layer is embedded in the cooler. There is also a possibility.

(Reference form 1)
FIG. 6 shows another embodiment.
The above described example embodiment, an example with an integrated multilayer substrate layer inside the cooler, as shown in FIG. 6, a separate independent multilayer substrate layer and the cooler, which cooler An example of mounting with a semiconductor chip is shown above. In this embodiment, the multilayer substrate layer has a flat plate shape.

The semiconductor device shown in FIG. 6 includes a multilayer substrate layer 51 in which the stress buffer layer 54, the insulator layer 53, and the electrode layer 52 are sequentially laminated and bonded from the cooler 55 side to the semiconductor chip 10 side. This is a semiconductor device in which the multilayer substrate layer 51 is bonded to the upper part of the cooler 55 by a bonding layer 57 and the semiconductor chip 10 is mounted and bonded to the semiconductor substrate 10 via the bonding layer 56.
Similarly to the above, the stress buffer layer 54 has a three-layer structure, and these three layers have different thermal expansion coefficients, and the thermal expansion is performed in the order of 54c, 54b, and 54a from the cooler 55 side to the semiconductor chip 10 side. The rate is getting smaller.

The multilayer substrate layer shown in this embodiment can also be easily manufactured using a cold spray or the like as in the above embodiment.
The multi-layer substrate layer shown in this embodiment has a flat plate shape, and is easy to manufacture because of its simple shape. Since the same substrate can be used independently, there is an advantage that the application range is widened.

As mentioned above, although this invention was demonstrated with some embodiment and an Example, this invention is not limited to these, A various deformation | transformation is possible within the range of the summary of this invention.
For example, in the semiconductor device mounting and bonding method of the semiconductor device described above, there is no problem even if a general Sn-based solder is used. However, with the configuration of the present invention, the solder layer itself is subjected to thermal cycling. Since it is not necessary to absorb the generated thermal stress, the options for the joining method can be expanded. For example, a bonding method having a relatively low stress buffering function, such as a bonding method using sintering of silver nanoparticles or copper nanoparticles, can be suitably used. In addition, for example, when using a eutectic reaction and joining by a joining method that uses a fine groove formed as a stress concentration part for the destruction of an oxide film, the joining part is less deteriorated with time and excellent in durability. A high-performance semiconductor device with low electrical resistance and thermal resistance at the interface can be obtained. In this case, it is sufficient that the stress concentration portion is formed in any one of the layers to be joined.

10, 40a, 40b Semiconductor chip 12 Negative electrode terminal 11, 21, 31, 41, 51 Multi-layer substrate layer
12, 22, 32, 52 Electrode layer 13, 23, 33, 53 Insulating layer
14, 24, 34, 54 Stress buffer layer 15, 25, 35, 45, 55 Cooler 16, 56, 57 Bonding layer

Claims (11)

In a semiconductor device including a semiconductor, a cooler for cooling the semiconductor, an electrode, an insulator, and a stress buffer material,
Between the semiconductor and the cooler, a multilayer substrate layer formed by laminating a stress buffer layer, an insulator layer and an electrode layer in this order from the cooler side is interposed,
The semiconductor is disposed on the electrode layer;
The multilayer substrate layer is embedded in the cooler;
At least the insulator layer and the electrode layer of the multilayer substrate layer are partially exposed from the surface of the cooler, and the exposed portion has a multiple ring structure in which the diameter of the electrode layer and the insulator layer is increased in this order,
A semiconductor device, wherein a buried portion of the multilayer substrate layer has a curved or bent cross-sectional shape.   2. The semiconductor according to claim 1, wherein the stress buffer layer and the electrode layer are made of a composite material including copper (Cu) or aluminum (Al) and an additive for reducing the thermal expansion coefficient of copper or aluminum. apparatus.   The semiconductor device according to claim 2, wherein the content of the additive contained in the stress buffer layer gradually increases from the cooler side toward the insulating layer side.   3. The stress buffer layer is composed of a plurality of layers, and the content of the additive in each layer is gradually increased from the cooler side layer to the insulating layer side layer. The semiconductor device described. The additive to the stress buffer layer is at least one selected from the group consisting of silicon carbide (SiC), alumina (Al ₂ O ₃ ), boron carbide (B ₄ C), tungsten, molybdenum, graphite, and carbon fiber. The semiconductor device according to claim 2, wherein the semiconductor device is a material of   The additive in the electrode layer is at least one material selected from the group consisting of conductive diamond, graphite, carbon fiber, and carbon nanotube (CNT). The semiconductor device according to one item.   The semiconductor device according to claim 1, wherein a plurality of multilayer substrate layers and a semiconductor are formed for one cooler. In manufacturing the semiconductor device according to any one of claims 1 to 7,
The method of manufacturing a semiconductor device, characterized in that the multi-layer substrate layer, stress buffer layers in the condenser are sequentially formed integrally laminated by cold spray or sprayed insulating layer and electrode layer. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the cooler has a recess, and the multilayer substrate layer is formed in the recess. In manufacturing the semiconductor device according to any one of claims 1 to 7,
The cooler, the stress buffer layer, the insulator layer, and the electrode layer are joined by a joining method using a combination of a eutectic reaction and a fine groove formed as a stress concentration portion for destruction of an oxide film. A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 10, wherein the cooler has a recess, and the multilayer substrate layer is formed in the recess.

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