JP6309548B2 - 低グリッチノイズdac - Google Patents
低グリッチノイズdac Download PDFInfo
- Publication number
- JP6309548B2 JP6309548B2 JP2015561554A JP2015561554A JP6309548B2 JP 6309548 B2 JP6309548 B2 JP 6309548B2 JP 2015561554 A JP2015561554 A JP 2015561554A JP 2015561554 A JP2015561554 A JP 2015561554A JP 6309548 B2 JP6309548 B2 JP 6309548B2
- Authority
- JP
- Japan
- Prior art keywords
- stages
- current
- dac
- bit
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/78—Simultaneous conversion using ladder network
- H03M1/785—Simultaneous conversion using ladder network using resistors, i.e. R-2R ladders
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0863—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
- H03M1/687—Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/742—Simultaneous conversion using current sources as quantisation value generators
- H03M1/747—Simultaneous conversion using current sources as quantisation value generators with equal currents which are switched by unary decoded digital signals
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/791,536 | 2013-03-08 | ||
| US13/791,536 US8896472B2 (en) | 2013-03-08 | 2013-03-08 | Low glitch-noise DAC |
| PCT/US2014/020373 WO2014138098A1 (en) | 2013-03-08 | 2014-03-04 | Low glitch-noise dac |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016251363A Division JP2017103783A (ja) | 2013-03-08 | 2016-12-26 | 低グリッチノイズdac |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2016513915A JP2016513915A (ja) | 2016-05-16 |
| JP6309548B2 true JP6309548B2 (ja) | 2018-04-11 |
Family
ID=50389507
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015561554A Expired - Fee Related JP6309548B2 (ja) | 2013-03-08 | 2014-03-04 | 低グリッチノイズdac |
| JP2016251363A Pending JP2017103783A (ja) | 2013-03-08 | 2016-12-26 | 低グリッチノイズdac |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016251363A Pending JP2017103783A (ja) | 2013-03-08 | 2016-12-26 | 低グリッチノイズdac |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US8896472B2 (enExample) |
| EP (1) | EP2965431B1 (enExample) |
| JP (2) | JP6309548B2 (enExample) |
| KR (1) | KR101633008B1 (enExample) |
| CN (1) | CN105009457B (enExample) |
| WO (1) | WO2014138098A1 (enExample) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9124282B1 (en) * | 2014-03-10 | 2015-09-01 | Analog Devices Global | Digital-to-analog converter with correction for parasitic routing resistance |
| US9178524B1 (en) * | 2014-05-27 | 2015-11-03 | Qualcomm Incorporated | Hybrid R-2R structure for low glitch noise segmented DAC |
| JP6784020B2 (ja) * | 2015-12-03 | 2020-11-11 | セイコーエプソン株式会社 | 回路装置、発振器、電子機器及び移動体 |
| KR20170083222A (ko) * | 2016-01-08 | 2017-07-18 | 삼성전자주식회사 | 헤드폰 드라이버 및 이를 포함하는 사운드 프로세서 |
| US10200055B2 (en) * | 2017-01-11 | 2019-02-05 | Analog Devices Global | Glitch characterization in digital-to-analog conversion |
| WO2018133927A1 (en) * | 2017-01-18 | 2018-07-26 | Huawei Technologies Co., Ltd. | Digital-to-analog converter circuit with two encoding schemes |
| US9819357B1 (en) * | 2017-05-11 | 2017-11-14 | Qualcomm Incorporated | Current removal for digital-to-analog converters |
| US10454487B1 (en) | 2018-08-30 | 2019-10-22 | Qualcomm Incorporated | Segmented resistor architecture for digital-to-analog converters |
| CN114337676B (zh) * | 2021-12-14 | 2024-05-17 | 山东芯慧微电子科技有限公司 | 一种精简结构的iDAC电路 |
| CN114640352B (zh) * | 2022-03-28 | 2023-05-09 | 电子科技大学 | 一种基于电流舵和r-2r电阻混合型的dac |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5442318A (en) * | 1993-10-15 | 1995-08-15 | Hewlett Packard Corporation | Gain enhancement technique for operational amplifiers |
| JPH10112654A (ja) * | 1996-10-07 | 1998-04-28 | Toshiba Corp | 電流セグメント方式ディジタル・アナログ変換器 |
| US6518906B2 (en) * | 2000-07-25 | 2003-02-11 | Agere Systems Guardian Corp. | Use of current folding to improve the performance of a current -steered DAC operating at low supply voltage |
| JP3751812B2 (ja) * | 2000-09-21 | 2006-03-01 | 株式会社東芝 | カスコードトランジスタを出力段に有する電子回路装置 |
| US6650265B1 (en) * | 2001-04-30 | 2003-11-18 | Engim, Inc. | Method and architecture for varying power consumption of a current mode digital/analog converter in proportion to performance parameters |
| US6633248B2 (en) | 2001-05-29 | 2003-10-14 | Intel Corporation | Converting digital signals to analog signals |
| US6583744B2 (en) * | 2001-06-22 | 2003-06-24 | Texas Instruments Incorporated | Correction circuit for beta mismatch between thermometer encoded and R-2R ladder segments of a current steering DAC |
| US6642867B1 (en) * | 2002-07-03 | 2003-11-04 | Maxim Integrated Products, Inc. | Replica compensated heterogeneous DACs and methods |
| US6703956B1 (en) * | 2003-01-08 | 2004-03-09 | Agilent Technologies, Inc. | Technique for improved linearity of high-precision, low-current digital-to-analog converters |
| US7132970B2 (en) * | 2004-10-29 | 2006-11-07 | Broadcom Corporation | Delay equalized Z/2Z ladder for digital to analog conversion |
| US7042381B1 (en) * | 2004-10-29 | 2006-05-09 | Broadcom Corporation | Delay equalized Z/2Z ladder for digital to analog conversion |
| JP2006279172A (ja) * | 2005-03-28 | 2006-10-12 | Sharp Corp | オフセット除去回路およびそれを用いた差動増幅器 |
| DE602007005977D1 (de) * | 2006-01-26 | 2010-06-02 | Nihon Dempa Kogyo Co | Vco-ansteuerschaltung und frequenzsynthesizer |
| TWI370620B (en) | 2007-11-15 | 2012-08-11 | Univ Chung Yuan Christian | Folded r-2r ladder current-steering digital to analog converter |
| WO2010087410A1 (ja) | 2009-01-29 | 2010-08-05 | 日本電信電話株式会社 | 電流スイッチ・セルおよびディジタル/アナログ変換器 |
| US7812665B2 (en) * | 2009-02-23 | 2010-10-12 | Number 14 B.V. | Amplifiers with input offset trim and methods |
| US8169353B2 (en) * | 2009-09-30 | 2012-05-01 | Qualcomm, Incorporated | Wideband digital to analog converter with built-in load attenuator |
| US8094055B2 (en) * | 2010-01-26 | 2012-01-10 | Power Integrations, Inc. | Compact digital-to-analog converter |
| JP2012050004A (ja) * | 2010-08-30 | 2012-03-08 | Renesas Electronics Corp | Da変換器 |
| CN102403966B (zh) * | 2010-09-14 | 2015-07-22 | 意法半导体研发(上海)有限公司 | 减少数模转换器电压内插放大器输入差分对的方法和装置 |
| US8860597B2 (en) | 2011-07-06 | 2014-10-14 | Qualcomm Incorporated | Digital to-analog converter circuitry with weighted resistance elements |
-
2013
- 2013-03-08 US US13/791,536 patent/US8896472B2/en active Active
-
2014
- 2014-03-04 CN CN201480012819.8A patent/CN105009457B/zh active Active
- 2014-03-04 KR KR1020157027325A patent/KR101633008B1/ko not_active Expired - Fee Related
- 2014-03-04 JP JP2015561554A patent/JP6309548B2/ja not_active Expired - Fee Related
- 2014-03-04 WO PCT/US2014/020373 patent/WO2014138098A1/en not_active Ceased
- 2014-03-04 EP EP14713304.5A patent/EP2965431B1/en not_active Not-in-force
-
2016
- 2016-12-26 JP JP2016251363A patent/JP2017103783A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| WO2014138098A1 (en) | 2014-09-12 |
| KR20150119479A (ko) | 2015-10-23 |
| US20140253357A1 (en) | 2014-09-11 |
| EP2965431A1 (en) | 2016-01-13 |
| JP2017103783A (ja) | 2017-06-08 |
| US8896472B2 (en) | 2014-11-25 |
| CN105009457B (zh) | 2018-05-18 |
| JP2016513915A (ja) | 2016-05-16 |
| CN105009457A (zh) | 2015-10-28 |
| EP2965431B1 (en) | 2018-08-15 |
| KR101633008B1 (ko) | 2016-06-23 |
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