JP6289689B1 - Memory control device and computer system - Google Patents

Abstract

An object of the present invention is to eliminate waiting for instruction execution by DMA transfer and shorten the processing time of a processor. When a read request for reading data from a specified address Raddr in a memory 12 is detected by an access detector 22, a transfer management unit 23 of the memory control device 13 sets an area including the specified address Raddr as a transfer destination. It is determined whether there is an unexecuted DMA transfer. If there is no such unexecuted DMA transfer, the transfer management unit 23 reads data from the designated address Raddr and transmits it to the processor 11. If there is such an unexecuted DMA transfer, the transfer management unit 23 reads the data from the transfer source address of the data transferred to the designated address Raddr in the unexecuted DMA transfer and transmits the data to the processor 11. Thereafter, the transfer management unit 23 performs the unexecuted DMA transfer. [Selection] Figure 3

Description

  The present invention relates to a memory control device and a computer system.

Generally, a computer system includes a CPU, a memory, and a DMAC. “CPU” is an abbreviation for Central Processing Unit. “DMAC” is an abbreviation for DMA Controller. “DMA” stands for Direct Memory
Abbreviation for Access.

  Data transfer between memory areas is a process that consumes hardware resources and time among the processes of a computer. Since the DMAC performs the transfer process instead of the data transfer by the CPU, the CPU can execute processes other than the transfer in parallel with the transfer process. The transfer processing by DMAC is called DMA transfer.

  An instruction for generating a DMA transfer is called a DMA transfer instruction. A subsequent instruction of the instruction may access the transfer destination area of the DMA transfer by the DMA transfer instruction. That is, there may be a dependency between the DMA transfer instruction and the subsequent instruction. In this case, the subsequent instruction needs to be executed after waiting for the end of the preceding DMA transfer instruction.

  As a specific example, it is assumed that there is a dependency between an instruction A that performs DMA transfer and an instruction B that is a subsequent instruction of the instruction A. In that case, execution of the instruction B in the CPU is waited until the DMAC completes the DMA transfer by the instruction A from the CPU. The completion of the DMA transfer is notified by an interrupt from the DMAC to the CPU. Therefore, execution of the instruction B in the CPU is waited until the DMAC generates an interrupt to the CPU.

  Although a technique for devising the arrangement of instructions so that the dependency relationship does not occur as much as possible is applied to a compiler or the like, the dependency relationship is not completely eliminated. Therefore, there is a possibility that the CPU waits for DMA transfer.

  In Patent Document 1, the DMAC detects a reference request from the CPU for data to be transferred by DMA, performs DMA transfer of the data to be requested by reference prior to the DMA transfer being executed, and stores the transferred data. A technique to be referred to the CPU is described.

JP 2004-145376 A

  In the technique described in Patent Document 1, the CPU cannot refer to the target data until the DMAC completes the DMA transfer of the target data for the reference request and generates an interrupt to the CPU. That is, when there is a dependency between the DMA transfer instruction and the subsequent instruction, it is inevitable that the CPU waits for the DMA transfer.

  An object of the present invention is to eliminate the waiting time for executing an instruction by DMA transfer and to shorten the processing time of the processor.

A memory control device according to an aspect of the present invention includes:
A memory control device that performs DMA transfer, which is data transfer between memory areas,
An access detection unit for detecting a request from the processor;
When a read request for reading data from the designated address of the memory is detected by the access detection unit, if there is no DMA transfer that is performed with the area including the designated address as a transfer destination, the data is read from the designated address. If there is an unexecuted DMA transfer, the data is read from the transfer source address of the data to be transferred to the designated address in the unexecuted DMA transfer and transmitted to the processor. A transfer management unit that performs the unexecuted DMA transfer.

  In the present invention, if the DMA transfer of the target data of the reference request is not performed when the memory control device detects the reference request from the processor for the data of the DMA transfer target, before the DMA transfer is performed, The processor refers to the data before transfer. Therefore, it is possible to eliminate the waiting for instruction execution by DMA transfer and to shorten the processing time of the processor.

1 is a block diagram illustrating a configuration of a computer system according to a first embodiment. FIG. 3 is a diagram illustrating a configuration of a memory of the computer system according to the first embodiment. 1 is a block diagram illustrating a configuration of a memory control device according to a first embodiment. FIG. 3 is a diagram showing a configuration of a transfer source block pointer, a transfer management table, and an update management table held by the memory control device according to the first embodiment. 4 is a flowchart illustrating a processing procedure when a read request is received from a processor in the memory control device according to the first embodiment. FIG. 3 is a diagram illustrating an example of the operation of the computer system according to the first embodiment. 4 is a flowchart illustrating a processing procedure when a write request is received from a processor in the memory control device according to the first embodiment. 4 is a flowchart showing a DMA transfer processing procedure in the memory control device according to the first embodiment; 4 is a flowchart showing a DMA transfer processing procedure in the memory control device according to the first embodiment; 5 is a flowchart showing a processing procedure of initialization in the memory control device according to the first embodiment. 6 is a flowchart showing a transfer management table registration processing procedure in the memory control device according to the first embodiment; 5 is a flowchart showing a transfer management table search processing procedure in the memory control device according to the first embodiment; 6 is a flowchart illustrating a processing procedure for searching a final block of a transfer management table in the memory control device according to the first embodiment;

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals. In the description of the embodiments, the description of the same or corresponding parts will be omitted or simplified as appropriate. The present invention is not limited to the embodiments described below, and various modifications can be made as necessary. For example, the embodiment described below may be partially implemented.

Embodiment 1 FIG.
This embodiment will be described with reference to FIGS.

*** Explanation of configuration ***
A configuration of a computer system 10 according to the present embodiment will be described with reference to FIG.

  The computer system 10 includes a processor 11, a memory 12, a memory control device 13, and a peripheral bus bridge 14. The processor 11 is connected to other hardware such as the memory control device 13 and the peripheral bus bridge 14 via the system bus 16 and controls these other hardware. The memory control device 13 is connected to the memory 12 via the memory bus 17 and controls the memory 12. The peripheral bus bridge 14 is connected to an external I / O device 15 via the I / O bus 18, and transmits data to the I / O device 15 and receives data from the I / O device 15. “I / O” is an abbreviation for Input / Output.

  The processor 11 is a CPU, for example.

  The memory 12 is, for example, a RAM or a flash memory. “RAM” is an abbreviation for Random Access Memory.

  The memory control device 13 is, for example, a logic IC, FPGA, or ASIC. “IC” is an abbreviation for Integrated Circuit. “FPGA” is an abbreviation for Field-Programmable Gate Array. “ASIC” is an abbreviation for Application Specific Integrated Circuit.

  The I / O device 15 is, for example, an input device such as a mouse, a keyboard, or a touch panel, or an output device such as a display or a printer.

  The configuration of the memory 12 will be described with reference to FIG.

  The memory 12 is managed by n blocks having a certain capacity as a unit. That is, the memory 12 has n areas. “N” is a power of 2. Therefore, the block number can be easily obtained from the memory address.

  Each block is composed of m entries with the width of the memory bus 17 as a unit. “M” is a power of 2.

  The configuration of the memory control device 13 will be described with reference to FIG.

  The memory control device 13 includes a system bus I / F 21, an access detection unit 22, a transfer management unit 23, an access control unit 24, and a DMAC 25. “I / F” is an abbreviation for InterFace.

  The system bus I / F 21 is connected to the processor 11 via the system bus 16. The access control unit 24 is connected to the memory 12 via the memory bus 17.

  The memory control device 13 has a function of performing DMA transfer, which is data transfer between areas of the memory 12. In order to realize this function, in this embodiment, a DMAC 25 that controls DMA transfer and an access control unit 24 that accesses the memory 12 are arranged in the memory control device 13. As the DMAC 25, the same one as the conventional DMAC can be used. As the access control unit 24, the same circuit as a conventional memory access circuit can be used.

  When the memory control device 13 detects a reference request from the processor 11 for the DMA transfer target data, if the DMA transfer of the reference request target data is not performed, the transfer is performed before the DMA transfer is performed. It further has a function of causing the processor 11 to refer to previous data. In order to realize this function, in the present embodiment, an access detection unit 22 that detects a request from the processor 11 through the system bus I / F 21 is interposed between the system bus I / F 21, the access control unit 24, and the DMAC 25. The transfer management unit 23 is arranged in the memory control device 13.

  In the following description, when the request from the processor 11 is a write request, a memory address indicating a write target is indicated as a designated address Waddr. When the request from the processor 11 is a read request, a memory address indicating a reading target is indicated as a designated address Raddr, and a memory address indicating a transfer source of data transferred to the designated address Raddr is indicated as an address Saddr.

The configuration of the transfer source block pointer 30, the transfer management table 40, and the update management table 50 held by the transfer management unit 23 will be described with reference to FIG. In FIG. 4, “don't
“care” is an initial value having no meaning.

  The transfer source block pointer 30 includes a flag 31. The transfer source block pointer 30 indicates the block number of the DMA transfer source when the flag 31 is “valid”, which is equivalent to indicating the transfer source block number 41 of the transfer management table 40. In the initial state, the flag 31 is set to “invalid”.

  The transfer management table 40 includes items such as a transfer source block number 41, a transfer destination block number 42, a chain block number 43, and an update flag 44. Each item exists for each block number. That is, there are n items.

  The transfer source block number 41 means the block number of the transfer source block at the time of DMA transfer.

  The transfer destination block number 42 is a block number to which data of the block of the transfer source block number 41 is transferred. That is, the transfer destination block number 42 means the block number of the transfer destination block at the time of DMA transfer.

  The chain block number 43 is a transfer source block number 41 of a block to be transferred next when performing DMA transfer of a plurality of blocks. However, if the transfer source block number 41 and the chain block number 43 are the same, it means that the corresponding block is the last block subject to DMA transfer. In the initial state, the same block number as the transfer source block number 41 is set in the chain block number 43.

  The update flag 44 indicates whether or not the block having the transfer destination block number 42 is a block requested to be rewritten by the processor 11 before the DMA transfer. In the initial state, the update flag 44 is set to “invalid”.

  As described above, in the present embodiment, the transfer management table 40 held by the transfer management unit 23 has transfer source block numbers 41 and numbers identifying the transfer source and transfer destination areas in the DMA transfer before the execution, respectively. It is set as the transfer destination block number 42. In the present embodiment, even if any combination of numbers is “stored” as the transfer source block number 41 and the transfer destination block number 42 in the transfer management table 40, the flag 31 of the transfer source block pointer 30 is “invalid”. Sometimes the combination setting is invalid. As a modification, the transfer source block pointer 30 is not applied, and only the combination is “stored” in the transfer management table 40, and the combination is set as the transfer source block number 41 and the transfer destination block number 42. It may be considered that it is set.

  The update management table 50 includes items such as a transfer destination block number 51, a table valid flag 52, an update data buffer 53, and an update flag 54. The update management table 50 manages the data of the block having the transfer destination block number 42 in which the update flag 44 of the transfer management table 40 is “valid”. There are k update management tables 50. “K” is an arbitrary integer.

  The transfer destination block number 51 means the block number of a block requested to be rewritten by the processor 11 before the DMA transfer.

  The table valid flag 52 indicates whether the update management table 50 is valid. In the initial state, the table valid flag 52 is set to “invalid”.

  The update data buffer 53 is a buffer for storing data after being rewritten by a request from the processor 11. The update data buffer 53 is a buffer having a capacity of one block. In other words, the update data buffer 53 is composed of m entries.

  One update flag 54 is assigned to each entry in the update data buffer 53. The update flag 54 of the entry storing the data rewritten by the request from the processor 11 becomes “valid”. In the initial state, the update flag 54 is set to “invalid”.

  As described above, in the present embodiment, the update management table 50 held by the transfer management unit 23 has the specified address when a write request for writing data to the specified address Waddr of the memory 12 is detected by the access detection unit 22. This is used only when there is an unexecuted DMA transfer with the area including Waddr as the transfer destination. The update management table 50 includes a number for identifying a transfer destination area in the unexecuted DMA transfer and information indicating a position in the update data buffer 53 where data to be transferred to the designated address Waddr is written. It is set as the transfer destination block number 51 and update information. The update information may be recorded in an arbitrary format, but in the present embodiment, it is recorded in the format of the update flag 54 for each entry. In the present embodiment, even if a combination of some number and information indicating some position is “stored” in the update management table 50 as the transfer destination block number 51 and the update information, the table valid flag 52 is “invalid”. Sometimes the combination setting is invalid. As a modification, the table validity flag 52 is not applied, and the combination is “stored” in the update management table 50, and the combination is “set” as the transfer destination block number 51 and the update information. You may consider that

*** Explanation of operation ***
The operation of the memory control device 13 according to the present embodiment will be described with reference to each flowchart. The operation of the memory control device 13 corresponds to the memory control method according to the present embodiment.

  With reference to FIG. 5, a processing procedure when the memory control device 13 receives a read request from the processor 11 will be described.

  In step S <b> 101, the transfer management unit 23 determines whether there is an unexecuted DMA transfer when the access detection unit 22 detects a read request for reading data from the specified address Raddr of the memory 12. If there is an unexecuted DMA transfer, the transfer management unit 23 performs the process of step S102. On the other hand, if there is no unexecuted DMA transfer, the transfer management unit 23 performs the process of step S104.

  In step S <b> 102, the transfer management unit 23 searches for the transfer destination block number 42 in the transfer management table 40.

  In step S <b> 103, the transfer management unit 23 determines whether or not the memory read address of the processor 11 is included in the area of the transfer destination block number 42. That is, the transfer management unit 23 determines whether there is an unexecuted DMA transfer in which the area including the designated address Raddr is a transfer destination. Specifically, the transfer management unit 23 determines whether or not there is such an unexecuted DMA transfer depending on whether or not the number for identifying the area including the designated address Raddr is set in the transfer management table 40 as the transfer destination block number 42. Determine. If there is no such unexecuted DMA transfer, the transfer management unit 23 performs the process of step S104. On the other hand, if there is such an unexecuted DMA transfer, the transfer management unit 23 performs the process of step S105. That is, when a read request is detected by the access detection unit 22, if the number for identifying the area including the designated address Raddr is set in the transfer management table 40 as the transfer destination block number 42, the transfer management unit 23 The process of step S105 is performed.

  In step S <b> 104, the transfer management unit 23 reads data from the memory 12. Specifically, the transfer management unit 23 uses the access control unit 24 to read data from the designated address Raddr. Then, the transfer management unit 23 performs the process of step S108.

  In step S <b> 105, the transfer management unit 23 acquires the transfer source block number 41 corresponding to the transfer destination block number 42 hit in step S <b> 103 from the transfer management table 40.

  In step S106, the transfer management unit 23 calculates an address Saddr to be read in the area of the transfer source block number 41 acquired in step S105. Specifically, the transfer management unit 23 transfers the acquired transfer source block number 41 and the specified address Raddr to the specified address Raddr in an unexecuted DMA transfer that uses the area including the specified address Raddr as the transfer destination. The data transfer source address Saddr is calculated.

  In step S107, the transfer management unit 23 reads data from the address Saddr calculated in step S106. Specifically, the transfer management unit 23 uses the access control unit 24 to read data from the calculated address Saddr.

  In step S108, the transfer management unit 23 returns the data read in step S102 or step S107 to the processor 11 and ends the operation of FIG. Specifically, the transfer management unit 23 transmits the read data to the processor 11 via the system bus I / F 21. If it is determined in step S101 that there is an unexecuted DMA transfer, the transfer management unit 23 further uses the DMAC 25 to transmit an interrupt to notify the completion of the DMA transfer to the processor 11.

  If it is determined in step S101 that there is an unexecuted DMA transfer, the transfer management unit 23 performs the unexecuted DMA transfer after the operation of FIG.

  Here, FIG. 6 shows an example in which the instruction A, the instruction B, the instruction C, and the instruction D are sequentially executed in the processor 11.

  In this example, it is assumed that there is a dependency relationship between an instruction A accompanied by DMA transfer and an instruction B that is a subsequent instruction of the instruction A and accompanied by reading of the memory 12. When the memory control device 13 receives the instruction A from the processor 11 by the operation of FIG. 5, that is, before performing the DMA transfer requested by the instruction A, the memory control device 13 immediately receives an interrupt for notifying the completion of the DMA transfer. To cause the processor 11 to proceed with subsequent processing. Therefore, it is possible to eliminate the waiting for execution of an instruction by DMA transfer and to shorten the processing time of the processor 11.

  With reference to FIG. 7, a processing procedure when the memory control device 13 receives a write request from the processor 11 will be described.

  In step S201, the transfer management unit 23 determines whether there is an unexecuted DMA transfer when the access detection unit 22 detects a write request for writing data to the designated address Waddr of the memory 12. If there is an unexecuted DMA transfer, the transfer management unit 23 performs the process of step S202. On the other hand, if there is no unexecuted DMA transfer, the transfer management unit 23 performs the process of step S204. Note that the transfer management unit 23 has already received the data transmitted from the processor 11 along with the write request via the system bus I / F 21 at the time of performing the process of step S201.

  In step S202, the transfer management unit 23 searches for the transfer destination block number 42 in the transfer management table 40.

  In step S203, the transfer management unit 23 determines whether or not the memory write address of the processor 11 is included in the area of the transfer destination block number 42. That is, the transfer management unit 23 determines whether there is an unexecuted DMA transfer in which an area including the designated address Waddr is a transfer destination. Specifically, the transfer management unit 23 determines whether or not there is such an unexecuted DMA transfer depending on whether or not the number for identifying the area including the designated address Waddr is set in the transfer management table 40 as the transfer destination block number 42. Determine. If there is no such unexecuted DMA transfer, the transfer management unit 23 performs the process of step S204. On the other hand, if there is such an unexecuted DMA transfer, the transfer management unit 23 performs the process of step S205. That is, when the write request is detected by the access detection unit 22, if the number for identifying the area including the designated address Waddr is set in the transfer management table 40 as the transfer destination block number 42, the transfer management unit 23 The process of step S205 is performed.

  In step S <b> 204, the transfer management unit 23 writes data to the memory 12. Specifically, the transfer management unit 23 uses the access control unit 24 to write the data transmitted from the processor 11 to the designated address Waddr, and ends the operation of FIG.

  In step S205, the transfer management unit 23 changes the update flag 44 corresponding to the transfer destination block number 42 hit in step S203 to “valid”.

  In step S206, the transfer management unit 23 searches the update management table 50 in which the table valid flag 52 is “invalid”.

  In step S207, the transfer management unit 23 sets the transfer destination block number 51 of the update management table 50 in which the table valid flag 52 is “invalid” and the transfer destination in which the update flag 44 is “valid” in the transfer management table 40. Change to the same block number as block number 42.

  In step S208, the transfer management unit 23 calculates the address of the data to be written in the area of the transfer destination block number 42 hit in step S203. Specifically, the transfer management unit 23 calculates which entry in the transfer destination block is the write destination from the designated address Waddr.

  In step S209, the transfer management unit 23 determines a target entry in the update data buffer 53 from the address calculated in step S208.

  In step S210, the transfer management unit 23 writes data to the target entry determined in step S209. That is, the transfer management unit 23 writes the data transmitted from the processor 11 in the update data buffer 53.

  In step S211, the transfer management unit 23 changes the update flag 54 corresponding to the target entry in which the data is written in step S210 to “valid”. That is, the transfer management unit 23 secures the update data buffer 53 later. Then, the transfer management unit 23 ends the operation of FIG. Note that the transfer management unit 23 may perform the process of step S211 before the process of step S210. That is, the transfer management unit 23 may reserve the update data buffer 53 before writing data.

  If it is determined in step S201 that there is an unexecuted DMA transfer, the transfer management unit 23 performs the unexecuted DMA transfer after the operation of FIG. However, if the transfer management unit 23 determines in step S203 that there is an unexecuted DMA transfer with the area including the designated address Waddr as the transfer destination, the transfer management unit 23 transfers the data to the designated address Waddr after the operation of FIG. Untransferred DMA transfer excluding data transfer and data transfer from the update data buffer 53 to the designated address Waddr are performed. As will be described later, the transfer management unit 23 releases the update data buffer 53 after performing data transfer from the update data buffer 53 to the designated address Waddr.

  The DMA transfer processing procedure will be described with reference to FIGS.

  In step S301, the transfer management unit 23 determines whether the flag 31 of the transfer source block pointer 30 is “valid”. If the flag 31 is “invalid”, the transfer management unit 23 ends the operation of FIG. On the other hand, if the flag 31 is “valid”, the transfer management unit 23 performs the process of step S302.

  In step S302, the transfer management unit 23 selects the transfer source block number 41 in the transfer management table 40 pointed to by the transfer source block pointer 30 as a target.

  In step S303, the transfer management unit 23 determines whether the update flag 44 of the target block in the transfer management table 40 is “valid”. If the update flag 44 is “invalid”, the transfer management unit 23 performs the process of step S304. On the other hand, if the update flag 44 is “valid”, the transfer management unit 23 performs the process of step S401.

  In step S304, the transfer management unit 23 reads data for the block size from the address corresponding to the target transfer source block number 41.

  In step S <b> 305, the transfer management unit 23 acquires the transfer destination block number 42 corresponding to the target transfer source block number 41 from the transfer management table 40. Then, the transfer management unit 23 writes the data read in step S304 for the block size to the address corresponding to the acquired transfer destination block number 42.

  In step S <b> 306, the transfer management unit 23 acquires the chain block number 43 corresponding to the target transfer source block number 41 from the transfer management table 40. Then, the transfer management unit 23 determines whether or not the target transfer source block number 41 matches the acquired chain block number 43. If they match, the transfer management unit 23 performs the process of step S307. On the other hand, if they do not match, the transfer management unit 23 performs the process of step S308.

  In step S307, the transfer management unit 23 changes the flag 31 of the transfer source block pointer 30 to “invalid” and ends the operation of FIG.

  In step S308, the transfer management unit 23 selects the chain block number 43 acquired in step S306 as a target. That is, the transfer management unit 23 selects the transfer source block number 41 that matches the chain block number 43 acquired in step S306 as a target.

  In step S309, the transfer management unit 23 sets the chain block number 43 corresponding to the transfer source block number 41 that is the target immediately before step S308 in the transfer management table 40 to the same block number as the transfer source block number 41. change. That is, the transfer management unit 23 returns the chain block number 43 of the target block immediately before step S308 to the initial value. Then, the transfer management unit 23 performs the process of step S303 again.

  In step S401, the transfer management unit 23 targets the update management table 50 in which the table valid flag 52 is “valid” and the transfer destination block number 51 matches the transfer destination block number 42 of the transfer management table 40. Select Then, the transfer management unit 23 uses “i” as a counter that is incremented by 1 from 0 to m, and performs a loop process from step S402 to step S406.

  In step S402, the transfer management unit 23 determines whether the update flag 54 of the entry i in the update data buffer 53 of the target update management table 50 is “valid”. If the update flag 54 is “invalid”, the transfer management unit 23 performs the process of step S403. On the other hand, if the update flag 54 is “valid”, the transfer management unit 23 performs the process of step S405.

  In step S403, the transfer management unit 23 reads data from the corresponding address of the transfer source block. That is, the transfer management unit 23 reads the entry i in the area of the target transfer source block number 41.

  In step S404, the transfer management unit 23 selects the data read in step S404 as transfer source data. Then, the transfer management unit 23 performs the process of step S406.

  In step S405, the transfer management unit 23 selects the entry i in the update data buffer 53 of the target update management table 50 as transfer source data.

  In step S406, the transfer management unit 23 writes the transfer source data to the corresponding address of the transfer destination block. That is, the transfer management unit 23 overwrites the entry i in the area of the transfer destination block number 42 corresponding to the target transfer source block number 41 with the transfer source data. If the counter i is less than m, the transfer management unit 23 performs the process of step S402 again. If the counter i is m, the transfer management unit 23 performs the process of step S407.

  In step S407, the transfer management unit 23 changes the update flag 54 of the entry in which the update flag 54 is “valid” in the update data buffer 53 of the target update management table 50 to “invalid”. That is, the transfer management unit 23 releases the update data buffer 53. The transfer management unit 23 also changes the table valid flag 52 of the target update management table 50 to “invalid”. Further, the transfer management unit 23 sets the update flag 44 of the target block in the transfer management table 40 to “invalid”. Then, the transfer management unit 23 performs the process of step S306.

  As described above, in the present embodiment, the transfer management unit 23 uses the update management table as a transfer destination block number 51 to identify a transfer destination area in each DMA transfer when performing each DMA transfer. If it is set to 50, update information corresponding to the transfer destination block number 51 is acquired from the update management table 50. Then, the transfer management unit 23 performs the individual DMA transfer except for the data transfer to the specified address Waddr of the write request and the specified address Waddr from the position indicated in the acquired update information in the update data buffer 53. Data transfer to

  With reference to FIG. 10, the initialization process will be described.

  In step S501, the transfer management unit 23 waits until the reset signal is asserted.

  In step S502, the transfer management unit 23 waits until the reset signal is released.

  In step S503, the transfer management unit 23 sets the flag 31 of the transfer source block pointer 30 to “invalid”. Then, the transfer management unit 23 uses “i” as a counter that is incremented by 1 from 0 to n, and performs a loop process from step S504 to step S506.

  In step S504, the transfer management unit 23 selects the transfer source block number 41 that matches the block number i in the transfer management table 40 as a target.

  In step S505, the transfer management unit 23 sets the same block number i as the transfer source block number 41 to the chain block number 43 corresponding to the target transfer source block number 41.

  In step S506, the transfer management unit 23 sets the update flag 44 corresponding to the target transfer source block number 41 to “invalid”. If the counter i is less than n, the transfer management unit 23 performs the process of step S504 again. If the counter i is n, the transfer management unit 23 sets “i” to a counter that is incremented by 1 from 0 to k, and performs the loop processing from step S507 to step S509.

  In step S507, the transfer management unit 23 selects the i-th update management table 50 as a target.

  In step S508, the transfer management unit 23 sets the table valid flag 52 of the target update management table 50 to “invalid”. Then, the transfer management unit 23 uses “j” as a counter that is incremented by 1 from 0 to m, and performs the loop processing in step S509.

  In step S509, the transfer management unit 23 sets the update flag 54 of the entry j in the update data buffer 53 of the target update management table 50 to “invalid”. If the counter j is less than m, the transfer management unit 23 performs the process of step S509 again. If the counter j is m and the counter i is less than k, the transfer management unit 23 performs the process of step S507 again. If the counter j is m and the counter i is k, the transfer management unit 23 ends the operation of FIG.

  With reference to FIG. 11, the transfer management table registration processing procedure will be described.

  In step S601, the transfer management unit 23 receives a DMA transfer source address, a DMA transfer size, and a DMA transfer destination address as settings related to the DMA transfer from the processor 11.

  In step S602, the transfer management unit 23 sets the DMA transfer source block number which is the block number of the area including the DMA transfer source address set in step S601, and the block number of the area including the DMA transfer destination address set in step S601. The DMA transfer destination block number is calculated.

  In step S603, the transfer management unit 23 substitutes the DMA transfer size set in step S601 for the variable “remaining transfer size”. The transfer management unit 23 substitutes the DMA transfer source block number calculated in step S602 for the variable “transfer source block number Stmp”. The transfer management unit 23 substitutes the DMA transfer destination block number calculated in step S602 for the variable “transfer destination block number Dtmp”.

  In step S604, the transfer management unit 23 determines whether the flag 31 of the transfer source block pointer 30 is “invalid”. If the flag 31 is “invalid”, the transfer management unit 23 performs the process of step S605. On the other hand, if the flag 31 is “valid”, the transfer management unit 23 performs the process of step S611.

  In step S605, the transfer management unit 23 changes the transfer source block pointer 30 to “transfer source block number Stmp”. The transfer management unit 23 changes the flag 31 of the transfer source block pointer 30 to “valid”.

  In step S606, the transfer management unit 23 changes the transfer destination block number 42 corresponding to the transfer source block number 41 that matches the “transfer source block number Stmp” in the transfer management table 40 to “transfer destination block number Dtmp”.

  In step S607, the transfer management unit 23 determines whether the “remaining transfer size” matches the block size. If they match, the transfer management unit 23 ends the operation of FIG. On the other hand, if they do not match, the transfer management unit 23 performs the process of step S608.

  In step S608, the transfer management unit 23 changes the chain block number 43 corresponding to the transfer source block number 41 that matches the “transfer source block number Stmp” in the transfer management table 40 to a block number that is one greater than the current value. To do.

  In step S609, the transfer management unit 23 increments “transfer source block number Stmp” by one.

  In step S610, the transfer management unit 23 decrements the “remaining transfer size” by the block size. Then, the transfer management unit 23 performs the process of step S606 again.

  In step S611, the transfer management unit 23 performs a transfer management table search process to be described later.

  In step S612, the transfer management unit 23 determines whether the search result in step S611 is “registered”. If the search result is “registered”, the transfer management unit 23 performs the process of step S613. On the other hand, if the search result is “unregistered”, the transfer management unit 23 performs the process of step S614.

  In step S613, the transfer management unit 23 performs DMA transfer. The processing procedure of DMA transfer is as shown in FIGS.

  In step S614, the transfer management unit 23 performs a final block search process of the transfer management table 40 described later.

  In step S615, the transfer management unit 23 changes the chain block number 43 corresponding to the transfer source block number 41 that matches the final block number acquired in step S614 in the transfer management table 40 to “transfer source block number Stmp”. To do. Then, the transfer management unit 23 performs the process of step S606 again.

  With reference to FIG. 12, the processing procedure of the transfer management table search in step S611 will be described.

  In step S701, the transfer management unit 23 temporarily sets the search result as “unregistered”. The transfer management unit 23 substitutes the DMA transfer source block number calculated in step S602 for “search target block number Xtmp” which is a variable. The transfer management unit 23 sets a value indicating “not searched” in the transfer source search flag.

  In step S <b> 702, the transfer management unit 23 substitutes the same block number as the transfer source block number 41 in the transfer management table 40 pointed to by the transfer source block pointer 30 for the variable “non-search target block number Ytmp”.

  In step S703, the transfer management unit 23 substitutes the DMA transfer size set in step S601 for the “remaining search size” that is a variable.

  In step S704, the transfer management unit 23 determines whether “search target block number Xtmp” and “non-search target block number Ytmp” match. If they do not match, the transfer management unit 23 performs the process of step S705. On the other hand, if they match, the transfer management unit 23 performs the process of step S706.

  In step S705, the transfer management unit 23 determines whether the “search target block number Xtmp” matches the transfer destination block number 42 corresponding to the transfer source block number 41 that matches the “non-search target block number Ytmp”. judge. If they match, the transfer management unit 23 performs the process of step S706. On the other hand, if they do not match, the transfer management unit 23 performs the process of step S707.

  In step S706, the transfer management unit 23 sets the search result to “registered” and ends the operation of FIG.

  In step S707, the transfer management unit 23 determines whether “search target block number Xtmp” and the chain block number 43 corresponding to the transfer source block number 41 that matches “non-search target block number Ytmp” match. To do. If they do not match, the transfer management unit 23 performs the process of step S708. On the other hand, if they match, the transfer management unit 23 performs the process of step S709.

  In step S708, the transfer management unit 23 changes “non-search target block number Ytmp” to the same block number as the chain block number 43 corresponding to the transfer source block number 41 that matches “non-search target block number Ytmp”. . Then, the transfer management unit 23 performs the process of step S704 again.

  In step S709, the transfer management unit 23 decrements the “remaining search size” by the block size.

  In step S710, the transfer management unit 23 determines whether the “remaining search size” is zero. If the “remaining search size” is larger than 0, the transfer management unit 23 performs the process of step S711. On the other hand, if the “remaining search size” is 0, the transfer management unit 23 performs the process of step S712.

  In step S711, the transfer management unit 23 increments “search target block number Xtmp” by one. Then, the transfer management unit 23 performs the process of step S702 again.

  In step S712, the transfer management unit 23 determines whether the transfer source search flag is “unsearched”. If the transfer source search flag is “not searched”, the transfer management unit 23 performs the process of step S713. On the other hand, if the transfer source search flag is “searched”, the transfer management unit 23 ends the operation of FIG. 12 while keeping the search result “unregistered”.

  In step S713, the transfer management unit 23 changes the transfer source search flag to a value indicating “searched”.

  In step S714, the transfer management unit 23 substitutes the DMA transfer destination block number calculated in step S602 for “search target block number Xtmp”.

  With reference to FIG. 13, the process procedure of the last block search of the transfer management table 40 in step S614 will be described.

  In step S801, the transfer management unit 23 substitutes the same block number as the transfer source block number 41 in the transfer management table 40 pointed to by the transfer source block pointer 30 for the variable “transfer source block number Ztmp”.

  In step S802, the transfer management unit 23 determines whether the “transfer source block number Ztmp” and the chain block number 43 corresponding to the transfer source block number 41 that matches the “transfer source block number Ztmp” match. . If they do not match, the transfer management unit 23 performs the process of step S803. On the other hand, if they match, the transfer management unit 23 performs the process of step S804.

  In step S803, the transfer management unit 23 substitutes the chain block number 43 corresponding to the transfer source block number 41 that matches the “transfer source block number Ztmp” in the “transfer source block number Ztmp”.

  In step S804, the transfer management unit 23 acquires “transfer source block number Ztmp” as the final block number of the transfer management table 40, and ends the operation of FIG.

*** Explanation of the effect of the embodiment ***
In the present embodiment, when the memory control device 13 detects a reference request from the processor 11 for DMA transfer target data, if the DMA transfer of the reference request target data has not been performed, the DMA transfer is performed. First, the processor 11 is referred to the data before transfer. For this reason, it is possible to eliminate the waiting for the execution of an instruction by DMA transfer, and to shorten the processing time of the processor 11.

  According to the present embodiment, even when there is a dependency between a DMA transfer instruction and a subsequent instruction of the DMA transfer instruction, the subsequent instruction can be executed without waiting for the preceding DMA transfer instruction to end. That is, even if there is a dependency between an instruction that executes DMA transfer for transferring data in the memory 12 and a subsequent instruction of the instruction, the subsequent instruction is executed without waiting for the DMA transfer to shorten the processing time. And the time until completion of the processing performed by the processor 11 can be shortened.

*** Other configurations ***
As a modification of the present embodiment, one or more components among the components built in the memory control device 13 may be arranged outside the memory control device 13. As a specific example, the DMAC 25 may be disposed outside the memory control device 13, electrically connected to the memory control device 13, and operated according to a command from the transfer management unit 23. Alternatively, the access control unit 24 may be disposed outside the memory control device 13, electrically connected to the memory control device 13, and operated according to a command from the transfer management unit 23. In any example, the memory control device 13 can exhibit a function of performing DMA transfer.

  As another modification, at least one of the DMAC 25 and the access control unit 24 may be incorporated in the transfer management unit 23.

  10 computer system, 11 processor, 12 memory, 13 memory controller, 14 peripheral bus bridge, 15 I / O device, 16 system bus, 17 memory bus, 18 I / O bus, 21 system bus I / F, 22 access detection Unit, 23 transfer management unit, 24 access control unit, 25 DMAC, 30 transfer source block pointer, 31 flag, 40 transfer management table, 41 transfer source block number, 42 transfer destination block number, 43 chain block number, 44 update flag, 50 update management table, 51 transfer destination block number, 52 table valid flag, 53 update data buffer, 54 update flag.

Claims (4)

In a memory control device that performs DMA transfer, which is data transfer between memory areas,
An access detection unit for detecting a request from the processor;
When a write request for writing data to the specified address of the memory is detected by the access detection unit, if there is no unexecuted DMA transfer with the area including the specified address as the transfer destination, the data transmitted from the processor If there is an unexecuted DMA transfer to the designated address, the data transmitted from the processor is written to the buffer, and then the unexecuted DMA transfer excluding the data transfer to the designated address and the buffer A memory control device comprising: a transfer management unit that performs data transfer from the designated address to the designated address. When the write request is detected by the access detection unit, the transfer management unit secures the buffer if there is an unexecuted DMA transfer, and performs data transfer from the buffer to the designated address. after, a memory control device according to claim 1, releasing the buffer. The transfer management unit includes a transfer destination block number indicating a number for identifying a transfer destination area in the unexecuted DMA transfer and information indicating a position where data to be transferred to the designated address is written in the buffer. And an update management table to be set as update information, and when performing each DMA transfer, a number for identifying a transfer destination area in the individual DMA transfer is set in the update management table as a transfer destination block number. If so, the update information corresponding to the transfer destination block number is acquired from the update management table, and the individual DMA transfer excluding the data transfer to the designated address and the acquired update information in the buffer. the memory control device according to claim 1 or 2 from the position shown carrying out the data transfer to the specified address. The memory control device according to any one of claims 1 to 3 ,
The memory;
A computer system comprising the processor.

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