JP2010152837A - Buffer device - Google Patents

Abstract

Provided is a buffer device capable of reducing a waiting time of a CPU even when there are a plurality of block transfer requests.
By comparing whether or not the read access target area of the read request overlaps with the access target area of each access request stored in the access request storage unit 10, the read access target area is the write access target area of the write request. If it overlaps with the transfer source area of the DMA transfer request, it acquires the write data of the write request from the access request storage unit 10 and returns it to the CPU 2 as read data. Is issued to the arbitration circuit unit 12, and when it overlaps the transfer destination area of the DMA transfer request, a read request in which the address area of the read access target is converted to the transfer source area of the DMA transfer request is issued to the arbitration circuit unit 12.
[Selection] Figure 1

Description

  The present invention relates to a buffer device that reduces the processing time by suppressing the influence on the CPU when the CPU executes a block transfer instruction having a long execution time and executing the subsequent processes as much as possible. .

  The processing of the CPU often includes block transfer that transfers data collectively. As an example of block transfer, when the preceding process ends and moves to the next process, the result of the preceding process is transferred to the work area of the subsequent process by block transfer or received via communication. For example, when the data is copied to the work area, the result processed by the CPU may be sent to the outside by communication.

  Since this block transfer process is constituted by a plurality of memory accesses, the execution time is long. In addition, DMAC (Direct Memory Access Controller) is generally used for block transfer, but once the CPU issues an instruction for block transfer to the DMAC, the bus to which the memory to be transferred is connected is issued by the DMA. Will be occupied by access. Even after the DMAC is activated, if the CPU has a built-in memory or cache that can be accessed independently of the DMA target memory, it may be possible to continue the subsequent processing. However, the DMA is often performed on the main memory and often waits until the DMA is completed.

  As a general method, there is a method in which DMA transfer is temporarily interrupted and CPU access is given priority. However, when data is written to a DMA target area in operation or when data is read from a DMA transfer destination area. If the CPU access is not issued after the DMA for the area is completed, a correct result cannot be obtained. In order to construct a high-speed system, shortening the DMA execution time is a big problem.

  Patent Document 1 describes a method of reducing the waiting time of the CPU in the case of read access to the DMA transfer destination area in addition to the above-described method of temporarily interrupting DMA transfer. In this DMA transfer control method, even if it is a DMA transfer target area, if the transfer has already been completed, the DMA is temporarily stopped and CPU access is performed. In the case of read access to the transfer destination area, the DMA is temporarily interrupted, the access address requested by the CPU is DMA transferred first, and the data acquired at that time is transferred to the CPU as read data and interrupted. Resumed DMA. This makes it possible to shorten the waiting time for CPU access during DMA execution.

JP 2004-145376 A

  The above-described method of prioritizing CPU access generated during the DMA operation has a problem that it cannot cope with a DMA request generated multiple times in a short time. When queuing a plurality of DMA requests with the DMAC, it is necessary to determine whether or not a subsequent single access can be executed in advance for all the DMA requests. Even if the processing described in 1 is performed, correct data cannot be obtained in subsequent CPU accesses, so it is necessary to wait until the preceding DMA processing is completed.

  The present invention has been made in order to solve the above-described problems. Even when there are a plurality of DMA requests, the CPU wait time can be shortened and the CPU access related to the DMA transfer request can be achieved. Even if it exists, it aims at obtaining the buffer apparatus which can overtake the preceding DMA process and can acquire correct data.

  The buffer device according to the present invention includes an access request storage unit that stores a write request and a DMA transfer request issued from a CPU in a first-in first-out manner, and an access distribution unit that distributes the write request and the DMA transfer request output from the access request storage unit A DMA control unit that controls DMA transfer to the memory according to the DMA transfer request distributed by the access distribution unit, a read request to the memory, a write request distributed by the access distribution unit, and a DMA transfer request issued from the DMA control unit The arbitration circuit unit that executes access to the memory according to each access request, and the read request issued to the memory issued by the CPU are input, and the read access target area of the read request is stored in the access request storage unit Access target area of each access request A read access processing unit that issues a read request in which the read access target area is address-converted to the transfer source area of the DMA transfer request to the arbitration circuit unit when it is overlapped with the transfer destination area of the DMA transfer request Is provided.

  According to the present invention, it is checked whether the read access target area of the read request overlaps with the access target area of each access request stored in the access request storage unit. If it overlaps the target area, the write data of the write request is acquired from the access request storage unit and returned to the CPU as read data. If it overlaps the transfer source area of the DMA transfer request, the read data precedes the DMA transfer request. When the request is issued to the arbitration circuit unit and overlaps with the transfer destination area of the DMA transfer request, a read request in which the read access target area is converted to the transfer source area of the DMA transfer request is issued to the arbitration circuit part. By doing so, the access request issued subsequently from the CPU overtakes the access of the access request storage unit, so that the waiting time of the CPU can be shortened and the DMA stored in the storage unit Even in the case of a read request in which the transfer area of the transfer request and the access target area overlap, it is possible to acquire correct read data in a short time.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing the configuration of a memory system using a buffer device according to Embodiment 1 of the present invention. In FIG. 1, this memory system includes a buffer device 1, a CPU (also called a central processing unit, also referred to as a processor) 2, a CPU I / F unit 3, a DMA transfer request receiving unit 4, and a memory 5, which are connected to each other via a system bus. The buffer device 1 includes an access request storage unit 10, a DMA control unit 11, an arbitration circuit unit 12, an access request control unit (storage control unit) 13, a read access processing unit 14, and an access distribution unit 15. Here, DMA refers to directly transferring data between memories without using CPU instructions (machine language).

  The access issued by the CPU 2 is distributed to the DMA transfer request receiving unit 4 and the buffer device 1 by the CPU I / F unit 3. The write request is issued to the access request storage unit 10 in the buffer device 1, and the read request is issued to the read access processing unit 14. The DMA transfer request receiving unit 4 receives a DMA transfer request from the CPU 2 as divided information, and issues a DMA transfer request to the buffer device 1 when all of the divided information is collected.

  The write request and the DMA transfer request are stored in the access request storage unit 10. The access request storage unit 10 is a FIFO that can accept a plurality of write requests and DMA transfer requests, and basically issues them to the access distribution unit 15 in order from the previously stored access request.

  All entries in the FIFO can be freely referred to. The access request control unit 13 controls the operation of the access request storage unit 10 and inserts a new request for each entry of the FIFO in the access request storage unit 10 in addition to the basic operation described above. Processing such as exchanging each other is possible. This function will be described in the second and subsequent embodiments.

(1) Normal Operation of Buffer Device 1 A case where the buffer device 1 operates normally in response to a write request issued by the CPU 2 will be described. The write request issued from the CPU 2 is stored in the access request storage unit 10 through the CPU I / F unit 3.

  The write request viewed from the CPU 2 ends when it is stored in the access request storage unit 10 of the buffer device 1, and an ACK (access end) response is returned to the CPU 2 via the CPU I / F unit 3. When the access request storage unit 10 is full and the write request is not accepted, the output of the ACK response to the CPU 2 is stopped and the CPU 2 is put in a waiting state.

  As described above, while the access request storage unit 10 can store the write request issued from the CPU 2, the CPU 2 can receive the ACK response and advance the process, but the access request storage unit 10 is full. At the time, the CPU 2 must wait until the access request storage unit 10 becomes free.

(2) When CPU 2 issues a DMA transfer request As shown in FIG. 1, the DMA transfer request reception unit 4 includes a transfer source address register 40, a transfer destination address register 41, a transfer data number register 42, and a transfer start register 43. Prepare. The CPU 2 sets the transfer source address register 40, the transfer destination address register 41, the transfer data number register 42 and the transfer start register 43 in an arbitrary order via the CPU I / F unit 3, and writes to the transfer start register 43. The DMA transfer request is transferred to the buffer device 1 using the access as a trigger. When a write request is issued from the CPU 2 to the internal register, the DMA transfer request reception unit 4 returns an ACK response to the CPU 2.

  The DMA transfer request is stored in the access request storage unit 10 together with other write requests issued so far, and is processed from the access request at the head of the FIFO. If the access request storage unit 10 does not have a free table for registering access requests, the DMA transfer request acceptance unit 4 does not return an ACK response to the write request to the transfer start register 43, thereby Transition to the wait state. The configuration of the registers 40 to 43 that generate the DMA transfer request to be transferred to the buffer device 1 in the DMA transfer request reception unit 4 is an example.

(3) Details of Access Request Storage Unit FIG. 2 is a diagram showing the configuration of the access request storage unit in FIG. 1, and the access request storage unit 10 is composed of table data in which information related to access requests is registered. The Here, the information related to the access request includes five items of information: a flag 100, a type 101, an address 102, address data 103, and additional information 104. A combination of these item information is called an access request entry 105, and the example shown in FIG. 2 describes a FIFO that can receive eight access requests. In FIG. 2, for the 8-stage access request storage unit 10, the first stage of the FIFO is the access request entry 105-0, and the last stage is the access request entry 105-7.

  Whether the access request is valid is set in the flag 100, and identification information for distinguishing the DMA transfer request from the write request is set in the type 101. In the address 102, a write address is set for a write request, and a transfer source address is set for a DMA transfer request. In the address data 103, write data is set for a write request, and a transfer destination address is set for a DMA transfer request.

  Further, in the additional information 104, if it is a write request, byte enable information indicating validity / invalidity of the addressed byte lane constituting the write data is set, and if it is a DMA transfer request, block transfer is performed by the DMA. Size is set. The access requests stored in the access request storage unit 10 are issued in order from the access request of the old access request entry 105-0 stored earlier, as indicated by an arrow in FIG.

  The access requests registered in the access request storage unit 10 are output to the access distribution unit 15 in the above-described access issue order. The access distribution unit 15 issues a write request directly to the arbitration circuit unit 12 and issues a DMA transfer request to the DMA control unit 11. When DMA is executed by the DMA control unit 11 that has received the DMA transfer request, a number of access requests are issued from the DMA control unit 11 to the arbitration circuit unit 12. In this way, by storing information necessary for DMA transfer in the access request storage unit 10 as one FIFO entry, the buffer device 1 can be used efficiently, and the buffer device 1 overflows, that is, the access request stores the access request. The probability of exceeding the capacity of the unit 10 can be kept low.

(4) Details of Read Access Processing As shown in FIG. 1, the read access processing unit 14 includes an address conversion unit 141 and a write buffer collation unit 142. A read request issued from the CPU 2 via the CPU I / F unit 3 is notified to the read access processing unit 14. The address conversion unit 141 receives the read request and outputs it to the write buffer collation unit 142.

  If the read address to be read-accessed does not overlap the access request area of the write request or DMA transfer request stored in the access request storage unit 10, the write buffer verification unit 142 determines that the read request is the arbitration circuit unit 12. Issue to Further, since the arbitration circuit unit 12 performs processing by assigning priorities in the order of a read request, a write request, and a DMA transfer request, the read request is promptly executed.

  On the other hand, when the read address matches the address of the write request stored in the access request storage unit 10 (the address set in the address 102), the write buffer collation unit 142 passes through the address conversion unit 141, Write data is acquired from the address data 103 of the access request storage unit 10. The write buffer verification unit 142 returns the acquired write data as read data to the CPU 2 via the CPU I / F unit 3.

  Since the write request has byte enable as the additional information 104 as shown in FIG. 2, the write buffer collation unit 142 holds the data of the matched byte lane as read data. Thereafter, the write buffer collation unit 142 continues the collation process of the access request storage unit 10, ends the collation process when all the read data requested to be read is prepared, and returns the read data to the CPU 2. .

  The write buffer collation unit 142 does not actually access the memory 5 when all the read data is prepared by the collation processing of the access request storage unit 10. When the read data is insufficient, the write buffer collation unit 142 issues a read request to the arbitration circuit unit 12 and supplements the insufficient data with the data read from the memory 5 to generate read data.

  When the read address overlaps the transfer source area of the DMA transfer request stored in the access request storage unit 10 (the storage area of the memory 5 specified by the transfer source address and the transfer size), the write buffer verification unit 142 The read request can be processed in advance. That is, the write buffer collation unit 142 instructs the arbitration circuit unit 12 to read the read data from the transfer source area of the memory 5 and return it to the CPU 2 via the CPU I / F unit 3. Since the transfer source area of the DMA transfer request is not changed by DMA processing, it is not necessary to perform address conversion processing for read access.

  If the read address is included in the DMA transfer destination area of the memory 5 (the storage area of the memory 5 specified by the transfer destination address and transfer size), the correct data will be obtained if the order of executing DMA transfer and read access is changed. May not be obtained. In this case, the DMA transfer request stored in the access request storage unit 10 is used to convert the DMA transfer destination address to the DMA transfer source address, and read access is performed. That is, the converted address is set as a read address. Here, since data is copied from the DMA transfer source area to the DMA transfer destination area, read access to the DMA transfer source area after conversion can be performed regardless of the access issue order even before the DMA transfer. It is possible to get the correct value.

Specifically, the address conversion unit 141 calculates a transfer source address from the transfer source address and transfer destination address of the DMA transfer request and the read address of the read request according to the following formula (1), and reads to this address: Replace with request and continue processing. When address conversion is performed in response to a DMA transfer request, the subsequent verification processing of the write buffer verification unit 142 is performed using the converted address.
Transfer source address after conversion = read address-transfer destination address + transfer source address (1)

  FIG. 3 is a diagram illustrating an operation example of the read access processing unit in FIG. 1, and illustrates a case where a read request is issued in a state where eight access requests are stored in the access request storage unit 10. . In the address column in FIG. 3, regarding the write request, whether or not the write address stored in the access request storage unit 10 and the read address issued by the CPU 2 to the read access processing unit 14 match is “match”. ”Or“ mismatch ”, and regarding the DMA transfer request, whether or not the transfer destination area of the DMA transfer information stored in the access request storage unit 10 overlaps with the read address is“ included ”or“ not included ” Is determined.

  When the write buffer collation unit 142 collates with the read request using the information stored in the access request storage unit 10, the access request stored in the access request storage unit 10 is collated from the newest stored order. The corresponding byte lane is extracted based on the address and byte enable information. In addition, the new access request entry 105 is prioritized for each byte lane to generate read data.

  For example, in the write request of the newest access request entry 105-7, the write address (write address set in the address 102) matches the read address. Therefore, the write buffer collation unit 142 extracts a byte lane that is valid based on byte enable (byte enable set in the additional information 104) information from the write data (write data set in the data 103) of the write request. Then, it is held as a read data byte 3 constituting the read data.

  Next, since the byte lane corresponding to the read data byte 2 constituting the read data is valid following the read data byte 3 based on the byte enable information, the write buffer collation unit 142 determines that the byte from the write data. A lane is extracted and held as read data byte 2.

  Thereafter, in the write data of the access request entry 105-7, since the byte lane corresponding to the read data byte 1 following the read data byte 2 is invalid, the write buffer collation unit 142 next selects the new access request entry 105-. 6 is determined whether the byte lane corresponding to the read data byte 1 is valid. Here, since the byte lane is valid, the byte lane is extracted from the write data of the access request entry 105-6 and held as the read byte 1.

  In the write data of the access request entry 105-6, since the byte lane corresponding to the read data byte 0 following the read data byte 1 is invalid, the write buffer collation unit 142 next sets information on the new access request entry 105-5. The verification process is executed with

  Here, since the DMA transfer request is set in the access request entry 105-5 and the read address is included in the transfer destination area, the address conversion unit 141 sets the read address and the access request entry 105-5 in the read address. Using the set transfer destination address and transfer source address, the transfer destination address is converted into the transfer source address from the above formula (1), and the converted address is set as the read address (indicated as the address in FIG. 3 changes). ).

  Thereafter, the write buffer collation unit 142 collates the read address after conversion calculated by the address conversion unit 141 with the write address of the write request of the access request entry 105-4 to determine that there is a mismatch, and similarly accesses The write address of the write request in the request entry 105-3 is collated to determine that they do not match.

  Since the write address of the write request of the access request entry 105-2 matches the read address after conversion (indicated as a match with the changed address in FIG. 3), the write buffer collation unit 142 stores the access request entry 105-2. Based on the byte enable information, it is determined that the byte lane corresponding to the read data byte 0 is valid, and the byte lane is extracted from the write data of the access request entry 105-2 and held as the read byte 0. Since the byte lanes corresponding to the read bytes 3 to 1 are already held by other entries, they are not held even if the byte enable information is valid.

  Thereafter, the write buffer collation unit 142 collates the read address after conversion calculated by the address conversion unit 141 with the write address of the write request of the access request entry 105-1, and determines that there is a mismatch. It is determined that they do not match by collating with the write address of the write request of the request entry 105-0. As described above, from the access request entry 4 to the access request entry 0, the write buffer collation unit 142 collates with the address converted by the address conversion unit 141.

  As described above, according to the first embodiment, whether or not the read access target area of the read request overlaps with the access target area of each access request stored in the access request storage unit 10 is checked. When the target area overlaps with the write access target area of the write request, the write data of the write request is acquired from the access request storage unit 10 and returned to the CPU 2 as read data. When the target area overlaps with the transfer source area of the DMA transfer request, Prior to the DMA transfer request, when the read request is issued to the arbitration circuit unit 12 and overlaps the transfer destination area of the DMA transfer request, the read request in which the address area of the read access area is converted to the transfer source area of the DMA transfer request is arbitrated. Issued to the circuit unit 12. By doing so, the access request issued subsequently from the CPU 2 can overtake the access of the access request storage unit 10 and the waiting time of the CPU 2 can be shortened. In addition, even in the case of a read request in which the transfer area of the DMA transfer request stored in the access request storage unit 10 and the access target area overlap, it is possible to acquire correct read data in a short time.

  Further, according to the first embodiment, when the read access processing unit 14 converts the read access target area of the read request into the transfer source area of the DMA transfer request, the read access target area after the conversion becomes the access request Since it is checked whether or not it overlaps with the access target area of each access request after the DMA transfer request stored in the storage unit 10, it is possible to control the order in which the access requests are issued even after address conversion. it can. In addition, the frequency at which the access request exceeds the capacity of the access request storage unit 10 can be kept low.

Embodiment 2.
In the second embodiment, a description will be given of a buffer device that is prioritized from a request with a short access processing time for a DMA transfer request or a write request that does not cause a problem even if the order is changed.

  The memory system according to the second embodiment has the same basic configuration as that described with reference to FIG. 1 in the first embodiment, but the access request control unit executes an access request in the access request storage unit. It differs in that the process of changing the order is performed. Hereinafter, each configuration of the memory system according to the second embodiment will be described with reference to FIG.

  FIG. 4 is a diagram showing an operation example of the access request control unit according to the second embodiment of the present invention. In the example shown in FIG. 4, the access request control unit 13 invalidates the access requests from the access request entry 105-7 to the access request entry 105-4 in the access request storage unit 10, and newly writes to the access request entry 105-3. A request is added, a write request is stored in the access request entry 105-2 so far, and a DMA transfer request is stored in the access request entries 105-1 and 105-0.

(1) Overview of Overtaking Process Further, the access request control unit 13 sets “new” in the flag 100 of the newly added access request entry 105-3 in the access request storage unit 10. Thereafter, the access request control unit 13 determines whether or not the write request with the flag 100 “new” can be overtaken with respect to the access request of the previous access request entry 105-2. If overtaking is possible, the write request in the access request entry 105-3 is replaced with the access request in the previous access request entry 105-2. This replacement process is executed until it is determined that overtaking is impossible. In the access request storage unit 10, the access request entry flag 100 when the overtaking is disabled is effectively changed.

  The conditions under which the write request can be overtaken with respect to the preceding access request entry include the access target area for the write request or DMA transfer request of the preceding access request entry, and the write target area for the write request of the access request entry to be determined And are not overlapping.

  The access request control unit 13 compares the access target areas of the write request or DMA transfer request of all access request entries in the access request storage unit 10 with the write request to be added at a time, and The access request entry for inserting the write request to be added may be specified within 10.

  As described above, when the access request storage unit 10 receives a write request issued by the CPU 2, the access request control unit 13 determines the write access target area of the write request and the access request access area of the access request storage unit 10. The access request entry to be inserted is determined depending on whether or not.

(2) When a plurality of DMA transfer requests are entered in the FIFO Here, when a plurality of DMA transfer requests are entered in the access request storage unit 10, the access request control unit 13 In the table, the transfer area is determined from the previously stored old DMA transfer request, and it is determined that a DMA transfer request whose transfer area does not overlap with the write access target area of the newly issued write request can be overtaken. . Even write requests can be processed in the same manner, and it is determined that a newly issued write request with respect to the preceding write request can be overtaken unless the areas overlap.

  Under the determination conditions described above, the target address of the write request newly issued from the CPU 2 does not match the access target areas of all the access request entries 105 stored in the access request storage unit 10 (not included at all). If so, it is possible to pass all access requests stored in the access request storage unit 10 and issue direct access to the arbitration circuit unit 12. However, if the DMA is being executed by the DMA control unit 11, it is not determined whether the DMA transfer request can be overtaken. Therefore, the ancestor area of the DMA and the access target area of the write request overlap. , There is a possibility of malfunction.

Therefore, in the second embodiment, the access request control unit 13 outputs to the DMA control unit 11 when outputting the DMA transfer request from the access request storage unit 10 to the DMA control unit 11 via the access distribution unit 15. The DMA transfer request is also left in the access request entry 105-0 at the head of the access request storage unit 10.
Thereby, the access request control unit 13 also compares the above-described DMA transfer request executed by the DMA control unit 11 by comparing the transfer area of the access request entry 105-0 with the access target area of the new write request. It is possible to determine whether overtaking is possible in the same procedure.
When the access request control unit 13 receives a notice of completion of execution of the DMA transfer request from the DMA control unit 11, the access request control unit 13 deletes the DMA transfer request left in the access request entry 105-0 and advances the FIFO one step.

(3) Processing when a DMA transfer request is issued from the DMA transfer request receiving unit 4 The access request control unit 13 stores a transfer area of a DMA transfer request newly issued from the DMA transfer request receiving unit 4 and an access request storage. A comparison is made with the access target area (the write target area of the write request or the transfer area of the DMA transfer request) of the old access request previously stored in the unit 10, and the new DMA transfer request transfer area and the access target area are It is determined that the access requests that do not overlap can be overtaken.
Here, from the viewpoint of efficiently using the buffer device 1, the transfer size of data to be transferred by a newly issued DMA transfer request (which can be specified by the size set in the additional information 104) precedes. Only when it is smaller than the transfer size of the DMA transfer request, it is overtaken.

  As described above, in the second embodiment, the access request control unit 13 determines that the access target area of the access request issued from the CPU 2 overlaps with the access target area of the access request stored in the access request storage unit 10. If not, the access request issued from the CPU 2 is output to the access distribution unit 15 prior to the access request stored in the access request storage unit 10. In this way, it is possible to secure a large number of unused access request entries 105 in the access request storage unit 10, and it is possible to preferentially process a request with a short processing time. As a result, a DMA transfer request having a small transfer size can overtake a transfer request having a large transfer size within a range where the transfer result does not become abnormal, that is, a range where the transfer areas do not overlap.

Embodiment 3 FIG.
In the second embodiment, the DMA transfer request being executed by the DMA control unit 11 is also left in the access request entry 105-0 of the access request storage unit 10, and the access target area of the newly issued write request is If it does not overlap with the transfer area of the DMA transfer request, it is determined that overtaking is possible and can be issued directly to the arbitration circuit unit 12.
However, the DMA control unit 11 must wait for the subsequent DMA transfer request to be stored after the access request entry 105-1 if the DMA that is once unable to be interrupted is being executed. there were.
Therefore, in the third embodiment, DMA transfer requests to be executed when a DMA transfer request with a small transfer size is issued are switched while a DMA transfer request with a large transfer size is divided and executed. .

  The basic configuration of the memory system according to the third embodiment is the same as that described with reference to FIG. 1 in the first embodiment, but the access request control unit executes the access request in the access request storage unit. It differs in that the process of changing the order is performed. Hereinafter, each configuration of the memory system according to the third embodiment will be described with reference to FIG.

  FIG. 5 is a diagram illustrating an operation example of the access request control unit according to the third embodiment of the present invention. The access request control unit 13 according to the third embodiment defines a DMA maximum execution size that defines the predetermined transfer size for causing the DMA control unit 11 to divide and execute a DMA transfer request for each predetermined transfer size. Information 106 is set. In FIG. 5, consider a case where access issuance proceeds and the DMA transfer request stored in the access request entry 105-1 is moved to the access request entry 105-0.

  At this time, if the transfer size set in the additional information 104 of the DMA transfer request to be moved exceeds the transfer size specified by the DMA maximum execution size information 106, the access request control unit 13 performs the DMA transfer. The request is divided by the transfer size specified by the DMA maximum execution size information 106, moved to the access request entry 105-0 first, and the DMA information related to the DMA transfer request left in the access request entry 105-1 is updated. To do.

  The DMA transfer request issued after being divided into access request entries 105-0 has the transfer size stored in the additional information 104 without changing the contents of the flag 100, type 101, transfer source address 102, and transfer destination address 103. The transfer size is changed to that defined in the DMA maximum size information 106.

  Further, the access request control unit 13 holds the contents of the flag 100 and the type 101 as they are for the DMA transfer request remaining in the access request entry 105-1, and defines the transfer source address 102 as “transfer source address 102 + DMA maximum size information 106. Transfer size ”, transfer destination address 103 as“ transfer size specified by transfer destination address 103 + DMA maximum size information 106 ”, and additional information 104 as“ transfer size specified by transfer size−DMA maximum size information 106 ”. And

  The DMA control unit 11 executes a DMA transfer request for a predetermined transfer size specified in the DMA maximum size information 106 stored in the access request entry 105-0. When the DMA is completed, the access request control unit 13 determines that the updated transfer size of the DMA transfer request left in the access request entry 105-1 exceeds the transfer size specified by the DMA maximum execution size information 106. In the same procedure as described above, the DMA transfer request is divided by the transfer size specified by the DMA maximum execution size information 106 and moved to the access request entry 105-0 first. The DMA information related to the DMA transfer request left in the above is updated. If the transfer size specified by the DMA maximum execution size information 106 is not exceeded, the data is moved to the access request entry 105-0 as it is and output to the access distribution unit 15.

  Further, the access request control unit 13 issues a DMA transfer request having a transfer size smaller than the DMA transfer request left in the access request entry 105-0 to the access request entry 105-1, while the DMA control unit 11 is executing DMA. If there is no overlap between the transfer areas of both DMA transfer requests, the remaining DMA transfer request is moved to the access request entry 105-1, and the newly issued DMA transfer request is transferred to the access request entry 105-1. Move to -0.

  As described above, the access request control unit 13 divides DMA transfer requests having a transfer size equal to or smaller than the transfer size specified by the DMA maximum execution size information 106 and issues a new DMA transfer request with a smaller transfer size in the same manner as described above. If there is no overlap in the transfer area, the DMA transfer request output to the access distribution unit 15 is switched in ascending order of transfer size.

  As described above, according to the third embodiment, when the DMA request is arranged in the output order in the access request storage unit 10, the access request control unit 13 is provided on the condition that there is no overlap of transfer areas. The output order from the access request storage unit 10 is switched so that a DMA transfer request with a small DMA transfer size precedes. In particular, when a DMA transfer request is output from the access request storage unit 10 to the access distribution unit 15, a new DMA transfer request is generated by dividing the DMA transfer size so that the DMA transfer size is a predetermined value or less, and the DMA transfer is performed. Output from the access request storage unit 10 in ascending order of size. As described above, the storage area of the buffer device 1 can be promptly switched by switching the DMA transfer request to be executed when the DMA transfer request with a small transfer size is issued while executing the DMA transfer request with a large transfer size in small sections. Can be freed up.

Embodiment 4 FIG.
In the first to third embodiments, the read access processing unit 14 requires the same number of collation circuits as the access request entry in the address conversion unit 141 and the write buffer collation unit 142. By dividing the processing corresponding to the request into processing synchronized with a plurality of clocks, the circuit scale is reduced as a single verification circuit.

The basic configuration of the memory system according to the fourth embodiment is the same as that described with reference to FIG. 1 in the first embodiment, but the configuration of the read data processing unit is different. The configuration other than the read data processing unit will be described with reference to FIG.
FIG. 6 is a block diagram showing the configuration of the read access processing unit according to the fourth embodiment of the present invention. In FIG. 6, the read access processing unit 14 according to the fourth embodiment includes a request entry selector 310, a counter 311, a control circuit 312, a selector 313, a read data extraction unit 314, an address conversion unit 315, an address holding unit 316, and a read access issue. A circuit 317 and a data holding unit 318 are provided.

  The request entry selector 310 selects the access request entry 105 to be processed from among the access request entries 105-7 to 105-0 of the access request storage unit 10 in synchronization with the counting operation by the counter 311. The counter 311 is a counter whose start and stop are controlled by the control circuit 312. The control circuit 312 controls the overall operation of the read access processing unit 14.

  The selector 313 selects an address used for collation processing from the read address of the read request and the address held by the address holding unit 316. The read data extraction unit 314 determines whether the write request of the access request entry 105 selected by the request entry selector 310 overlaps the access range defined by the address selected by the selector 313. , The overlapping byte lane data is extracted from the write data of the access request entry 105.

  When the address selected by the selector 313 is included in the transfer destination area of the DMA transfer request of the access request entry 105, the address conversion unit 315 converts the transfer destination address into a transfer source address and sets it as a read address. The address holding unit 316 holds the read address of the read request issued from the CPU 2 and the converted read address converted by the address conversion unit 315. The read access issue circuit 317 issues a read request to the arbitration circuit unit 12 under the control of the control circuit 312. The data holding unit 318 holds the byte lane data extracted by the read data extraction unit 314, and outputs the data to the read access issue circuit 317 when all the data is obtained.

Next, the operation will be described.
(1) When a Write Request is Selected by the Request Entry Selector 310 The request entry selector 310 uses the access request entry 105 from the access request storage unit 10 using every clock generated by the counter 311, that is, the count value of the counter 311. The access request entries to be processed are selected in the order of −7 to 105-0.

  On the other hand, the selector 313 uses the read address of the read request issued from the CPU 2 via the CPU I / F unit 3 only for the first verification process, and is held in the address holding unit 316 for the second and subsequent verification processes. To use the address. That is, the selector 313 inputs the read address of the read request issued from the CPU 2 and outputs the read address to the read data extraction unit 314, whereby the first verification process is executed, and the read address passes through the address conversion unit 315. Are held in the address holding unit 316. The selector 313 selects the read address held in the address holding unit 316 or the address converted by the address conversion unit 315 and outputs the selected address to the read data extraction unit 314, whereby the second and subsequent matching processes are executed. .

  The read data extraction unit 314 stores the storage area of the memory 5 specified by the read address selected by the selector 313 and the memory 5 specified by the write address of the write request of the access request entry 105 selected by the request entry selector 310. The collation process is performed to check whether or not the storage area overlaps. At this time, if the two overlap, the read data extraction unit 314 extracts the data of the byte lane corresponding to the overlapping portion validated by the byte enable information of the write request of the access request entry 105 from the write data. And output to the data holding unit 318.

  The data holding unit 318 holds the data input from the read data extraction unit 314 as a read byte. The above-described collation processing is executed for the write request of the access request entry 105 selected in order by the request entry selector 310 until all the data requested to be read is collected in the data holding unit 318.

  The read data extraction unit 314 ends the collation process for the write request of the access request entry 105 selected from the access request storage unit 10 when all the data requested to be read is collected in the data holding unit 318. At this time, the data holding unit 318 outputs the read data including all the data to the control circuit 312 together with the verification processing completion notification. When the control circuit 312 receives the completion notification of the collation processing, the control circuit 312 returns the data input from the data holding unit 318 to the CPU 2 via the CPU I / F unit 3.

  Note that the data holding unit 318 controls that when all the data is not available when the collation processing for all the access request entries 105 selected from the access request storage unit 10 by the request entry selector 310 is completed. Notify the circuit 312. Upon receiving the notification, the control circuit 312 notifies the read access issue circuit 317 of a read access issue instruction for instructing issue of a read request related to the read address corresponding to the deficient data used in the collation processing.

  When the read access issuance circuit 317 receives the read access issuance instruction from the control circuit 312, the read access issuance circuit 317 issues a read request regarding the read address of the insufficient data to the arbitration circuit unit 12. The arbitration circuit unit 12 executes the read request, acquires insufficient data from the memory 5, and outputs the data to the data holding unit 318. The data holding unit 318 compensates for the shortage of the read data with the data input from the arbitration circuit unit 12 and outputs to the control circuit 312 that the read data and processing are completed. As a result, the control circuit 312 returns the data input from the data holding unit 318 to the CPU 2 via the CPU I / F unit 3.

(2) When a DMA transfer request is selected by the request entry selector 310 The address conversion unit 315 reads the read address selected by the selector 313 if the access request entry 105 selected by the request entry selector 310 is a DMA transfer request. Is included in the transfer destination area of the DMA transfer request, and if it is included, the DMA transfer destination address in the DMA transfer request is set to the DMA transfer source in the same procedure as in the first embodiment. The address is converted into an address and stored in the address holding unit 316 as a read address.

  Thereafter, the selector 313 selects the converted read address held in the address conversion unit 316 and outputs it to the read data extraction unit 314. As a result, the converted read address is used for collation processing for the access request of the access request entry 105 selected thereafter.

  If the selected access request entry 105 is a write request or a read access that is completely unrelated to the transfer area of the DMA transfer request, address conversion is not performed, and the address selected by the selector 313 is changed. The address holding unit 316 holds it as it is. By this processing, the address converted can be used for collation with the next access request entry 105.

  As described above, according to the fourth embodiment, the read access processing unit 14 collates each access request fetched from the access request storage unit 10 in synchronization with a predetermined clock, and performs processing according to the collation result. Execute. Thus, by executing the processing for the read request for each clock, the circuit scale of the read access processing unit 14 can be greatly reduced. The read access processing unit 14 so far has required the same number of collation circuits as the request entries in the address conversion unit 141 and the write buffer collation unit 142. By using the configuration of FIG. It can be realized by a verification circuit.

It is a block diagram which shows the structure of the memory system using the buffer apparatus by Embodiment 1 of this invention. FIG. 2 is a diagram schematically showing a configuration of an access request storage unit in FIG. 1. FIG. 3 is a diagram illustrating an operation example of a read access processing unit in FIG. 1. It is a figure which shows the operation example of the access request control part by Embodiment 2 of this invention. It is a figure which shows the operation example of the access request control part by Embodiment 3 of this invention. It is a block diagram which shows the structure of the read access process part by Embodiment 4 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Buffer apparatus, 2 CPU, 3, 15 CPU I / F part, 4 DMA transfer request reception part, 5 Memory, 10 Access request storage part, 11 DMA control part, 12 Arbitration circuit part, 13 Access request control part (Storage control part) ), 14 read access processing unit, 15 access distribution unit, 40 transfer source address register, 41 transfer destination address register, 42 transfer data number register, 43 transfer start register, 100 flag, 101 type, 102 address, 103 address data, 104 Additional information, 105-0 to 105-7, access request entry, 106 DMA maximum size information, 141, 315 address conversion unit, 142 write buffer verification unit, 310 request entry selector, 311 counter, 312 control circuit, 313 selector, 314 read Data extraction unit, 316 address holding unit, 317 read access issuing circuit, 318 data holding unit.

Claims (6)

In a buffer device provided between the CPU and the memory and temporarily holding a write request to the memory,
An access request storage unit that stores the write request and DMA transfer request issued from the CPU in a first-in first-out manner;
An access distribution unit that distributes the write request and the DMA transfer request output from the access request storage unit;
A DMA control unit that controls DMA transfer to the memory according to the DMA transfer request distributed by the access distribution unit;
An arbitration circuit unit that inputs a read request to the memory, the write request distributed by the access distribution unit, and a DMA transfer request issued from the DMA control unit, and executes access to the memory according to each access request;
Input a read request issued from the CPU to the memory, and check whether the read access target area of the read request overlaps with the access target area of each access request stored in the access request storage unit A read access processing unit that issues a read request in which the read access target area is address-converted to the transfer source area of the DMA transfer request when it overlaps the transfer destination area of the DMA transfer request to the arbitration circuit unit. Feature buffer device.   When the read access processing unit converts the read access target area of the read request into the transfer source area of the DMA transfer request, the read access target area after the DMA transfer request stored in the access request storage unit 2. The buffer device according to claim 1, wherein it is checked whether or not each access request overlaps with an access target area.   When the access target area of the access request issued from the CPU does not overlap the access target area of the access request stored in the access request storage unit, the access request issued from the CPU is stored in the access request storage unit. 3. The buffer apparatus according to claim 1, further comprising a storage control unit that outputs the access request to the access distribution unit prior to the access request.   When the DMA transfer requests are arranged in the output order in the access request storage unit, the storage control unit stores the access request so that a DMA transfer request with a small DMA transfer size is preceded on condition that there is no overlapping of transfer areas. 4. The buffer device according to claim 3, wherein the output order from the units is switched.   When the storage control unit outputs a DMA transfer request from the access request storage unit to the access distribution unit, the storage control unit generates a new DMA transfer request by dividing the DMA transfer size so that the DMA transfer size is equal to or less than a predetermined value. 5. The buffer device according to claim 3, wherein the buffer is output from the access request storage unit in ascending order of transfer size.   6. The read access processing unit according to claim 1, wherein the read access processing unit collates each access request fetched from the access request storage unit in synchronization with a predetermined clock, and executes processing according to the collation result. The buffer device according to any one of the above.

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