WO2014147768A1

WO2014147768A1 - Control device, control program, and control method

Info

Publication number: WO2014147768A1
Application number: PCT/JP2013/057909
Authority: WO
Inventors: 雅紀日下田; 早坂　和美
Original assignee: 富士通株式会社
Priority date: 2013-03-19
Filing date: 2013-03-19
Publication date: 2014-09-25
Also published as: JP6132010B2; JPWO2014147768A1

Abstract

A NAND controller (6a) selects one logical block number and identifies, in an address conversion table cache (12), a physical address associated with the logical address containing the selected logical block number. In addition, the NAND controller (6a) moves each instance of data stored in a page indicated by the identified physical address to a physical page which is contained in one physical block and the physical page number of which is identical to the logical page number of each instance of data. In addition, the NAND controller (6a) associates the selected physical block number and the physical block number of the physical block to which the data has been moved, and stores these in a quick-reference table (13).

Description

Control device, control program, and control method

The present invention relates to a control device, a control program, and a control method.

Conventionally, an information processing system using a non-volatile memory that operates faster than a magnetic disk is known. As an example of such an information processing system, an information processing system using a plurality of NAND flash memory devices as storage is known. In the following description, the NAND flash memory device is described as a NAND device.

For example, a controller that reads data from a NAND device has an address conversion table that associates a logical address used for data designation by the information processing system with a physical address indicating an area of the NAND device in which data to be read is stored. Have. When the controller receives the data read request and the logical address to be read, the controller obtains a physical address associated with the received logical address from the address conversion table. The controller then accesses the area indicated by the acquired physical address and reads data from the NAND device.

Here, since the size of the address conversion table is proportional to the total capacity of the NAND device, it is not realistic to store the entire address conversion table in the controller for a large capacity storage. For this reason, a technique is known in which an address conversion table is stored on a NAND device, and a controller holds a part of the address conversion table.

For example, the controller holds a part of the address conversion table and a conversion table tag indicating a physical address in which the address conversion table is stored. When receiving the read request and the logical address, the controller determines whether or not the received logical address is included in the held address conversion table. When the received logical address is included in the held address conversion table, the controller reads data from the NAND device using the physical address associated with the logical address.

On the other hand, when the received logical address is not included in the held address conversion table, the controller identifies the physical address in which the address conversion table including the received logical address is stored using the conversion table tag. In addition, the controller reads a part of the address conversion table from the NAND device using the identified physical address. Then, the controller acquires a physical address associated with the logical address from the read address conversion table, and reads data from the NAND device using the acquired physical address.

JP 2012-174086 A Japanese Patent No. 3251968 Japanese Patent No. 4643315

However, in the technique in which the controller holds a part of the address conversion table described above, if the read address does not include the logical address to be read, the address conversion table is read from the NAND device. Thereafter, data is read from the NAND device in accordance with the read address conversion table, so that there is a problem that latency when reading data from the NAND device increases.

Also, as the capacity of the NAND device increases, the overall size of the address conversion table also increases. As a result, the probability that the logical address to be read is included in the address conversion table held by the controller is lowered, and the latency is increased.

In one aspect, the present application aims to shorten the time required for address conversion in accessing a nonvolatile memory.

In one aspect, the control device reads data from a storage device. Further, the control device stores a conversion table in which a physical number obtained by combining a physical block number and a physical page number is associated with a logical number obtained by combining a logical block number and a logical page number. Further, the control device selects one logical block number, and identifies the physical number associated with the logical number including the selected logical block number from the conversion table. In addition, the control device stores the data in the storage area indicated by the identified physical number in the storage area included in one block and indicated by the same physical page number as the logical page number included in the logical number of the data Move to. In addition, the control device stores a quick lookup table in which the physical block number of the block to which the data has been moved is associated with the logical block number selected by the selection unit. Then, when receiving the logical number indicating the area in which the data to be read is stored, the control device acquires the physical block number associated with the logical block number included in the received logical number from the early lookup table. Thereafter, the control device reads data stored in the area indicated by the same physical page number as the logical page number included in the received logical number, among the data stored in the block indicated by the acquired physical block number.

In one aspect, it is possible to shorten the time required for address conversion in accessing a nonvolatile memory.

FIG. 1 is a diagram illustrating the information processing apparatus according to the first embodiment. FIG. 2 is a first diagram for explaining a conventional writing process. FIG. 3 is a second diagram for explaining the conventional writing process. FIG. 4 is a diagram for explaining the flow of the alignment process. FIG. 5 is a diagram for explaining the flow of the reading process. FIG. 6 is a diagram illustrating a functional configuration of the NAND controller according to the first embodiment. FIG. 7 is a diagram for explaining the conversion table tag. FIG. 8 is a diagram for explaining an example of the address conversion table held by the NAND controller. FIG. 9 is a diagram for explaining an example of the early lookup table. FIG. 10 is a diagram for explaining the entire address conversion table. FIG. 11 is a diagram for explaining the flow of address conversion using the address conversion table. FIG. 12 is a diagram for explaining the flow of address conversion using the early lookup table. FIG. 13 is a flowchart for explaining the flow of data read processing. FIG. 14 is a flowchart for explaining the flow of data write processing. FIG. 15 is a flowchart for explaining the flow of the alignment process. FIG. 16 is a flowchart for explaining a first variation of the alignment process. FIG. 17 is a flowchart for explaining a second variation of the alignment process. FIG. 18 is a diagram illustrating a functional configuration of a NAND controller that executes alignment processing according to the frequency of occurrence of read requests and write requests. FIG. 19 is a flowchart for explaining a third variation of the alignment process. FIG. 20 is a diagram for explaining a functional configuration of a NAND controller in which a conversion table tag and a quick lookup table are shared. FIG. 21 is a diagram for explaining the flow of the address conversion process when the conversion table tag and the early lookup table are shared. FIG. 22 is a diagram for explaining the functional configuration of the NAND controller that holds a part of the early lookup table. FIG. 23 is a diagram for explaining the flow of the address conversion process executed using the early lookup table tag. FIG. 24 is a diagram illustrating an example of a NAND controller that executes a control program.

Embodiments of a control device, a control program, and a control method according to the present application will be described below in detail with reference to the accompanying drawings. The disclosed technology is not limited by this embodiment. In addition, the embodiments may be combined as appropriate within a consistent range.

In the following first embodiment, an example of an information processing apparatus including the control apparatus according to the present application will be described with reference to FIG. FIG. 1 is a diagram illustrating the information processing apparatus according to the first embodiment. In the example shown in FIG. 1, the information processing apparatus 1 includes a plurality of memories 2a and 2b, a plurality of CPUs (Central Processing Units) 3a and 3b, an I / O (Input Output) hub 4, and a plurality of SSDs (Solid State Drives). 5a and 5b. Further, the SSD 5a includes a NAND controller 6a and a plurality of storage devices 7a to 10a.

Further, the SSD 5b includes a NAND controller 6b and a plurality of storage devices 7b to 10b. In the following description, the NAND controller 6b and the plurality of storage devices 7b to 10b perform the same functions as the NAND controller 6a and the plurality of storage devices 7a to 10a, and the description thereof is omitted.

The memories 2a and 2b are storage devices that store data used by the

CPUs

3a and 3b for arithmetic processing. The

CPUs

3a and 3b are arithmetic processing devices that perform various arithmetic processes using data stored in the memories 2a and 2b. For example, the

CPUs

3a and 3b use NUMA (Non-Uniform Memory Access) technology to acquire data stored in the memories 2a and 2b, and execute arithmetic processing using the acquired data.

Further, the

CPUs

3a and 3b acquire data stored in the respective SSDs 5a and 5b via the I / O hub 4, and execute arithmetic processing using the acquired data. Specifically, the CPU 3a issues a data read request or write request to the SSD 5a, and reads or writes data from each of the storage devices 7a to 10a. For example, the CPU 3a issues a read request in which a logical address designating data is stored to the SSD 5a. In addition, the CPU 3a issues a write request in which a logical address designating a data write destination and data to be written are stored.

The storage device 7a is a nonvolatile memory that stores various data. Specifically, the storage device 7a has a plurality of pages as data storage areas, and writes data in units of pages. The storage device 7a has a plurality of blocks each having a plurality of pages, and erases data in units of blocks.

The NAND controller 6a accesses each of the storage devices 7a to 10a, and reads and writes data. For example, the NAND controller 6a associates logical addresses used when the

CPUs

3a and 3b specify storage areas in which data is stored with physical addresses indicating storage areas of the storage devices 7a to 10a in which data is stored. An address translation table.

When the NAND controller 6a receives the logical address together with the read request, the NAND controller 6a uses the address conversion table to identify the physical address associated with the logical address, and reads data from the storage area indicated by the identified physical address. . Thereafter, the NAND controller 6a transmits the read data to the CPU 3a via the I / O hub 4.

In the following description, in order to facilitate understanding, the logical address that is the top address of each page is simply described as a logical address, and the physical address that is the top address of each page is simply described as a physical address. In addition, the system executed by the information processing apparatus 1 issues a read request and a write request for a logical address that is the top address of each page.

The NAND controller 6a performs the following processing when the storage devices 7a to 10a have a plurality of blocks and each block includes ^2q pages. First, the NAND controller 6a uses the lower q bits of the logical address as a logical page number for identifying a page in one logical block, and the upper p bits of the remaining logical addresses as one logical block. The logical block address shown in FIG.

Further, the NAND controller 6a uses the upper p bits of the physical address as a physical block address indicating one physical block, and the lower q bits of the physical address for identifying each page in one physical block. The physical page number. That is, the NAND controller 6a divides a logical address into a logical block address indicating a logical block and a logical page number indicating a logical page for each logical block. The NAND controller 6a divides the physical address into a physical block address indicating a physical block and a physical block number indicating a physical page for each physical block.

Here, in the technique of converting a logical address to a physical address using the address conversion table, when the capacity of the storage device increases, the number of entries in the address conversion table also increases, and the circuit scale of the NAND controller increases. . For example, FIG. 2 is a first diagram for explaining a conventional writing process. In the example shown in FIG. 2, in order to facilitate understanding, a storage device in which the number of blocks is “8” and the number of pages in each block is “4” is described. In the example illustrated in FIG. 2, processing executed by the NAND controller having an address conversion table in which a logical block address and a physical block address are associated with each other is described.

For example, as shown in FIG. 2A, the file system issues a write request for the logical page indicated by the logical page number “1” among the logical pages included in the logical block address “L4”. That is, the file system issues a write request for the logical address “L4-1”. Then, the NAND controller obtains the physical block address “P7” associated with the logical block address “L4” as shown in (B) of FIG. 2, and writes it as shown in (C) of FIG. Identify the block that contains the page of interest.

Subsequently, as shown in FIG. 2D, the NAND controller copies all data of the physical block indicated by the physical block address “P7” to the spare block. At this time, the NAND controller updates the data of the physical page number “1” that is the same as the logical page number “1” that is the target of the write request with the data that is the target of the write. Thereafter, as shown in FIG. 2E, the NAND controller updates the physical block address “P7” associated with the logical block address “L4” to the physical block address “P8” of the spare block. Then, the NAND controller erases the data of the block indicated by the physical block address “P7”.

Also, as another conventional example, the address conversion table may be managed for each page. For example, FIG. 3 is a second diagram for explaining a conventional writing process. In the example shown in FIG. 3, for the sake of easy understanding, the storage device in which the number of blocks is “8” and the number of pages in each block is “4” is described as in FIG. In the example illustrated in FIG. 3, the process executed by the NAND controller having the address conversion table in which the logical address and the physical address are associated is described.

For example, as shown in FIG. 3F, the file system issues a write request to the logical page number “3” of the logical block address “L0”, that is, the logical address “L0-3”. Then, the NAND controller obtains the physical address “P4-3” associated with the logical address “L0-3” as shown in (G) of FIG. 3, and as shown in (H) of FIG. Identify the page where the pre-update data is stored. Subsequently, as shown in (I) of FIG. 3, the NAND controller updates the data of the page indicated by the physical address “P4-3” and copies it to the spare block. Thereafter, the NAND controller updates the physical address “P4-3” associated with the logical address “L0-3” to “P8-0” as shown in (J) of FIG. To do.

However, in the conventional NAND system, the size of the address conversion table is proportional to the total capacity of the NAND device regardless of whether the address conversion table is stored for each block or page unit. Will increase.

Therefore, the NAND controller 6a stores the address conversion table in the storage devices 7a to 10a and holds a part of the address conversion table. For example, in the address conversion table, a physical address physically indicating the storage area indicated by the logical address is stored in an entry associated with each logical address. In addition, the NAND controller 6a includes a conversion table tag that associates a physical address in which an address conversion table for converting a logical address having a common upper i bit of a logical address into a physical address and an upper i bit of the logical address are associated with each other. Hold.

Then, the NAND controller 6a acquires the physical address associated with the upper i bits of the logical address to be read or written from the conversion table tag, and from the storage area indicated by the acquired physical address, Read a part. Here, the storage area indicated by one physical address stores an address conversion table in which the physical address of the conversion destination is stored in a plurality of entries associated with the lower j bits of the logical address. Therefore, the NAND controller 6a can read the physical address of the entry associated with the lower j bits of the logical address to be read or written in the read address conversion table. In the following description, the upper i bits of the logical address are simply described as the upper address, and the lower j bits are described as the lower address.

Here, in the technology in which the NAND controller holds a part of the address conversion table, when the logical address to be processed is not included in the address conversion table to be held, the NAND controller converts the address conversion table including the logical address to be processed. Get from. Then, the logical address is converted into a physical address using the address conversion table acquired from the NAND controller, and the memory is accessed using the converted physical address. As a result, in the technique in which the NAND controller holds a part of the address conversion table, it takes time for address conversion, and the latency of memory access increases.

Therefore, the NAND controller 6a executes the following alignment process when a predetermined condition is met. That is, the NAND controller 6a selects a plurality of logical addresses having a common logical block address, and identifies a physical address associated with the selected logical address using the address conversion table.

Then, the NAND controller 6a moves the data stored in the identified physical address from the first page included in the spare block to each page in the order of logical page numbers. That is, the NAND controller 6a aligns and moves the data so that the logical page number of each data and the physical page number of the movement destination have the same value. Then, the NAND controller 6a stores the logical block address of the aligned data and the physical block address of the block to which the data has been moved in association with each other.

Further, when the NAND controller 6a receives the logical address together with the read request, the NAND controller 6a acquires the upper bits of the received logical address, that is, the physical block address stored in association with the logical block address of the data to be read. Here, the logical page number and the physical page number of each data have the same value in the aligned block. Therefore, the NAND controller 6a acquires the physical address where the data to be read is stored by adding the logical page number of the received logical address to the acquired physical block address. Thereafter, the NAND controller 6 acquires data to be read using the acquired physical address.

In this way, the NAND controller 6a moves each data of the page designated by the logical address having the common logical block address to one physical block. At this time, the NAND controller 6a moves each data to a page indicated by the same physical page number as the logical page number of each data. Then, the NAND controller 6a stores a fast lookup table 13 in which a physical block address indicating a physical block that is a destination of each data is associated with a logical block address of the moved data.

After that, when receiving the logical address to be read, the NAND controller 6a acquires the physical block address associated with the logical block address included in the logical address from the early lookup table 13. Then, the NAND controller 6a acquires a physical address indicating a storage area in which data to be read is stored by adding the logical page number of the received logical address to the acquired physical block address.

As a result, even when the physical address corresponding to the logical address to be read is not stored in the address conversion table cache 12, the NAND controller 6 a performs the address conversion without performing the read process of the address conversion table 20. realizable. For this reason, the NAND controller 6a can shorten the latency of the address conversion process.

Here, an example of processing executed by the NAND controller 6a will be described with reference to FIGS. First, the alignment process executed by the NAND controller 6a will be described with reference to FIG. FIG. 4 is a diagram for explaining the flow of the alignment process. In the example shown in FIG. 4, in order to facilitate understanding, the storage devices 7a to 10a in which the number of blocks is “8” and the number of pages in each block are “4” are described as in FIG.

For example, the NAND controller 6a confirms the fast-drawing table, and as shown in (K) in FIG. 4, the physical block address is not associated with the logical block address “L0” and is not registered or has a valid physical It is determined that the block address is not associated. In such a case, the NAND controller 6a selects the logical addresses “L0-0” to “L0-3” including the logical block address “L0”, as indicated by (L) in FIG. Further, the NAND controller 6a uses the address conversion table to convert the logical addresses “L0-0” to “L0-3” into physical addresses “P0-0”, “P7-0”, “P2-2”, “P4”. -3 ”. Then, as indicated by (M) in FIG. 4, the page indicated by each physical address is identified.

Next, the NAND controller 6a moves the data of each identified page to the spare block. At this time, as shown in FIG. 4 (N), the NAND controller 6a has the same logical page number of the logical address used when designating each data and the physical page number of the page to which the data is moved. Each data is moved so that it becomes.

Specifically, the NAND controller 6a moves the data of the logical address “L0-0” stored in the physical address “P4-0” to the physical address “P8-0”. Further, the NAND controller 6a moves the data of the logical address “L0-1” stored in the physical address “P7-0” to the physical address “P8-1”. Further, the NAND controller 6a moves the data of the logical address “L0-2” stored in the physical address “P2-2” to the physical address “P8-2”. Further, the NAND controller 6a moves the data of the logical address “L0-3” stored in the physical address “P4-3” to the physical address “P8-3”.

Then, the NAND controller 6a updates the address conversion table as indicated by (O) in FIG. 4 and also stores the logical block address “L0” and the physical address in the early lookup table as indicated by (P) in FIG. The block address “P8” is stored in association with each other.

Next, an example of processing executed by the NAND controller 6a using the early lookup table when reading data will be described with reference to FIG. FIG. 5 is a diagram for explaining the flow of the reading process. In the example shown in FIG. 5, in order to facilitate understanding, the storage devices 7a to 10a in which the number of blocks is “8” and the number of pages in each block is “4” are described, as in FIG.

For example, in the example shown in FIG. 5, the file system issues a read request to the logical address “L0-3” as indicated by (Q) in FIG. In such a case, as shown in (R) in FIG. 5, the NAND controller 6a quickly sets the physical block address “P8” associated with the logical block address “L0” of the logical address “L0-3”. Get from the pull table. Here, in the block indicated by the physical block address “P8”, each data is stored in the same physical page number as the logical page number of each data.

Therefore, the NAND controller 6a has the same logical page number “3” of the logical address “L0-3” among the pages included in the block of the physical block address “P8”, as shown in FIG. Data is read from the page indicated by the physical page number “3”. As a result, even when the logical address “L0-3” is not included in the held address conversion table, the NAND controller 6a performs address conversion without reading the address conversion table from the storage devices 7a to 10a. Can do.

Next, the functional configuration of the NAND controller 6a will be described with reference to FIG. FIG. 6 is a diagram illustrating a functional configuration of the NAND controller according to the first embodiment. In the example illustrated in FIG. 6, the NAND controller 6 a includes a conversion table tag 11, an address conversion table cache 12, an early search table 13, a requester interface unit 14, and a request arbitration unit 15. The NAND controller 6 a includes an address conversion control unit 16, a device access control unit 17, a data alignment control unit 18, and a garbage collection control unit 19. The storage devices 7a to 10a store an address conversion table 20 and user data 21.

The conversion table tag 11 is a table in which an upper address is associated with a physical address in which an address conversion table for converting a logical address including the upper address into a physical address is stored. For example, FIG. 7 is a diagram illustrating a conversion table tag. In the example shown in FIG. 7, the conversion table tag 11 has a plurality of entries respectively associated with the upper addresses “0” to “2 ⁱ −1” of the logical address.

Each entry of the translation table tag 11 includes a physical address (table PA: Physical Address) “a” to “a” that stores an address translation table for converting a logical address including the associated upper address into a physical address. “M” is stored. The values of the physical addresses “a” to “m” change to different values every time a part of the address conversion table held by the NAND controller 6a is changed.

Returning to FIG. 6, the address translation table cache 12 is a part of the address translation table 20 stored on the storage devices 7a to 10a. For example, FIG. 8 is a diagram for explaining an example of the address conversion table held by the NAND controller. In the example shown in FIG. 8, the address conversion table cache 12 has entries associated with lower addresses “0” to “2 ^j −1”. Further, the address conversion table cache 12 stores valid bits (Valid) and data PA “BA” to “BN”, which are physical addresses in which data is stored, in association with each entry.

Here, the valid bit is a bit indicating whether or not the associated physical address is a valid physical address. For example, in the example shown in FIG. 8, the physical address “BC” of the entry associated with the lower address “2” is a valid physical address, but the physical address of the entry associated with the lower address “1”. “BB” is not a valid physical address.

Note that the NAND controller 6a holds, as the address translation table cache 12, a range specified by the physical address indicated by the translation table tag in the address translation table 20. For example, in the example illustrated in FIGS. 8 and 10, the NAND controller 6 a holds the address conversion table cache 12 stored in the physical page whose physical address is “b”.

Returning to FIG. 6, the early lookup table 13 stores the logical block address and the physical block address in association with each other. For example, FIG. 9 is a diagram for explaining an example of the early lookup table. For example, in the example shown in FIG. 9, the early lookup table has entries associated with logical block addresses “0” to “2 ^p −1”. In addition, the fast-drawing table 13 stores a registration flag and a physical block address in association with each entry. Here, the registration flag is a flag indicating whether or not the data is aligned and moved to the block indicated by the associated physical block address. When the data is aligned and moved, the flag is “1” and the data is aligned. When it is not moved, it is “0”.

Returning to FIG. 6, the address conversion table 20 is an address conversion table used when converting a physical address into a logical address. For example, FIG. 10 is a diagram illustrating the entire address conversion table. For example, as shown in FIG. 10, the address conversion table 20 is a table stored in the range of physical addresses “a” to “m” in the storage areas of the storage devices 7a to 10a. The address conversion table 20 has entries associated with logical page numbers “0” to “2 ^j −1” in one page, and the valid bit and each logical page number are included in each entry. The physical address where the indicated data is stored is stored.

For example, in the address conversion table stored in the page indicated by the physical address “a”, the physical address “0” and the low-order addresses “0” to “2 ^j −1” corresponding to the logical addresses “0” to “2 ^j −1” “AA” to “AN” are stored. The address conversion table stored in the page indicated by the physical address “b” includes the physical address “1” corresponding to the logical address having the upper address “1” and the lower addresses “0” to “2 ^j −1”. “BA” to “BN” are stored. Further, the address conversion table stored in the page indicated by the physical address “m” corresponds to the logical address having the upper address “2 ⁱ −1” and the lower addresses “0” to “2 ^j −1”. Physical addresses “MA” to “MN” are stored. Here, the correspondence between the physical addresses “a” to “m” stored in the address conversion table and the higher addresses “0” to “2 ⁱ −1” of the logical address is managed by the conversion table tag 11.

Returning to FIG. 6, the requester interface unit 14 receives a read request or a write request via the I / O hub. When receiving the read request, the requester interface unit 14 outputs the received read request to the request arbitration unit 15. Further, when the requester interface unit 14 receives data that is the target of a read request from the device access control unit 17, the requester interface unit 14 outputs the received data to the

CPUs

3a and 3b that are the issuers of the read request.

Further, when the requester interface unit 14 receives a write request, it executes the following write process. For example, the requester interface unit 14 outputs a read request including the logical address stored in the received write request to the request arbitration unit 15. When the requester interface unit 14 receives the data to be read, the requester interface unit 14 updates the received data with the data to be written. The requester interface unit 14 then outputs a write request including the logical address stored in the received write request and the updated data to the request arbitration unit 15.

The request arbitration unit 15 arbitrates read requests and write requests from the requester interface unit 14, the data alignment control unit 18, and the garbage collection control unit 19, and executes them in the order according to the arbitration result. For example, when receiving a read request, the request arbitration unit 15 outputs a logical address to be read to the address conversion control unit 16. When the request arbitration unit 15 receives a physical address to be read from the address translation control unit 16, it issues a read request for the received physical address to the device access control unit 17.

Further, when the request arbitration unit 15 receives the write request, the request arbitration unit 15 inquires of the address translation control unit 16 and acquires the physical address of the spare block in which no data is stored in each page. Thereafter, the request arbitration unit 15 outputs a write request for requesting writing of updated data to the device access control unit 17 for the acquired physical address. In addition, the request arbitration unit 15 outputs the logical address stored in the write request and the physical address storing the data to the address conversion control unit 16.

The address conversion control unit 16 converts a logical address into a physical address. For example, when receiving the logical address, the address conversion control unit 16 refers to the early lookup table 13 and identifies an entry associated with the logical block address of the received logical address. Further, the address conversion control unit 16 determines whether or not the registration flag of the identified entry is “1”.

Then, when the registration flag of the identified entry is “1”, the address translation control unit 16 acquires the physical block address stored in the identified entry. Further, the address conversion control unit 16 generates a physical address by adding the lower q bits of the received logical address, that is, the logical page number, to the acquired physical block address.

On the other hand, if the registration flag of the identified entry is “0”, that is, if the received logical address is not aligned, the address translation control unit 16 executes address translation processing using the address translation table. . For example, the address conversion control unit 16 acquires the physical address stored in the entry associated with the higher-order address of the received logical address among the entries of the conversion table tag 11.

Then, the address conversion control unit 16 acquires a part of the address conversion table 20 by outputting the acquired physical address to the device access control unit 17. Then, the address translation control unit 16 sets a part of the received address translation table 20 as the address translation table cache 12. Then, the address translation control unit 16 acquires the physical address stored in the entry associated with the lower address of the received logical address among the entries of the address translation table cache 12. Thereafter, the address translation control unit 16 outputs the acquired physical address to the request arbitration unit 15.

Further, the address conversion control unit 16 receives from the request arbitration unit 15 the logical address stored in the write request and the physical address storing the data. Then, the address translation control unit 16 acquires a part of the address translation table 20 as the address translation table cache 12 using the upper address of the received logical address. Then, the address translation control unit 16 rewrites the physical address of the entry associated with the lower address of the logical address in the acquired address translation table cache 12 with the physical address received from the request arbitration unit 15.

Thereafter, the address translation control unit 16 outputs the address translation table cache 12 to the device access control unit 17 and instructs rewriting of the address translation table 20 stored in the storage devices 7a to 10a. Here, when the address translation table cache 12 is written back to the storage devices 7a to 10a, it is not written back to the cache source page. For this reason, the address translation control unit 16 updates the translation table tag 11 so that the physical address to which the address translation table cache 12 is written back is associated with the upper bits of the logical address corresponding to the written address translation table cache 12. .

In addition, the address conversion control unit 16 sets the registration flag of the entry associated with the logical block address of the received logical address among the entries of the early lookup table 13 to “0”. That is, the address translation control unit 16 invalidates the corresponding entry among the entries in the fast-drawing table 13 when the aligned data is moved to another physical block due to data writing.

Next, an example of address conversion executed by the address conversion control unit 16 will be described with reference to FIGS. First, the flow of address conversion executed by the address conversion control unit 16 using the address conversion table will be described with reference to FIG. FIG. 11 is a diagram for explaining the flow of address conversion using the address conversion table.

First, when receiving the logical address, the address conversion control unit 16, as shown in (S) in FIG. 11, of the entries associated with the upper address of the received logical address among the entries of the conversion table tag 11. Get physical address. Then, since the address translation control unit 16 obtains the physical address “b”, the address translation table stored in the physical address “b” is obtained as the address translation table cache 12 as shown in FIG. To do.

Next, as shown in FIG. 11 (U), the address translation control unit 16 stores the physical stored in the entry associated with the lower address of the received logical address among the entries of the address translation table cache 12. The address “BC” is acquired. Then, the address translation control unit 16 outputs the acquired physical address “BC” to the request arbitration unit 15 as a translation result, as indicated by (V) in FIG.

Next, address conversion executed by the address conversion control unit 16 using the early lookup table 13 will be described with reference to FIG. FIG. 12 is a diagram for explaining the flow of address conversion using the early lookup table. For example, as shown in (W) of FIG. 12, the address translation control unit 16 selects an entry associated with the logical block address that is the upper p bits of the received logical address from among the entries of the early lookup table 13. Identify. Here, since the registration flag of the identified entry is “1”, the address translation control unit 16 acquires the physical block address “B” stored in the identified entry.

Further, as shown in (X) of FIG. 12, the address conversion control unit 16 uses the logical page number that is the lower q bits of the received logical address as the physical page number, and the physical block address “ It is added to the lower part of “B”. As a result, the address conversion control unit 16 performs address conversion without reading the address conversion table from the storage devices 7a to 10a even when the address conversion table for converting the received logical address to the physical address is not held. be able to.

Referring back to FIG. 6, the device access control unit 17 executes data write / read processing on the storage devices 7a to 10a. For example, the device access control unit 17 receives a data write request from the request arbitration unit 15 or the address translation control unit 16. In such a case, the device access control unit 17 writes the data stored in the write request to the page indicated by the physical address stored in the received write request. Then, the device access control unit 17 transmits a write completion notification to the issuer of the write request.

Further, when the device access control unit 17 receives a data read request from the request arbitration unit 15 or the address conversion control unit 16, the device access control unit 17 reads data from the page indicated by the physical address stored in the received read request. Then, the device access control unit 17 transmits the read data to the read request issuer.

The data alignment control unit 18 executes data alignment processing at a predetermined timing. For example, the data alignment control unit 18 executes the following processing for each logical block address “0” to “2 ^p −1”. First, the data alignment control unit 18 is associated with the logical block address that is the target of the alignment process among the entries of the early lookup table 13 directly or through the request arbitration unit 15 and the address conversion control unit 16. Check the registration flag of the entry. When the registration flag is “1”, the data alignment control unit 18 checks the registration flag of the entry associated with the next logical block address.

When the registration flag of the entry associated with the logical block address that is the target of the alignment process is “0”, the data alignment control unit 18 executes the following process. First, the data alignment control unit 18 secures a spare physical block that is a data alignment destination. For example, the data alignment control unit 18 causes the garbage collection control unit 19 to execute garbage collection to secure a spare physical block. Then, the data alignment control unit 18 indicates the data of the pages indicated by the logical page numbers “0” to “2 ^q −1” as indicated by the physical page numbers “0” to “2 ^q −1” of the spare physical block. Move to page.

A detailed example will be described. For example, the data alignment control unit 18 secures a spare physical block with the physical block address “X” in order to perform alignment processing for a certain logical block address “x”. Then, the data alignment control unit 18 issues a read request to read the data of the page indicated by the logical block address “x” and the logical page number “0”. Then, the data alignment control unit 18 issues a write request to write the read data to the page indicated by the physical block address “X” and the logical page number “0”.

Next, the data alignment control unit 18 issues a read request to read the data of the page indicated by the logical block address “x” and the logical page number “1”. Then, the data alignment control unit 18 issues a write request to write the read data to the page indicated by the physical block address “X” and the logical page number “1”. By repeatedly executing such processing up to the logical page number “2 ^q −1”, the data alignment control unit 18 performs alignment for data whose logical block address is “x”.

In addition, when the alignment process is completed for one logical block address, the data alignment control unit 18 instructs the device access control unit 17 via the request arbitration unit 15 to update the early lookup table 13. Specifically, the data alignment control unit 18 instructs to store a physical block indicating a physical block that is a data transfer destination in an entry associated with the logical block address subjected to the alignment process. As a result, the device access control unit 17 stores the physical block address that is the data transfer destination in the entry associated with the logical block address that has undergone the alignment process, and changes the registration flag to “1”.

In addition, when the alignment process is completed for one logical block address, the data alignment control unit 18 determines whether or not the registration flag of the entry in the early lookup table 13 associated with the next logical block address is “0”. Determine. By executing such processing for all logical block addresses, the data alignment control unit 18 can align all data.

The garbage collection control unit 19 executes garbage collection using a physical block in which valid data is stored in some pages as a spare block. For example, the garbage collection control unit 19 reads the address conversion table 20 and identifies physical blocks in which valid data is stored in some pages as erasure target blocks. The garbage collection control unit 19 issues a read request by designating a page storing valid data in the erasure target block, and reads the data.

Next, the garbage collection control unit 19 designates a page in which valid data is not stored among the physical blocks other than the erasure target block, and writes the read data. Then, the garbage collection control unit 19 outputs to the request arbitration unit 15 an erasure request instructing erasure of data in the erasure target block. In such a case, the request arbitration unit 15 transfers an erasure request to the device access control unit 17. Then, the device access control unit 17 erases the data of the block to be erased.

For example, the requester interface unit 14, the request arbitration unit 15, the address translation control unit 16, the device access control unit 17, the data alignment control unit 18, and the garbage collection control unit 19 are electronic circuits. Here, as an example of the electronic circuit, an integrated circuit such as ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array), or CPU (Central Processing Unit) or MPU (Micro Processing Unit) is applied.

Further, the conversion table tag 11, the address conversion table cache 12, and the quick lookup table 13 are information stored in a storage device such as a semiconductor memory element such as a RAM (Random Access Memory) or a flash memory.

Next, the flow of processing executed when the NAND controller 6a reads data will be described with reference to FIG. FIG. 13 is a flowchart for explaining the flow of data read processing. For example, the NAND controller 6a receives a read request including a logical address from a system realized by a program executed by the

CPUs

3a and 3b (step S101). Then, the NAND controller 6a searches for an entry associated with the logical block address, which is the higher-order bit of the received logical address, from among the entries in the early lookup table 13 (step S102). Then, the NAND controller 6a determines whether or not the registration flag of the searched entry is “1” (step S103).

Here, if the registration flag of the searched entry is not “1” (No at Step S103), the NAND controller 6a is an entry associated with the higher-order address of the received logical address among the entries of the conversion table tag 11. Is searched (step S104). Further, the NAND controller 6a acquires a part of the address conversion table 20 as the address conversion table cache 12 using the physical address stored in the searched entry. Then, the NAND controller 6a searches for the entry associated with the lower address of the received logical address among the obtained entries of the address translation table cache 12 (step S105).

Here, the NAND controller 6a determines whether or not the valid bit of the searched entry is “1” (step S106). If the valid bit of the searched entry is not “1” (No at Step S106), the NAND controller 6a notifies the system of an address exception error notification (Step S107), and ends the processing abnormally. On the other hand, if the valid bit of the searched entry is “1” (Yes at Step S106), the NAND controller 6a converts the received logical address into a physical address stored in the searched entry (Step S108).

Then, the NAND controller 6a issues a read request (Read) including the acquired physical address (Step S109). The read data is returned to the system (step S110), and the process is terminated. On the other hand, if the registration flag of the searched entry is “1” (Yes at Step S103), the NAND controller 6a skips the processes of Steps S104 to S106. Then, the NAND controller 6a converts the logical address into a physical address that combines the physical block address stored in the searched entry and the logical page number of the received logical address (step S108).

Next, the flow of processing executed when the NAND controller 6a writes data will be described with reference to FIG. FIG. 14 is a flowchart for explaining the flow of data write processing. For example, the NAND controller 6a receives a write request including a logical address from the system (step S200). Then, the NAND controller 6a searches for an entry associated with the logical block address, which is the higher-order bit of the received logical address, among the entries in the early lookup table 13 (step S201). Then, the NAND controller 6a determines whether or not the registration flag of the searched entry is “1” (step S202).

Here, if the registration flag of the searched entry is not “1” (No at Step S202), the NAND controller 6a has an entry associated with the higher-order address of the received logical address among the entries of the conversion table tag 11. Is searched (step S203). Further, the NAND controller 6a acquires a part of the address conversion table 20 as the address conversion table cache 12 using the physical address stored in the searched entry. Then, the NAND controller 6a searches for the entry associated with the lower address of the received logical address among the obtained entries of the address translation table cache 12 (step S204).

Here, the NAND controller 6a determines whether or not the valid bit of the searched entry is “1” (step S205). If the valid bit is “1” (Yes at Step S205), the NAND controller 6a converts the received logical address into a physical address stored in the searched entry (Step S206). On the other hand, if the registration flag of the searched entry is “1” (Yes at step S202), the NAND controller 6a skips the processing of steps S203 to S205. Then, the NAND controller 6a converts the logical address into a physical address that combines the physical block address stored in the searched entry and the logical page number of the received logical address (step S206).

Subsequently, the NAND controller 6a issues a read request to the physical page indicated by the acquired physical address (step S207), and updates the read data with the write data (step S208). Then, the NAND controller 6a issues an updated data write request (Write) to the new physical page (step S209).

Further, the NAND controller 6a updates the physical address associated with the logical address of the write request received from the system in the address conversion table cache 12 to the physical address indicating the physical page to which data is newly written. Then, the NAND controller 6a writes back the address conversion table cache 12 to the storage devices 7a to 10a, and updates the address conversion table 20 (step S210).

Further, the NAND controller 6a updates the conversion table tag 11 (step S211). Specifically, the NAND controller 6a updates the physical address of the entry associated with the upper bits of the logical address received from the address system to the physical address written back to the address conversion table cache 12. Next, the NAND controller 6a invalidates the entry by setting the registration flag of the entry associated with the logical block address of the received logical address to “0” among the entries of the early lookup table 13 (step S212). . Thereafter, the NAND controller 6a returns a completion notification to the system (step S213) and ends the process.

Note that if the valid bit of the searched entry is “0”, the NAND controller 6a does not store data in the physical page indicated by the physical address stored in the searched entry. Therefore, the NAND controller 6a performs steps S206 to S208. Skip processing.

Next, the flow of the alignment process executed by the NAND controller 6a will be described with reference to FIG. FIG. 15 is a flowchart for explaining the flow of the alignment process. For example, the NAND controller 6a executes the alignment process shown in FIG. 15 in response to a predetermined time interval or an execution instruction from the system.

First, the NAND controller 6a searches for an entry associated with the logical block address “0” among the entries in the quick lookup table 13 (step S301). Then, the NAND controller 6a determines whether or not the registration flag of the searched entry is “0” (step S302).

Here, when the registration flag is “0” (Yes at Step S302), the NAND controller 6a executes the alignment process of the subsequent Steps S303 to S307. First, the NAND controller 6a secures a spare physical block for alignment (step S303). Next, the NAND controller 6a issues a read request to the page having the logical block address “0” and the logical page number “0” (step S304). Subsequently, the NAND controller 6a writes the read data to the physical page indicated by the same physical page number as the logical page number “0” among the physical pages of the spare physical block (step S305).

Further, the NAND controller 6a determines whether or not the data has been aligned for all the logical page numbers having the logical block address “0” (step S306). If the NAND controller 6a has not aligned the data for all the logical page numbers having the logical block address “0” (No in step S306), the NAND controller 6a performs other logical page numbers (for example, logical page number “1”). The process of step S304 is performed.

Further, when the data is aligned for all the logical page numbers having the logical block address “0” (Yes at Step S306), the NAND controller 6a updates the early lookup table 13 (Step S307). Specifically, the NAND controller 6a stores the physical block address of the spare physical block in the entry associated with the logical block address “0” among the entries of the fast-drawing table 13, and sets the registration flag to “1”. To do.

Thereafter, the NAND controller 6a determines whether or not the alignment process has been executed for all the logical block addresses (step S308). Then, if the alignment process has not been performed for all logical block addresses (No at Step S308), the NAND controller 6a performs the process at Step S301 for the next logical block address (for example, logical block address “1”). To do. If the registration flag of the searched entry is not “0” (No at Step S302), the NAND controller 6a skips the alignment process and executes the process at Step S308 because the alignment process has already been performed. .

[Effect of NAND controller 6a]
As described above, the NAND controller 6a stores the address conversion table cache 12 in which the physical block address and the physical page number are associated with the logical address including the logical block address and the logical page number. In addition, the NAND controller 6a selects one logical block number, and acquires a physical address associated with the logical address including the selected logical block number from the address conversion table cache 12. Then, the NAND controller 6a converts the physical page data indicated by the acquired physical address into the physical page included in one physical block, and has the same physical page number as the logical page number included in the logical address of each data. Move to the indicated physical page. Thereafter, the NAND controller 6a associates the physical block address of the physical block to which the data has been moved with the selected logical block number and stores them in the early lookup table 13.

Further, when receiving the logical address indicating the logical page in which the data to be read is stored, the NAND controller 6a acquires the physical block address associated with the logical block address included in the logical address from the early lookup table 13. Then, the NAND controller 6a, among the physical pages included in the physical block indicated by the physical block address acquired from the quick lookup table 13, has the physical page number indicated by the same physical page number as the logical page number included in the received logical address. Read data from the page.

For this reason, the NAND controller 6a can reduce the time required for address conversion even when the address conversion table 20 for converting a logical address indicating a logical page storing read target data into a physical address is not held. Can do. As a result, the NAND controller 6a can improve the latency of access to the storage devices 7a to 10a.

In addition, for example, in the technology that holds a part of the address conversion table, the holding ratio becomes relatively small as the size of the address conversion table increases, so the probability that a logical address hits the cache deteriorates, and the address conversion becomes difficult. The time required will increase. Further, as the size of the address conversion table increases, the size of the conversion table tag also increases. Therefore, a technique for preventing an increase in circuit scale by caching a part of the conversion table tag can be considered. However, in such a method, when data is read from or written to the storage device, a plurality of accesses are performed. As a result, latency when accessing the storage device increases.

However, regardless of the size of the address conversion table 20, the NAND controller 6a can always perform address conversion on the logical addresses subjected to the alignment processing. As a result, the NAND controller 6a can improve read performance and write performance for the storage devices 7a to 10a.

In addition, the quick lookup table 13 can be realized with the same number of entries as the number of physical blocks included in the storage devices 7a to 10a. As a result, the size of the quick lookup table 13 is much smaller than when the number of entries equal to the number of physical pages included in the storage devices 7a to 10a is set in the address translation table 20. Therefore, the NAND controller 6a can improve the read performance and the write performance for the storage devices 7a to 10a without increasing the circuit scale.

Also, the NAND controller 6a uses the upper bits of the logical address as the logical block address and the lower bits of the logical address as the logical page number. Also, the NAND controller 6a uses the upper bits of the physical address as the physical block address and the lower bits of the physical address as the physical page number. Therefore, the NAND controller 6a can make any number of logical pages a constituent unit of the early lookup table. The NAND controller 6a can easily perform address conversion without performing complicated processing.

Further, the NAND controller 6a duplicates data stored in a physical block including an unused physical page to another block, and erases data in the physical block including an unused physical page. 19 Since the NAND controller 6a uses the physical block from which the garbage collection control unit 19 has erased data as a spare block, the NAND controller 6a efficiently performs data alignment processing even when the free space of the storage devices 7a to 10a is small. be able to.

The NAND controller 6a described above targets all the entries in the early lookup table 13 when executing the data alignment process. However, the embodiment is not limited to this. For example, the NAND controller 6a may perform alignment control for only some of the logical block addresses among all the logical block addresses in one alignment process.

For example, the NAND controller 6a executes the alignment process for each entry of the early lookup table 13, and stores a last logical block address for which the alignment process has been performed when a predetermined time has elapsed. Then, the NAND controller 6a may restart the alignment process from the logical block address next to the stored logical block address when performing the next alignment process.

Hereinafter, the flow of processing executed by the NAND controller 6a will be described with reference to FIG. FIG. 16 is a flowchart for explaining a first variation of the alignment process. Of the processes shown in FIG. 16, steps S403 to S409 execute the same processes as steps S301 to S307 shown in FIG.

For example, the NAND controller 6a loads the end address, which is the logical block address that was last subjected to the alignment process in the previous alignment process (step S401). Next, the NAND controller 6a sets a value obtained by adding 1 to the loaded end address as the start address of the alignment process (step S402). Then, the NAND controller 6a executes the process of step S403 from the start address.

Further, when executing the process of step S409, the NAND controller 6a determines whether or not a predetermined time has elapsed since the start of the alignment process (step S410). If the predetermined time has elapsed (Yes at Step S410), the NAND controller 6a stores the last logical block address on which the alignment process has been executed as an end address (Step S411), and ends the process. On the other hand, if the predetermined time has not elapsed since the start of the alignment process (No at Step S410), the NAND controller 6a executes the process at Step S403 for the next logical block address.

Also, the NAND controller 6a divides each entry in the quick-draw table 13 into a plurality of groups, and assigns a group number (group number) to each group. The NAND controller 6a may perform the alignment process only for one group in one alignment process.

For example, FIG. 17 is a flowchart for explaining the second variation of the alignment process. Of the processes shown in FIG. 17, steps S503 to S509 are the same as steps S301 to S307 shown in FIG.

For example, the NAND controller 6a loads the group number that was last subjected to the alignment process in the previous alignment process (step S501). Next, the NAND controller 6a sets the group number next to the loaded group number as the target of the alignment process (step S502). Then, the NAND controller 6a executes the process of step S503 for the first entry to which the group number that is the target of the alignment process is assigned.

Further, when executing the process of step S509, the NAND controller 6a determines whether or not the alignment process has been performed on all the entries to which the group number to be subjected to the alignment process is assigned among the entries in the quick-draw table 13. (Step S510). If the NAND controller 6a performs the alignment process for all the entries to which the group number to be the alignment process is assigned (Yes in step S510), the NAND controller 6a stores the group number for which the alignment process has been performed (step S511). The process is terminated. On the other hand, if the NAND controller 6a has not performed the alignment process for all entries to which the group number to be subjected to the alignment process has been assigned (No at step S510), the NAND controller 6a executes the process of step S503 for the next logical block address. To do.

The NAND controller 6a can shorten the processing time required for one alignment process when the alignment process is executed for each part of the logical block address. As a result, the NAND controller 6a can make scheduling of the alignment process flexible.

In addition, the NAND controller 6a counts the frequency of occurrence of read requests or write requests for each logical block address, and executes alignment processing for logical block addresses with a high frequency of read requests and a low frequency of write requests. May be. Hereinafter, the NAND controller 6c that executes the alignment process for a group of logical block addresses that have a high frequency of read requests and a low frequency of write requests will be described.

FIG. 18 is a diagram illustrating a functional configuration of a NAND controller that executes alignment processing according to the frequency of occurrence of read requests and write requests. Of the functional configuration of the NAND controller 6c shown in FIG. 18, the same functional configuration as that of the NAND controller 6a shown in FIG.

For example, the NAND controller 6c includes a data alignment control unit 18a and a request counter 22. The request counter 22 acquires the contents of the read request and the write request received by the requester interface unit 14 via the I / O hub 4. The request counter 22 counts the number of read requests and the number of write requests received by the requester interface unit 14 for each group including a plurality of logical block addresses.

Further, when the request counter 22 receives the notification of execution of the alignment process from the data alignment control unit 18a, the request counter 22 calculates a value obtained by subtracting the number of write requests from the number of read requests counted for each group. Then, the request counter 22 notifies the data alignment control unit 18a of the logical block address included in the group having the largest calculated value. That is, the request counter 22 notifies the data alignment control unit 18a of logical block addresses included in a group having a large number of read requests and a small number of write requests.

The data alignment control unit 18a notifies the request counter 22 of an alignment process execution notification when executing the alignment process in response to a predetermined time interval or an alignment process execution request from the system. When the data alignment control unit 18a receives the logical block address from the request counter 22, the data alignment control unit 18a executes alignment processing on the received logical block address in the same manner as the data alignment control unit 18.

For example, the data alignment control unit 18a and the request counter 22 are electronic circuits. Here, as an example of the electronic circuit, an integrated circuit such as ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array), or CPU (Central Processing Unit) or MPU (Micro Processing Unit) is applied.

Next, the flow of alignment processing executed by the NAND controller 6c will be described with reference to FIG. FIG. 19 is a flowchart for explaining a third variation of the alignment process. Of the processes shown in FIG. 19, steps S603 to S609 are the same as the processes in steps S301 to S307 shown in FIG.

For example, the NAND controller 6c subtracts the number of write requests from the number of read requests for each group (step S601). Next, the NAND controller 6c sets the group with the largest subtraction result value as the target of the current alignment process (step S602). Then, the NAND controller 6c executes the process of step S603 for the logical addresses included in the group subjected to the alignment process. Further, when executing the process of step S609, the NAND controller 6c determines whether or not the alignment process has been executed for all the logical block addresses in the group (step S610).

Then, if the NAND controller 6c has performed the alignment process for all the logical block addresses in the group (Yes at step S610), the process ends. On the other hand, if the NAND controller 6c has not performed the alignment process for all the logical block addresses in the group (No in step S610), the NAND controller 6c executes the process of step S603 for the next logical block address in the group.

[Effect of NAND controller 6c]
As described above, the NAND controller 6c counts the number of read requests and the number of write requests for each logical block address. Then, the NAND controller 6c executes the alignment process for the logical block address having the largest number obtained by subtracting the number of write requests from the number of read requests. For this reason, the NAND controller 6c can execute an effective alignment process.

That is, when logical pages with logical block addresses with a large number of read requests and a small number of write requests are aligned on a physical block, there is little probability of invalidity, and address conversion using the early lookup table 13 is performed. Many are thought to be implemented. For this reason, the NAND controller 6c preferentially aligns the logical block addresses with a large number of read requests and a small number of write requests, so that an efficient alignment process can be executed.

In the first and second embodiments, the logical unit and the physical block are the data units registered in the quick-drawing table 13, but the embodiment is not limited to this. That is, the NAND controllers 6a to 6c may divide the logical address and the physical address in arbitrary data units and register them in the early lookup table 13.

For example, the NAND controllers 6a to 6c may associate the upper i bits of the logical address with the upper i bits of the physical address as the fast lookup table 13. Further, when such division is performed, the conversion table tag 11 and the quick lookup table 13 may be shared.

Hereinafter, a NAND controller 6d in which the conversion table tag 11 and the quick lookup table 13 are made common will be described with reference to FIG. FIG. 20 is a diagram for explaining a functional configuration of a NAND controller in which a conversion table tag and a quick lookup table are shared. Of the functional configuration of the NAND controller 6d shown in FIG. 20, the same functional configuration as that of the NAND controller 6a shown in FIG.

For example, the NAND controller 6d includes a quick lookup table 13a and an address conversion control unit 16a. The early lookup table 13a has a plurality of entries associated with upper i bits of the logical address. In the same manner as the early lookup table 13, the early lookup table 13a stores each entry in association with a registration flag and the higher-order i bits of the physical address. Similarly to the translation table tag 11, the fast lookup table 13 a is a physical address in which an address translation table for converting a logical address including a higher address associated with each entry into a physical address is stored in each entry. Is stored further.

The address translation control unit 16a performs the same processing as the address translation control unit 16. At this time, the address conversion control unit 16 a uses the early lookup table 13 a as the translation table tag 11 and the early lookup table 13. Hereinafter, the flow of address conversion processing executed by the address conversion control unit 16a will be described with reference to FIG.

FIG. 21 is a diagram for explaining the flow of the address conversion process when the conversion table tag and the early lookup table are shared. As shown in FIG. 21, each entry of the early lookup table 13a is associated with upper addresses “0” to “2 ⁱ −1” which are upper i bits of the logical address. In addition, each entry of the fast-drawing table 13a stores “A” to “M” that are higher-order i bits of the physical address. Each entry of the early lookup table 13a stores physical addresses “a” to “m” in which an address conversion table for converting a logical address including a corresponding higher address into a physical address is stored.

For example, when the address translation control unit 16a receives the logical address, as shown in FIG. 21 (a), the entry associated with the higher order address of the received logical address among the entries of the early lookup table 13a. Identify. For example, in the example shown in FIG. 21, the address translation control unit 16a identifies an entry associated with the upper address “1”.

Then, the address conversion control unit 16a executes the following process when the registration flag of the identified entry is “0”. First, the address translation control unit 16a acquires the physical address “b” stored in the identified entry, and as shown in FIG. 21B, the address translation table 20 stored in the physical address “b”. To get a part of. Then, the address translation control unit 16a sets a part of the acquired address translation table 20 as the address translation table cache 12 as shown in (c) of FIG.

Further, as shown in FIG. 21 (d), the address translation control unit 16a identifies an entry associated with the lower address of the received logical address among the entries of the address translation table cache 12. Then, the address translation control unit 16a outputs the physical address “BC” stored in the identified entry to the request arbitration unit 15 as a translated physical address.

The address conversion control section 16a, for example, if the upper address of the logical address received is "2 ⁱ -1", of each entry in the fast lookup table 13a, the upper address "2 ⁱ -1" Identifies the associated entry. Then, since the registration flag of the identified entry is “1”, the address translation control unit 16a acquires the upper i bits “M” of the physical address stored in the identified entry. Then, the address translation control unit 16a outputs, to the request arbitration unit 15, a physical address having the acquired “M” as the upper i bits and the lower address of the received logical address as the lower j bits as the translated physical address. .

For example, the address conversion control unit 16a is an electronic circuit. Here, as an example of the electronic circuit, an integrated circuit such as an ASIC or FPGA, or a CPU or MPU is applied. The fast-drawing table 13a is information stored in a storage device such as a semiconductor memory.

[Effect of NAND controller 6d]
Thus, the NAND controller 6d stores the address conversion table cache 12. The NAND controller 6d has a fast-drawing table 13a having an entry in which the upper bits of the logical address, the registration flag, and the upper bits of the physical address indicating the physical storage area to which data is arranged are associated with each other. In addition, the NAND controller 6d stores, in each entry, a physical address in which a conversion table for converting a logical address including the upper bits of the logical address of the same entry into a physical address is stored in the fast-draw table 13a.

Then, the NAND controller 6d acquires the upper bits from the logical address to be read, and if the registration flag associated with the acquired upper bits is “0”, the physical address associated with the acquired upper bits. Is used to obtain the address conversion table. In addition, when the registration flag associated with the acquired upper bit is “1”, the NAND controller 6d acquires the upper bit of the physical address associated with the acquired upper bit. Then, the NAND controller 6d reads data from the page indicated by the physical address obtained by adding the lower bits of the logical address to be read to the acquired upper bits.

In this way, the NAND controller 6d integrates the conversion table tag 11 and the quick lookup table 13a into one table. As a result, the NAND controller 6d can reduce the latency required for table search and update, and improve the access performance to the storage devices 7a to 10a. Further, since the NAND controller 6d reduces the storage capacity for storing the conversion table tag 11 and the fast-drawing table 13a, the circuit scale can be reduced.

In the first to third embodiments, an example in which the quick-drawing table is installed on the NAND controllers 6a to 6d has been described, but the embodiments are not limited to this. Therefore, in the following fourth embodiment, a NAND controller 6e will be described in which the early lookup table 13a is installed on the storage devices 7a to 10a and a part of the early lookup table 13a is held as the early lookup table cache 13b.

FIG. 22 is a diagram for explaining the functional configuration of the NAND controller that holds a part of the quick lookup table. Of the functional configuration of the NAND controller 6e shown in FIG. 22, the same functional configuration as that of the NAND controller 6a shown in FIG. For example, the NAND controller 6e includes an early lookup table tag 11a, an address translation control unit 16b, and an early lookup table cache 13b. Further, the storage devices 7a to 10a store the quick-drawing table 13a.

The early lookup table tag 11a associates an index that is the upper k bits of the upper address of the logical address with a physical address that stores the early lookup table of each logical address including the upper address including the corresponding index. Remember. The early lookup table cache 13b is a part of the early lookup table 13a stored in the storage devices 7a to 10a.

Hereinafter, the flow of processing executed by the address translation control unit 16b will be described with reference to FIG. FIG. 23 is a diagram for explaining the flow of the address conversion process executed using the early lookup table tag. For example, when the address translation control unit 16b receives the logical address that is the target of the read request, as shown in (f) of FIG. 23, the fast lookup table tag 11a using the index that is the upper k bits of the received logical address. Search for. Then, the address conversion control unit 16b acquires the physical address “z” in which the fast lookup table for performing the fast lookup of the higher address included in the received logical address is stored from the fast lookup table tag 11a.

Next, as shown in (g) of FIG. 23, the address conversion control unit 16b acquires a part of the quick lookup table 13a stored in the page indicated by the acquired physical address “z”. As shown in (h), the fast-drawing table cache 13b is assumed. Next, as shown in (i) of FIG. 23, the address translation control unit 16b selects an entry associated with the upper address of the logical address that is the target of the read request among the entries in the early lookup table cache 13b. Identify.

Here, since the registration flag of the identified entry is “0”, the address translation control unit 16b acquires the physical address “f” stored in the identified entry. Further, the address translation control unit 16b acquires a part of the address translation table 20 stored in the physical address “f” as shown in (j) of FIG. Then, the address conversion control unit 16b sets a part of the acquired address conversion table 20 as the address conversion table cache 12 as shown in (k) of FIG.

Further, as shown in (l) of FIG. 23, the address translation control unit 16b identifies an entry associated with the lower address of the received logical address among the entries of the address translation table cache 12. Then, the address translation control unit 16b outputs the physical address “BC” stored in the identified entry to the request arbitration unit 15 as a translated physical address, as shown in (m) of FIG.

For example, the address conversion control unit 16b is an electronic circuit. Here, as an example of the electronic circuit, an integrated circuit such as an ASIC or FPGA, or a CPU or MPU is applied. The early lookup table tag 11a and the early lookup table cache 13b are information stored in a storage device such as a semiconductor memory.

[Effect of NAND controller 6e]
As described above, the NAND controller 6e includes the early lookup table tag 11a in which an index is associated with a physical address indicating a page storing a fast lookup table for a logical address including an upper address including the index. The NAND controller 6e stores a part of the early lookup table 13a as the early lookup table cache 13b.

Then, the NAND controller 6e acquires the physical address associated with the index of the logical address to be read from the early lookup table tag 11a. Thereafter, the NAND controller 6e uses the acquired physical address to hold a part of the early lookup table 13a as the early lookup table cache 13b. In addition, the NAND controller 6e acquires the upper bits of the physical address associated with the upper bits of the logical address to be read from the held early lookup table cache 13b.

In this way, the NAND controller 6e holds the early lookup table 13a on the storage devices 7a to 10a and holds a part of the early lookup table 13a. Therefore, the NAND controller 6e uses the early lookup table even when the capacity of the early lookup table 13a increases as a result of the increase in the capacity of the storage devices 7a to 10a and the increase in the capacity of the address conversion table. Address translation can be performed.

Also, the size of the quick lookup table 13a can be within, for example, about 1/100 to 1/1000 of the size of the address conversion table 20. As a result, the NAND controller 6e does not significantly reduce the cache hit rate of the early lookup table even when a part of the early lookup table 13a is held as the early lookup table cache 13b. Therefore, the NAND controller 6e can prevent an increase in time required for address conversion.

Although the embodiments of the present invention have been described so far, the embodiments may be implemented in various different forms other than the embodiments described above. Therefore, another embodiment included in the present invention will be described below as a fifth embodiment.

(1) Unit of alignment processing The NAND controller 6a described above performs data alignment processing for each logical block in accordance with the physical blocks of the storage devices 7a to 10a. However, the embodiment is not limited to this. That is, the NAND controller 6a does not need to adjust the size of the logical block to the physical block of the storage devices 7a to 10a, and can execute the data alignment process for the logical block of any size.

For example, the NAND controller 6a may use a continuous logical page smaller than a physical block of about several pages as a unit of alignment processing. The NAND controller 6a can also execute data alignment processing in units of logical blocks each having a size that is as large as a plurality of physical blocks. That is, the NAND controller 6a can divide the logical address into an arbitrary number of bits when dividing the logical address into the logical block address and the logical page address.

(2) Lifetime of Storage Device The NAND controllers 6a to 6e described above execute data write processing accompanying data movement when executing the alignment processing. Here, when considering the lifetime of the storage devices 7a to 10a, it is desirable not to perform excessive alignment in order to reduce the number of write processes. In particular, it is desirable not to perform alignment processing on data that is not actually used by the file system.

Therefore, the NAND controllers 6a to 6e may perform alignment processing in consideration of a data invalidity notification command called Trim. For example, the NAND controllers 6a to 6e may avoid alignment processing for data that is not actually used by excluding pages that are targets of Trim from management targets.

(3) About the early lookup table and the address conversion table When the NAND controller 6a receives the logical address, the NAND controller 6a checks the early lookup table 13, and the registration flag of the entry corresponding to the logical block address included in the logical address is “ In the case of “1”, the address conversion using the early lookup table 13 was performed. In addition, when the registration flag of the corresponding entry is “0”, the NAND controller 6a executes the address conversion process using the address conversion table.

However, the embodiment is not limited to this. For example, the NAND controller 6a executes the address conversion process using the quick lookup table 13 and the address conversion process using the address conversion table in parallel, and when the address conversion is completed in either process, the other You may cancel the process.

(4) Program The various processes described in the above embodiments may be realized by executing a control program prepared in advance by an arithmetic processing unit in the NAND controller. In the following, an example of a computer that executes a control program having the same function as that of the NAND controller 6a will be described with reference to FIG.

FIG. 24 is a diagram illustrating an example of a NAND controller that executes a control program. As illustrated in FIG. 24, the NAND controller 6 f includes a CPU (Central Processing Unit) 30 and a device access control unit 35. The CPU 30 is connected to the memory device 6g.

In the memory device 6g, a conversion table tag 11, an address conversion table cache 12, a quick lookup table 13, and a control program 36 are stored in advance. In addition, the address translation table 20 and the user data 21 are stored in advance in the storage devices 7a to 10a.

Here, when the CPU 30 reads out the control program 36 from the memory device 6g, expands and executes it, the control program 36 functions as follows. That is, the control program 36 functions as an address translation control process 31, a request arbitration process 32, a data alignment control process 33, and a garbage collection control process 34. Here, the address translation control process 31, the request arbitration process 32, and the data alignment control process 33 exhibit the same functions as the address translation control unit 16, the request arbitration unit 15, and the data alignment control unit 18 shown in FIG. Moreover, the garbage collection control process 34 exhibits the same function as the garbage collection control unit 19 shown in FIG.

Note that the control program 36 is not necessarily stored in the memory device 6g from the beginning. For example, each program is stored in a “portable physical medium” such as a flexible disk, so-called FD (Flexible Disk), CD (Compact Disk) -ROM, DVD (Digital Versatile Disk), magneto-optical disk, and IC card.

Then, the NAND controller 6f may solve the

CPUs

3a and 3b to acquire and execute each program from these portable physical media. Further, each program stored in another computer or a server device may be acquired and executed via a public line, the Internet, a LAN, a WAN (Wide Area Network), or the like.

1 Information processing apparatus 2a,

2b Memory

3a, 3b CPU
4 I / O hub 5a, 5b SSD
6a to 6f NAND controller 6g Memory device 7a to 10a, 7b to 10b Storage device 11 Conversion table tag 11a Early lookup table tag 12 Address

translation table cache

13, 13a Early lookup table 13b Early lookup table cache 14 Requester interface unit 15

Request arbitration unit

16, 16a, 16b Address conversion control unit 17 Device

access control unit

18, 18a Data alignment control unit 19 Garbage collection control unit 20 Address conversion table 21 User data 30 CPU
31 Address translation control process 32 Request arbitration process 33 Data alignment control process 34 Garbage collection control process

Claims

A physical block number that physically indicates the block and a logical number that combines a logical block number that logically indicates a block having a plurality of storage areas and a logical page number that logically indicates a storage area included in the block, and the storage A first storage unit that stores a conversion table in which physical numbers that combine physical page numbers that physically indicate areas are associated;
A selection unit for selecting one logical block number;
An identification unit for identifying a physical number associated with a logical number including a logical block number selected by the selection unit from a conversion table stored in the first storage unit;
The data in the storage area indicated by the physical number identified by the identification unit is stored in a storage area indicated by the same physical page number as the logical page number included in the logical number of the data. A moving part to be moved;
A second storage unit that stores a fast-drawing table that associates the physical block number of the block to which the moving unit has moved the data with the logical block number selected by the selection unit;
When a logical number indicating an area in which data to be read is stored is received, a physical block number associated with the logical block number included in the received logical number is acquired from the fast lookup table stored in the second storage unit. An acquisition unit to
A reading unit that reads data stored in an area indicated by the same physical page number as the logical page number included in the received logical number, among the data stored in the block indicated by the physical block number acquired by the acquisition unit; A control device comprising:
The upper bit of the logical address that logically indicates the storage area is the logical block number, the lower bit of the logical address is the logical page number, and the upper bit of the physical address that physically indicates the storage area is the physical block The control apparatus according to claim 1, wherein a number is used, and a lower-order bit of the physical address is used as the physical page number.
It has an erasing unit for erasing data in the block by copying the data stored in the block including the unused storage area to another block,
The control device according to claim 1, wherein the moving unit moves the data to a block from which the erasing unit has erased the data.
For each group including a plurality of logical block numbers, the counter has a counting unit that counts the number of data read requests and the number of data write requests.
The selection unit selects a logical block number included in a group having the largest number obtained by subtracting the number of write requests from the number of read requests counted by the counting unit. The control device described.
The first storage unit stores a part of the conversion table stored in a storage device,
The second storage unit selects the physical block number of the block to which the moving unit has moved the data, a flag indicating whether the moving unit has moved the data to the block, and the selection unit selected Stores a fast lookup table in which a logical block number is associated with a physical number indicating an area in which a conversion table for converting a logical number including the logical block number into a physical number is stored, and the moving unit moves the data Then, a flag indicating that the data has been moved in association with the physical block number of the block to which the data has been moved is stored in the quick lookup table,
If the flag indicating that the data has been moved is associated with the logical block number included in the logical number to be read, the acquisition unit sets the physical block number associated with the logical block number. If the flag indicating that the data has been moved is not associated with the logical block number, the conversion table stored in the storage area indicated by the physical number associated with the logical block number is stored. Storing in the first storage unit;
The reading unit, when a flag indicating that the data has been moved is not associated with the logical block number included in the logical number to be read, the conversion table stored in the first storage unit 3. The control device according to claim 1, wherein a physical number associated with a logical number to be read is acquired using and the data is read from a storage area indicated by the acquired physical number. .
A physical address indicating a storage area in which the early lookup table is stored is associated with an index that is an upper bit of the logical address stored in the early lookup table stored in the storage area indicated by the physical address. A third storage unit;
The second storage unit stores a part of the quick lookup table stored in the storage device,
The acquisition unit acquires the physical address associated with the higher-order bit index of the logical address to be read from the third storage unit, and reads the fast lookup table read from the storage area indicated by the acquired physical address. The second storage unit stores the high-order bits of the physical address associated with the high-order bits of the logical address to be read out from the fast lookup table stored in the second storage unit and stored in the second storage unit. The control device according to claim 2, wherein the control device is obtained from a stored fast-drawing table.
In the computer of the control device that reads data from the storage device,
Select one logical block number that logically indicates a block having a plurality of storage areas,
A logical number obtained by combining a logical block number and a logical page number that logically indicates a storage area included in the block, and a physical block number that physically indicates the block and a physical page number that physically indicates the storage area. Identifying a physical number associated with a logical number including the selected logical block number from a first storage unit storing a conversion table in which the combined physical numbers are associated;
The storage area data indicated by the identified physical number is moved to a storage area included in one block and indicated by the same physical page number as the logical page number included in the logical number of the data,
The physical block number of the block to which the data has been moved and the logical block number selected by the selection unit are associated with each other and stored in the second storage unit,
When a logical number indicating an area in which data to be read is stored is received, a physical block number associated with a logical block number included in the received logical number is acquired from the second storage unit,
Out of the data stored in the block indicated by the acquired physical block number, the process of reading the data stored in the area indicated by the same physical page number as the logical page number included in the received logical number is executed. A characteristic control program.
A control device that reads data from the storage device
Select one logical block number that logically indicates a block having a plurality of storage areas,
A logical number obtained by combining a logical block number and a logical page number that logically indicates a storage area included in the block, and a physical block number that physically indicates the block and a physical page number that physically indicates the storage area. Identifying a physical number associated with a logical number including the selected logical block number from a first storage unit storing a conversion table in which the combined physical numbers are associated;
The storage area data indicated by the identified physical number is moved to a storage area included in one block and indicated by the same physical page number as the logical page number included in the logical number of the data,
The physical block number of the block to which the data has been moved and the logical block number selected by the selection unit are associated with each other and stored in the second storage unit,
When a logical number indicating an area in which data to be read is stored is received, a physical block number associated with a logical block number included in the received logical number is acquired from the second storage unit,
Executing the process of reading the data stored in the area indicated by the same physical page number as the logical page number included in the received logical number among the data stored in the block indicated by the acquired physical block number Characteristic control method.