JP6028866B2 - Information processing apparatus, control circuit, control program, and control method - Google Patents

Description

  The present invention relates to an information processing device, a control circuit, a control program, and a control method.

  2. Description of the Related Art Conventionally, an information processing apparatus that uses a nonvolatile memory that operates faster than a magnetic disk as a storage or memory system is known. As an example of such an information processing apparatus, an information processing apparatus using a NAND flash memory device as a storage device such as a storage is known. In the following description, the NAND flash memory device is described as a NAND device.

  Here, the NAND device writes and reads data in units of pages, which are data storage areas, and erases data in units of blocks including a plurality of pages. In addition, the NAND device cannot overwrite new data on a page in which data is written, and in order to write data, data is written to a page of a block from which data has been erased in advance. In addition, in the NAND device, since an element that holds data deteriorates when data is erased, data cannot be read or written from a page where data is frequently written.

  For this reason, there is a technique for leveling the deterioration of elements using information indicating whether data is written to each page of the NAND device and information indicating the number of times data is written to each page. Are known. For example, the information processing apparatus has a management table including information indicating whether data is written and the number of times data is written for each page of the NAND device. In addition, when writing data to the NAND device, the information processing apparatus refers to the management table, and among the pages where data has not been written, the page with the least number of times data has been written is assigned to all the NAND devices. Search from the page. Then, the information processing apparatus writes data in the retrieved page and updates the management table.

JP 2006-074241 A

  However, the technique for searching for the data write target using the management table described above has a problem that the time required for data writing increases because the page to which data is written is searched from all pages of the NAND device. .

  An object of one aspect is to provide an information processing device, a control circuit, a control program, and a control method that reduce the time required for writing data.

An information processing apparatus according to one embodiment includes a storage device having a plurality of storage areas. In addition, the information processing device includes a storage area included in the storage device, write information indicating whether or not data is written in the storage area, and count information indicating the number of times data is written in the storage area. A storage unit that stores the information in association with each other is provided. Further, the information processing apparatus determines a range for searching for a storage area to which data is written from a plurality of storage areas of the storage device in accordance with a logical address of data to be written to the storage device. The information processing apparatus uses a write information and number information storing unit in association with each storage area decision unit decides to store, among the storage areas included in the determined range, the data write A search is made for a storage area that is not rare and has the smallest number of data writes . Then, the information processing apparatus writes the data in the searched storage area.

  According to one embodiment, the time required for writing data can be reduced.

FIG. 1 is a diagram illustrating the information processing apparatus according to the first embodiment. FIG. 2 is a diagram for explaining an example of a conventional management table. FIG. 3 is a schematic diagram illustrating an example of a functional configuration of the NAND controller according to the first embodiment. FIG. 4 is a diagram illustrating an example of an address table. FIG. 5 is a diagram illustrating an example of the management table. FIG. 6 is a diagram illustrating an example of channel determination processing. FIG. 7 is a diagram for explaining the flow of processing in which a conventional NAND controller writes data. FIG. 8 is a time chart when the conventional NAND controller stores data in the physical page of the same channel. FIG. 9 is a time chart when the conventional NAND controller reads a plurality of data from the same channel. FIG. 10 is a diagram illustrating a process when the NAND controller according to the first embodiment writes data. FIG. 11 is a time chart when the NAND controller according to the first embodiment writes data. FIG. 12 is a time chart when the NAND controller according to the first embodiment reads data. FIG. 13 is a flowchart for explaining the flow of processing executed by the NAND controller according to the first embodiment. FIG. 14 is a diagram illustrating an example of a NAND controller that executes a control program.

  Hereinafter, embodiments of an information processing apparatus, a control circuit, a control program, and a control method according to the present application will be described in detail with reference to the accompanying drawings. The disclosed technology is not limited by the following embodiments. In addition, the embodiments may be combined as appropriate within a consistent range.

  In Example 1 below, an example of an information processing apparatus according to the present application will be described with reference to FIG. FIG. 1 is a diagram illustrating the information processing apparatus according to the first embodiment. In the example shown in FIG. 1, the information processing apparatus 1 includes a plurality of memories 2a and 2b, a plurality of CPUs (Central Processing Units) 3a and 3b, an I / O (Input Output) hub 4, and a plurality of SSDs (Solid State Drives). 5a and 5b. The SSD 5a includes a NAND controller 6a and a plurality of NAND devices 7a to 7h. The SSD 5b includes a NAND controller 6b and a plurality of NAND devices 8a to 8h.

  In the following description, the NAND controller 6b and the plurality of NAND devices 8a to 8h exhibit the same functions as those of the NAND controller 6a and the plurality of NAND devices 7a to 7h, and the description thereof is omitted.

  The memories 2a and 2b are storage devices that store data used by the CPUs 3a and 3b for arithmetic processing. The CPUs 3a and 3b are arithmetic processing devices that perform various arithmetic processes using data stored in the memories 2a and 2b. For example, the CPUs 3a and 3b use NUMA (Non-Uniform Memory Access) technology to acquire data stored in the memories 2a and 2b, and execute arithmetic processing using the acquired data.

  Further, the CPUs 3a and 3b acquire data stored in the respective SSDs 5a and 5b via the I / O hub 4, and execute arithmetic processing using the acquired data. Specifically, the CPU 3a issues a data read request or write request to the SSD 5a, and reads or writes data from each of the NAND devices 7a to 7h. For example, the CPU 3a issues a read request storing a logical address designating data to be read to the SSD 5a. In addition, the CPU 3a issues a write request in which a logical address that specifies a data write destination and data to be written are stored.

  The NAND device 7a is a nonvolatile memory that stores various data. More specifically, the NAND device 7a has a plurality of physical pages, which are data storage areas, and writes data in units of physical pages. The NAND device 7a has a plurality of physical blocks having a plurality of physical pages, and erases data in units of blocks. Here, one physical page has a storage capacity of, for example, 8 kilobytes, and one physical block has, for example, 128 physical pages.

  The NAND controller 6a accesses each of the NAND devices 7a to 7h, and reads and writes data. For example, the NAND controller 6a associates a logical address used when designating a storage area where the data of each CPU 3a, 3b is stored with a physical address indicating a storage area of the NAND devices 7a to 7h where the data is stored. Have an address table.

  When the NAND controller 6a receives the logical address together with the read request, the NAND controller 6a uses the address table to identify the physical address associated with the logical address, and reads data from the storage area indicated by the identified physical address. Thereafter, the NAND controller 6a transmits the read data to the CPU 3a via the I / O hub 4.

  In the following description, in order to facilitate understanding, a logical address that is the start address of each physical page is simply described as a logical address, and a physical address that is the start address of each physical page is simply described as a physical address. In addition, the system executed by the information processing apparatus 1 issues a read request and a write request for a logical address that is a head address of each physical page.

  Here, the NAND device 7a cannot overwrite new data on the page in which the data is written. Further, the deterioration of the elements of the NAND device 7a progresses when data is erased. For this reason, when writing data, the conventional NAND controller searches for the physical page with the smallest number of times data has been written from the NAND devices 7a to 7h. Then, data is written to the retrieved physical page.

  For example, FIG. 2 is a diagram illustrating an example of a conventional management table. FIG. 2 shows an example of the management table stored in the conventional NAND controller. In the example shown in FIG. 2, each entry of the management table is written with the physical addresses of the NAND devices 7a to 7h, the number of times of writing that is the number of times data is written to the physical page indicated by each physical address, and the data. Are stored in association with valid bits indicating whether or not the Here, if the value of the valid bit is “1”, it indicates that the data has been written after being erased. If the value is “0”, the data has been written after the data has been erased. Indicates that it is not included.

  For example, when a conventional NAND controller receives data to be written, it refers to all entries in the management table illustrated in FIG. 2, and among physical pages in which no data is stored, the physical page with the smallest number of data writes Search for. In the example illustrated in FIG. 2, the NAND controller selects the physical address “P04” having the smallest write count value among the physical addresses having the valid bit value “0”. Thereafter, the NAND controller writes data to the physical page indicated by the selected physical address “P04”.

  However, when the NAND controller retrieves a physical page that is a data write destination from all the entries in the management table, the time required to write the data increases, and as a result, the access performance to the NAND devices 7a to 7h deteriorates. . Further, when the storage capacity of the NAND devices 7a to 7h increases, the number of entries in the management table also increases, so that the time required for writing data further increases.

  Therefore, the NAND controller 6a according to the first embodiment executes the following processing. First, when receiving the data to be written, the NAND controller 6a determines a range of physical addresses to search for a data write destination according to the value of the logical address of the received data. Then, the NAND controller 6a searches for a physical page in which no data is written from the physical page indicated by the physical address included in the determined range, and writes the data to the searched physical page.

  For example, the NAND controller 6a divides the physical address of each physical page of the NAND devices 7a to 7h into a predetermined number of groups, and assigns consecutive numbers starting from “0” to each group. Then, the NAND controller 6a calculates a remainder when the logical address of the data to be written is divided by a predetermined number, and sets a group to which the calculated remainder is distributed as a search target. Thereafter, the NAND controller 6a searches for a physical page in which no data is stored from the physical page indicated by the physical address included in the group to be searched, and writes the data to the searched physical page.

  As described above, the NAND controller 6a does not search all the physical pages of the NAND devices 7a to 7h but searches only the physical pages in the range corresponding to the logical address of the data to be written. Therefore, the NAND controller 6a can reduce the time for searching for the write destination page when writing data. The NAND controller 6a manages the number of times data is written to each physical page, and no data is stored in the physical page indicated by the physical address included in the search target range. A physical page having the smallest number of times of “” may be searched.

  Hereinafter, an example of a functional configuration of the NAND controller 6a according to the first embodiment will be described with reference to FIG. FIG. 3 is a schematic diagram illustrating an example of a functional configuration of the NAND controller according to the first embodiment.

  In the example illustrated in FIG. 3, the NAND controller 6a includes an address table storage unit 10, a management table storage unit 11, a CPU interface unit 12, a channel determination unit 13, a management table control unit 14, an address table control unit 15, and a channel switching unit 16. Have The NAND controller 6a includes a plurality of NAND interface units 17a to 17d.

  Also, each of the NAND devices 7a to 7h is connected to any one of channels # 0 to # 3, which is a path for accessing the NAND devices 7a to 7h, in accordance with the physical address range of the physical page of each NAND device 7a to 7h. Sorted. For example, NAND devices 7a and 7e are allocated to channel # 0, NAND devices 7b and 7f are allocated to channel # 1, NAND devices 7c and 7g are allocated to channel # 2, and NAND devices 7d and 7h are To channel # 3.

  The NAND interface units 17a to 17d of the NAND controller 6a are interfaces for accessing NAND devices distributed to different channels. Note that the NAND interface units 17b to 17d perform the same functions as the NAND interface unit 17a, and the following description is omitted.

  In the example shown in FIG. 3, the functional configuration for writing new data is described among the functional configurations of the NAND controller 6a. However, the embodiment is not limited to this. For example, the NAND controller 6a has a wear leveling function that moves data to another physical page according to the time elapsed since the data was written. May be. In addition, for example, the NAND controller 6a has a garbage collection function for generating a spare block by moving only valid data in a physical block to a new physical block and erasing data stored in the source physical block. You may have.

  The address table storage unit 10 stores an address table in which a logical address used when the CPUs 3a and 3b specify data and a physical address indicating a physical page in which the data is stored are associated with each other. Hereinafter, an example of the address table stored in the address table storage unit 10 will be described with reference to FIG.

  FIG. 4 is a diagram illustrating an example of an address table. In the example shown in FIG. 1, the address table 10a has a plurality of entries, and in each entry, a logical address and a physical address indicating a physical page storing data indicated by the logical address are stored in association with each other. Yes. Here, in the example shown in FIG. 4, as the physical address of each physical page, a channel number that identifies the channel to which the NAND device in which the physical page exists is assigned, and a device address that identifies the physical page in the same channel, The physical address that is combined is described.

  For example, in the example illustrated in FIG. 4, the address table 10a indicates that the data indicated by the logical address “L101” is stored in the physical page indicated by the physical address “# 0, P02”. Here, the physical page indicated by the physical address “# 0, P02” is the physical page indicated by the device address “P02” among the physical pages of the NAND devices 7a and 7e included in the channel # 0.

  The address table 10a indicates that the data indicated by the logical address “L102” is stored in the physical page indicated by the physical address “# 1, P05”. The address table 10a indicates that the data indicated by the logical address “L103” is stored in the physical page indicated by the physical address “# 2, P11”.

  When the physical address is a bit string having a predetermined length, the upper bits having a predetermined length may be associated with the channel number, and the remaining bit string may be associated with the device address. In the following description, the NAND controller 6a uses a physical address that combines a channel number and a device address.

  Returning to FIG. 3, the management table storage unit 11 obtains the physical address of each physical page, the number of times of writing indicating the number of times data has been written, and the valid bit indicating whether or not the data has been written after erasing data. The associated management table is stored. Hereinafter, an example of the management table stored in the management table storage unit 11 will be described with reference to FIG.

  FIG. 5 is a diagram illustrating an example of the management table. In the example shown in FIG. 5, the management table 11a has a plurality of entries, and a physical address and management information are stored in association with each entry. Here, in the example shown in FIG. 5, the physical address is a combination of a channel number and a device address, and the management information is a write count and a valid bit. In the example shown in FIG. 5, the number of times of writing for 30 physical pages with channel numbers “# 0” to “# 3” and device addresses “P01” to “P10” is stored in the management table 11a. And a valid bit are stored.

  For example, in the example illustrated in FIG. 5, the management table 11 a stores data “23”, the number of times data is written for the physical page indicated by the channel number “# 0” and the device address “P01”, and data after the data is erased. The fact that it has been written is stored. That is, in the management table 11a, data is written “23” times in the physical page having the device address “P01” among the physical pages of the NAND devices 7a and 7e of the channel # 0, and the data is deleted after the data is erased. Indicates that it has been written.

  Further, for example, in the management table 11a, data is written “24” times for the physical page indicated by the channel number “# 0” and the device address “P02”, and data is written after the data is erased. There is no information stored. That is, in the management table 11a, data is written “24” times in the physical page with the device address “P02” among the physical pages of the NAND devices 7a and 7e of the channel # 0, and the data is deleted after the data is erased. Indicates that it has not been written.

  Returning to FIG. 3, the CPU interface unit 12 is a request interface for receiving requests to the NAND devices 7a to 7h from the CPUs 3a and 3b. For example, the CPU interface unit 12 receives a read request including a logical address from the CPUs 3 a and 3 b via the I / O hub 4. Then, the CPU interface unit 12 extracts the logical address to be read from the read request, and outputs the extracted logical address to the address table control unit 15. Thereafter, when the CPU interface unit 12 receives the data to be read from the channel switching unit 16, the CPU interface unit 12 transmits the data to the CPUs 3a and 3b that are the issuing source of the read request.

  The CPU interface unit 12 receives a write request including data to be written to the NAND devices 7a to 7h and a logical address of data to be written from the CPUs 3a and 3b. In such a case, the CPU interface unit 12 outputs the data to be written to the channel switching unit 16.

  The CPU interface unit 12 extracts the logical address of the data to be written from the write request and outputs the extracted logical address to the channel determination unit 13 and the address table control unit 15. Thereafter, when the CPU interface unit 12 receives a response signal indicating that the writing is completed from the channel switching unit 16, the CPU interface unit 12 transmits a response to the CPUs 3a and 3b that are the write request issuers.

  The channel determination unit 13 determines a range to search for a physical page that is a data write destination according to the logical address of the data to be written to the NAND devices 7a to 7h. The channel determination unit 13 is an example of a determination unit described in the claims. For example, the channel determination unit 13 groups the physical pages of the NAND devices 7a to 7h for each channel, and determines the physical page that is the data write destination according to the remainder value obtained by dividing the logical address by the number of channels. Determine which channels you have. Then, the channel determination unit 13 notifies the channel number of the determined channel to the management table control unit 14, and ends the processing when receiving a response indicating that data has been written from the channel switching unit 16.

  For example, if the remainder when the logical address is divided by the number of channels is “0”, the channel determination unit 13 notifies the management table control unit 14 of the channel number “# 0”. Further, when the remainder when the logical address is divided by the number of channels 4 is “1”, the channel determination unit 13 notifies the management table control unit 14 of the channel number “# 1”. In addition, when the remainder when the logical address is divided by the number of channels 4 is “2”, the channel determination unit 13 notifies the management table control unit 14 of the channel number “# 2”. In addition, when the remainder when the logical address is divided by the number of channels 4 is “3”, the channel determination unit 13 notifies the management table control unit 14 of the channel number “# 3”.

  Note that the channel determination unit 13 may group the physical pages of the NAND devices 7a to 7h into an arbitrary number of groups. For example, the channel determination unit 13 groups the physical pages of the NAND devices 7a to 7h into n groups, and associates values from “0” to “n−1” with each group. Then, the channel determination unit 13 calculates a remainder when the logical address indicating the write target data is divided by n, and searches the physical page that is the data write destination for the group associated with the calculated remainder. It may be a target.

  For example, when the channel determination unit 13 receives a logical address from the CPU interface unit 12, the channel determination unit 13 determines a channel having a physical page to which data is written according to the value of the lower 2 bits of the received logical address. Also good. For example, when the lower two bits of the referenced logical address are “00”, the channel determination unit 13 notifies the management table control unit 14 of the channel number “# 0”.

  In addition, the channel determination unit 13 notifies the management table control unit 14 of the channel number “# 1” when the lower 2 bits of the referenced logical address is “01”. In addition, when the lower 2 bits of the referenced logical address is “10”, the channel determination unit 13 notifies the management table control unit 14 of the channel number “# 2”. If the lower 2 bits of the referenced logical address is “11”, the channel determination unit 13 notifies the management table control unit 14 of the channel number “# 3”.

  The management table control unit 14 searches for a physical page as a data write destination from physical pages included in a range determined according to the logical address of the data to be written, among the physical pages of the NAND devices 7a to 7h. To do. The management table control unit 14 is an example of a search unit described in the claims. Specifically, the management table control unit 14 selects a physical page in which data has not been written and the number of times of data writing is smallest from the physical page in the channel indicated by the channel number received from the channel determination unit 13. Search for.

  For example, when the management table control unit 14 receives the channel number “# 1” from the channel determination unit 13, the management table control unit 14 refers to the management table 11 a stored in the management table storage unit 11 and the physical address whose channel number is “# 1”. Identify the range. Then, the management table control unit 14 searches the physical address in the identified range for the physical address having the associated valid bit “0” and the smallest number of data writes. As a result, for example, the management table control unit 14 identifies the physical address “# 1, P02”.

  Then, the management table control unit 14 outputs the identified physical address “# 1, P02” to the channel switching unit 16 and the address table control unit 15. Thereafter, when receiving a response indicating that data has been written from the channel switching unit 16, the management table control unit 14 adds 1 to the number of times of writing associated with the physical address output to the channel switching unit 16, and The bit is updated to “1”.

  The management table control unit 14 may have a function of updating the management table 11a in accordance with various functions that the NAND controller 6a has. For example, when the NAND controller 6a exhibits the wear leveling function or the garbage collection function, the management table control unit 14 adds 1 to the number of writes associated with the physical address to which the data is to be moved, and sets the valid bit. It may be updated to “1”.

  The address table control unit 15 performs conversion between a logical address and a physical address. For example, when receiving the logical address to be read from the CPU interface unit 12, the address table control unit 15 refers to the address table 10a and acquires a physical address associated with the received logical address. Then, the address table control unit 15 outputs the acquired physical address to the channel switching unit 16.

  When the address table control unit 15 receives the logical address of the data to be written from the CPU interface unit 12, the address table control unit 15 specifies the entry storing the received logical address from the address table 10a. The address table control unit 15 receives a physical address from the management table control unit 14. When the address table control unit 15 receives a response indicating that data has been written from the channel switching unit 16, the address table control unit 15 updates the physical address stored in the identified entry to the physical address received from the management table control unit 14. To do.

  Similar to the management table control unit 14, the address table control unit 15 may update the address table 10a when the NAND controller 6a exhibits a wear leveling function or a garbage collection function. For example, the address table control unit 15 may update the physical address associated with the logical address of the data to be moved to the physical address to which the data is to be moved.

  The channel switching unit 16 writes data to the physical page searched by the management table control unit 14. Hereinafter, processing executed by the channel switching unit 16 when reading data and processing executed by the channel switching unit 16 when writing data will be described.

  First, a process executed by the channel switching unit 16 when reading data will be described. For example, when receiving a physical address from the address table control unit 15, the channel switching unit 16 extracts a channel number and a device address from the received physical address. Then, the channel switching unit 16 outputs the extracted device address and the data read request to the NAND interface unit corresponding to the extracted channel number.

  As a result, the channel switching unit 16 receives the data to be read from the NAND interface unit that has output the data read request. In such a case, the channel switching unit 16 outputs the received data to the CPU interface unit 12. For example, the channel switching unit 16 receives the physical address “# 0, P01” and the data read request from the address table control unit 15. In such a case, the channel switching unit 16 outputs a device address “P01” and a data read request to the NAND interface unit 17a that accesses the NAND devices 7a and 7e of the channel # 0.

  As a result, the channel switching unit 16 receives data stored in the physical page indicated by the device address “P01” among the physical pages of the NAND devices 7a and 7e of the channel # 0. Then, the channel switching unit 16 outputs the received data to the CPU interface unit 12.

  Next, processing executed by the channel switching unit 16 when writing data will be described. For example, the channel switching unit 16 receives a physical address from the management table control unit 14 and receives data to be written from the CPU interface unit 12. Then, the channel switching unit 16 extracts the channel number and device address from the received physical address, and outputs the extracted device address, data, and data write request to the NAND interface unit corresponding to the extracted channel number.

  As a result, the channel switching unit 16 receives a response indicating that data has been written from the NAND interface unit that has output the data write request. Thereafter, the channel switching unit 16 outputs a response indicating that data has been written to the CPU interface unit 12, the channel determination unit 13, the management table control unit 14, and the address table control unit 15.

  For example, the channel switching unit 16 receives the physical address “# 2, P05” from the management table control unit 14 and receives data to be written from the CPU interface unit 12. In such a case, the channel switching unit 16 outputs the device address “P05”, the write target data, and the data write request to the NAND interface unit 17c that accesses the NAND devices 7c and 7g of the channel # 2. . When the channel switching unit 16 receives the response from the NAND interface unit 17c, the channel switching unit 16 writes data to the CPU interface unit 12, the channel determination unit 13, the management table control unit 14, and the address table control unit 15. Output a response.

  The NAND interface unit 17a is an interface for reading data and writing data from the NAND devices 7a and 7e of the channel # 0. The NAND interface units 17a to 17d are examples of the writing unit and the input / output unit described in the claims. For example, when receiving the device address “P01” and the data read request, the NAND interface unit 17a reads data from the physical page indicated by the device address “P01” among the physical pages included in the NAND devices 7a and 7e. Then, the NAND interface unit 17a outputs the read data to the channel switching unit 16.

  The NAND interface unit 17a receives the device address “P05”, the data to be written, and the data write request. In such a case, the received data is written to the physical page indicated by the device address “P05” among the physical pages of the NAND devices 7a and 7e. Then, the NAND interface unit 17a outputs a response indicating that the data has been written to the channel switching unit 16.

  The NAND interface unit 17b is an interface for reading and writing data from the NAND devices 7b and 7f of the channel # 1. The NAND interface unit 17b is an interface for reading and writing data from the NAND devices 7c and 7g of the channel # 2.

  The NAND interface unit 17c is an interface for reading and writing data from the NAND devices 7c and 7g of the channel # 3. The NAND interface unit 17d is an interface for reading and writing data from the NAND devices 7d and 7h of the channel # 4.

  The CPU interface unit 12, the channel determination unit 13, the management table control unit 14, the address table control unit 15, and the channel switching unit 16 can process data read requests issued in succession in parallel. For example, when the CPU interface unit 12 continuously receives write requests, the CPU interface unit 12 outputs data relating to the previously received write request to the channel switching unit 16 and outputs a logical address to the channel determining unit 13. Then, before receiving the response from the channel switching unit 16, the CPU interface unit 12 outputs the data related to the received write request to the channel switching unit 16 and outputs the logical address to the channel determination unit 13.

  For example, when the physical address “# 1, P01” is received from the address table control unit 15, the channel switching unit 16 outputs a device address “P01” and a data read request to the NAND interface unit 17a. Subsequently, the channel switching unit 16 receives the physical address “# 2, P05” from the address table control unit 15.

  In such a case, the channel switching unit 16 outputs the device address “P05” and the data read request to the NAND interface unit 17b before receiving the data of the device address “P01” from the NAND interface unit 17a. As a result, the NAND controller 6a can process a plurality of data read requests issued in succession in parallel.

  For example, the CPU interface unit 12, the channel determination unit 13, the management table control unit 14, the address table control unit 15, the channel switching unit 16, and the NAND interface units 17a to 17d are electronic circuits. Here, as an example of the electronic circuit, an integrated circuit such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA), a central processing unit (CPU), a micro processing unit (MPU), or the like is applied.

  The address table storage unit 10 and the management table storage unit 11 are storage devices such as a semiconductor memory element such as a RAM (Random Access Memory) and a flash memory.

  Next, the flow of processing for specifying a channel for searching for a physical page to which data is to be written will be described with reference to FIG. FIG. 6 is a diagram illustrating an example of channel determination processing. For example, when receiving the logical address from the CPU interface unit 12, the NAND controller 6a calculates a remainder when the logical address is divided by the number of channels 4 as shown in FIG.

  Then, as shown in FIG. 6B, the NAND controller 6a refers to the management table 11a, and data is not written from the physical page of the channel corresponding to the calculated remainder value, and Search for the physical page with the least number of data writes. For example, when the calculated remainder value is “1”, the NAND controller 6a writes data from the physical page whose channel number is “# 1” and whose device addresses are “P01” to “P10”. Search for the previous physical page.

  As a result, for example, as illustrated in (C) of FIG. 6, the NAND controller 6a specifies a physical page having a channel number “# 1” and a device address “P02” as a data write destination. Then, as shown in FIG. 6D, the NAND controller 6a writes data via the NAND interface unit 17b that accesses the NAND devices 7b and 7f whose channel number is “# 1”.

  In this manner, the NAND controller 6a determines the search range of the physical page that is the data write destination according to the logical address of the data, and searches the physical page that is the left of the data write from the determined range. The time required for writing data can be reduced. The NAND controller 6a groups the physical pages included in the NAND devices 7a to 7h for each channel, and associates each group with a channel number starting from 0. Then, the NAND controller 6a sets a search range to a group in which the same channel number is associated with the remainder value obtained by dividing the logical address by the number of channels.

  For this reason, the NAND controller 6a stores, for example, four pieces of data to which consecutive logical addresses are assigned in physical pages having different channel numbers, so that writing and reading of each piece of data can be executed in parallel. As a result, the NAND controller 6a can shorten the time required for data writing and reading, and can improve the access performance to the NAND devices 7a to 7h.

  Hereinafter, the effect that the NAND controller 6a can improve the access performance to the NAND devices 7a to 7h will be described in detail with reference to the drawings. First, the time required for the conventional NAND controller to write data of successive logical addresses to the NAND devices 7a to 7h will be described with reference to FIGS. In the following description, a conventional NAND controller is referred to as a NAND controller 50.

  FIG. 7 is a diagram for explaining the flow of processing in which a conventional NAND controller writes data. For example, as shown in FIG. 7A, the NAND controller 50 receives a data write request from the CPU via an I / O hub or the like. Then, as shown in FIG. 7B, the NAND controller 50 uses the management table to search for a physical page as a data write destination. For example, the NAND controller 50 searches the physical pages of the NAND devices 7a to 7h for a physical page in which data is not stored and the number of times data is written is smallest.

  Then, as shown in FIG. 7C, the NAND controller 50 switches the channel from which the channel switching unit outputs data according to the channel number of the physical address of the searched physical page. Further, as shown in FIG. 7D, the NAND controller 50 outputs the data to be written to the channel switching unit and stores the data in the retrieved physical page. For example, the NAND controller 50 stores data in the physical pages of the NAND devices 7a and 7e of the channel # 0 as shown in (e) of FIG.

  The NAND controller 50 stores the retrieved physical page and the logical address of the data in the address table, as shown in (f) of FIG. When the data writing is completed, the NAND controller 50 updates the management table as shown in (g) of FIG. 7, and the CPU that is the issuing source of the write request as shown in (h) of FIG. Output a response to

  Here, the NAND controller 50 may store a plurality of data indicated by successive logical addresses in a physical page of the same channel. For example, when data having a lower access frequency than other data is stored in a physical block with channel # 0, the NAND controller 50 transfers the data to another physical block by wear leveling processing or garbage collection processing after a predetermined time has elapsed. Move. As a result, the channel # 0 includes a spare block in which the number of times of data writing to each physical page is smaller than that of other physical pages and data is not written.

  In such a case, when receiving a plurality of data write requests, the NAND controller 50 selects each physical page included in the spare block of channel # 0 as a write destination of each data. As a result, since the NAND controller 50 sequentially writes a plurality of data to the NAND devices 7a and 7e using the same NAND interface, the data writing process cannot be performed in parallel.

  For example, FIG. 8 is a time chart when a conventional NAND controller stores data in a physical page of the same channel. In FIG. 8, when the NAND controller 50 receives the write requests A to E and the data A to E to be written, the time when the data A to E is written to the channel # 0. The chart is described. Note that data A to E are given consecutive logical addresses.

  For example, the NAND controller 50 sequentially receives write requests A to E and write data A to E from the CPU. Then, the NAND controller 50 executes the write request A and stores data A in the physical page of channel # 0. Further, when the writing of the data A is completed, the NAND controller 50 executes the write request B and stores the data B in the physical page of the channel # 0. Thereafter, the NAND controller 50 sequentially executes the write requests C to E, and sequentially stores the data C to E in the physical page of the channel # 0. Thus, since the NAND controller 50 stores the continuously received data A to E in the physical page in the same channel # 0, the write requests A to E cannot be executed in parallel. Data writing performance for the NAND devices 7a to 7h is deteriorated.

  In addition, data at successive logical addresses is often read out simultaneously. However, the NAND controller 50 cannot execute read requests in parallel when data of consecutive logical addresses are stored in physical pages in the same channel, and deteriorates the data read performance for the NAND devices 7a to 7h. .

  For example, FIG. 9 is a time chart when a conventional NAND controller reads a plurality of data from the same channel. FIG. 9 shows a time chart of a read process that is executed when the NAND controller 50 continuously receives a plurality of data read requests A to E from the channel # 0. Note that the data A to E to be read are given consecutive logical addresses as in FIG.

  For example, the NAND controller 50 continuously receives read requests A to E from the CPU. Then, the NAND controller 50 executes a read request A, reads data A from the physical page of channel # 0, and transmits it to the CPU. Further, after transmitting the data A, the NAND controller 50 executes the read request B, reads the data B from the physical page of the channel # 0, and transmits it to the CPU. Thereafter, the NAND controller 50 sequentially executes the read requests C to E, and sequentially reads and transmits the data C to E. As described above, when the data indicated by the continuous logical addresses is stored in the physical page in the same channel, the NAND controller 50 cannot execute the read request in parallel, and has the data read performance for the NAND devices 7a to 7h. It gets worse.

  On the other hand, the NAND controller 6a according to the first embodiment determines a channel to which data is written according to the remainder when the logical address is divided by the number of channels, and stores the data in the physical page in the determined channel. . As a result, the NAND controller 6a stores each data in a physical page of a different channel when writing data of successive logical addresses to the NAND devices 7a to 7h. Therefore, the NAND controller 6a can execute processing in parallel when writing and reading data of successive logical addresses, so that data write performance and data read performance for the NAND devices 7a to 7h are possible. Can be improved.

  For example, FIG. 10 is a schematic diagram illustrating a process when the NAND controller according to the first embodiment writes data. For example, the NAND controller 6a receives a data write request as shown in (E) of FIG. 10, and receives data to be written as shown in (F) of FIG. Then, the NAND controller 6a uses the channel determination unit 13 to determine a channel corresponding to the logical address of the data, as shown in FIG. Specifically, the NAND controller 6a determines a channel to which data is to be written according to a remainder value obtained by dividing the logical address by the number of channels.

  Then, as shown in FIG. 10H, the NAND controller 6a refers to the management table 11a and searches the physical page that is the data write destination from the physical page of the determined channel. Then, the NAND controller 6a switches the channel from which the channel switching unit 16 outputs data, as indicated by (I) in FIG. Thereafter, as shown in FIG. 10J, the NAND controller 6a outputs data to be written to the NAND interface of the determined channel.

  Further, as shown in (K) in FIG. 10 and (L) in FIG. 10, the NAND controller 6a associates the logical address of the data to be written with the physical address of the physical page in which the data is written. Store in the address table 10a. Further, when the data writing is completed, the NAND controller 6a updates the management table 11a as shown in (M) in FIG. 10, and outputs a response as shown in (N) in FIG.

  As a result, the NAND controller 6a, for example, writes data of successive logical addresses on physical pages of different channels, so that write requests can be executed in parallel. For example, FIG. 11 is a time chart when the NAND controller according to the first embodiment writes data. FIG. 11 shows a time chart of processing executed when the NAND controller 6a continuously receives write requests A to E and data A to E. Further, it is assumed that the data A to E are given continuous logical addresses.

  For example, the NAND controller 6a sequentially receives write requests A to E and write data A to E from the CPU 3a. Then, the NAND controller 6a executes the write request A, and determines the channel to which the data A is written from the logical address of the data A as the channel # 0. Then, the NAND controller 6a stores the data A in the physical page of channel # 0.

  On the other hand, the NAND controller 6a executes the write request B before the writing of the data A is completed, and determines the channel to which the data B is written from the logical address of the data B as the channel # 1. Then, the NAND controller 6a stores data B in the physical page of channel # 1. Thereafter, the NAND controller 6a executes each of the write requests C to E, and determines channels # 2, # 3, and # 1 as write destinations of the data C to E, respectively. Then, the NAND controller 6a writes the data C to E to the physical pages of channel # 2, channel # 3, and channel # 1, respectively.

  As a result, as shown in FIG. 11, the NAND controller 6a executes the write requests A to D in parallel, and executes the write request E after the write request A ends. For this reason, the NAND controller 6a can improve the writing performance with respect to the NAND devices 7a to 7h as a result of shortening the time for writing data to the NAND devices 7a to 7h.

  Further, since the NAND controller 6a writes the data of consecutive logical addresses to different channels, the processing can be executed in parallel when reading the data of consecutive logical addresses. For example, FIG. 12 is a time chart when the NAND controller according to the first embodiment reads data. FIG. 12 shows a time chart of processing executed when the NAND controller 6a continuously receives the read requests A to E.

  For example, the NAND controller 6a continuously receives read requests A to E from the CPU 3a. Then, the NAND controller 6a executes a read request A, reads data A from the physical page of channel # 0, and transmits it to the CPU 3a. Further, since the data B is written in a physical page of a channel different from that of the data A, the NAND controller 6a executes the read request B in parallel with the reading of the data A, and transfers the data B to the physical of the channel # 1. Read from the page and send to CPU 3a.

  The NAND controller 6a executes the read requests C to E in parallel, reads the data C to E from the channel # 2, the channel # 3, and the channel # 1 in parallel, and reads the read data C to E, respectively. It transmits to CPU3a. As a result, as shown in FIG. 12, the NAND controller 6a reads data A to D in parallel from different channels, and reads data E after reading data A. As a result, the NAND controller 6a can improve the read performance for the NAND devices 7a to 7h as a result of shortening the time for reading the data of the continuous logical addresses from the NAND devices 7a to 7h.

  Next, the flow of processing executed by the NAND controller 6a will be described with reference to FIG. FIG. 13 is a flowchart for explaining the flow of processing executed by the NAND controller according to the first embodiment. For example, the NAND controller 6a receives a write command from the CPU (step S101). Then, the NAND controller 6a extracts a logical address from the write command (step S102), and determines a channel number from the extracted logical address (step S103). That is, the NAND controller 6a determines the search range of the physical page that is the data write destination from the logical address.

  Subsequently, the NAND controller 6a refers to the management table 11a and selects the device address of the physical page to be written from the device address of the determined channel number (step S104). Then, the NAND controller 6a writes data to the physical page indicated by the selected device address and channel number (step S105). Subsequently, the NAND controller 6a updates the management table 11a (step S106), updates the address table 10a (step S107), and ends the process.

[Effect of NAND controller 6a]
As described above, the NAND controller 6a searches for the physical page that is the data write destination among the physical pages of the NAND devices 7a to 7h according to the logical addresses of the data to be written to the NAND devices 7a to 7h. To decide. Then, the NAND controller 6a searches for a physical page in which no data is written from the determined range of physical pages, and writes the data to the searched physical page. For this reason, the NAND controller 6a can reduce the time required for writing data as a result of reducing the time required to search for a physical page as a data write destination.

  The NAND controller 6a has a management table 11a in which physical addresses of physical pages, valid bits, and data write counts are stored in association with each other. Then, the NAND controller 6a uses the management table 11a to search a physical page in which the number of times data has been written is the smallest among the physical pages in which no data has been written, from the determined range of physical pages. Thereafter, the NAND controller 6a writes data to the searched physical page. For this reason, the NAND controller 6a equalizes the number of times data is written to each physical page, so that the lifetime of the NAND devices 7a to 7h can be utilized to the maximum.

  The NAND controller 6a includes a plurality of NAND interface units 17a to 17d that access physical pages of different channels among the physical pages of the NAND devices 7a to 7h. Further, the NAND controller 6a determines a NAND interface unit used for data writing according to the logical address of the data to be written. That is, the NAND controller 6a determines a channel for writing data according to the logical address of the data. Then, the NAND controller 6a searches the physical page that is the data write destination from the physical pages of the determined channel.

  For this reason, when the NAND controller 6a receives a plurality of write requests successively, the NAND controller 6a writes data to physical pages of different channels. As a result, the NAND controller 6a can improve the write performance of the NAND devices 7a to 7h as a result of executing a plurality of write requests in parallel.

  The NAND controller 6a determines a NAND interface unit to which data is written according to a remainder value obtained by dividing the logical address of the data by the number of the NAND interface units 17a to 17d. That is, the NAND controller 6a determines the channel of the physical page to which data is written according to the remainder value obtained by dividing by the number of channels.

  For this reason, the NAND controller 6a writes data of successive logical addresses to physical pages of different channels. As a result of executing write requests in parallel, the write performance for the NAND devices 7a to 7h can be improved. Further, since the NAND controller 6a writes the data of consecutive logical addresses to the physical pages of different channels, it can execute the read request of the consecutive logical addresses in parallel. As a result, the NAND controller 6a can improve the reading performance for the NAND devices 7a to 7h.

  The NAND controller 6a determines NAND interface units 17a to 17d used for data writing according to the value of the lower bit of the logical address. That is, the NAND controller 6a determines a channel having a physical page to which data is written according to the value of the lower bit of the logical address.

  Therefore, the NAND controller 6a can determine a channel having a physical page as a data write destination with a simple circuit configuration without having a circuit for performing complicated processing. As a result, the NAND controller 6a can shorten the time for determining a channel having a physical page to which data is written. The NAND controller 6a can reduce the circuit scale.

  Although the embodiments of the present invention have been described so far, the embodiments may be implemented in various different forms other than the embodiments described above. Therefore, another embodiment included in the present invention will be described below as a second embodiment.

(1) Range to be searched The NAND controller 6a described above determines a channel having a physical page to which data is written according to a remainder value obtained by dividing the logical address of data by the number of channels. However, the embodiment is not limited to this. That is, the NAND controller 6a groups the physical pages of the NAND devices 7a to 7h by an arbitrary number, and the physical page that is the data write destination according to the remainder value obtained by dividing the logical address of the data by the number of groups. The group to search for may be determined.

  Further, the NAND controller 6a may not include consecutive physical pages in the same group. For example, if the logical address of data is an odd number, the NAND controller 6a may search for a physical page that is a data write destination from the physical page indicated by the odd number of physical addresses. In addition, when the logical address of data is an even number, the NAND controller 6a may search for a physical page that is a data write destination from the physical page indicated by the even number of physical addresses.

(2) Functional configuration of NAND controller 6a The above-described functional configuration of the NAND controller 6a is merely an example, and any configuration can be adopted as long as the NAND controller 6a can perform the same processing. For example, the NAND controller 6a has a table control unit that combines the address table storage unit 10 and the management table storage unit 11 into a single storage unit and functions as the management table control unit 14 and the address table control unit 15. Also good.

  In the example described above, an example in which the NAND controller 6a searches for a physical page to which data is written from the physical pages of the NAND devices 7a to 7h has been described. However, the embodiment is not limited to this. That is, the NAND controller 6a may operate as a storage medium to which any technique is applied, for example, a memory controller such as a memory, as long as data is written.

(3) Program The functions exhibited by the NAND controller 6a described in the above embodiments may be realized by executing a control program prepared in advance by an arithmetic processing unit in the NAND controller. In the following, an example of a computer that executes a control program having the same function as that of the NAND controller 6a will be described with reference to FIG.

  FIG. 14 is a diagram illustrating an example of a NAND controller that executes a control program. As illustrated in FIG. 14, the NAND controller 6c includes a CPU 40 and NAND interface units 17a to 17d. The CPU 40 is connected to the memory device 11b. Note that the memory device 11b may be a memory built in the NAND controller 6c.

  The memory device 11b stores an address table 10a and a management table 11a in advance. Here, the control program 30 functions as follows when the CPU 40 reads out, expands and executes the control program 30. That is, the control program 30 causes the CPU 40 to operate as the CPU interface unit 31, the table control unit 32, the channel determination unit 33, and the channel switching unit 34. Here, the CPU interface unit 31, the channel determination unit 33, and the channel switching unit 34 illustrated in FIG. 14 cause the CPU 40 to perform the same functions as the CPU interface unit 12, the channel determination unit 13, and the channel switching unit 16 illustrated in FIG. . Further, the table control unit 32 illustrated in FIG. 14 causes the CPU 40 to perform the same functions as those of the management table control unit 14 and the address table control unit 15 illustrated in FIG.

  Note that the NAND controller 6c may execute the control program 30 using an arithmetic device such as an MPU or FPGA instead of the CPU. Further, the control program 30 may be stored in, for example, the memory device 11b and the NAND devices 7a to 7h, or may be executed by the CPU 40 by other methods. For example, each program is stored in a “portable physical medium” such as a flexible disk, so-called FD (Flexible Disk), CD (Compact Disk) -ROM, DVD (Digital Versatile Disk), magneto-optical disk, or IC card.

  Then, the NAND controller 6c may acquire and execute each program from these portable physical media via the CPUs 3a and 3b. Further, each program stored in another computer or a server device may be acquired and executed via a public line, the Internet, a LAN, a WAN (Wide Area Network), or the like.

1 Information processing apparatus 2a, 2b Memory 3a, 3b, 40 CPU
4 I / O hub 5a, 5b SSD
6a to 6c NAND controllers 7a to 7h, 8a to 8h NAND devices 10 Address table storage unit 11 Management table storage unit 12 CPU interface unit 13 Channel determination unit 14 Management table control unit 15 Address table control unit 16 Channel switching unit 17a to 17d NAND Interface part

Claims (7)

A storage device having a plurality of storage areas;
A storage area of the storage device, write information indicating whether or not data is written to the storage area, and number of times information indicating the number of times data is written to the storage area are stored in association with each other. A storage unit to
A determination unit that determines a range for searching for a storage area to which the data is written from a plurality of storage areas of the storage device according to a logical address of data to be written to the storage device;
Data is written out of the storage areas included in the range determined by the determination unit using the write information and the number of times information stored in the storage unit in association with each storage area determined by the determination unit. A search unit that searches for a storage area that has the least number of times data is written, and
An information processing apparatus comprising: a writing unit that writes the data into a storage area searched by the search unit. Among the plurality of storage areas of the storage device, each having a plurality of input / output units that access storage areas of different ranges,
The determining unit determines an input / output unit used for writing the data according to a value of a logical address of data to be written to the storage area,
The information processing apparatus according to claim 1, wherein the search unit searches for a storage area to which the data is written from a storage area accessed by the input / output unit determined by the determination unit. The determining unit, according to the logical address of the data to be written in the storage area to the remainder obtained by dividing the number of the input-output unit, according to claim 2, characterized in that determining the output unit to be used for writing the data The information processing apparatus described in 1. The information processing apparatus according to claim 2 , wherein the determination unit determines an input / output unit used for writing the data according to a value of a lower bit of a logical address of data to be written to the storage area. . A determination unit that determines a range for searching for a storage area to which the data is written, in accordance with a logical address of data to be written to a storage device having a plurality of storage areas;
A storage area of the storage device, write information indicating whether or not data is written to the storage area, and number of times information indicating the number of times data is written to the storage area are stored in association with each other. The storage unit included in the range determined by the determination unit using the write information and the number of times information stored in the storage unit in association with each storage region determined by the determination unit . Among them, a search unit that searches for a storage area where data is not written and the number of times data is written is the smallest ,
And a writing unit for writing the data into the storage area searched by the search unit. On the computer,
In accordance with a logical address of data to be written to a storage device having a plurality of storage areas, a range for searching the storage area to which the data is written is determined from the plurality of storage areas of the storage device.
A storage area of the storage device, write information indicating whether or not data is written to the storage area, and number of times information indicating the number of times data is written to the storage area are stored in association with each other. refers to the storage unit that, using a write information and count information the storage unit in association with each memory area with the determined, among the storage region included in a range in which the determined, data write A control program that searches for a storage area that is not rarely written and has the smallest number of times data is written, and executes a process of writing the data to the searched storage area. Information processing device
In accordance with a logical address of data to be written to a storage device having a plurality of storage areas, a range for searching the storage area to which the data is written is determined from the plurality of storage areas of the storage device.
A storage area of the storage device, write information indicating whether or not data is written to the storage area, and number of times information indicating the number of times data is written to the storage area are stored in association with each other. refers to the storage unit that, using a write information and count information the storage unit in association with each memory area with the determined, among the storage region included in a range in which the determined, data write A control method comprising: searching a storage area that is not rarely written and having the smallest number of times data has been written, and writing the data into the searched storage area.

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