JP2007164318A - Storage system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten a processing time accompanying the the change of the assignment of a logical address to a physical block to be performed for the leveling of the number of times of rewriting and for facilitating countermeasures to disturbance. <P>SOLUTION: A non-volatile memory uses a block region (BLK) as the group of non-volatile memory cells as an initialization unit. A control circuit performs the assignment of one vacant block (BLK-V) and the assignment of a logical address to the residual block region by a super block (SB) unit as the group of the block regions. A latest address conversion table showing the assignment is stored in the block region to which writing has been finally operated among the super blocks, and the location of an address conversion table held by each super block is held in the block region (BLK-C) for management. The physical address corresponding to the access request is acquired by using the address conversion table on the super block to which the logical address relating to the access request has been assigned. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a non-volatile storage device used for a non-volatile file memory or the like, for example, a technique effective when applied to a flash memory card or a hard disk compatible flash disk.

  In rewriting of an electrically rewritable nonvolatile memory such as a flash memory, an electrical stress is applied to the memory cell, and the characteristics of the memory cell deteriorate as the number of rewrites increases. When rewriting concentrates on a part of physical blocks which are simply rewritten or erased in the file memory, the characteristic deterioration becomes significant only for the part of physical blocks. Therefore, by appropriately changing the correspondence between the logical address and the physical address, it is possible to alleviate the concentration of such characteristic deterioration on the local physical address. On the other hand, even in a physical block that is not subject to rewriting or erasing, if the word line or bit line is the same as the memory cell transistor of the physical block that is subject to rewriting, the so-called word line disturb or bit Under the influence of line disturbance, the threshold voltage of the memory cell may change cumulatively, and the stored information may change undesirably (data corruption). In order to deal with the data corruption caused by the disturbance, as described in Patent Documents 1 and 2, logical address assignment may be exchanged between a physical block with a relatively small number of rewrites and another physical block.

JP 2004-310650 A US Pat. No. 5,568,439

  The present inventor has studied the leveling of the number of rewrites and countermeasures against the disturbance by counting the number of times of rewriting (erasing number) of the physical block and replacing the block with a larger number of rewrites and the block with a smaller number of rewrites. According to this, when the number of physical block rewrites has become a fixed value, when replacing with a block with a small number of rewrites, it takes a relatively long time to search for a block with a small number of rewrites, and the rewrite time is greatly increased To reduce the access performance. For example, to search for the block with the smallest number of rewrites, it is necessary to read the number of rewrites stored in all the blocks and find the block with the least number of rewrites. Reading all blocks requires an enormous amount of time, and performance degradation is inevitable. In order to manage the number of rewrites in units of physical blocks, an area for storing the number of rewrites for each physical block is required. In this case, it is necessary to update the number of rewrites separately from the rewrite of the data part for the physical block. When the number of erasures is stored in the management information that is simply included in the same erasure as the physical block, the management information is read before the physical block is rewritten, and the number of rewrites is saved. Thereafter, a process for transferring the management information whose number of rewrites has been updated to the flash memory is required, and this also causes a decrease in access performance.

  An object of the present invention is to make it possible to shorten the processing time associated with the logical address assignment change for the physical block, which is performed for leveling the number of rewrites and countermeasures against disturbance.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  << Address Management Form in Superblock Unit >> The storage device (1) according to the present invention includes a nonvolatile memory (2) and a control circuit (3). The nonvolatile memory can be erased by initializing the stored information in a block area (BLK) unit that is a set of a plurality of nonvolatile memory cells that can rewrite the stored information. Write processing for writing information in the block area is enabled. For example, when a set of a plurality of page areas (PAGs) is defined as the block area (BLK), the non-volatile memory has a page area unit that is a set of a plurality of non-volatile memory cells in which stored information can be rewritten. Write processing for writing storage information is enabled, and erasure processing for initializing storage information in units of block areas, which is a set of a plurality of page areas, is enabled. The control circuit allocates one free block (BLK-V) in units of super blocks (SB (SB-0 to SB-15)), which is a set of a plurality of block areas for data, and logic for the remaining block areas. The address assignment is performed, and the latest address conversion table (SBTBL) indicating the assignment is held in one block area where the last write process is performed in the super block, and the address conversion table in each super block is stored. An address table (CPTBL) indicating the physical address of the block area is stored in the management block area (BLK-C). When responding to an access request from the outside, the control circuit obtains a physical address corresponding to the logical address related to the access request from an address conversion table corresponding to the super block to which the logical address related to the access request is assigned. Acquires and performs block area access control using the acquired physical address.

  According to the above address management mode for block areas, a logical address range is allocated in units of super blocks, one empty block is secured in the super block, and logical address allocation to the remaining block areas in the super block is variable. Is done. Since the range in which the logical address allocation is made variable is in the corresponding par block, in most cases, the leveling of the number of rewrites and the countermeasure against the disturbance may be considered in each super block. The number of times of rewriting may be considered in the super block, and it is not necessary to grasp the number of times of rewriting for each block area in the entire range of the nonvolatile memory. An address conversion table that indicates allocation of logical addresses to block areas may be formed in units of super blocks. In each super block, the address conversion table is held in the block area where the last write processing is performed, so that the address conversion table can be rewritten together with the rewriting of the block area. An address table indicating a physical address in which a valid management table is stored in each super block is changed every time the block area is rewritten, but can be collectively managed in the management block area. As a result, it is possible to reduce the processing time associated with the logical address assignment change to the physical block, which is performed for leveling the number of rewrites and countermeasures against disturbance.

  As one specific form of the present invention, the control circuit reads an address table from a non-volatile memory when responding to an access request from the outside and not acquiring the address table. When the address conversion table corresponding to the super block to which the logical address related to the access request is assigned is not acquired, the control circuit searches the physical address of the address conversion table from the acquired address table, and the searched physical The address conversion table stored in the address is acquired from the nonvolatile memory. The control circuit acquires a physical address corresponding to the logical address related to the access request from the acquired address conversion table, and enables access control of the block area using the acquired physical address.

  << Write Sequence >> As a specific form of the present invention in terms of a write sequence for the block area, when the control circuit performs a rewrite process in response to an access request from the outside, the control circuit uses the physical address of the current empty block. The logical address related to the access request is newly assigned, the block area of the physical address acquired from the address conversion table is assigned to a new empty block, and data rewriting for the block area to which a new logical address is assigned is controlled. The location of the address conversion table changed by the rewrite control is reflected in the address table.

  << Sequential Location Change Writing of Address Table >> As a more specific form of the present invention in terms of management of the address table, the control circuit has a plurality of management block areas (BLK) for storing the address table. -C), the address block is stored by sequentially switching the management block area, and for each address table write, a plurality of address table storage positions on the block area to be written are set. Control is performed to change sequentially, and the flag information table (FLGTBL) indicating the storage location of the changed address table (CPTBL) is updated on the write target block area, and a new address table is added to the management block area. When there is no more free space to write To clear the area. By sequentially changing the write position of the address table, the write position becomes an index of the number of rewrites.

  << First Form of Replacement Process >> As a specific form of the present invention in terms of a replacement process for replacing a logical address between physical blocks, the address table stores replacement target physical address information for each block area in a super block. It has a region (REPA). When detecting the execution timing of the replacement process, the control circuit acquires information on the replacement target physical address in block area units from the address table, and adds the logical address of the acquired replacement target physical address to the physical address of the current free block. And assigning the block area of the acquired replacement target physical address to a new empty block, exchanging data between the new empty block and the block area to which the new logical address is assigned, and data The update is controlled, the location of the address conversion table changed by the update control of the data is reflected in the address table, and the information on the physical address to be replaced in the block area in the super block held by the address table is updated.No process for searching for a block area with a small number of rewrites is required to specify a replacement process target. The rule for updating the information of the replacement target physical address in block area units may be changed sequentially.

  As a more specific form of the replacement process, attention is paid to the fact that by sequentially changing the write position of the address table, the write position becomes an index of the number of rewrites. That is, the control circuit uses a plurality of management block areas (BLK-C) to store the address table, and sequentially uses the management block areas to store the address table. Each time the address table is written, control is performed to sequentially change a plurality of storage positions of the address table on the block area to be written, and flag information indicating the storage position of the changed address table is further written. Updating is performed on the block area, and when there is no free area for writing a new address table in the management block area, the management block area is deleted. Furthermore, the control circuit detects that the management block area has been erased after the write process as the execution timing of the replacement process.

  As a more specific form, the control circuit sets the physical address indicated by the replacement target physical address information on the address table related to the super block that is the target of the rewrite process performed immediately before the replacement process.

  Further, as another specific form, the control circuit is configured such that the physical address information indicated by the replacement target physical address information on the address table related to the super block adjacent to the super block that is the target of the rewrite processing performed immediately before the replacement processing. Change the address. According to this, since the super block next to the super block that was the target of the rewrite process immediately before becomes the target of the replacement process, even if one super block is frequently rewritten, it is replaced with the adjacent super block. Processing can be performed. Even if rewriting for one super block is concentrated, it is possible to contribute to leveling of the number of rewritings in other super blocks. Also. Assuming a configuration in which the word lines are shared between adjacent super blocks, disturbance occurs even between different super blocks. Therefore, when only a specific super block is frequently rewritten, the influence of disturb is totally A mitigating effect can be expected.

  As yet another specific form, when the physical address corresponding to the acquired replacement target physical address information is an empty block, the control circuit updates the replacement target physical address information related to the super block and performs replacement processing. finish. When only a specific super block whose physical address corresponding to the replacement target physical address information is an empty block is frequently rewritten, it is possible to avoid a situation in which the replacement process is not substantially performed in the super block. That is, when writing concentrates on a specific address, if the replacement process in the super block to be written becomes “replacement target = empty block” and the replacement target is not updated, “replacement target = empty block” ”, The disturbance prevention function may be lost. By updating the replacement target when “replacement target = empty block”, it becomes possible to implement the disturbance countermeasure regardless of the address specified in the writing process.

  << Second Form of Replacement Process >> As another specific form of the present invention in terms of a replacement process for replacing a logical address between physical blocks, the address table is a physical address to be replaced in units of block areas in a plurality of super blocks. It has an address area (REPA) for storing information and a number area (NMBA) for storing the number of rewrite processes of the block area in the plurality of super blocks. The control circuit increments the value in the number-of-times area related to the super block that is the target of the rewrite process in the rewrite process. When detecting the execution timing of the replacement process, the control circuit acquires information on the replacement target physical address in block area units from the address table, and adds the logical address of the acquired replacement target physical address to the physical address of the current free block. And assigning the block area of the acquired replacement target physical address to a new empty block, exchanging data between the new empty block and the block area to which the new logical address is assigned, and data Controls updating, reflects the location of the address translation table changed by updating the data to the address table, and updates information on physical addresses to be replaced in block areas in a plurality of super blocks held by the address table You .

  As a specific form of the replacement process, the control circuit detects that the value of the number of times area updated in the rewrite process has reached a predetermined value as the execution timing of the replacement process. Since the value of the number-of-times area indicates the number of times the block area has been rewritten in the plurality of super blocks, assuming a configuration in which word lines are shared between the plurality of super blocks, disturbs are different in super. Since it also occurs between blocks, when only a specific super block is frequently rewritten, it is possible to expect an effect of alleviating the influence of disturbance by the plurality of super blocks.

  As a more specific form, the control circuit sets the physical address indicated by the replacement target physical address information on the address table related to the super block that is the target of the rewrite process performed immediately before the replacement process.

  As another specific form, when the physical address corresponding to the acquired replacement target physical address information is an empty block, the control circuit updates the replacement target physical address information related to the super block and performs replacement processing. Exit. When only a specific super block whose physical address corresponding to the replacement target physical address information is an empty block is frequently rewritten, it is possible to avoid a situation in which the replacement process is not substantially performed in the super block.

  Furthermore, also in the second form of the replacement process, it is possible to employ means for sequentially changing the write position of the address table. That is, the control circuit uses a plurality of management block areas to store the address table, and sequentially switches the management block areas to store the address table and writes the address table. Each time, control is performed to sequentially change a plurality of storage positions of the address table on the block area to be written, and flag information indicating the storage position of the changed address table is updated on the block area to be written. When there is no more free area for writing a new address table in the management block area, the management block area is erased.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to reduce the processing time associated with the logical address assignment change to the physical block performed for leveling the number of rewrites and for countermeasures against disturbance.

"Memory card"
FIG. 2 shows a flash memory card which is an example of a storage device according to the present invention. The flash memory card (FMC) 1 includes an erasable and writable nonvolatile memory such as a flash memory (FLASH) 2 and a card controller (CCRL) 3 as a control circuit for performing memory control and external interface control. Become.

  The card controller 3 performs external interface control in accordance with, for example, an IDE disk interface specification with a host computer (HST) 6 as a card host. The card controller 3 has an access control function for accessing the flash memory 2 in accordance with an instruction from the host computer 6. This access control function is a hard disk compatible control function. For example, when the host computer 6 manages a set of sector data as file data, the card controller 3 associates a sector address as a logical address with a physical memory address to flash memory. 2 access control is performed. According to FIG. 1, the card controller 3 includes a host interface circuit (HIF) 10, a central processing unit (CPU) 11, a ROM 12, a RAM 13, a flash interface circuit (FIF) 14, an error detection and correction circuit (ECC) 15, a buffer. An interface circuit (BIF) 16 and a buffer memory (BMRY) 17 are provided.

  The host interface circuit 10 includes ATA (ATA Attachment), IDE (Integrated Device Electronics), SCSI (Small Computer System Interface, etc.), MMC (MultiMediaCard: Registered Trademark), and PCMCIA (Perm. Control the command interface and data input / output with the host computer 6. The host interface circuit 10 decodes the memory card command issued from the host computer 6 and instructs the CPU 11 to perform processing according to the decoding result by interruption or the like.

  The CPU 11 uses the RAM 13 as a work area, executes a program stored in the ROM 12, and controls the card controller 3 as a whole.

  The flash interface circuit 14 issues a flash access command to the flash memory 2 under the control of the CPU 11 to control data rewriting and reading.

  The buffer interface circuit 16 performs data transfer control between the host interface circuit 10 and the buffer memory 17 and data transfer control between the buffer memory 17 and the flash interface circuit 14. The write data input by the host interface circuit 10 is temporarily stored in the buffer memory 17, and then the write data transferred from the buffer memory 17 to the flash interface circuit 10 can be written to the flash memory. The read data read from the flash memory 2 is temporarily stored in the buffer memory 17, and then the read data transferred from the buffer memory 17 to the host interface circuit 10 is output to the host computer 6.

  The flash memory 2 has a memory array (MARY) 20 and a data register (DREG) 21 which are representatively shown. The memory array 20 has a large number of nonvolatile memory cells that can electrically rewrite stored information. The nonvolatile memory cell may employ, for example, a MOS stack gate structure having a floating gate as a charge storage layer, or a split gate structure having a silicon nitride film as a charge storage layer. In either case, the threshold voltage is increased by performing a process (writing process) for injecting electrons into the charge storage region (releases holes), and also releases electrons (injects holes) from the charge storage region. The threshold voltage is lowered by performing initialization processing (erasing processing). The nonvolatile memory cell can store information by the difference in threshold voltage between the writing process and the erasing process. By storing two threshold voltage states that can be selectively programmed in one nonvolatile memory cell, binary storage can be performed. It is also possible to perform quaternary storage with four threshold voltage states that can be selectively programmed in one nonvolatile memory cell.

  Although there is no particular limitation, the memory array is a set of a plurality of page PAGs, which enables a write process to write storage information in a page area (also simply referred to as a page) PAG, which is a set of a plurality of nonvolatile memory cells. An erasing process for initializing the stored information in a block area (also simply referred to as a block) BLK is made possible. In short, the page PAG is a writing unit (PGM unit), and the block BLK is an erasing unit (ERS unit). For example, one page PAG (one page) has a storage capacity of, for example, 2 kilobytes (KB) +64 KB, and one block BLK (one block) has a size of four pages. One block of non-volatile memory cells is not particularly limited, but is connected to a common word line. For example, by applying a negative high voltage to an erase processing selection word line and setting a well region to a ground potential, for example, an FN tunnel Can be erased in one block unit. Non-volatile memory cells of one block and four pages sharing a word line are arranged along the word line one by one for each page, and the drains of the non-volatile memory cells are selectively connected to bit lines on a page basis. The When a write process is performed, a positive high voltage is applied to the word line, the source of one page of nonvolatile memory cells is connected to the bit line, and the bit line corresponding to the memory cell selected for writing is connected to the bit line from the drain. A current path toward the source is formed, and formation of a current path from the drain to the source is suppressed in the memory cell that is not selected for writing. Hot electrons are generated by the source current flowing through the non-volatile memory cell through the current path, whereby electrons are injected into the charge storage region of the non-volatile memory cell, and the threshold voltage is increased. In data rewriting, after erasing in units of blocks, a writing process is performed in units of pages for the four pages constituting the block.

  The data register 21 is not particularly limited, but can input / output data in units of pages to / from the memory array 20 and store a maximum of one block of data. The data register 21 inputs and outputs data in units of bytes with the flash interface circuit 14. For example, in data rewriting, data read from the erase target block BLK is saved in the data register 21. The saved data is modified by the write data supplied from the flash interface circuit 14 or the like. The modified data is written in the erased block BLK in units of pages.

<< Data management form in units of super blocks >>
FIG. 1 illustrates a data configuration in the memory array 2. The page address, which is a physical address of the page unit of the memory array 21, is set to 0000h to 0FFFh. h means a hexadecimal number. One page (writing unit) PAG is 2112 bytes. One page PAG includes four sectors (512 bytes) as a data area (DataArea), an ECC code (8 bytes) area for the sector, and a 32-byte management area (ControlArea). Four pages PAG form one block BLK (erase unit). Here, the number of blocks BLK is 400h.

  A unit of 64 blocks BLK is defined as a super block SB. In the example of FIG. 1, 16 super blocks (SB) are each composed of 64 blocks BLK. FIG. 1 typically shows 16 super blocks SB-0 to SB-15.

  The super blocks SB-0 to SB-14 are used as a user data area (UseDataArea) for storing user data. One super block SB can store user data for 63 blocks BLK. The remaining one is secured as an empty block BLK-V. In the example of FIG. 1, page addresses: 0014h to 0017h are empty blocks BLK-V in the super block SB-0. In the super block SB-1, page addresses: 0100h to 0103h are empty blocks BLK-V. Although details will be described later, in data rewriting or the like, after erasing an empty block, the erased empty block is always set as a write target block. Further, the block in which the rewrite target user data is stored before the rewriting is set as a new empty block. Therefore, if the block is rewritten, not only the correspondence between the logical address and the page address but also the allocation state of the empty block is changed.

  The management area of each block BLK in the super blocks SB-0 to SB-14, which is the user data area, is an area for storing an SB table (SBTBL) as an address conversion table in the super block SB. The intra-SB table SBTBL is a table showing allocation of empty blocks BLK-V in the super block SB and logical addresses for the remaining blocks BLK. When the block is rewritten in the super block SB, the storage location of the new in-SB table SBTBL is finally subjected to the writing process (in short, the most recently written process is performed). It is set as an area (Control Area). The management area described as “latest” in FIG. 1 holds the latest SB table SBTBL in the super block SB. In short, FIG. 1 shows that the user data 000h to 00Fh was written last in the super block SB-0, so that the management area of the page addresses 0004h to 0007h holds the latest SB table SBTBL. ing.

  FIG. 3 illustrates the configuration of the SB table SBTBL. In the SB table SBTBL, page addresses corresponding to consecutive 63 × 4 logical addresses assigned to the super block are sequentially stored from the upper left end of the figure, and finally the page addresses of the empty blocks BLK-V are stored. It has become so. Taking the super block SB-0 of FIG. 1 as an example, the head of the in-SB table SBTBL has page addresses PADRS [UserData (0h to Fh)]: 0004h to 0007h in which user data 0h to Fh are stored. Page address PADRS [UserData (10h to 1Fh)]: 00FCh to 00FFh in which user data 10h to 1Fh are stored in the last page address PADRS [VBLK]: 0014h to 0017h to which an empty block BLK-V is allocated. Is held. According to this, the logical addresses for the first four sectors assigned to the super block SB-0 are assigned to page addresses PADRS: 0004h to 0007h, and the logical addresses for the next four sectors are assigned to page addresses PADRS: 00FCh to 00FFh. Yes.

  In FIG. 1, the super block SB-15 is used as an alternative area and a chip table area. The replacement area is a block used in place of a bad block. For example, in FIG. 1, page addresses 0008h to 000Bh in the super block SB-0 are defective blocks, and blocks of page addresses 0F00h to 0F03h are used to replace them. Similarly, blocks of page addresses 0F04h to 0F07h are used to replace defective blocks of page addresses 0010h to 0013h.

  The chip table area in FIG. 1 is composed of two management blocks BLK-C. In the chip table area CTAREA allocated to the two management blocks BLK-C, as illustrated in FIG. 4, a chip table for registering the page address of the latest SB table SBTBL and the replacement target page address. Stores CPTBL. In addition, a flag table FLGTBL having a chip table flag for indicating where the latest chip table CPTBL is stored is stored in the management area of the chip table area CTAREA.

  FIG. 4 shows a chip table area CTAREA, a chip table CPTBL stored therein, and a flag table FLGTBL of chip table flags. The chip table CPTBL sequentially holds the page address of the latest SB table in each of the super blocks SB-1 to SB14, starting with the page address of the latest SB table in the super block SB-0. The replacement target page addresses in the super blocks SB-1 to SB14 are sequentially held starting with the replacement target page address in the block SB-0, and finally the ECC code for them is held. The chip table CPTBL has a table size of, for example, 512 bytes. The replacement target is a physical block to be rewritten to prevent disturbance. The area REPA is an area for holding a replacement target page address in units of super blocks. The details of the replacement process and the rewrite process for preventing disturbance will be described later.

  Columns 0 to 3 corresponding to 4 sectors are assigned to each page of the chip table area CTAARE, and the management block BLK-C is used in order to store the chip table CPTBL, and each write of the chip table CPTBL is performed. Control to sequentially switch the write column position on the page. For example, as illustrated in FIG. 4, if column 0 of page address 0FF8h in the upper management block BLK-C is used as a writing base point of the chip table CPTBL, page address 0FFCh in the lower management block BLK-C is used in the next writing. Column 0, and in the next write, column 1 of page address 0FF8h in the upper management block BLK-C is sequentially changed as indicated by the arrow, and finally the page in the lower management block BLK-C. It is changed to the position of column 3 at address 0FFFh.

  FIG. 5 shows an example of the flag table FLGTBL. The chip table flag flag table FLGTBL indicating the storage position of the latest chip table in the chip table area CTAREA has an 8 × 4 flag area corresponding to the chip table storage areas of column 0 to column 3 for 8 pages. The flag table FLGTBL is initialized to FFh when the chip table area CTAREA is erased, and the head chip table flag is changed from FFh to 00h when the latest chip table is stored at the head of the chip table area CTAREA ( S1). Thereafter, the chip table flag is changed from FFh to 00h at the corresponding position on the flag table FLGTBL according to the change of the storage position of the latest chip table (S2, S3). When all the chip table flags on the flag table FLGTBL have become 00h (S4), when changing the storage position of the chip table, the page addresses 0FF8h to 0FFBh are first erased and initialized. Then, the latest chip table and chip table flag are written in the page of 0FF8h (S5). Next, when the latest chip table is written in the chip table area of 0FFCh to 0FFFh, the page address of 0FFCh to 0FFFh is first erased and initialized, and then the latest chip table is stored in the page of 0FFCh. A chip table flag is written (TR1).

  According to the configuration of the chip table CPTBL and the flag table FLGTBL, the flag “00h” is searched from the direction opposite to the update direction of the flag table FLGTBL, and the column position of the page address corresponding to the position where the flag “00h” is detected is determined. It becomes the storage position of the latest chip table. As a result, it is possible to obtain the page address in which the latest SB table SBTBL corresponding to the super block SB assigned to the logical address related to the access request is stored from the obtained chip table CPTBL, and it is necessary to use the page address. What is necessary is just to acquire SB intra-table SBTBL. As described above, in the data rewrite, the data write destination is the empty block BLK-V at that time, and the logical address assignment is changed. Therefore, if the data rewrite occurs, the storage position of the latest SB table SBTBL is stored. As a result, the chip table CPTBL is updated accordingly, and the flag table FLGTBL is also updated. The CPU 11 reads necessary tables into the RAM 13 for reference and operation with respect to the SB table SBTBL, the chip table CPTBL, and the flag table FLGTBL. When the CPU 11 changes the read table, the CPU 11 performs control to reflect the change in the block on the flash memory. In the following, various access control modes when the data management mode in units of super blocks is adopted will be described.

《Lead processing》
FIG. 6 illustrates a read processing flow. When a read command is issued from the host computer 6 (S1021), the CPU 11 calculates the number (SB number) of the super block SB corresponding to the logical address designated thereby (S102). For example, when the host computer 6 designates the logical address of the user data 300h as the logical address, the SB number is the super block SB-0 according to FIG. The CPU 11 checks whether or not the in-SB table SBTBL of the calculated SB number has already been read out to the RAM 13 (S103). If it has been read, the CPU 11 acquires the page address where the logical address related to the access request is stored from the SB table SBTBL on the RAM 13 (S110).

  If the necessary in-SB table SBTBL has not been read out to the RAM 13, it is confirmed whether the chip table CPTBL in which the latest position of the in-SB table is registered has already been read out on the RAM 13 (S105). If it has been read, the CPU 11 acquires the page address where the latest SB table is stored from the chip table CPTBL on the RAM 13 (S108). If the chip table CPTBL has not been read out to the RAM 13, the flag table FLGTBL is read out as the management information of the chip table area CTAREA and the position of the latest chip table is specified (S106). In accordance with this, the latest chip table is read into the RAM 13 (S107). Using the read chip table CPTBL, the page address of the latest SB table is acquired (S108). If the example of FIG. 4 is followed, it turns out that the newest SB table SBTBL is stored in page address 0004h-0007h. Then, the CPU 11 reads the latest SB table into the RAM 13 (S109).

  The CPU 11 acquires the page address corresponding to the access target logical address using the latest SB table on the RAM 13 (S110). According to the example of FIG. 3, since it can be seen that the user data 300h of the access target logical address is stored in the page addresses 0000h to 0003h, the CPU 11 reads the user data from the page addresses 0000h to 0003h to the buffer memory 17 (S111). ). Finally, the CPU 11 outputs the user data read to the buffer memory 17 to the host computer 6 via the host interface circuit 10 (S112). When the host computer 6 further reads user data (for example, when reading the user data 301h continuously), steps S102 to S112 are repeated.

《Rewrite processing》
FIG. 7 illustrates a rewrite processing flow. FIG. 8 is an explanatory diagram illustrating the correspondence between the processing steps of FIG. 7 and the registered addresses of the table when the rewriting process for the logical addresses of the user data 300h to 30Fh is taken as an example.

  When a write command is issued from the host computer 6 (S201), the CPU 11 calculates the number of the super block SB (SB number) corresponding to the logical address designated thereby (S202). For example, when the host computer 6 designates the logical address of the user data 300h to 30Fh as the logical address, the SB number is the super block SB-0 according to FIG. The CPU 11 checks whether or not the in-SB table SBTBL of the calculated SB number has already been read out to the RAM 13 (S203). If the necessary SB table SBTBL has not been read to the RAM 13, it is confirmed whether the chip table CPTBL in which the latest position of the SB table SBTBL is registered has already been read on the RAM 13 (S205). If it has been read, the CPU 11 acquires the page address where the latest SB table is stored from the chip table CPTBL on the RAM 13 (S208). If the chip table CPTBL has not been read out to the RAM 13, the flag table FLGTBL is read out as the management information of the chip table area CTAREA, and the position of the latest chip table is specified (S206). Accordingly, the latest chip table is read out to the RAM 13 (S207). Using the read chip table CPTBL, the page address of the latest SB table is acquired (S208). If the example of FIG. 4 is followed, it turns out that the newest SB table SBTBL is stored in page address 0004h-0007h. Then, the CPU 11 reads the latest SB table into the RAM 13 (S209).

  Thereafter, the CUP 11 acquires the page address of the empty block BLK-V in the access target super block SB using the latest SB table on the RAM 13 (S210). In the example of FIG. 3, the empty blocks are page addresses 0014h to 0017h. Next, the empty block BLK-V is erased (S211).

  Here, the page address to which the logical address to be accessed this time is assigned is acquired using the SB table SBTBL on the RAM 13, and the block data of the page address is saved in the buffer memory 17. The saved data is modified on the buffer memory 17 with the write data supplied from the host computer 6 this time, and used for the write process described later. For example, when the write data supplied from the host computer is for one page, the remaining three pages are left as they are. Thereafter, the CPU 11 updates the page address to which the logical address to be accessed this time is assigned and the page address of the empty block in the SB table SBTBL on the RAM 13 (S212). According to the example of FIG. 8, page address information 0000h to 0003h corresponding to the logical address of the user data 300 to 30Fh in the SB table is changed to 0014h to 0017h, and page address information 0014h to 0017h related to the empty block in the SB table. Is updated to 0000h to 0003h.

  Next, the CPU 11 controls writing of the modified write data and the in-SB table SBTBL updated in step S212 to the empty blocks 0014h to 0017h erased in step S211 (S213).

  Further, in the chip table on the RAM 13, the page address storing the latest SB in-table SBTBL in the super block to be rewritten this time is updated (S214). According to the example of FIG. 8, the page address of the latest SB-0 table is updated to 0014h to 0017h. Thereafter, the CPU 11 writes the chip table CPTBL and the flag table FLGTBL updated in the RAM 13 to the next column position of the chip table area CTAREA (S215). The update procedure of the chip table CPTBL and the flag table FLGTBL is as described with reference to FIG. 5, and if necessary, erasure is performed on one block of the chip table area CTAARE in advance. Finally, a replacement process S216 is performed. When the host computer 6 further writes other user data continuously, steps S202 to S216 are repeated.

  In the write process, the block corresponding to the access target logical address is replaced with the empty block at that time. By this replacement, it is possible to achieve leveling of the number of times of rewriting for the block and a countermeasure for disturbing the block having a low frequency of rewriting. However, when the access target logical address by the host computer 6 is biased, the effect is not sufficient. The replacement process described below as a specific example is intended to improve this point, and enables a random replacement process mainly by the card controller 3.

《Replacement process》
FIG. 9 illustrates a replacement process flow. When the page addresses 0FFCh to 0FFFh are erased in the chip table area CTAREA in step S215 of FIG. 7, replacement processing is executed (S301). In short, every time the rewriting process is performed, the replacement process is performed at a timing when the process of sequentially writing the latest chip table CPTBL in the chip table area CTALEA is completed.

  First, the replacement target of the super block SB updated by the rewriting process is acquired from the chip table CPTBL (S302). In the example of FIG. 4, the replacement target page address of the super block SB-0 is 000Ch to 000Fh. It is confirmed whether the replacement target page address is an empty block. If it is an empty block, the replacement process is not performed (S303). This is because there is no substantial replacement target.

  When performing the replacement process, first, the current empty block is erased (S304). The empty block is acquired from the SB table SBTBL on the RAM 13. Next, in the SB table on the RAM 13, the page address of the user data to be replaced and the page address of the empty block are updated (S305). In the example, when the page addresses 000Ch to 000Fh are to be replaced and the free block is the page address 0014h to 0017h, the page address 000Ch to 000Fh is set to the free block and the page address of the user data 020h to 02Fh in the SB table. Is updated to 0014h to 0017h.

  The user data 020h to 02Fh and the updated SB table are written in the erased empty blocks (page addresses: 0014h to 0017h) (S306). Here, the user data 020h to 02Fh is once read to the buffer memory 17 of the card controller 3 and then written to an empty block.

  Since the page address in which the latest SB-0 table is stored is changed and the replacement process is executed, the page address of the latest SB table and the page address to be replaced in the chip table CPTBL on the RAM 13 are changed. Update (S307). For example, the page address of the latest SB table is updated to 0014h to 0017h, and the page address to be replaced is updated to 0010h to 0013h, which is the next block to be replaced. However, since page addresses 0010h to 0013h are defective blocks, page addresses 0F04h to 0F07h are registered as replacement targets. Finally, the latest chip table CPTBL and flag table FLGTBL are written to the chip table area CTAARE of the flash memory 2 (S308).

  FIG. 10 illustrates a page address update procedure for replacement. The page address to be replaced moves to the next page address every time a replacement process occurs. In addition, after the last page address of the super block, it moves to the top page address of the super block. For example, the page addresses 00FCh to 00FFh are followed by page addresses 0000h to 0003h.

  According to the data management form in units of super blocks described above, the block corresponding to the logical address to be accessed and the empty block at that time are replaced for each super block. Disturbance countermeasures for blocks with few can be achieved. At this time, it is not necessary to count the number of physical block rewrites or search for a block with a small number of rewrites, so that the rewrite processing time can be shortened and the writing performance can be improved. Further, since random replacement processing within the super block by the card controller 3 itself can be performed at a predetermined timing, even if the access target logical address by the host computer 6 is biased, the effectiveness of the above leveling and disturbance countermeasures Can be secured.

<< Second example of replacement process >>
FIG. 11 shows a second example of the replacement process. The difference from the first example in FIG. 9 is the timing for performing the replacement process and the method for selecting the replacement target. That is, when page addresses 0FF8h to 0FFBh are erased in the chip table area in step S215 in FIG. 7, replacement processing is executed (S401). The replacement target is not selected from the same super block as the rewriting process, but is performed on the adjacent super block (S402). For example, when the previous rewrite target is a block belonging to the super block SB-0, the replacement target is the replacement target page address of the adjacent super block SB-1, and for example, according to the example of FIG. 4, the super block SB- 1 page addresses 0100h to 0103Fh. Other processing procedures are the same as those in FIG.

  According to the replacement processing procedure of FIG. 11, since the super block next to the super block that was the target of the rewrite process immediately before becomes the target of the replacement process, even if one super block is frequently rewritten, A replacement process can be performed on the block. Even if rewriting for one super block is concentrated, it is possible to contribute to leveling of the number of rewritings in other super blocks.

<< Third example of replacement process >>
FIG. 12 shows a third example of the replacement process. The difference from the first example of FIG. 9 is that the page to be replaced that is stored in the chip table when it is not necessary to rescue the data stored in the replacement target, that is, when the replacement target is an empty block. The process of updating the address (S508) is performed. For example, when the previous rewrite target is a block belonging to the super block SB-0, when the replacement target page address is 0014Ch to 0017h, and this is an empty block, the replacement target page address is set to the adjacent page address 0018h. Change to ~ 001AFh. Other processing procedures are the same as those in FIG. According to this, when writing concentrates on a specific address, if the replacement target in the super block to be written becomes “replacement target = empty block” and the replacement target is not updated, the “replacement target” = Disabling function may be lost because there is a high possibility of becoming “= free block”. By updating the replacement target when “replacement target = empty block”, it becomes possible to implement a countermeasure against disturbance regardless of the address specified in the writing process.

<Another method for specifying the replacement target>
Next, an example in which the replacement target in the replacement process is managed in units of a plurality of super blocks will be described. FIG. 13 illustrates the configuration of the chip table at that time, FIG. 14 illustrates the rewrite processing flow at that time, and FIG. 15 illustrates the replacement processing flow at that time.

  When managing the replacement processing target in units of a plurality of super blocks, the chip table CPTBL is changed as shown in FIG. The basic configuration is the same as in FIG. 4 except that the page address to be replaced is managed in units of a plurality of super blocks and an area for holding the number of updates in units of a plurality of super blocks is added. For example, the management unit is set to super blocks SB-0 to SB-3, and the range that can be taken by the page address to be replaced at this time is the entire range of the super blocks SB-0 to SB-3. FBFh, and the number of updates is the sum of the number of updates in the entire super blocks SB-0 to SB-3.

  The rewrite processing flow at this time is changed as shown in FIG. 13, but the basic processing procedure is almost the same as in FIG. The difference is that since the number of updates is counted in units of a plurality of super blocks SB, the processing steps S609 and S610 for calculating the management unit number from the user data address which is a logical address, and the number of updates managed in the chip table CPTBL are set. It is processing step S617 to update.

  Further, the replacement process is also changed as shown in FIG. 15, but the basic processing procedure is almost the same as that in FIG. The difference is that the replacement processing trigger is when the number of updates in units of a plurality of super blocks reaches a specified value, for example, FFFh.

  According to this replacement target designation procedure, data can be relieved when data relieving due to disturbance is required in units of a plurality of super blocks. For example, when the influence of disturb occurs across a plurality of super blocks SB, even if writing concentrates on a specific super block, the range subject to disturb (other super blocks that are not affected by writing but are affected by disturb) ) Can all be repaired by replacement processing. In short, although different from the block configuration described so far, if a configuration in which word lines are shared in whole or in part between different super blocks is assumed, disturbance occurs between different super blocks. When only a specific super block is frequently rewritten, it is possible to expect an effect of alleviating the influence of disturb as a whole.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the memory array configuration of the flash memory may be an AND type or a NAND type. The page size, block size, and super block size can be changed as appropriate. In addition, the erasing and writing methods, the word line configuration and the well configuration for the erasing unit can be changed as appropriate. In short, the present invention is not limited to a specific configuration of the memory array.

It is explanatory drawing which illustrates the structure of the data which the memory | storage device which concerns on this invention hold | maintains. It is a block diagram which illustrates the flash memory card which is an example of the memory | storage device which concerns on this invention. It is explanatory drawing which illustrates the structure of table SBBT in SB. It is explanatory drawing which shows an example of flag table FLGTBL of the chip table area | region CTAREA, the chip table CPTBL stored there, and a chip table flag. It is explanatory drawing which shows an example of flag table FLGTBL. It is a flowchart which illustrates a read processing procedure. It is a flowchart which shows the rewriting process procedure. It is explanatory drawing which illustrates a response | compatibility with the process step of FIG. 7, and the registration address of a table when the rewriting process with respect to the logical address of user data 300h-30Fh is made into an example. It is a flowchart which shows a replacement process procedure. It is explanatory drawing which illustrates the page address update procedure of replacement | exchange object. It is a flowchart which shows the process sequence which concerns on the 2nd example of replacement processing. It is a flowchart which shows the process sequence which concerns on the 3rd example of replacement processing. It is explanatory drawing which illustrates the structure of a chip table when it is made to manage the replacement object in a replacement process per several superblock units. 14 is a flowchart showing a rewrite processing procedure when the chip table shown in FIG. 13 is adopted. It is a flowchart which shows the replacement process procedure in the case of employ | adopting the chip table shown by FIG.

Explanation of symbols

1 Flash memory card (FMC)
2 Flash memory (FLASH)
3 Card controller (CCRL)
6 Host computer (HST)
10 Host interface circuit (HIF)
11 Central processing unit (CPU)
12 ROM
13 RAM
14 Flash interface circuit (FIF)
15 Error detection and correction circuit (ECC)
16 Buffer interface circuit (BIF)
17 Buffer memory (BMRY)
20 memory array (MARY)
21 Data register (DREG)
PAG page area (page)
BLK block area (block)
BLK-V Empty block BLK-C Management block SB (SB-0 to SB-15) Super block SB-0 to SB-14 User data area SBTBL In-SB table as address conversion table CTAREA Chip table area CPTBL Chip table FLGTBL flag table NMBA Rewrite count holding area REPA Holding area for page address to be replaced

Claims (18)

A storage device having a nonvolatile memory and a control circuit,
The non-volatile memory can be erased to initialize the memory information in a block area unit, which is a set of a plurality of non-volatile memory cells in which the memory information can be rewritten. Write processing to write information is enabled,
The control circuit allocates one free block and logical addresses to the remaining block areas in units of super blocks, which is a set of a plurality of block areas for data, and stores the latest address conversion table indicating the allocation. It is held in one block area where the last write processing is performed in the super block, and an address table indicating the physical address of the block area having the address conversion table in each super block is stored in the management block area.
When responding to an access request from the outside, the control circuit obtains a physical address corresponding to the logical address related to the access request from an address conversion table corresponding to the super block to which the logical address related to the access request is assigned. A storage device that can acquire and control access to a block area using the acquired physical address.   The storage device according to claim 1, wherein the block area is a set of a plurality of page areas, and the page area is a processing unit of the writing process.   When the control circuit responds to an access request from the outside, when the address table is not acquired, the control circuit reads the address table from the nonvolatile memory and corresponds to the super block to which the logical address related to the access request is assigned. When the address conversion table to be acquired is not acquired, the physical address of the address conversion table is searched from the acquired address table, and the address conversion table stored in the searched physical address is acquired from the nonvolatile memory and acquired. The storage device according to claim 1, wherein a physical address corresponding to a logical address related to the access request is acquired from an address conversion table.   When the control circuit performs a rewrite process in response to an access request from the outside, the control circuit newly assigns a logical address related to the access request to the physical address of the current empty block, and the physical address acquired from the address conversion table The block area is allocated to a new empty block, data rewriting is controlled for the block area to which a new logical address is assigned, and the location of the address conversion table changed by the rewriting control is reflected in the address table. The storage device according to 1.   The control circuit uses a plurality of management block areas to store the address table, and sequentially switches and uses the management block areas to store the address table, each time the address table is written. The control is performed to sequentially change a plurality of storage positions of the address table on the block area to be written, and the flag information indicating the storage position of the changed address table is updated on the block area to be written, 5. The storage device according to claim 4, wherein the management block area is erased when there is no more free area for writing the address table in the management block area. The address table has an area for storing physical address information for replacement in block area units in a super block,
When detecting the execution timing of the replacement process, the control circuit acquires information on the replacement target physical address in block area units from the address table, and adds the logical address of the acquired replacement target physical address to the physical address of the current free block. And assigning the block area of the acquired replacement target physical address to a new empty block, exchanging data between the new empty block and the block area to which the new logical address is assigned, and data The update is controlled, the location of the address conversion table changed by the update control of the data is reflected in the address table, and the information on the physical address to be replaced in the block area in the super block held by the address table is updated. Motomeko 4 storage device according. The control circuit uses a plurality of management block areas to store the address table, and sequentially switches and uses the management block areas to store the address table, each time the address table is written. The control is performed to sequentially change a plurality of storage positions of the address table on the block area to be written, and the flag information indicating the storage position of the changed address table is updated on the block area to be written, When there is no more free space to write a new address table in the management block area, the management block area is deleted.
The storage device according to claim 6, wherein the control circuit detects that the management block area has been erased after the writing process as an execution timing of the replacement process.   The storage device according to claim 7, wherein the control circuit targets a physical address indicated by replacement target physical address information on the address table related to a super block that is a target of a rewrite process performed immediately before the replacement process.   8. The control circuit sets the physical address indicated by the replacement target physical address information on the address table related to the super block adjacent to the super block that is the target of the rewrite process performed immediately before the replacement process, as a replacement target. Storage device.   The storage device according to claim 9, wherein the adjacent super block shares a word line with a nonvolatile memory cell in the super block to be rewritten.   7. The storage device according to claim 6, wherein when the physical address corresponding to the acquired replacement target physical address information is an empty block, the control circuit updates the replacement target physical address information related to the super block and ends the replacement processing. . The address table has an address area for storing physical address information to be replaced in units of block areas in a plurality of super blocks, and a number area for storing the number of rewrite processing times of the block areas in the plurality of super blocks,
The control circuit increments the value of the number-of-times area related to the super block that is the target of the rewrite process in the rewrite process,
When detecting the execution timing of the replacement process, the control circuit acquires information on the replacement target physical address in block area units from the address table, and adds the logical address of the acquired replacement target physical address to the physical address of the current free block. And assigning the block area of the acquired replacement target physical address to a new empty block, exchanging data between the new empty block and the block area to which the new logical address is assigned, and data Controls updating, reflects the location of the address translation table changed by updating the data to the address table, and updates information on physical addresses to be replaced in block areas in a plurality of super blocks held by the address table You Memory device according to claim 4, wherein.   The storage device according to claim 12, wherein the control circuit detects that the value of the number-of-times area updated in the rewriting process has reached a predetermined value as an execution timing of the replacing process.   The storage device according to claim 13, wherein the control circuit targets a physical address indicated by replacement target physical address information on the address table related to a superblock that is a target of a rewrite process performed immediately before the replacement process.   13. The storage device according to claim 12, wherein when the physical address corresponding to the acquired replacement target physical address information is an empty block, the control circuit updates the replacement target physical address information related to the super block and ends the replacement process. .   The control circuit uses a plurality of management block areas to store the address table, and sequentially switches and uses the management block areas to store the address table, each time the address table is written. The control is performed to sequentially change a plurality of storage positions of the address table on the block area to be written, and the flag information indicating the storage position of the changed address table is updated on the block area to be written, 13. The storage device according to claim 12, wherein the management block area is erased when there is no more free area for writing the address table in the management block area. A storage device having a nonvolatile memory and a control circuit,
The non-volatile memory can be erased to initialize the memory information in a block area unit, which is a set of a plurality of non-volatile memory cells in which the memory information can be rewritten. Write processing to write information is enabled,
The control circuit allocates one free block and logical addresses to the remaining block areas in units of super blocks, which is a set of a plurality of block areas for data, and stores the latest address conversion table indicating the allocation. It is held in one block area where the last write processing is performed in the super block, and an address table indicating the physical address of the block area having the address conversion table in each super block is stored in the management block area.
When the control circuit responds to an access request from the outside, when the address table is not acquired, the control circuit reads the address table from the nonvolatile memory and corresponds to the super block to which the logical address related to the access request is assigned. When the address conversion table to be acquired is not acquired, the physical address of the address conversion table is searched from the acquired address table, and the address conversion table stored in the searched physical address is acquired from the nonvolatile memory and acquired. A storage device that acquires a physical address corresponding to a logical address related to the access request from an address conversion table and enables access control of a block area using the acquired physical address. A storage device having a nonvolatile memory and a control circuit,
The non-volatile memory is a set of a plurality of page areas in which a write process for writing the storage information in a page area unit, which is a set of a plurality of non-volatile memory cells that can rewrite the stored information, is possible. Erase processing that initializes stored information in block area units is enabled,
The control circuit allocates one free block and logical addresses to the remaining block areas in units of super blocks, which is a set of a plurality of block areas for data, and stores the latest address conversion table indicating the allocation. It is held in one block area where the last write processing is performed in the super block, and an address table indicating the physical address of the block area having the address conversion table in each super block is stored in the management block area.
When the control circuit responds to an access request from the outside, when the address table is not acquired, the control circuit reads the address table from the nonvolatile memory and corresponds to the super block to which the logical address related to the access request is assigned. When the address conversion table to be acquired is not acquired, the physical address of the address conversion table is searched from the acquired address table, and the address conversion table stored in the searched physical address is acquired from the nonvolatile memory and acquired. A storage device that acquires a physical address corresponding to a logical address related to the access request from an address conversion table and enables access control of a block area using the acquired physical address.

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