CN108121668B

CN108121668B - Memory mapping control device and control method

Info

Publication number: CN108121668B
Application number: CN201810014096.5A
Authority: CN
Inventors: 王雪春; 尤伟其; 倪永良
Original assignee: Huada Semiconductor Co ltd
Current assignee: Xiaohua Semiconductor Co ltd
Priority date: 2018-01-08
Filing date: 2018-01-08
Publication date: 2020-10-02
Anticipated expiration: 2038-01-08
Also published as: CN108121668A

Abstract

The invention relates to a memory mapping control device, comprising: an erasure control ERC module that receives an operation instruction for a non-volatile memory, the operation instruction including a ROM address; the initial loading ILD module is communicated with the erasing control ERC module, and when the chip is reset to remove the initial loading, the initial loading ILD module sends out the reading operation of the physical address of the memory for storing the erasing information and stores the mapping relation between the ROM address and the physical address of the memory; and a bus select BSL module that communicates with the erase control ERC module and the initialize load ILD module, and that receives information from the erase control ERC module or the initialize load ILD module based on the performed operation selection and outputs the received information.

Description

Memory mapping control device and control method

Technical Field

The present invention generally relates to the field of memory technologies, and more particularly, to a memory mapping control apparatus and a control method thereof.

Background

FLASH memory (FLASH) is a nonvolatile memory that can hold data for a long time without current supply. The storage unit of FLASH is a three-terminal device, and has the same name as the field effect transistor: source, drain and gate. The difference is that the field effect transistor is in a single-gate structure, the FLASH is in a double-gate structure, and a floating gate is added between the gate and the substrate. Fig. 1 shows a schematic structural diagram of a FLASH memory cell.

A silicon dioxide insulating layer is arranged between the floating gate and the silicon substrate and is used for protecting charges in the floating gate from leaking. Thus, the data in FLASH remains after power is turned off.

1) For programming of flash memory, i.e., control gate de-charging, the gate is pressurized such that the floating gate stores an increased amount of charge above the threshold value, which is denoted as data 0.

2) For erasing the flash memory, the floating gate is discharged by pressurizing the source, and when the charge is below the threshold, it is denoted as data 1.

The charge and discharge of the floating gate is actually the migration of electrons, and because the thickness of the silicon dioxide insulating layer is only 10 nanometers, the electron migration brings abrasion to the insulating layer each time. When the silicon dioxide insulating layer is damaged, electrons may be retained in the insulating layer, which causes the negative charge of the layer to increase continuously, thus affecting the correctness of FLASH storage data, and when the erasing times exceed the service life of the circuit, the FLASH storage function is lost. Structurally, the source levels of FLASH are commonly connected, so FLASH erase must be performed in units of blocks (hereinafter referred to as sectors).

The embedded FLASH is limited by the structure of the embedded FLASH, and the erasing frequency can only be between 10K and 100K generally. Therefore, there is a need in the art for an apparatus and a method for controlling erase of a rom, by which the increase of several times of the erase times can be achieved without changing the structure of the existing memory.

Disclosure of Invention

The task of the invention is to provide a memory mapping control device, comprising:

an erasure control ERC module that receives an operation instruction for a non-volatile memory, the operation instruction including a ROM address;

the initial loading ILD module is communicated with the erasing control ERC module, and when the chip is reset to remove the initial loading, the initial loading ILD module sends out the reading operation of the physical address of the memory for storing the erasing information and stores the mapping relation between the ROM address and the physical address of the memory; and

a bus select BSL module in communication with the erase control ERC module and the initialize load ILD module and that receives information from the erase control ERC module or the initialize load ILD module based on the performed operation selection and outputs the received information,

wherein, when the erasure control ERC module receives an erasure instruction, the erasure control ERC module is configured to:

determining a ROM address based on the erase instruction;

acquiring a mapping relation between a ROM address and a memory physical address from the initialization loading ILD module; and

and judging whether the nonvolatile memory is erased or not.

In one embodiment of the invention, the initialization load ILD module comprises an index register that stores a mapping of ROM addresses to memory physical addresses.

In one embodiment of the invention, the operation instruction is a read instruction, a program instruction, or an erase instruction; or judging whether the memory is erased or not according to whether all the sectors corresponding to the nonvolatile memory are full of data or not.

In one embodiment of the invention, when the erase control ERC module receives a read instruction or a program instruction, the erase control ERC module is configured to: determining a ROM address according to a received read instruction or a received programming instruction, acquiring a mapping relation between the ROM address and a memory physical address from the initialized loading ILD module, determining a memory physical address of a specific operation, and sending the memory physical address to a bus selection BSL module;

if the erasure control ERC module judges that the nonvolatile memory is erased, the erasure control ERC module sends an erasure instruction to a bus selection BSL module, and the bus selection BSL module sends the erasure instruction to an external memory controller;

and if the erasure control ERC module judges that the nonvolatile memory is not erased, outputting a programming instruction of the erasure number information address to obtain the mapping relation between the ROM address and the physical address of the memory when the chip resets and releases the initialization loading, and refreshing the mapping relation between the ROM address and the physical address of the memory stored in the initialization loading ILD module.

Another task of the present invention is to provide a nonvolatile memory control method, including:

receiving an operation instruction for a nonvolatile memory, wherein the operation instruction comprises a ROM address;

determining the mapping relation between the ROM address and the physical address of the memory;

when an erasing instruction is received, judging whether the nonvolatile memory is erased or not;

and if the nonvolatile memory is not erased, outputting a programming instruction of the erasing times information address, and refreshing the mapping relation between the ROM address and the memory physical address.

In another embodiment of the present invention, the method further comprises:

when the chip is reset and the initialization loading is removed, sending out the reading operation of the physical address of the memory for storing the erasing information, and storing the mapping relation between the ROM address and the physical address of the memory;

if the nonvolatile memory is erased, the erasing instruction is directly sent to a memory controller;

upon receiving a read or program instruction, the memory physical address of the particular operation is determined and sent to the memory controller.

It is a further object of the present invention to provide a memory circuit, comprising:

a ROM including at least one ROM space;

the nonvolatile memory (FLASH) comprises at least one sector, wherein each sector comprises a plurality of sub-sectors, n sub-sectors are used for storing data of the same ROM space, and n is more than or equal to 2;

and the memory mapping control device establishes an address mapping between one ROM space and one sub-sector of the n sub-sectors so as to store the data of the ROM space in the one sub-sector of the n sub-sectors.

In yet another embodiment of the present invention, a sector has n sub-sectors, and the n sub-sectors within a sector are used to store data for the same ROM space.

In yet another embodiment of the present invention, when an erase instruction is received in a ROM space, the memory map control means is configured to:

determining a ROM address based on the erase instruction;

acquiring a mapping relation between a current ROM address and a physical address of a nonvolatile memory; and

judging whether n sub-sectors corresponding to the ROM space are erased or not;

if the sector needs to be erased, n sub-sectors corresponding to the ROM space are erased, and after the sector is erased, the address of the ROM space points to the first unserviceable sub-sector in the n corresponding sub-sectors;

if the erasing is not needed, the address of the ROM space points to the next uninvolved sub-sector in the corresponding n sub-sectors;

judging whether n sub-sectors are erased or not according to whether n sub-sectors corresponding to one ROM space are commonly used or not;

when a ROM space receives a programming or read command, the memory map control device is configured to: the ROM space is mapped with the addresses of the sub-sectors that the ROM space points to.

In still another embodiment of the present invention, a memory map control apparatus includes:

a bus select BSL module in communication with the erase control ERC module and the initialize load ILD module and to receive information from the erase control ERC module or the initialize load ILD module based on the performed operation selection and to output the received information.

In yet another embodiment of the present invention, the memory circuit further includes: the bus controller is used for sending the instructions received by the ROM and the addresses of the ROM to the memory mapping control device, and the control circuit of the nonvolatile memory is used for operating the nonvolatile memory according to the mapping relation.

The embodiment of the invention realizes the increase of the erasing times by more than 10 times by adding an erasing times control module (SMC for short) in the FLASH control. The method of 'space exchange times' is used for obtaining more erasing times. The "space replacement count" is a count for replacing a relatively large number of times of erasing with a relatively large storage space (storage space of FLASH).

Drawings

To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.

FIG. 1 shows a schematic structural diagram of a FLASH memory cell;

FIG. 2 illustrates a comparison of memory circuits before and after an erase action occurs, according to one embodiment of the present invention;

FIG. 3 shows a schematic structural diagram of a memory circuit according to one embodiment of the present invention;

FIG. 4 illustrates the redefinition of the ROM address and FLASH physical address mapping relationship after SMC module intervention;

figure 5 illustrates a flow diagram for controlling a memory using an SMC module according to one embodiment of the invention.

Detailed Description

In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

In a Micro Control Unit (MCU) chip, there is a FLASH control circuit for receiving a command from a CPU to read and write a read-only memory (ROM) and outputting a FLASH read-write control signal. The updating of chip programs and data is done by programming and erasing the ROM. The number of erasures of the ROM depends entirely on the characteristics of the FLASH. When the data updating of the same address exceeds the specified times of FLASH, the correctness of FLASH storage data cannot be ensured by rewriting again.

FIG. 2 shows a comparison of memory circuits before and after an erase action occurs, according to one embodiment of the present invention. In fig. 2, each square at a ROM address represents a ROM space, and each square at a FLASH physical address represents a FLASH space (i.e., a sub-sector). As shown in fig. 2, the ROM of the MCU chip is 256 byte spaces (0000H to 00FFH, and 0000H to 00FFH indicate addresses corresponding to the respective spaces), and FLASH is physically configured with 16 × 256 byte spaces (0000H to 0 FFFH). The SMC module is provided with an index register and is used for storing the mapping relation between the ROM address and the FLASH physical address. When the ROM space (0000H 00FFH) is full of data, the user needs to issue an erase command to write again. After receiving an erasing instruction on the bus, the SMC module changes the mapping relation of addresses by modifying the numerical value of the index register and remaps the ROM address to the unused FLASH space. When the SMC receives the erasing command again after the 16 256-byte physical spaces are completely written, the hardware circuit executes a real erasing action, and at the moment, the ROM space remaps to the FLASH head address, or the ROM space remaps to any 256-byte physical address of the FLASH, and the process is repeated. When the FLASH physical space is configured with N times of ROM space, the number of times of erasing the ROM increases to N times. In other words, each ROM address corresponds to N FLASH physical addresses. In the embodiment shown in fig. 2, N is 16, and N256-byte spaces are one block, i.e., N256-byte spaces are one sector.

FIG. 3 shows a schematic diagram of a memory circuit according to an embodiment of the invention. As shown in fig. 3, the SMC module 300 is located between a bus control module (bus controller)200 and a FLASH controller (FLASH controller) 400. The SMC module 300 includes an initialize load ild (initial load) module 310, an erase control erc (eraasecontrol) module 320, and a bus select bsl (bus select) module 330. The operation of the initialize load ILD module 310, the erase control ERC module 320, and the bus select BSL module 330 is described below in conjunction with the overall chip action, including the index registers.

After the chip reset is released, i.e. the chip is started, the initial loading ILD module 310 sends out a FLASH address read operation for storing the erase information, and the FLASH address read operation is output to the FLASH controller 200 through the bus selection BSL module 330, and then the erase information is read and stored in the index register 311. Through the above operations, the SMC module 300 may further obtain a mapping relationship between the ROM address and the FLASH physical address.

When the CPU sends a read instruction or a program instruction to the ROM, the control signal is directly sent out to the FLASH controller 200 through the erase control ERC module 320 and the bus selection BSL module 330, and the address is mapped and converted by the index register and then synchronously output. Specifically, the erase control ERC module 320 receives a read instruction or a program instruction, determines a ROM address according to the received read instruction or program instruction, and then obtains a mapping relationship between the ROM address and a FLASH physical address from an index register in the initial load ILD module 310, thereby determining a FLASH physical address of a specific operation, and sends the FLASH physical address to the bus selection BSL module 330. The bus select BSL module 330 sends the FLASH physical address to the FLASH controller 200. The FLASH controller 200 operates the FLASH memory based on the physical address. The corresponding data is returned to the bus controller 100 directly after reading.

When the CPU issues an erase command to the ROM (as a unit in the ROM), the erase control ERC module 320 determines whether a real erase operation is required according to the value of the current index register, if so, the erase command is transmitted to the FLASH controller 200, otherwise, a program command to the erase frequency information address is output for the initial loading after the chip is reset and restarted, and the value of the index register is refreshed to point to the unused FLASH space. Hereinafter, a method of programming the erase count information address will be described in detail with reference to specific embodiments. Wherein, the real erasing action means that all sub-sectors in the corresponding sector are imposed, and then all sub-sectors in the corresponding sector are erased; a non-true erase operation (false erase operation) means that if there are more sub-sectors in the corresponding sector that are not expropriated, all sub-sectors in the corresponding sector need not be erased, but only the value of the index register needs to be pointed to the unused sub-sectors.

In the embodiment of the invention, the space of the FLASH physical head address can be used as the erasing time information storage space. Figure 4 shows a ROM address and FLASH physical address mapping diagram according to one embodiment of the invention. As shown in fig. 4, FLASH is physically 4 kbytes as one erase unit, the physical space is configured with 16 times of ROM space, and the 16 equally divided 256 byte spaces are first defined as sub-sector 0, sub-sector 1, sub-sector 2 to sub-sector 15. Wherein, the sub-sector 0 is used as an index sector for storing the erasing information of the other 15 sub-sectors, and one ROM space corresponds to one index register. Fig. 4 shows the redefinition of the mapping relationship between the ROM address and the FLASH physical address after the SMC module is involved.

In fig. 4, action (r) represents that the SMC module reads the index sub-sector data; action two represents that the SMC module decodes the ROM address so as to find a corresponding index register; action c represents determining the mapping relationship according to the value of the index register.

Those skilled in the art can set the mapping rule between the value of the index register and the sub-sector address according to the actual size of the index register, the size of the FLASH memory space, and the like. Table 1 below shows a sub-sector mapping rule according to one embodiment of the present invention. However, those skilled in the art will appreciate that table 1 is merely an exemplary embodiment and that the scope of the present invention is not limited thereto. In other embodiments of the present invention, other sub-sector mapping rules may be used. It is within the scope of the present invention to determine the sub-sector mapping rule of the information of the currently explicated sub-sectors, the explicated sub-sectors, and the non-explicated sub-sectors according to the data stored in the sub-sectors.

TABLE 1 sub-sector Address mapping Table

A sub-sector mapping rule according to an embodiment of the present invention is described in detail in conjunction with fig. 4 and table 1. As shown in fig. 4, the FLASH memory space includes 16 sub-sectors, where sub-sector 0 is an index sub-sector and is used to store the erasure information of the remaining 15 sub-sectors. The sub-sector currently being recruited is represented by a 14-bit numerical value of the index sub-sector. Indicating with the data 0 bit indexing the sub-sector from left to right 1 st address whether sub-sector 1 is being levied (high data is not significant): a value of 1 indicates that sub-sector 1 is not solicited; a value of 0 indicates that sub-sector 1 has been imposed. The data 0 bit indexing the 2 nd address of sub-sector indicates whether sub-sector 2 is being expropriated: a value of 1 indicates that sub-sector 2 is not solicited; a value of 0 indicates that sub-sector 2 has been imposed. By analogy, indexing the 14 th address data bit of a sub-sector 0 indicates whether sub-sector 15 is being recruited.

When the CPU issues a program or read instruction to the ROM, the SMC module maps the ROM address to the corresponding sub-sector according to the value of the index register. For example, when the value obtained from the index register corresponding to a ROM address is 11_1111_1111_1111, the mapping is sub-sector 1, and a program or read instruction is performed on sub-sector 1.

When the CPU sends an erasing instruction to the ROM, the SMC module programs and writes 0 to the first uninvolved index sub-sector address according to the value of the index register, and updates the value of the index register to enable the CPU to point to the next sub-sector. When the SMC finds that all sub-sectors within a sector have been explicuted, the SMC performs a true erase operation on the entire 4 kbyte space (the minimum unit of erase, i.e., a sector), including indexing the sub-sector data to also be cleared to 1. When all the sub-sectors in one sector are imposed, the sector is erased, which is beneficial to reducing the erasing times of each FLASH and improving the service time of the FLASH.

For example, when the CPU issues an erase instruction to the ROM, if the value obtained from the index register corresponding to one ROM address is 11_1111_1111_1111, the mapped sub-sector is sub-sector 1, and the value obtained from the index register corresponding to one ROM address is programmed and written to 11_1111_1110, so that the sub-sector mapped to one ROM address is sub-sector 2, and when there is a program or read instruction, the sub-sector 2 is programmed or read, and the erase instruction at this time is not a real erase operation; when a CPU sends an erasing instruction to a ROM, if the value obtained from the index register corresponding to a ROM address is 00_0000_0000_0000 or more (the value not listed in Table 1), the corresponding sector is completely erased, the value obtained from the index register corresponding to a ROM address is programmed and written to 11_1111_1111_1111, the sub-sector mapped by a ROM address is newly made to be the sub-sector 1, and the sub-sector 1 is programmed or read when a programming or reading instruction exists, and the erasing instruction at this time is a real erasing action.

And if the system is reset, the SMC module reads the index sub-sector data again and stores the index sub-sector data in the index register. And the address mapping relation can be correctly executed after the chip is reset and restarted.

In one embodiment of the present invention, when the index register has an irregular sequence (the lowest row in table 1), the SMC module outputs an error flag and an interrupt request, which informs the user that an erase command should be issued to ensure that the system is operating correctly. Although the user can operate the index register on the ROM according to the manual instruction without irregular sequence, the functional addition can help to improve the stability of the chip.

First, at step 510, the chip reset is released. Through this step, the chip is activated, and then, a read operation, a program operation, and an erase operation may be performed on the chip.

The erase count information is read and saved in the index register at step 520.

In step 530, when a read instruction is received, the ROM address is determined according to the received read instruction, and then the mapping relationship between the ROM address and the FLASH physical address is obtained from the index register in the initial loading ILD module, so as to determine the FLASH physical address of the specific operation, and the FLASH physical address is sent to the bus selection BSL module. The bus selection BSL module sends the FLASH physical address to the FLASH controller, and the FLASH controller controls reading of the corresponding data in the FLASH physical address, step 531.

In step 540, when a programming instruction is received, a ROM address is determined according to the received programming instruction, then a mapping relationship between the ROM address and a FLASH physical address is obtained from an index register in the initialized loading ILD module, so as to determine a FLASH physical address for a specific operation, the FLASH physical address is sent to the bus selection BSL module, the bus selection BSL module sends the FLASH physical address to the FLASH controller, the FLASH controller controls to program corresponding data in the FLASH physical address, and step 541.

When an erase command is received, step 550, it is determined whether to perform a real erase operation according to the value in the current index register, step 551. If a true erase operation is required, an erase command is sent to the memory controller in step 552. If a true erase operation is not required, a program command for the address of the erase count information is output in step 553 to prepare for an initial load after a reset restart of the chip and to flush the index register value to point to an unused memory space.

The memory control device and the memory control method can increase the erasing times by multiple. The size of the memory can be configured as desired. Although the above embodiment of the present invention has been described by taking FLASH as an example, it should be understood by those skilled in the art that the scope of the present invention is not limited to FLASH, and any memory capable of storing data when power is down may store the erase time information, for example, the memory capable of storing data when power is down may also be an EPROM. Therefore, the memory mapping control device and the control method disclosed by the invention are suitable for various types of nonvolatile memories. According to the memory control device and the control method disclosed by the invention, the same address of the ROM is mapped to different physical addresses of the FLASH through hardware circuit processing.

In some embodiments of the present invention, the erase times information may also be saved using redundant bits of FLASH. For example, the general 1 FLASH physical address is 8 bits, 1 FLASH of 9 bits is customized, and the erasure count information is stored in the 9 th bit. In other words, unlike the case of using a separate sub-sector for holding the erasure count information shown in fig. 4, in this embodiment, there is no separate sub-sector for holding the erasure count information in the entire storage space, and each sub-sector has an erasure count information storage area for exclusively holding the erasure count information.

While several embodiments of the present invention have been described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous variations, substitutions and modifications will occur to those skilled in the art without departing from the scope of the invention. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.

Claims

1. A memory map control device, comprising:

determining a ROM address based on the erase instruction;

determining whether to erase the non-volatile memory,

when the erase control ERC module receives a read instruction or a program instruction, the erase control ERC module is configured to: determining a ROM address according to a received read instruction or a received programming instruction, acquiring a mapping relation between the ROM address and a memory physical address from the initialized loading ILD module, determining a memory physical address of a specific operation, and sending the memory physical address to a bus selection BSL module;

2. The memory mapping control device of claim 1, wherein the initial load ILD module comprises an index register storing a mapping of ROM addresses to memory physical addresses; the nonvolatile memory is FLASH; the nonvolatile memory comprises at least one sector, each sector comprises a plurality of sub-sectors, n sub-sectors are used for storing data of the same ROM space, and n is larger than or equal to 2.

3. The memory mapping control device of claim 1, wherein the operation instruction is a read instruction, a program instruction, or an erase instruction; or judging whether the nonvolatile memory is erased or not according to whether all the sectors corresponding to the nonvolatile memory are full of data or not.

4. A non-volatile memory control method, comprising:

when an erasing instruction is received, judging whether the nonvolatile memory is erased or not, wherein the nonvolatile memory is FLASH; the nonvolatile memory comprises at least one sector, each sector comprises a plurality of sub-sectors, n sub-sectors are used for storing data of the same ROM space, and n is larger than or equal to 2, wherein whether n sub-sectors are erased or not is judged according to whether n sub-sectors corresponding to one ROM space are used or not;

5. The method of claim 4, further comprising:

6. A memory circuit, comprising:

a ROM including at least one ROM space;

the nonvolatile memory comprises at least one sector, wherein each sector comprises a plurality of sub-sectors, n sub-sectors are used for storing data of the same ROM space, and n is more than or equal to 2;

a memory map control means for establishing an address map of a ROM space and one of the n sub-sectors to store data of the ROM space in the one of the n sub-sectors,

when an erase command is received in a ROM space, the memory map control means is configured to:

determining a ROM address based on the erase instruction;

judging whether n sub-sectors corresponding to the ROM space are erased or not;

7. The memory circuit of claim 6, wherein a sector has n sub-sectors, the n sub-sectors within a sector being for storing data of the same ROM space; the nonvolatile memory is FLASH.

8. The memory circuit of claim 6, wherein the memory map control means comprises:

9. The memory circuit of claim 6, wherein the memory circuit further comprises: the bus controller is used for sending the instructions received by the ROM and the addresses of the ROM to the memory mapping control device, and the control circuit of the nonvolatile memory is used for operating the nonvolatile memory according to the mapping relation.