CN111061649B - Storage space self-adaptive allocation method of memory - Google Patents
Storage space self-adaptive allocation method of memory Download PDFInfo
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- CN111061649B CN111061649B CN201911028035.5A CN201911028035A CN111061649B CN 111061649 B CN111061649 B CN 111061649B CN 201911028035 A CN201911028035 A CN 201911028035A CN 111061649 B CN111061649 B CN 111061649B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to a self-adaptive distribution method of storage space of a memory, dividing all sectors of each storage chip in the memory into a data area and a mark area, after reading information of each storage chip one by one, mapping a hardware address space of an actual data area of each storage chip into a logic address space, and mapping the mark area of each storage chip into a mark space address table; performing an erase operation for the sector that is displayed to be not erased, and updating a flag byte of the sector in a flag space for the sector in each memory chip that has been performed with the erase operation; setting a data initial address which needs to be written into a memory chip as a logic address of the memory chip; taking all the existing data of the sector to be written and the data to be written together as final data of the sector to be written; the microcontroller erases sector data or directly writes final data into the sector according to whether the sector in the memory chip is erased or not, so that the memory chip is prevented from being erased repeatedly, and the service life of the memory is prolonged.
Description
Technical Field
The present invention relates to the field of memories, and in particular, to a method for adaptively allocating a memory space of a memory.
Background
In embedded products, big data processing applications are increasingly being used. The memory in the product is frequently used due to the need to process large data. For example, memory is frequently used to log, save freeze data, record fault information, and the like. The current application operation for the memory mainly comprises a read-write operation and an erase operation for data, and meanwhile, due to the limitation of the maximum erasing times (generally 10 ten thousand times) of the memory, how to optimize the application operation of the memory so as to prolong the service life of the memory is more and more important.
In order to effectively save the storage space of the memory, the existing memory mainly follows the frequently executed erasing and reading and writing operation for data, the frequently executed erasing-reading and writing operation belongs to a simple repeated process, the direct targeting is to the physical hardware address of the memory chip, and the erasing frequency are basically determined by the writing frequency and the writing frequency. In this way, it is necessary to perform repeated erasing operations very frequently, which not only reduces the space use efficiency of the memory, but also greatly shortens the service life of the memory.
Disclosure of Invention
The invention aims to provide a storage space self-adaptive allocation method of a memory aiming at the prior art.
The technical scheme adopted for solving the technical problems is as follows: the self-adaptive memory space allocation method for the memory is suitable for the memory with a microcontroller and a plurality of memory chips, and is characterized by comprising the following steps of:
step 1, dividing the storage space of each storage chip in the memory into a data area and a marking area; the memory chip is provided with N sectors, the data area occupies the first N-1 sectors of the memory chip, and the marking area occupies the last sector of the memory chip; n is more than or equal to 2, and N is E R;
step 2, after the memory chips are electrified, reading the information of each memory chip one by one according to the enabling sequence from small to large; wherein the memory chip information at least comprises the space size of the memory chip;
step 3, according to the read information of each memory chip, mapping the hardware address space of the actual data area of each memory chip into a logic address space, and mapping the mark area of each memory chip into a mark space address table;
step 4, reading the mark space address table, and executing erasing operation for the sector which is displayed to be not erased in the mark space address table;
step 5, updating the flag byte of the sector in the flag space for the sector which has been subjected to the erasing operation in each memory chip;
step 6, setting a data initial address to be written into the memory chip as a logic address of the memory chip according to the mapping relation between the hardware address space and the logic address space in the memory chip;
step 7, reading all the existing data of the sector to be written in the memory chip, and taking the all the existing data and the data to be written in the memory chip as final data of the sector to be written;
step 8, the microcontroller in the memory makes a judgment as to whether the sector in the memory chip has performed an erase operation:
when all hardware addresses in the sector change, the data of the sector are erased; otherwise, the final data is directly written into the sector.
In order to solve the problem that the final data to be written involves two sectors in the same memory chip, as an improvement, in the memory space adaptive allocation method of the present invention, when the final data to be written in the memory chip involves two sectors thereof, the erasing operation judgment of step 8 is performed for each sector, so as to perform erasing of the data in the sector or directly write the final data into each sector according to the judgment result.
In order to solve the problem that the final data to be written involves two front and rear memory chips, as an improvement, in the memory space adaptive allocation method of the present invention, when the data to be written is in the two front and rear memory chips, the following operations are performed:
the method comprises the steps of respectively obtaining the capacity and the initial address of each of a front storage chip and a rear storage chip;
and (3) according to the capacity and the initial address of each memory chip, respectively executing writing operation on the last sector of the previous memory chip and the first sector of the next memory chip, and then executing the judgment of the erasing operation in the step (8) so as to execute the data in the erasing sector or directly write the data to be written into each sector according to the judgment result.
Specifically, in the storage space adaptive allocation method of the memory, the flag byte after sector update is 0x55.
In the self-adaptive storage space allocation method of the memory, each storage chip has 256 sectors; the 1 st to 255 th sectors are occupied by the data area, and the 256 th sector is occupied by the mark area.
Further, in the storage space self-adaptive allocation method of the memory, the microcontrollers of the memory chips are respectively connected with the memory chips through SPI ports.
Further improved, the microcontroller controls the read-write or erasing operation of each memory chip through a chip selection signal.
Preferably, in the method for adaptively allocating the storage space of the memory, in step 8, the microcontroller of the memory determines whether all hardware addresses in a sector of the memory chip change according to a bit-by-bit comparison of the write addresses.
Furthermore, in the storage space adaptive allocation method of the memory, the storage chip information further includes manufacturer information of the storage chip.
Specifically, in the storage space adaptive allocation method of the memory, the memory is a memory of an embedded product.
Compared with the prior art, the invention has the advantages that:
firstly, the storage space self-adaptive allocation method for the memory does not need to limit the number and the storage capacity of the memory chips in the memory, can realize the compatibility of a plurality of memory chips, and can also realize the self-adaptive detection of whether the over-erasing operation is executed for each sector in the memory chips;
secondly, after the initialization is executed for any sector in the memory chip, based on the self-adaptive detection result, the initialization operation is not repeatedly executed for the initialized sector, so that the sector initialization efficiency in the memory chip is effectively improved;
finally, whether the over-erasing operation is executed on each sector in the memory chip is detected, and only the data to be written is written into the memory chip which does not execute the writing operation, so that the erasing times of the memory chip are reduced, and the service life of the memory is prolonged.
Drawings
Fig. 1 is a flow chart of a method for adaptively allocating storage space of a memory according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the embodiments of the drawings.
As shown in fig. 1, the present embodiment provides a method for adaptively allocating a memory space of a memory, which is suitable for a memory having a microcontroller and a plurality of memory chips. The memory selected in the embodiment is a memory of an embedded product; the microcontroller of the memory chip is respectively connected with the memory chip through SPI ports; the microcontroller controls the read-write or erasing operation of each memory chip through the chip selection signal. Specifically, the storage space adaptive allocation method of the memory in this embodiment includes the following steps:
step 1, dividing the storage space of each storage chip in a memory into a data area and a marking area; the method comprises the steps that a storage chip is provided with N sectors, a data area occupies the first N-1 sectors of the storage chip, and a marking area occupies the last sector of the storage chip; n is more than or equal to 2, and N is E R;
for example, according to the above description, it is assumed that each memory chip has 256 sectors; wherein, the 1 st to 255 th sectors are occupied by the data area, and the 256 th sector is occupied by the mark area;
step 2, after the memory chips are electrified, reading the information of each memory chip one by one according to the enabling sequence from small to large; the memory chip information at least comprises the space size of the memory chip; of course, the read information of the memory chip may further include manufacturer information of the memory chip;
step 3, according to the read information of each memory chip, mapping the hardware address space of the actual data area of each memory chip into a logic address space, and mapping the mark area of each memory chip into a mark space address table; wherein, according to the mapping relation, each hardware address corresponds to a logic address in a hardware address space and a logic address space; likewise, the tag area of each memory chip also has an address in the tag space address table;
step 4, reading the mark space address table, and executing erasing operation for the sector which is displayed to be not erased in the mark space address table;
step 5, updating the flag byte of the sector in the flag space for the sector which has been subjected to the erasing operation in each memory chip; for example, in the present embodiment, for a sector for which an erase operation has been performed, its updated flag byte is adjusted to 0x55;
step 6, setting a data initial address to be written into the memory chip as a logic address of the memory chip according to the mapping relation between the hardware address space and the logic address space in the memory chip;
step 7, reading all the existing data of the sector to be written in the memory chip, and taking the all the existing data and the data to be written in the memory chip as final data of the sector to be written;
step 8, the microcontroller in the memory makes a judgment as to whether the sector in the memory chip has performed an erase operation:
when all hardware addresses in the sector change, the data of the sector are erased; otherwise, the final data is directly written into the sector. In step 8 of this embodiment, the microcontroller of the memory determines whether all hardware addresses in the sector of the memory chip change according to the bit-by-bit comparison of the write addresses. That is, the microcontroller of the memory judges whether or not it has changed according to the write address one by one for all the hardware addresses in the sector, thereby avoiding missing part of the changed hardware addresses.
In addition, in order to solve the problem that the final data to be written involves two sectors in the same memory chip, the adaptive allocation method for the memory space of the memory in this embodiment is further improved by performing the erase operation judgment of step 8 for each sector when the final data to be written in the memory chip involves two sectors thereof, so as to perform the data in the erased sector according to the judgment result or directly write the final data in each sector.
Of course, the problem that the final data to be written involves two memory chips is also encountered in the writing process, and the audience rating is improved. Specifically, for this case:
when the data to be written are in the front and rear memory chips, respectively acquiring the respective capacities and initial addresses of the front and rear memory chips; and (3) according to the capacity and the initial address of each memory chip, respectively executing writing operation on the last sector of the previous memory chip and the first sector of the next memory chip, and then executing the judgment of the erasing operation in the step (8) so as to execute the data in the erasing sector or directly write the data to be written into each sector according to the judgment result.
While the preferred embodiments of the present invention have been described in detail, it is to be clearly understood that the same may be varied in many ways by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. The self-adaptive memory space allocation method for the memory is suitable for the memory with a microcontroller and a plurality of memory chips, and is characterized by comprising the following steps of:
step 1, dividing the storage space of each storage chip in the memory into a data area and a marking area; the memory chip is provided with N sectors, the data area occupies the first N-1 sectors of the memory chip, and the marking area occupies the last sector of the memory chip; n is more than or equal to 2, and N is E R;
step 2, after the memory chips are electrified, reading the information of each memory chip one by one according to the enabling sequence from small to large; wherein the memory chip information at least comprises the space size of the memory chip;
step 3, according to the read information of each memory chip, mapping the hardware address space of the actual data area of each memory chip into a logic address space, and mapping the mark area of each memory chip into a mark space address table;
step 4, reading the mark space address table, and executing erasing operation for the sector which is displayed to be not erased in the mark space address table;
step 5, updating the flag byte of the sector in the flag space for the sector which has been subjected to the erasing operation in each memory chip;
step 6, setting a data initial address to be written into the memory chip as a logic address of the memory chip according to the mapping relation between the hardware address space and the logic address space in the memory chip;
step 7, reading all the existing data of the sector to be written in the memory chip, and taking the all the existing data and the data to be written in the memory chip as final data of the sector to be written;
step 8, the microcontroller in the memory makes a judgment as to whether the sector in the memory chip has performed an erase operation:
when all hardware addresses in the sector change, the data of the sector are erased; otherwise, the final data is directly written into the sector; when the data to be written is in the front and back memory chips, the following operations are executed:
the method comprises the steps of respectively obtaining the capacity and the initial address of each of a front storage chip and a rear storage chip;
and (3) according to the capacity and the initial address of each memory chip, respectively executing writing operation on the last sector of the previous memory chip and the first sector of the next memory chip, and then executing the judgment of the erasing operation in the step (8) so as to execute the data in the erasing sector or directly write the data to be written into each sector according to the judgment result.
2. The method according to claim 1, wherein when the final data to be written into the memory chip involves two sectors, the judgment of the erase operation in step 8 is performed for each sector, respectively, so as to erase the data in the sector or directly write the final data into each sector according to the judgment result.
3. The method for adaptively allocating memory space according to claim 1 or 2, wherein the flag byte after sector update is 0x55.
4. The method for adaptively allocating a memory space of a memory according to claim 1 or 2, wherein each of the memory chips has 256 sectors; wherein, the 1 st to 255 th sectors are occupied by the data area, and the 256 th sector is occupied by the mark area.
5. The method for adaptively allocating the memory space of the memory according to claim 1 or 2, wherein the microcontrollers of the memory chips are respectively connected with the memory chips through SPI ports.
6. The method of claim 5, wherein the microcontroller controls the read-write or erase operation of each memory chip by a chip select signal.
7. The method according to claim 1, wherein in step 8, the microcontroller of the memory determines whether all hardware addresses in the sector of the memory chip have changed according to a bit-by-bit comparison of the write addresses.
8. The method for adaptively allocating memory space of claim 1, wherein said memory chip information further comprises manufacturer information of the memory chip.
9. The method for adaptively allocating memory space of a memory according to claim 1, wherein the memory is a memory of an embedded product.
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| CN113515070A (en) * | 2021-07-12 | 2021-10-19 | 珠海格力电器股份有限公司 | Motor equipment address processing method and device, storage medium and motor controller |
| CN113568579B (en) * | 2021-07-28 | 2022-05-03 | 深圳市高川自动化技术有限公司 | Memory, data storage method and data reading method |
| CN114115743A (en) * | 2021-11-29 | 2022-03-01 | 苏州迅镭激光科技有限公司 | Method for prolonging service life of data storage chip |
| CN114296634B (en) * | 2021-12-03 | 2024-01-30 | 珠海格力电器股份有限公司 | Method and device for detecting and storing and distributing memory resource utilization rate |
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