JPH1049447A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the size of a memory that is necessary for conversion of both addresses and also to shorten the longest access time in a semiconductor memory device which is unable to secure the 1:1 correspondence between the logical addresses and the physical addresses of a memory since the presence of a faulty block is allowed. SOLUTION: For instance, good blocks of a flash memory are divided every 1,000 pieces into 16 blocks, and the logical addresses 0 to 999 and 1,000 to 1,999 are allocated in the 1st and 2nd groups respectively. Then 0, 1,000, 2,000... are defined as a system with 1, 1,001 and 2,001... defined as another system and so on, and the logical addresses are divided into 1,000 systems. The logical address allocated to the relevant blocke and the position information on the next block are written into the physical blocks corresponding to the same system, so that the chain groups are formed. The blocks can be successively retrieved at and after the head one of them when a specific chain group where the relevant logic address belongs is known.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory in which a memory area is divided into a plurality of physical blocks, for example, a flash memory, and a memory for retrieving a physical address based on a logical address managed by a main controller. The present invention relates to a semiconductor memory device having a control unit.

[0002]

2. Description of the Related Art Attempts have been made to use a semiconductor hard disk instead of a mechanical hard disk. The mechanical hard disk has more in terms of price and capacity, but the semiconductor hard disk has more in terms of speed, power consumption, shock resistance, vibration resistance, weight, size and noise. DRAM as a semiconductor hard disk
Although the use of a flash memory or an SRAM has been considered, recently, a flash memory (EEPROM: Electr
ially Erasable Programmab
le ROM) is attracting attention. The reason is that the flash memory does not require a battery backup, and has the advantages that the element structure is simple, the degree of integration can be easily increased, and mass production can be performed at low cost.

A flash memory divides a memory area into a plurality of blocks (areas), and each block includes a data area and a redundant area. The data area is an area in which data is written, and the redundant area is an area in which management information such as ECC code for detecting and correcting an error occurring in the data and an error occurring in the data is written. Further, since the flash memory is a batch erasure type electrically rewritable element, overwriting cannot be performed, and writing cannot be performed unless the block has been erased. For example, the write unit is 264 bytes to 528 bytes, and the erase unit is 528 bytes to 64 kbytes.

[0004] In addition, some of the blocks are defective from the time of manufacture. In addition, since the number of times of erasing and writing is finite, acquired failures may occur. As described above, information on good or bad is stored. A spare block is prepared in the block group, and when a certain block becomes defective, the logical address assigned to that block is transferred to the spare block. As described above, since the flash memory allows a bad block, the number of logical addresses managed by the host computer, for example, the personal computer, is larger than the number of physical addresses (positional information of the physical blocks) of the flash memory. It is necessary to have a small relationship and to have a function of substituting a block whose life has expired.

From the above, the following method is known as a method of accessing a physical block based on a logical address.

(1) As one method, as shown in FIG. 8, a table 11 for converting a logical address into a physical address related to a usable block while avoiding a bad block is used. That is, when writing data to a physical block in the flash memory 13, the memory controller 12 provided in the memory disk 1 writes the logical address assigned to the physical block in a redundant area of the physical block, When starting a computer to which is applied, referring to the redundant area of each physical block, grasping which logical address the physical block corresponds to, and indicating the correspondence between the physical address and the logical address The table 11 is created. Therefore, even if a certain physical block is defective and a substitute physical block is used for the physical block, the physical address corresponding to the logical address can be immediately known by referring to this table 11, so that the conversion between the logical address and the physical address is performed. Can be performed at high speed.

(2) As another method, as shown in the conceptual diagram of FIG. 9, a logical address is associated with a physical address on a one-to-one basis. The replacement physical block is used for any of the defective physical blocks of the congenital failure and the acquired failure, and the physical block corresponding to the logical address is accessed once. If the physical block is defective, the replacement physical block is sequentially searched.

[0008]

Since the number of blocks tends to increase due to an increase in the address capacity, the above (1)
The conversion table method described in (1) requires a large-capacity RAM for storing the conversion table, and the conversion table must be written each time the computer is started up. Since a long time is required for writing, the waiting time becomes long.

The linear address method described in the above (2) has an advantage that a large-capacity RAM does not have to be used even if the number of blocks is large. However, when the allocated physical block is defective, the spare block is sequentially replaced. It is necessary to search for a substitute block, and the access time may be extremely long. For example, there may be a case where the data transfer speed cannot be kept up with the continuous data transfer speed of the camera.

The present invention has been made under such circumstances, and has as its object to reduce the size of a memory required for conversion between a logical address and a physical address, and to provide a semiconductor memory having a shortest access time. It is intended to provide a device.

[0011]

According to the present invention, a memory area is divided into a plurality of physical blocks, and each physical block has a data block.
A semiconductor memory including a data area and a redundant area, and a memory control unit that searches for a physical block corresponding to a logical address managed by the main control unit with reference to the redundant area. It is characterized by being constituted as follows. a. The redundant area of the physical block includes a first area in which a logical address assigned to the physical block is written and a second area in which position information described later is written. b. A logical address is divided into a plurality of systems, and a group of physical blocks to which logical addresses belonging to the same system are assigned is formed as a chain group. c. In each concatenated group of physical blocks, (k
The position information of the (+1) -th physical block is written. d. The memory control unit determines to which system the logical address to be searched belongs, and searches the logical address in order from the first physical block of the chain group of the physical blocks corresponding to the system, and finds the k-th physical block. If the logical address is assigned to the physical block, the physical block is accessed, and if not, the second area of the k-th physical block is referred to (k + 1).
It has a function of searching for the physical block of the number.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a semiconductor memory device according to an embodiment of the present invention, a logical address managed by a main control unit such as a host computer is divided into a plurality of systems, and a logical address of each system is divided into a semiconductor memory such as a flash memory. It is characterized in that a group of physical blocks to which logical addresses belonging to the same system are allocated is formed as a chained group, while being allocated to non-defective blocks (non-defective physical blocks) of the memory. For example, if m logical addresses are grouped into one system and divided into a first system, a second system,.
Of the m physical blocks of the flash memory corresponding to each system, the first block describes the position information of the second block, the second block describes the position information of the third block, and so on. The position information of the m-th block is written in the (m-1) -th block. If the position information of the first block is known in this way, the blocks are linked so that the blocks can be sequentially traced.

The total number of blocks is, for example, 16384,
A description will be given of a semiconductor memory device using a flash memory having a maximum number of defective blocks of, for example, 327 and a logical address number of, for example, 16,000. In flash memory, good blocks of flash memory are
The 1000 blocks are divided into 16 groups as one group, and the remaining good blocks are left as spare blocks for replacement. FIG. 1 is an explanatory view conceptually showing a state in which logical addresses are allocated to each block of the flash memory. Logical addresses 0 to 999 are allocated to a first group, and logical addresses 1000 to 1999 are allocated to a second group. Assigned, logical address 2000 to 299
9 to the third group,... 150 logical addresses
00 to 15999 are assigned to the 16th group. In FIG. 1, a solid line frame indicates a physical block, and a number in the frame indicates a logical address.

In this example, the horizontal arrangement of logical addresses corresponds to logical addresses of the same system. That is, 0, 100
The logical addresses 0, 2000, 3000,... 15000 belong to the first system, and 1, 1001, 2001, 3001
The logical address of 15001 belongs to the second system, and 99
9, 1999, 2999,... 15999 belong to the 1000th system. In a group of physical blocks to which logical addresses belonging to the same system are allocated, for example, in 16 physical blocks to which logical addresses of the first system are allocated, one group of physical blocks indicates the positions of two groups of physical blocks. Position information (physical addresses) is written in advance, three groups of physical addresses are written in two groups of physical blocks, and 16 groups of physical addresses are written in 15 groups of physical blocks. This is the same for other systems.

For such a chain of physical blocks,
2, the physical block of the flash memory includes a data area for writing data and a redundant area for writing management information of the physical block. The redundant area includes a first area for writing a logical address assigned to the physical block and a second area for writing position information (physical address) of a physical block belonging to a group next to a group related to the physical block. With
Further, it includes an area for writing ECC and the like for error detection at the time of data reading, an area for writing information on the quality of a physical block, and the like.

In FIG. 2, for convenience, if a code preceded by "A" is a physical address, a logical address previously assigned to the physical block is written in a first area of a redundant area of a non-defective physical block. I have. In this example, a physical block whose physical address starts from A0 and extends to A15999 is used as a main memory area. A0 is assigned a logical address 0, A1 is assigned a logical address 1,... A15999 is assigned a logical address 15999, and A1999 is assigned a logical address 15999.
The physical blocks after 6000 are set as spare blocks.

In the second area of the redundant area of the physical block (A0) of the first group to which the logical address 0 is allocated, the physical address to which the logical address 1000 of the second group is allocated, that is, A1000 is written. In the second area of the redundant area of the physical block (A1000) of the second group to which the logical address 1000 is assigned, the physical address of the third group to which the logical address 2000 is assigned, that is, A2000 is written. That is, logical addresses 0, 1000, 2000... 15
000 belongs to the first system, the physical blocks A0 and A100 to which the logical addresses of the first system are assigned.
In the second area of the redundant area of 0, A2000... A15000, the address of the next physical block of each physical block is written.

Here, the memory controller described later does not know the physical address relating to the first system,
If it is known that the address of the first physical block is A0, the position of the 16 physical blocks forming the chained group can be grasped by sequentially following the second area. Although the first system has been described as an example, the same applies to each system after the second system.

Next, the hardware configuration of the semiconductor memory device according to the present embodiment will be described with reference to FIG.
Reference numeral 2 denotes a memory disk corresponding to a semiconductor memory device. The memory disk 2 includes a plurality of flash memories 3 configured as described above, a memory controller 4 as a memory control unit, and an address table 5.
The memory controller 4 is connected to the host computer 6 as a main control unit via the interface 21, and writes data sent from the host computer 6 to a physical block of the flash memory 3 corresponding to a logical address related to the data. The host computer 6 has a function of reading data in the flash memory 3 corresponding to the logical address specified by the host computer 6 and sending the data to the host computer 6.

The memory controller 4 includes an arithmetic unit 41, a search unit 42, and a processing unit 4 as functional blocks.
3 is provided. The arithmetic unit 41 is a host computer 6
Has a function of calculating which system the logical address specified by the side belongs to. In the example shown in FIGS. 1 and 2, the logical address number is divided by the number of systems and the remainder is obtained. Thus, the system number is obtained. For example, if the logical address number is 500
If it is 9, the remainder is 9 by dividing by the number of systems of 1000, so the system number is 9.

The address table 5 is a table indicating which physical block address of one group of the flash memory 3 corresponds to the system number of the logical address, and is stored in, for example, a RAM. However, the search unit 42 obtains the address of one group of physical blocks of the flash memory 3 corresponding to the system number obtained by the arithmetic unit 41 with reference to the address table 5, and searches the logical addresses in order from the address of the physical block. It has a function to do. This search is processing for finding a physical block assigned to a logical address by following the position information of the second area sequentially from one group of physical blocks as described above.

After the search unit 42 finds a physical block corresponding to the logical address, the processing unit 43 writes the data sent from the host computer 6 into the data area of the physical block, And has a function of reading data from the data area.

The operation of such a semiconductor memory device will be described. The logical address assigned to the non-defective physical block of the flash memory 3 is written in the first area, and the position information (physical address) of the next physical block is written in the second area in advance. When control is performed using a computer, the reading speed is more problematic than the data writing speed, and one advantage of this embodiment is that the reading speed can be increased. Will be described with reference to FIGS. 4 and 5. FIG.

Assuming that a command to write data to a certain logical address n is sent from the host computer 6 to the memory disk 2 as shown in step S1 in FIG.
To which system belongs to by calculation. For example, if n is 2002 in the example of FIG.
The remainder obtained by dividing by 00 is 2, which indicates that the logical address n belongs to the system number 2.

The address of the physical block of the first group of the flash memory 3 corresponding to the system number is obtained by the search unit 42 with reference to the address table 5 (step S3). Since a plurality of flash memories 3 are actually provided, a flash memory corresponding to a system number of a logical address and an address of a physical block in the flash memory are obtained. Handle as one. Then, referring to the first area of the redundant area in order from the first physical block of the chain group of the physical blocks corresponding to the system number, the physical block to which the logical address n is assigned is searched. This search is performed in steps S4 to S
Equivalent to 7.

As shown in FIG. 2, for example, if n is 2002, the position (address) of the first physical block in the chain of corresponding physical blocks is A2, and the first area of A2 is referred to first. Since the logical address written here is 2, the position of the second physical block is ascertained by referring to the second area of A2. Next, the same search is performed on the second physical block A1002, and the physical blocks in the chain are sequentially traced. In this example, the logical address 200 in the third physical block A2002 is obtained.
2 is assigned, and data is written to this physical block (step S8).

Then, it is determined whether or not the data has been written (step S9 shown in FIG. 5). If the data can be written, the flow is terminated. If the data cannot be written, the physical block is defective and the "write" flag is not set. The data is written in the data area of the empty block in place of the empty block of the spare block, the assigned logical address is written in the first area, and the next (k + 1) th physical block is written in the second area. The address is written (step S10).

However, as it is, the position of the empty block cannot be found in the next search.
It is determined whether or not k is 1 (whether or not the physical block is the head) (step S11).
In the second area of the previous (k-1) th physical block,
The position of the empty block is written so that the chain is not interrupted (step S12). If k is 1, the position information of the corresponding physical block in the address table 5 is rewritten to the position information of the spare block (step S13).

FIG. 6 shows a case where an attempt was made to write the logical address 2002 into the physical block A2002 and it was found to be defective.
Blocks are being used instead. In this case, the position information written in the second area of the physical block A1002 immediately before the bad block A2002 is changed from A2002 to A1.
Rewritten to 6000.

When reading data from the flash memory 3, the memory controller 4 searches for a physical block corresponding to a logical address and reads data from the corresponding physical block in the same manner as in steps S1 to S8 in FIG. For example, as shown in FIG.
When reading the data of the logical address assigned to 6000, the data is sequentially traced from the A2 physical block of one group, and A16000 has already been written to the second area of the A1002 physical block of the second group ( Before the state of FIG. 6 is rewritten to A16000), the physical block of A16000 can be reached. In the above description, the addresses of the physical blocks are represented by serial numbers for convenience. However, if a physical block with a congenital failure is included, the block is not used and is therefore omitted.

According to the above-described embodiment, a table is required for conversion between a logical address and a physical address. However, as in the conventional conversion table method (method of FIG. 8), all logical addresses and physical addresses are converted. Rather than performing the association, the system number to which the logical address belongs and the physical address at the head of the concatenated group of physical blocks are associated with each other. Only about 17 is needed. The memory of the conversion table method requires 3,670,016 bits only for managing, for example, 16 flash memories. This corresponds to one 4 Mbit SRAM.

On the other hand, the chain method requires only 256,000 bits, and one 256 kbit SRAM is sufficient. Regarding access, regardless of whether the spare block area is used or not, the maximum is 16 times and the average is 8 times, which is longer than the conversion table method, but sufficient speed can be secured. Although the conventional linear address method (the method of FIG. 8) has a small probability, a very long case may occur as described above. In the present embodiment, since the minimum transfer speed is guaranteed, there is no possibility that the data transfer speed at the time of transfer by the camera cannot be caught.

The performance comparison between the present embodiment (chain method) and the conventional method can be expressed as follows based on the above-described example.

Conversion Table Method Linear Address Method Chain Method Maximum Number of Reads 1 384 16 RAM Size 16384w / 14bit 0 1000w / 10bit In the above-described embodiment, in the above-described embodiment, logical addresses are read one by one from the first physical block of the chain group. Although the search is performed to determine whether the block is an assigned physical block, the memory controller 4 determines not only which system the logical address specified by the host computer 6 belongs to, but also which physical block in the chain group. It also asks whether it corresponds to a block, without determining logical address matching for each physical block, traces the physical block at that order position at a stretch and reads the data of the physical block, or Data may be written to a physical block.

In the example described above, the value obtained by adding 1 to the quotient obtained by dividing the logical address number by the number of systems in the arithmetic unit 41 is the order position. For example, if the logical address is 2002, the quotient obtained by dividing the number of systems by 1000 is 2, so the physical block is in the third position. FIG. 6 shows a flowchart when data is read by such a method. That is, based on the read instruction of the logical address n (step S1), the order position of the chain group of the logical address n is obtained (step S2), and the physical block address of the first group is obtained by referring to the address table (step S1).
3) The physical blocks of the linked group are traced to the order position (step S4), and the data of the physical blocks is read (step S5).

In the above description, the logical address is managed by the main control unit, for example, the host computer. However, the access of data to the memory disk device is not limited to the intervention of the CPU, but may be, for example, a direct access memory (DMA). ) Is included in the present invention. Note that the semiconductor memory is not limited to a flash memory as long as it allows a defective block.

[0037]

As described above, the semiconductor memory device of the present invention has the effects that the memory required for exchanging the logical address and the physical address is small and the longest access time is short.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram conceptually showing a state in which a logical address is assigned to each physical block of a flash memory according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a configuration of a flash memory and a state in which physical blocks are linked.

FIG. 3 is a block diagram illustrating a hardware configuration of the semiconductor memory device according to the embodiment of the present invention;

FIG. 4 is a flowchart showing an operation when writing data to a flash memory.

FIG. 5 is a flowchart showing an operation when writing data to a flash memory.

FIG. 6 is an explanatory diagram showing a configuration of a flash memory and a state in which physical blocks are linked.

FIG. 7 is a flowchart showing an operation when reading data from a flash memory in another embodiment of the present invention.

FIG. 8 is an explanatory diagram showing an example of a method of searching for a physical address in a conventional semiconductor memory device.

FIG. 9 is an explanatory diagram showing another example of a method of searching for a physical address in a conventional semiconductor memory device.

[Explanation of symbols]

 2 Memory Disk 3 Flash Memory 4 Memory Controller 41 Operation Unit 42 Search Unit 43 Processing Unit 5 Address Table 6 Host Computer

Claims (1)

[Claims] A memory area is divided into a plurality of physical blocks. Each physical block includes a semiconductor memory including a data area and a redundant area, and a physical block corresponding to a logical address managed by a main control unit. And a memory control unit for searching by referring to the redundant area. A semiconductor memory device having the following configuration. a. The redundant area of the physical block includes a first area in which a logical address assigned to the physical block is written and a second area in which position information described later is written. b. A logical address is divided into a plurality of systems, and a group of physical blocks to which logical addresses belonging to the same system are assigned is formed as a chain group. c. In each concatenated group of physical blocks, (k is an integer equal to or greater than 1) in the second region of the k-th physical block, (k
The position information of the (+1) -th physical block is written. d. The memory control unit determines to which system the logical address to be searched belongs, and searches the logical address in order from the first physical block of the chain group of the physical blocks corresponding to the system, and finds the k-th physical block. If the logical address is assigned to the physical block, the physical block is accessed, and if not, the second area of the k-th physical block is referred to (k + 1).
It has a function of searching for the physical block of the number.