WO2017216892A1

WO2017216892A1 - Data transfer device and data transfer method

Info

Publication number: WO2017216892A1
Application number: PCT/JP2016/067753
Authority: WO
Inventors: 橋本　茂
Original assignee: 三菱電機株式会社
Priority date: 2016-06-15
Filing date: 2016-06-15
Publication date: 2017-12-21
Also published as: TW201800950A

Abstract

When a write request signal including an address that belongs to a DMA area and requesting a write is received from a CPU (50), a slave interface (10) subtracts the header address of the DMA area from said address to calculate an offset value of said address to the header address and registers the offset value as a record along with a record number in a table (43). A master interface (20) adds, to the offset value, the header address of an IO device buffer area which is the storage area of an IO buffer (71) read from and written to by the CPU (50) and converts the offset value to an address that belongs to the IO device buffer area, reads out data at the converted address, and writes the read data to a dual-port memory (30) to be associated with an identifier that is associated with the record number.

Description

Data transfer apparatus and data transfer method

This invention relates to a DMA (Direct Memory Access) device. For example, the present invention relates to a DMA device incorporated in a controller.

In the controller, the processing capacity of the CPU has been improving year by year, and the slow access speed of IO devices and external memory has become a bottleneck for improving performance. In order to take measures against slow access speed of external memory and IO device, the data of external memory and IO device is copied to high-speed memory by DMA, and the high-speed using DMA is referred to the copy of high-speed memory from CPU Is done.

In Patent Document 1, an internal memory stores a copy of data stored in an external memory in a data block of a predetermined size. When a copy of the read target data is not stored in the internal memory, the memory access control program reads the read target data from the external memory and supplies the read read target data to the read request source. Thereafter, the memory access control program reads the data block including the read target data from the external memory, and stores the read data block in the internal memory by using the DMA controller, thereby reducing the access time from the CPU to the memory. It is shortened.

In Patent Document 2, a data block including less data than all the cache lines of the data cache memory in the processor is written from the input / output adapter to a predetermined position in the memory through the memory bus. If it is determined that this data is contained in the data cache memory, all cache lines containing the data written in the memory are purged. Patent Document 2 proposes a cache coherent DMA write method that can execute a high-speed DMA transaction for a data block having a size smaller than the entire cache line by this purge.

Further, in Patent Document 3, a control program for a local memory realizes the following determination function, copy function, and read function by a processor.
(1) The determination function determines whether or not the tag address designating access data matches the tag address of the data in the storage area of the temporary storage device corresponding to the line number designating the access data.
(2) The duplication function starts the process of duplicating the data stored in the storage area of the temporary storage device in the register before the determination process is completed.
(3) The read function reads data from the register when it is determined by the determination function that they match.
(4) The processor reduces the data access time from the processor to the temporary storage device by starting the process of writing the data stored in the temporary storage device to the register before the cache hit determination is completed. .

JP 2011-070253 A JP 7-271670 A JP 2008-262390 A

Since the memory size of IO devices and external memory used by the controller is increasing, when trying to copy the contents of these memories to high-speed memory using DMA, the bus bandwidth is reduced due to reading of the IO devices and external memory. There is a problem that it is insufficient or the capacity of the high-speed memory is insufficient. The above problem can be solved by limiting the area copied by the DMA to only the part that is actually referred to by software (S / W).

However, in the controller, there is a problem that the S / W “referenced part” changes depending on the processing state, or the S / W cannot determine the “referenced part” next without reading a part of the IO device or the external memory. is there. Therefore, if partial transfer is to be performed, after determining the part to be transferred by S / W, the transfer area must be set to DMA and DMA activation must be performed, and the performance will not improve due to the setting overhead. There are challenges.

An object of the present invention is to provide a technique for performing partial copying of data from an IO device or external memory to a high-speed memory with low overhead.

The data transfer device of the present invention
When a write request signal that includes an address belonging to the first storage area that continues from the head address to the tail address and requests writing is received from the central processing unit, the head address is subtracted from the address by subtracting the head address. Calculate the offset value of the address
A request acquisition unit that registers the offset value as a record in a table in association with a record number;
The offset value is calculated by adding a head address of a second storage area that is a storage area of the storage device that is read and written by the central processing unit and is different from the first storage area to the offset value. A data acquisition unit for converting to an address belonging to a second storage area, reading the data of the converted address, and writing the read data in a data storage memory in association with an identifier associated with the record number; It is characterized by providing.

Since the data transfer apparatus of the present invention includes the request acquisition unit and the data acquisition unit, it is possible to perform partial copying of data of the IO device and external memory to the high-speed memory with low overhead.

FIG. 3 is a diagram of the controller 1-1 according to the first embodiment. FIG. 3 is a diagram illustrating the hardware configuration of the DMA 2 in the first embodiment. FIG. 3 is another diagram illustrating the hardware configuration of the DMA 2 in the diagram of the first embodiment. FIG. 3 is a diagram illustrating the address map as viewed from the CPU 50 of the controller 1 in the first embodiment. FIG. 3 is a diagram of the first embodiment, showing an outline of a data transfer method by DMA2. 5 is a flowchart of DMA setting by the S / W 51 in the diagram of the first embodiment. FIG. FIG. 3 is a flowchart of the DMA activation procedure by the S / W 51 in the first embodiment. FIG. 3 is a flowchart of the operation when the slave I / F 10 is written in the diagram of the first embodiment. FIG. 4 is a flowchart of the operation of the table controller 41 in the diagram of the first embodiment. FIG. 3 is a diagram illustrating the operation of the master I / F 20 in the first embodiment. FIG. 4 is a flowchart of the operation after the DMA activation by the S / W 51 in the diagram of the first embodiment. FIG. 3 is a flowchart illustrating an operation when the slave I / F 10 is read in the diagram of the first embodiment. FIG. 3 is a diagram of the first embodiment, showing another hardware configuration of the DMA 2. FIG. 5 is a configuration diagram showing a controller 1-2 of a second embodiment. FIG. 5 is a configuration diagram showing a controller 1-3 of a third embodiment. FIG. 6 is a configuration diagram showing a controller 1-4 of a fourth embodiment. FIG. 6 is a configuration diagram showing a controller 1-5 of a fifth embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the part which is the same or it corresponds in each figure. In the description of the embodiments, the description of the same or corresponding parts will be omitted or simplified as appropriate.
In the following embodiment, a CPU 50, an IO device 70, a slave I / F 10, and a master I / F 20 appear. CPU is an abbreviation for Central Processing Unit. IO is an abbreviation for Input Output. I / F is an abbreviation for Inter Face.

Embodiment 1 FIG.
*** Explanation of configuration ***
The controller 1-1 according to the first embodiment will be described with reference to FIGS. First, the configuration of the controller 1-1 will be described with reference to FIGS. FIG. 1 is a configuration diagram of the controller 1-1. FIG. 2 is a diagram showing a hardware configuration of a DMA (Direct Memory Access) device 2 (hereinafter referred to as DMA 2). FIG. 2 is a diagram in which DMA 2, the bus bridge circuit 80, the high-speed bus 81, and the low-speed bus 82 are extracted from FIG. The bus bridge circuit 80 is hereinafter referred to as a bus bridge 80. FIG. 3 is a diagram illustrating a relationship between the slave I / F 10 and the master I / F 20 included in the DMA 2 and the processor 801 and the like.

As shown in FIG. 1, the DMA 2 includes a central processing unit CPU 50, an external memory 60, an IO device 70, a bus bridge 80 connecting the high-speed bus 81 and the low-speed bus 82, and the DMA 2. DMA 2 is a data transfer device 902. The high-speed bus 81 is the first bus 981, and the low-speed bus 82 is the second bus 982 whose data transfer speed is lower than that of the first bus. Further, the CPU 50 and the high-speed bus 81, the external memory 60 and the low-speed bus 82, and the like are connected through connections 101 to 111 described later.

As shown in FIG. 1, the DMA 2 includes a slave I / F 10, a master I / F 20, a 2-port memory 30, and a table management device 40. The 2-port memory 30 is a data storage memory 930. The slave I / F 10 is a request acquisition unit 910. The slave I / F 10 is an interface device that exchanges data with the CPU 50.
The master I / F 20 is a data acquisition unit 920. The master / F 20 is an interface device that exchanges data with the IO buffer 71, the external memory 60, and the like. The IO buffer 71, the external memory 60, and the like are storage devices to which data is read and written by the CPU 50. The detailed configuration of the DAM 2 will be described later.

In the controller 1-1 of FIG. 1, there are 11 connections from the CPU-high speed bus connection 101 to the table management apparatus-master I / F connection 111. These will be described in the following (1) to (11). The CPU-high-speed bus connection 101 and the like shown in the following (1) to (11) are described as the connection 101 and the like in the following description of the embodiment.
(1) The CPU-high speed bus connection 101 connects the CPU 50 and the high speed bus 81.
(2) The low speed bus-external memory connection 102 connects the low speed bus 82 and the external memory 60.
(3) The low speed bus-IO device connection 103 connects the low speed bus 82 and the IO device 70.
(4) The high-speed bus-slave I / F connection 104 connects the high-speed bus 81 and the slave I / F 10.
(5) The master I / F-low speed bus connection 105 connects the master I / F 20 and the low speed bus 82.
(6) The slave I / F-master I / F connection 106 connects the slave I / F 10 and the master I / F 20.
(7) The slave I / F-table management device connection 107 connects the slave I / F 10 and the table management device 40.
(8) The slave I / F-2 port memory connection 108 connects the slave I / F 10 and the 2-port memory 30.
(9) The master I / F-2 port memory connection 109 connects the master I / F 20 and the 2-port memory 30.
(10) The master I / F-table management device connection 110 connects the master I / F 20 and the table management device 40.
(11) The table management apparatus-master I / F connection 111 also connects the master I / F 20 and the table management apparatus 40.

As shown in FIG. 2, the DMA 2 includes a processor 801, a RAM (Random Access Memory) 802, and a ROM (Read Only Memory) 803 as hardware. The ROM 803 stores a program for the processor 801 to realize functions such as the slave I / F 10. The processor 801 reads a program from the ROM 803 and realizes functions of the slave I / F 10, the master I / F 20, the table controller 41, and the like. As shown in FIG. 3, the correspondence between DMA2 and hardware is as follows.
(1) The slave I / F 10 is realized by the processor 801 and the RAM 802. Specifically, the processor 801 implements the function of the slave I / F 10. More specifically, a program read from the ROM 803 by the processor 801 implements the function of the slave I / F 10. The RAM 802 implements the write buffer 11.
(2) The master I / F 20 is realized by the processor 801 and the RAM 802. Specifically, the processor 801 implements the function of the master I / F 20. More specifically, a program that the processor 801 reads from the ROM 803 implements the function of the master I / F 20. The RAM 802 implements the base address register 21.
(3) The 2-port memory 30 is realized by the RAM 802.
(4) The table management device 40 includes a table controller 41, a size register 42, and a table 43. The function of the table controller 41 is realized by the processor 801. Specifically, the program read from the ROM 803 by the processor 801 implements the function of the table controller 41. The size register 42 is realized by the RAM 802. The table 43 is realized by the RAM 802.

As shown in FIG. 1, a CPU 50 on which “Software 1-1 of controller 1-1” (hereinafter referred to as S / W 51) operates is connected to a high-speed bus 81 via a connection 101. External memory 60 is connected to low speed bus 82 via connection 102. The IO device 70 has an IO device built-in buffer 71 therein. Hereinafter, the IO device built-in buffer 71 is referred to as an IO buffer 71. The IO device 70 is connected to the low speed bus 82 via the connection 103. The high speed bus 81 and the low speed bus 82 are connected by a bus bridge 80.

The DMA 2 includes a slave I / F 10, a master I / F 20, a 2-port memory 30, and a table management device 40.
(1) The slave I / F 10 has a write buffer 11.
(2) The master I / F 20 has a base address register 21 for storing the base address of the target device.
(3) The 2-port memory 30 has a plurality of data areas 32 each having a unique address 31.
(4) The table management device 40 includes a table controller 41, a size register 42 for storing the memory size of the target device, and a table 43.

In the table 43, a plurality of entries 49 are registered. The entry 49 has items of an entry number 44, an entry valid flag 45, a data valid flag 46, an address offset 47, and a status 48. Hereinafter, the entry valid flag 45 and the data valid flag 46 are referred to as an entry flag 45 and a data flag 46, respectively. The entry flag 45 is a flag indicating whether the entry 49 is valid or invalid. The data flag 46 is a flag indicating whether the data of the 2-port memory 30 corresponding to the entry number 44 is valid or invalid. In the following description, both the entry flag 45 and the data flag 46 indicate a valid state when described as set, and indicate an invalid state when described as reset.

The slave I / F 10 and the master I / F 20 are connected by a connection 106. The slave I / F 10 and the table management device 40 are connected by a connection 107. Slave I / F 10 and 2-port memory 30 are connected by connection 108. The master I / F 20 and the 2-port memory 30 are connected by a connection 109. The master I / F 20 and the table management device 40 are connected by a connection 110. Further, the table management device 40 and the master I / F 20 are connected by a connection 111. The connection 111 is connected by a connection 111 including a read instruction signal 111a for instructing reading and an entry number signal 111b that matches the contents of the entry number 44 of the entry 49 that is the source of the read instruction.

The slave I / F 10 is connected to the high-speed bus 81 via the connection 104. The connection 104 includes an address signal 104a, a control signal 104b, a read / write identification signal 104c, a read data signal 104d, a write data signal 104e, and a size signal 104f.

The master I / F 20 is connected to the low speed bus 82 via the connection 105.

FIG. 4 is an address map 90 of the controller 1-1 as seen from the CPU 50.
(1) In the address map 90, the head address is the TOP address 90a and the tail address is the BOTTOM address 90b.
(2) The address map 90 includes a DMA area 91, an external memory area 92, an IO device buffer area 93, and a DMA setting area 94. The IO device buffer area 93 is a storage area of the IO buffer 71. The external memory area 92 is a storage area of the external memory 60. When the S / W 51 transmits the write request signal 51W and the read request signal 51L to the slave I / F 10, the DMA area 91 includes a write address 91W included in the write request signal 51W and a read address 91L included in the read request signal 51L. Is a storage area to which
(3) The size of the DMA area 91 is set in the size register 42 (step S1 described later).
(4) In the DMA area 91, the head address is the DMA area TOP address 91a, and the tail address is the DMA area BOTTOM address 91b.
(5) In the external memory area 92, the start address is the external memory area TOP address 92a, and the end address is the external memory area BOTTOM address 92b.
(6) In the IO device buffer area 93, the head address is the IO device buffer area TOP address 93a, and the tail address is the IO device buffer area BOTTOM address 93b.
(7) In the DMA setting area 94, the head address is the DMA setting area TOP address 94a, and the tail address is the DMA setting area BOTTOM address 94b.

In the following, the DMA area TOP address 91a and the like are described as follows.
(1.1) The DMA area TOP address 91a is described as TOP / AD91a (DMA).
(1.2) The DMA area BOTTOM address 91b is BOTTOM / AD91b (DMA).
(2.1) The external memory area TOP address 92a is described as TOP / AD 92a.
(2.2) The external memory area BOTTOM address 92b is described as BOTTOM / AD92b.
(3.1) The IO device buffer area TOP address 93a is described as TOP / AD93a (IO).
(3.2) The IO device buffer area BOTTOM address 93a is described as BOTTOM / AF93b (IO).
(4.1) The DMA setting area TOP address 94a is described as TOP / AD 94a.
(4.2) The DMA setting area BOTTOM address 94b is described as BOTTOM / AD94b.

*** Explanation of operation ***
FIG. 5 is a diagram showing an outline of a data transfer method by the DMA 2 when the S / W 51 reads the IO buffer 71.
With reference to FIG. 5, first, an outline of a data transfer method by DMA2 will be described.

In step S01, the S / W 51 operating in the CPU 50 transmits to the slave I / F 10 a write request signal 51W that includes an address belonging to the first storage area that continues from the head address to the tail address and requests writing. Here, the first storage area is the DMA area 91, the top address is TOP / AD91a (DMA), and the end address is BOTTOM / AD91 (DMA). The address belonging to the DMA area 91 which is the first storage area is the write address 91W.
Write address 91W = [ΔAD (IO) + TOP / AD91a (DMA)]
Here, ΔAD (IO) is a value obtained by subtracting TOP / AD 93 a (IO) from the address AD when a certain address AD belongs to the IO device buffer area 93. That is, ΔAD (IO) is an offset value of the address AD with respect to TOP / AD9a (IO). ΔAD (IO) is also an offset value of the address AD with respect to TOP / AD91a (DMA) when TOP / AD91a (DMA) is added as the write address 91W. ΔAD (IO) may be described as ΔAD.

In step S02, when the slave I / F 10, which is the request acquisition unit 910, receives the write request signal 51W from the S / W 51, the top address TOP / AD 91a (DMA) from the write address 91W included in the write request signal 51W. ) Is subtracted to calculate the offset value ΔAD (IO) of the address with respect to TOP / AD91a (DMA). The slave I / F 10 registers ΔAD (IO) as a record in the table 43 in association with the record number. Here, the record is an entry 49 in the table 43, and the record number is an entry number in the table 43.

In step S03, the master I / F 20 that is the data acquisition unit 920 performs the following processing. The master I / F 20 is a storage area used by the IO buffer 71 that is a storage device 971 that is read and written by the CPU 50, and is the head of a second storage area that is different from the DMA area 91 that is the first storage area. By adding the address to the offset value ΔAD, the offset value ΔAD (IO) is converted into an address belonging to the second storage area. Here, the second storage area is the IO device buffer area 93, the top address is TOP / AD93a (IO), and the end address is BOTTOM / AD93b (IO).
The translated address is
Address = ΔAD (IO) + TOP / AD93a (IO)
It is. The master I / F 20 reads the data at the converted address. Since the converted address belongs to the IO device buffer area 93, the master I / F 20 reads data from the IO buffer 71.

In step S04, the master I / F 20 writes the read data in the 2-port memory 30 which is the data storage memory 930 in association with the identifier associated with the record number (entry number). Here, the identifier associated with the record number (entry number) corresponds to the address 31 in the 2-port memory 30.

Next, a case where the S / W 51 transmits a read request signal will be described. In step S05, the S / W 51 transmits to the slave I / F 10 a read request signal 51L that includes a read address 91L that is an address belonging to the DMA area 91 that is the first storage area and requests reading. The read address 91L is the same as the write address 91W and is as follows.
Read address 91L = [ΔAD (IO) + TOP / AD91a (DMA)]

In step S06, when the slave I / F 10 that is the request acquisition unit 910 receives the read request signal 51L from the S / W 51, the slave I / F 10 subtracts TOP / AD91a (DMA) from the read address included in the read request signal 51L. To calculate an address offset value ΔAD (IO) for TOP / AD91a (DMA). The slave I / F 10 searches whether or not the offset value ΔAD (IO) having the same value as the calculated offset value ΔAD (IO) is registered in the table 4, and when registered, the offset value registered in the table 43 is registered. Data associated with the identifier (address 31) corresponding to the record number (entry number) corresponding to ΔAD (IO) is obtained from the 2-port memory 30 which is the data storage memory 930 (step S07).

In step S08, the slave I / F 10 transmits the acquired data to the CPU 50.

Next, a data transfer method by the DMA 2 when the S / W 51 reads the IO buffer 71 will be described in detail with reference to FIGS.

FIG. 6 is a flowchart in which the S / W 51 operating on the CPU 50 performs DMA setting.

In step S1, the S / W 51 sets the size of the IO device buffer area 93 in the size register 42. As a setting example, the S / W 51 may set the start address and end address of the IO device buffer area 93, or may set the address size from the start address to the end address. The S / W 51 uses the CPU 50, connection 101, high-speed bus 81, and connection 104 to write to the slave I / F 10. The slave I / F 10 recognizes the write destination as the size register 42 by the address signal 104a. The slave I / F 10 writes the value of the write data received by the write data signal 104 e in the size register 42 of the table management device 40 using the connection 107.

In step S 2, the S / W 51 sets the TOP / AD 93 a (IO) of the IO device buffer area 93 in the base address register 21. In this case, the S / W 51 writes to the slave I / F 10 using the CPU 50, connection 101, high-speed bus 81, and connection 104. The slave I / F 10 recognizes the write destination as the base address register 21 based on the address signal 104a. The slave I / F 10 writes the write data received by the write data signal 104 e on the connection 104 to the base address register 21 using the connection 106.

FIG. 7 is a flowchart showing a procedure for starting DMA by the S / W 51.

In step S101, the S / W 51 determines the “address to be read” of the IO buffer 71 in accordance with the progress of the process. There may be a plurality of addresses to be read. Here, the “address to be read” is an address belonging to the IO device buffer area 93. That is, the address belongs to the storage area of TOP / AD93a (IO) to BOTTOM / AD93b (IO). The “address to be read” may include TOP / AD93a (IO) and BOTTOM / AD93b (IO). The address to be read is AD (IO) _k .

In step S103, the S / W 51 subtracts TOP / AD93a (IO) from AD (IO) _k which is each address (k = 1, 2,...) To be read. ΔAD (IO) is an address offset value of AD (IO) _{k with} respect to TOP / AD93a (IO). As an example, if the address of TOP / AD93a (IO) is “3001” and the address of AD (IO) _{k = 1} is “3004”,
ΔAD (IO) = AD (IO) _{k = 1−} TOP / AD93a (IO) = 3004-3001 = 3
It is. This indicates that AD (IO) _{k = 1} is the third in the IO device buffer area 93 from TOP / AD 93a (IO).

In step S104, the S / W 51 adds TOP / AD91a (DMA) to ΔAD (IO) as a subtraction result.

In step S105, the S / W 51 writes to the address obtained in S104. That is, the S / W 51 transmits the write request signal 51W to the slave I / F 10. Taking AD (IO) _{k = 1} as an example, S / W 51 is
Write address 91W = ΔAD (IO) + TOP / AD91a (DMA)
Is calculated, and the third address from TOP / AD 93a (IO) in the IO device buffer area 93 is converted into the third address from TOP / AD 91a (DMA) in the DMA area 91.

In step S106, the write in step S105 is stored in the write buffer 11 in the slave I / F 10 and later processed by the slave I / F 10. The processing by the slave I / F 10 is after S201 in FIG. After the issuance of a write by the S / W 51, the processing ends when viewed from the S / W 51. In the case of writing to the DMA area 91 in step S105, since the data has no meaning, any value may be written.

In steps S102 to S107, the process loops as many times as the number of data to be read.

FIG. 8 is a flowchart showing an operation when the slave I / F 10 is written by the S / W 51. The subject of the operation in FIG. 8 is the slave I / F 10.

(1) In step S201, the slave I / F 10 is waiting for a write to the DMA area 91.
(2) In step S202, the slave I / F 10 receives the write request signal 51W. The slave I / F 10 can recognize the write to the DMA area 91 by the address signal 104a, the control signal 104b, the read / write identification signal 104c, etc. included in the write request signal 51W. If there is a write, the process proceeds to step S203.
(3) In step S203, the slave I / F 10 uses the connection 107 to check the entry 49 of the table 43 of the table management apparatus 40 and searches for an entry flag 45 set. Since entry 49 is not registered at first, the process proceeds from step S204 to step NO → step S212 → step S209 → step S210 → step S211.
(4) In step S204, when the slave I / F 10 finds the entry 49 in which the entry flag 45 is set (step S204, YES), the process proceeds to step S205.
(5) In step S205, the slave I / F 10 matches the address offset 47 in the found entry 49 obtained by subtracting TOP / AD91a (DMA) from the written address (write address 91W). Look for entry 49. The address offset 47 is set to ΔAD (IO) as in step S210 described later.
That is, write address 91W = ΔAD (IO) + TOP / AD91a (DMA)
Therefore, the slave I / F 10 obtains ΔAD (IO) by subtracting TOP / AD91a (DMA) from the write address 91W, and creates an entry 49 having an address offset 47 that matches the obtained ΔAD (IO). look for. The slave I / F 10 has TOP / AD91a (DMA). For example, TOP / AD91a (DMA) is stored in the write buffer 11.
(6) In step S206, the entry flag 45 is set, and the address offset 47 (ΔAD (IO)) matches the value obtained by subtracting the TOP address 91a (DMA) from the write address (ΔAD (IO)). If the entry 49 to be found is found (step S206; YES), the process proceeds to step S213.
(7) In step S213, the slave I / F 10 checks the data flag 46 of the found entry 49. If the data flag 46 is set (step S214; YES), the process proceeds to S209. If the data flag 46 is not set (step S214; NO), the process ends.
(8) If YES in step S214, the slave I / F 10 resets the data flag 46 in step S209 and sets the status 48 to “read request not yet”. If the data flag 46 is not set (S214; NO), the slave I / F 10 does nothing because it is already reading.

(9) If the entry flag 45 is set in step S206, and the entry 49 whose address offset 47 matches the value obtained by subtracting the TOP address 91a (DMA) from the write address 91W is not found (step S206). NO), the process proceeds to step S207.
(10) In step S207, the slave I / F 10 searches for an entry 49 for which the entry flag 45 is not set.
(11) If there is a hit in step S208 (S208: YES), the process proceeds to S209. Therefore, in step S209, the slave I / F 10 resets the data flag 46 and sets the status 48 to “read request not yet”. In step S210, the slave I / F 10 sets the address offset 47 obtained by subtracting the TOP address 91a (DMA) from the write address, that is, ΔAD (IO) of the offset value acquired from the write address. In step S211, the slave I / F 10 sets the entry flag 45 of the hit entry 49.

(12) If no entry 49 for which the entry flag 45 is not set is found in step S208 (step S206; NO), the process proceeds to step S215. In step S215, the slave I / F 10 searches for an entry 49 in which the entry flag 45 is set and the data flag 46 is set. If the slave I / F 10 is not found, the slave I / F 10 waits until it is found (step S216).
(13) If found (S216; YES), the process proceeds to step S209.

(14) If the entry 49 in which the entry flag 45 is set is not found in step S204 (S204; NO), the process proceeds to step S212. In step S212, the slave I / F 10 selects one of the entries 49, assuming that the entry 49 is found. From step S212, the process proceeds to step S209. Therefore, the slave I / F 10 performs the processes of step S209, step S210, and step S211.

FIG. 9 is a flowchart showing the operation of the table controller 41. The subject of the operation in FIG.

(1) In step S301, the table controller 41 is searching for an entry 49 in which the entry flag 45 is set, the data flag 46 is reset, and the status 48 is unread request.
(2) If the table controller 41 finds the corresponding entry 49 (S302: YES), the process proceeds to step S303.
(3) In step S303, the table controller 41 requests the master I / F 20 to read the address offset 47. In this case, the table controller 41 transmits the address offset 47 (ΔAD (IO)) of the found entry 49 and the entry number 44 to the master I / F 20 as a read request. The address offset 47 is transmitted by the read instruction signal 111a, and the entry number 44 is transmitted by the entry number signal 111b.
(4) In step S304, the table controller 41 sets the status 48 of the found entry 49 to “read requested”.

FIG. 10 is a flowchart showing the operation of the master I / F 20. The subject of the operation in FIG. 10 is the master I / F 20.

(1) In step S401, the master I / F 20 waits for a read instruction from the table controller 41.
(2) If the master I / F 20 receives a read instruction in step S402, the process proceeds to step S403.
(3) In step S403, the master I / F 20 calculates an address obtained by adding the value of the base address register 21 to the address offset 47 (ΔAD (IO)) received by the read instruction signal 111a. The base address register 21 stores TOP / AD93a (IO) in step S2.
In other words, the master I / F 20
Address = ΔAD (IO) + TOP / AD93a (IO)
Is converted into an address in the IO device buffer area 93.
(4) In step S404, the master I / F 20 reads the calculated address value. That is, the master I / F 20 reads data at an address that belongs to the IO device buffer area 93 and is offset by ΔAD (IO) from TOP / AD 93 a (IO) that is the top address of the IO device buffer area 93. .
The address to be read is
Address = ΔAD (IO) + TOP / AD93a (IO)
Therefore, the S / W 51 matches the address of the IO buffer 71 that requests data.

(5) In step S405, the master I / F 20 calculates the address 31 where the read data is to be stored in the 2-port memory 30 from the entry number signal 111b (entry number). The simplest method for calculating the address 31 is to adopt the contents of the entry number signal 111 b (entry number itself) as the data address in the 2-port memory 30.
(6) In step S 406, the master I / F 20 writes the read data to the data area 32 of the calculated address 31 of the 2-port memory 30 using the connection 109. In step S407, the master I / F 20 uses the connection 110 to set the data flag 46 of the entry 49 indicated by the entry number signal 111b.

FIG. 11 is a flowchart of the operation of the S / W 51 after completion of DMA activation. The subject of the operation in FIG. 11 is S / W51.

(1) In step S501, the S / W 51 can perform processing that is not related to partial copy processing of data to the 2-port memory 30, which is a high-speed memory, after the processing shown in FIG. 7 is completed. When the processing not related to them is completed (S502; NO), the processing proceeds to S503.
(2) The S / W 51 subtracts TOP / AD93a (IO) from each address determined in step S101 (S504), adds TOP / AD91a (DMA) (S505), and for all addresses Read is performed (S506). That is, the S / W 51 transmits a read request signal 51L to the slave I / F 10.
(3) Steps S504, S505, and S506 are read processes corresponding to steps S103, S104, and S105, which are write processes.

FIG. 12 is a flowchart showing the operation of the slave I / F 10 when read from the S / W 51.

(1) In step S601, the slave I / F 10 waits for a read to the DMA area 91.
(2) The slave I / F 10 receives the read request signal 51L from the S / W 51. The read request signal 51L has an address signal 104a, a control signal 104b, a read / write identification signal 104c, and the like. In step S602, the slave I / F 10 can recognize the read to the DMA area 91 by the address signal 104a, the control signal 104b, and the read / write identification signal 104c.
(3) In step S603, the slave I / F 10 uses the connection 107 to check the entry 49 of the table 43 and searches for an entry flag 45 set.
(4) In step S604, when the entry 49 for which the entry flag 45 is set is found (S604; YES), the process proceeds to step SS605, and when it is not found (S604; NO), the process proceeds to step S612.

(5) In step S605, the slave I / F 10 searches for the entry 49 in which the address offset matches the one obtained by subtracting the TOP address 91a (DMA) from the read address. That is, since the read address 91L = ΔAD (IO) + TOP / AD91a (DMA), the slave I / F 10 acquires ΔAD (IO) by subtracting TOP / AD91a (DMA) from the read address 91L. The entry 49 having the address offset 47 that matches the ΔAD (IO) is searched.
(6) If an entry 49 whose address offset 47 matches ΔAD (IO) is found in step S606, the process proceeds to step S607. If not found, the process proceeds to step S612.

(7) In step S607, the slave I / F 10 checks the data flag 46 of the found entry 49 and waits until it is set (S608).
If the setting of the data flag 46 can be confirmed in step S608, the process proceeds to step S609.
(8) In step S609, the slave I / F 10 uses the address calculation method performed by the master I / F 20 in step S405 and the entry number 44 of the entry 49 in which the data flag 46 is confirmed to be set. An address 31 where 30 read data is stored is calculated.
(9) In step S610, the slave I / F 10 reads the data stored at the calculated address from the 2-port memory 30 using the connection 108 to obtain read data.
(10) In step S610, the slave I / F 10 returns the read data to the CPU 50 using the connection 104, the high-speed bus 81, and the connection 101.

(11) If the entry 49 for which the entry flag 45 is set is not found in step S604 (S604; NO), the process proceeds to step S612.
(12) In step S612, the slave I / F 10 performs the processing after step S203 when the slave I / F 10 is written by replacing the write address with the read address, and the processing returns to step S603.

(13) Also, if no corresponding entry is found in step S606 (S606; NO), the slave I / F 10 performs step S612, and the process returns to step S603.

When the operation when the slave I / F 10 is read is completed, the S / W 51 can obtain the read data, and thus executes a process using the read data.

The examples shown in FIGS. 6 to 12 show the case of DMA transfer of the IO buffer 71. In other words, the DMA transfer has been described by taking the IO buffer 71 as an example of a storage device to be read and written by the CPU 50. However, by changing the settings of the base address register 21 and the size register 42, the external memory The DMA transfer according to the present embodiment can also be applied to 60.

*** Effects of Embodiment 1 ***
As described above, according to the present embodiment, the following effects can be obtained.
(1) The S / W 51 writes the DMA area 91 with an offset. That is, the S / W 51 transmits the write request signal 51W to the slave I / F 10. In response to this write, the DMA 2 recognizes the address to be read, performs read, and stores the read data in the 2-port memory 30. For this reason, after the write request signal 51W is transmitted, the S / W 51 can perform the process of step S501 in FIG. 11, thereby eliminating the complexity when the S / W 51 performs the DMA setting.
(2) With the write address 91W (ΔAD (IO) + TOP / AD (DMA)), the address to be read by the DMA can be specified in detail. For this reason, the DMA does not read data that the S / W 51 does not need, but can read data that the S / W 51 needs. Therefore, the consumption of the bus bandwidth can be reduced, and the capacity of the 2-port memory 30 for storing read data can be saved.
(3) Further, the S / W 51 obtains necessary data by reading the DMA area 91 instead of reading the data in the IO device buffer area 93. That is, the read of the DMA area 91 requires a shorter number of clocks than the read of the IO device buffer area 93 by the S / W 51. For this reason, the processing performance of the S / W 51 is improved.
(4) Further, after the DMA 2 is activated, the reading of the IO device buffer area 93 by the DMA 2 (acquisition of data by the master I / F 20 (S 404 to S 406)) and the processing of the S / W 51 are performed in parallel. For this reason, the transfer completion waiting time of the DMA device 2 of the S / W 51 is eliminated, and the processing performance is improved.

*** Other configurations ***
Further, in the present embodiment, the case where the functions of “slave I / F 10, master I / F 20, and table controller 41” shown as the processor 801 are realized by software is shown in FIGS. The functions of “slave I / F 10, master I / F 20, and table controller 41” shown as the processor 801 may be realized by hardware. FIG. 13 shows a case where the functions of “slave I / F 10, master I / F 20, and table controller 41” shown as the processor 801 are realized by the processing circuit 99 that is hardware. The processing circuit 99 is connected to the signal line 99a. The processing circuit 99 realizes the functions of “slave I / F 10, master I / F 20, table controller 41” and the functions of the RAM 802 and ROM 803 shown as the processor 801. The processing circuit 99 is a dedicated electronic circuit that realizes the functions of “slave I / F 10, master I / F 20, table controller 41” shown as the processor 801 and the functions of the RAM 802 and ROM 803. Specifically, the processing circuit 99 includes a single circuit, a composite circuit, a programmed processor, a processor programmed in parallel, a logic IC, a GA (Gate Array), an ASIC (Application Specific Integrated Circuit), or FPGA (Field-Programmable / Gate / Array).

The functions of “slave I / F 10, master I / F 20, and table controller 41” shown as the processor 801 may be realized by one processing circuit 99 or may be realized by being distributed to a plurality of processing circuits 99. .

As another modification, the DMA 2 shown in FIG. 1 may be realized by a combination of software and hardware. That is, some functions of the DMA 2 shown in FIG. 1 may be realized by dedicated hardware, and the remaining functions may be realized by software.

The processor 801, the RAM 802, the ROM 803, and the processing circuit 99 are collectively referred to as “processing circuit”. That is, the functions of “slave I / F 10, master I / F 20, table controller 41” and the functions of RAM 802 and ROM 803 are realized by processing circuitry.

The functions of “slave I / F 10, master I / F 20, and table controller 41” shown as the processor 801 may be read as “process”, “procedure”, or “processing”. Further, the functions of “slave I / F 10, master I / F 20, and table controller 41” shown as the processor 801 may be realized by firmware.

Also, the operation of the controller 1-1 and DMA2 in FIG. 1 can be grasped as a method and a program. The program can be stored in a computer-readable recording medium. The program can be realized as a program product.

Embodiment 2. FIG.
FIG. 14 is a configuration diagram of the controller 1-2 according to the second embodiment. As shown in FIG. 14, the controller 1-2 further includes a timer 403 with respect to the controller 1-1 of the first embodiment. The timer 403 is connected to the table management device 40. The timer 403 is a programmable interval timer and periodically generates pulses. When the generated pulse is transmitted to the table management device 40, the table controller 41 resets the data flags 46 of all the entries 49 and sets the status 48 to a read request not yet.

As shown in steps S301 and S302 of FIG. 9, the table controller 41 always searches for an entry 49 in which the entry flag 45 is set, the data flag 46 is reset, and the status 48 is unread request. When such an entry 49 exists, the table controller 41 sets the status 48 of the entry 49 as a read request (S304) and uses the connection 111 to read the address offset 47 to the master I / F 20. Is requested (S303).

As a result, the address of the IO device buffer area 93 corresponding to the address offset 47 of the entry 49 in which the entry flag 45 is set is periodically read, and the data registered in the 2-port memory 30 is always the last pulse. It coincides with the data in the IO device buffer area 93 after the occurrence.

As a result, unless the address to be read of the IO buffer 71 is changed, the S / W 51 does not need to perform a write operation of the DMA area 91 for causing the DMA 2 to read the latest data in the IO device buffer area 93. Therefore, the processing performance of the S / W 51 is improved.

Embodiment 3 FIG.
FIG. 15 is a configuration diagram of the controller 1-3 according to the third embodiment. The controller 1-3 differs from the controller 1-1 of the first embodiment in the connection of the slave I / F 10 and the master I / F 20 to the bus. Instead of the connection 104 between the high-speed bus 81 and the slave I / F 10, the bus bridge 80 and the slave I / F 10 are connected by a bus bridge-slave I / F connection 112, and the connection 105 between the master I / F 20 and the low-speed bus 82 is performed. Instead, the master I / F 20 and the bus bridge 80 are connected by a master I / F-bus bridge connection 113. In the bus bridge 80, the high-speed bus switch 80a distributes access from the high-speed bus 81 into access to the low-speed bus 82 and access to the slave I / F 10 by address. Further, the low-speed bus switch 80b arbitrates access from the high-speed bus 81 and access from the master I / F 20, thereby enabling both the high-speed bus 81 and the master I / F 20 to access the low-speed bus 82.

Because of this connection, even when the DMA 2 cannot be connected to the high-speed bus 81 and the low-speed bus 82, the present invention can be applied, so that the same effect as in the first embodiment can be obtained.

Embodiment 4 FIG.
FIG. 16 is a configuration diagram of the controller 1-4 according to the fourth embodiment. The controller 1-4 differs from the controller 1-1 of the first embodiment in connection to the master I / F 20 bus. Instead of the connection 105 between the master I / F 20 and the low-speed bus 82, the master I / F 20 and the high-speed bus 81 are connected by the master I / F-high-speed bus connection 114.

By this connection, the present invention can be applied even when the DMA 2 cannot be connected to the low-speed bus 82, so that the same effect as that of the first embodiment can be obtained.

Embodiment 5 FIG.
FIG. 17 is a configuration diagram of the controller 1-5 according to the fifth embodiment. The controller 1-5 is different from the controller 1-1 of the first embodiment in connection to the bus of the slave I / F 10. Instead of the connection 104 between the high-speed bus 81 and the slave I / F 10, the low-speed bus 82 and the slave I / F 10 are connected by a low-speed bus-slave I / F connection 115.

Because of this connection, the present invention can be applied even when the DMA 2 cannot be connected to the high-speed bus 81, so that the same effect as in the first embodiment can be obtained.

Although the embodiments of the present invention have been described above, two or more of these embodiments may be implemented in combination. Alternatively, one of these embodiments may be partially implemented. Alternatively, two or more of these embodiments may be partially combined. In addition, this invention is not limited to these embodiment, A various change is possible as needed.

1-1, 1-2, 1-3, 1-4, 1-5 controller, 2 DMA, 10 slave I / F, 11 write buffer, 20 master I / F, 21 base address register, 30 2-port memory, 31 address, 32 data area, 40 table management device, 41 table controller, 42 size register, 43 table, 44 entry number, 45 entry flag, 46 data flag, 47 address offset, 48 status, 49 entry, 50 CPU, 51 S / W, 51W write request signal, 51L read request signal, 60 external memory, 70 IO device, 71 IO buffer, 80 bus bridge, 80a high speed bus switch, 80b low speed bus switch, 81 high speed bus, 82 low speed 90 address map, 90a TOP address, 90b BOTTOM address, 91 DMA area, 91W write address, 91L read address, 91a TOP / AD, 91b BOTTOM / AD, 92 external memory area, 92a TOP address, 92b BOTTOM address, 93 IO device buffer area, 93a TOP / AD, 93b BOTTOM / AD, 94 DMA setting area, 94a TOP / AD, 94b BOTTOM / AD, 99 processing circuit, 99a signal line, 101-111 connection, 104a address signal, 104b control signal 104c read / write identification signal, 104d read data signal, 104e write data signal, 104f size signal, 111a read instruction signal, 11 b Entry number signal, 112 bus bridge-slave I / F connection, 113 master I / F-bus bridge connection, 114 master I / F-high speed bus connection, 115 low speed bus-slave I / F connection, 403 timer, 801 processor 802 RAM, 803 ROM, 910 request acquisition unit, 920 data acquisition unit, 930 data storage memory, 971 storage device, 981 first bus, 982 second bus.

Claims

When a write request signal that includes an address belonging to the first storage area that continues from the head address to the tail address and requests writing is received from the central processing unit, the head address is subtracted from the address by subtracting the head address. Calculate the offset value of the address
A request acquisition unit that registers the offset value as a record in a table in association with a record number;
The offset value is calculated by adding a head address of a second storage area that is a storage area of the storage device that is read and written by the central processing unit and is different from the first storage area to the offset value. A data acquisition unit for converting to an address belonging to a second storage area, reading the data of the converted address, and writing the read data in a data storage memory in association with an identifier associated with the record number; A data transfer device comprising:
The request acquisition unit
When the read request signal including the address belonging to the first storage area and requesting the read is received from the central processing unit, the start address of the first storage area is determined from the address included in the read request signal. Calculate the offset value of the address with respect to the start address by subtracting,
When an offset value having the same value as the calculated offset value is registered in the table, the data associated with the identifier corresponding to the record number corresponding to the offset value registered in the table is Obtained from the data storage memory,
The data transfer device according to claim 1, wherein the acquired data is transmitted to the central processing unit.
The request acquisition unit and the data acquisition unit are:
The data transfer device according to claim 1, wherein the data transfer device is connected to a bus bridge circuit that connects a first bus and a second bus having a transfer speed slower than that of the first bus.
The request acquisition unit and the data acquisition unit are:
3. The device according to claim 1, wherein the first bus connected by the bus bridge circuit and the second bus having a slower transfer speed than the first bus are connected to the first bus. 4. Data transfer device.
The request acquisition unit and the data acquisition unit are:
3. The device according to claim 1, wherein the first bus connected by the bus bridge circuit and the second bus having a slower transfer speed than the first bus are connected to the second bus. 4. Data transfer device.
The table is
As an item of the record, it has a data flag indicating either the valid state or invalid state of the data acquired by the data acquisition unit,
The data acquisition unit
When the data is written to the data storage memory, the data flag of the record associated with the written data and the record number is set to be valid,
The table is
The data transfer device according to any one of claims 1 to 5, wherein the data flag is invalidated by the pulse of the timer device that periodically generates a pulse.
A data transfer device having a table and a data storage memory;
When a write request signal that includes an address belonging to the first storage area that continues from the head address to the tail address and requests writing is transmitted from the central processing unit, the head address is subtracted from the address by subtracting the head address. Calculate the offset value of the address,
The offset value is registered as a record in the table in association with the record number,
The offset value is calculated by adding a head address of a second storage area that is a storage area of the storage device that is read and written by the central processing unit and is different from the first storage area to the offset value. Converted to an address belonging to the second storage area,
Read the data of the converted address,
A data transfer method for writing read data in the data storage memory in association with an identifier associated with the record number.
The data transfer device
When the central processing unit transmits a read request signal that includes an address belonging to the first storage area and requests reading, the head address of the first storage area is determined from the address included in the read request signal. Calculate the offset value of the address with respect to the start address by subtracting,
When an offset value having the same value as the calculated offset value is registered in the table, the data associated with the identifier corresponding to the record number corresponding to the offset value registered in the table is Obtained from the data storage memory,
The data transfer method according to claim 7, wherein the acquired data is transmitted to the central processing unit.