JP2004145376A - Method and device for controlling dma transfer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a system that allows data in DMA transfer to be referred to and reduces the waiting time of a CPU in DMA transfer. <P>SOLUTION: The system comprises a detection means 12 to detect a request from a CPU 70 for reference to the data of DMA transfer object and uses a device 10 for controlling DMA transfer, that lets the CPU 70 refer to the data for which the request for reference has been detected prior to DMA transfer during execution. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a direct memory access (DMA) transfer control method and control device, and more particularly, to a memory-to-memory DMA transfer control method and control device.
[0002]
[Prior art]
FIGS. 9A, 9B, 9C, and 9D show the outline of the memory-to-memory DMA transfer performed between the memory areas of the main memory. In the data processing system of FIG. 9, a CPU (Central Processing Unit) 70 and a cache unit 72, a main memory 90, and a DMA controller 82 are connected to a system bus 80.
[0003]
The cache unit 72 is connected between the CPU 70 and the system bus 80, and includes a tag 74 and a cache 76. The cache 76 is a memory in which a part of the data stored in the main memory 90 is stored, and the tag 74 is a memory in which the address of the data stored in the cache 76 is stored. The CPU 70 accesses the cache 76 if the data to be accessed is in the cache 76, and accesses the main memory 90 if the data to be accessed is not in the cache 76.
[0004]
The main memory 90 is a semiconductor memory such as a dynamic random access memory (DRAM), and the DMA controller 82 performs memory-to-memory data transfer between memory areas of the main memory 90 without the intervention of the CPU 70. Data transfer between memory areas means data transfer from a transfer source in the main memory 90 to a transfer destination in the main memory 90 as shown in FIGS. 9 (a), 9 (b), 9 (c) and 9 (d). Data transfer by the DMA controller 82 (hereinafter, DMA data transfer) and processing by the CPU 70 can be executed in parallel. DMA data transfer includes copying data as well as data movement.
[0005]
For example, when a plurality of instructions or a group of instructions use the same data, the original data is often not used directly but copied and used in the main memory 90. DMA transfer is performed in data block units. FIG. 10A shows an example of the data block. The data block DB stores data DATA1, DATA2, DATA3, DATA4, DATA5, and AD8 'of the transfer source addresses AD1', AD2 ', AD3', AD4 ', AD5', AD6 ', AD7', and AD8 'of the main memory 90. It includes DATA6, DATA7, and DATA8. The data DATA1, DATA2, DATA3, DATA4, DATA5, DATA6, DATA7, DATA8 are copied to the transfer destination addresses AD1, AD2, AD3, AD4, AD5, AD6, AD7, AD8 of the main memory 90.
[0006]
As shown in FIG. 9A, the DMA controller 82 includes a register 84 (hereinafter, referred to as a transfer counter 84) for storing the number of data that has not been DMA-transferred, and a register for storing the address of the data being transferred. 86 (hereinafter, referred to as a transfer address 86). In the case of the data block DB in FIG. 10A, the transfer counter 84 stores “8” as the total number of data as an initial value. Each time the DMA transfer of data is completed, the DMA controller 82 decreases the value of the transfer counter 84 by one.
[0007]
The transfer address 86 stores a transfer source address and a transfer destination address of data during DMA transfer. In the case of the data block DB in FIG. 10A, the transfer source address AD1 ′ and the transfer destination address AD1 are stored as initial values. Each time the DMA transfer of data is completed, the DMA controller 82 updates the source and destination addresses.
[0008]
FIG. 10B shows an outline of the DMA data transfer of the data block DB. Each time data is transferred, the transfer counter 84 and the transfer address 86 are updated, and DATA1 to DATA8 are sequentially transferred. When the DMA transfer of DATA8 is completed, the transfer counter becomes "0" (not shown), and the DMA transfer of the data block DB ends. Here, “AD1 ′ → AD1” in the figure indicates that the source address is AD1 ′ and the destination address is AD1.
[0009]
Data for which the DMA transfer has not been completed cannot be accessed until the DMA transfer is completed. FIG. 11 shows an example of a procedure in which the CPU 70 accesses data at the DMA transfer destination. As shown in FIG. 9B, after the DMA transfer of the data block DB is started (S160), even if an access request to the data of the DMA transfer destination occurs from the CPU 70 (S162), the DMA transfer continues as it is. Is performed (S163). When the DMA transfer of the data block DB ends (S164), the DMA controller 82 notifies the CPU 70 of the end of the DMA transfer (interrupt signal INT) as shown in FIG. 9C (S166). Since the DMA transfer of the data block DB has been completed, the CPU 70 accesses the data after the DMA transfer as shown in FIG. 9D (S168).
[0010]
For example, as shown in FIG. 12, when an access request for DATA7 is generated from the CPU 70 (S162) after the transfer of DATA1 is completed (S180), the DMA transfer of DATA2 to DATA8 is completed (S182, S184, S186, S188, S190, S190). After performing S192 and S194), the CPU 70 accesses DATA7 (S168). During the DMA transfer of DATA2 to DATA8, the CPU 70 cannot access DATA7 and a waiting time occurs. Of course, the CPU 70 can cause the CPU 70 to execute other processing in parallel with the DMA transfer. However, there is not always another process that can be assigned to the CPU 70 during the DMA transfer.
[0011]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION It is an object of the present invention to enable access to data during a DMA transfer and reduce the waiting time of the CPU during the DMA transfer.
[0012]
[Means for Solving the Problems]
According to the memory-to-memory DMA transfer control method of the present invention, a detection step of detecting an access request from the CPU to data included in a data block being DMA-transferred, and a priority being given to the DMA transfer being executed, A transfer control step of causing the CPU to access the data for which the access request has been detected.
[0013]
The DMA transfer control device according to the present invention includes a detecting means for detecting an access request from the CPU to data included in the data block being DMA-transferred, and the CPU having the access request given priority to the DMA transfer being executed. Transfer control means for accessing the detected data. The detection means detects that the CPU accesses data included in the data block being DMA-transferred, and the transfer control means can preferentially DMA-transfer the data. Can be accessed at
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of a memory-to-memory DMA transfer control method and control device according to the present invention will be described in detail with reference to the drawings. In this example, it is assumed that the memory-to-memory DMA transfer is performed between the memory areas of the main memory. In the illustrated data processing system, it is assumed that the CPU 70, the cache unit 72, the system bus 80, and the main memory 90 are the same as those in the related art (FIG. 9A). Further, it is assumed that the data block DB to be DMA-transferred is the same as the conventional one (FIG. 10A).
[0015]
The memory-to-memory DMA transfer control device (DMA controller) 10 of the present invention shown in FIG. 1 includes a DMA hit detector 12 for detecting an access request from the CPU 70 to data included in a data block during a DMA transfer. Including. The DMA controller 10 functions as a unit that causes the CPU 70 to access data for which an access request has been detected by the DMA hit detector 12 in preference to the DMA transfer of the data block being executed. The DMA controller 10 including the DMA hit detector 12 is connected between the CPU 70 and the system bus 80.
[0016]
The DMA hit detector 12 detects whether or not the CPU 70 has requested access to data for which DMA transfer has not been completed. The DMA controller 10 performs the highest priority DMA transfer of data for which the DMA transfer detected by the DMA hit detector 12 has not been completed, and sends the data to the CPU 70 after the DMA transfer.
[0017]
The DMA controller 10 includes a transfer counter 84 and a transfer address 86 as in the prior art. By accessing the transfer counter 84 and the transfer address 86, the DMA hit detector 12 can know the address of the data whose DMA transfer has not been completed. The address of the data accessed by the CPU 70 is sent to the cache unit 72 and the DMA controller 10. The DMA hit detector 12 detects a match between the address of data requested to be accessed by the CPU 70 (hereinafter referred to as request data) and the address of data for which DMA transfer has not been completed. Hereinafter, a case where the DMA transfer of the requested data is not completed is referred to as a “DMA hit”.
[0018]
If a DMA hit is detected, the DMA transfer of the requested data has not been completed. The DMA controller 10 suspends the DMA transfer of the data block being executed, and performs the DMA transfer of the requested data first. When the DMA transfer of the request data is completed, the DMA controller 10 sends the request data to the MPU 70. Thereafter, the DMA transfer of the interrupted data block is resumed by referring to the transfer counter 84 and the transfer address 86.
[0019]
If no DMA hit is detected, the DMA transfer of the requested data has already been completed. In that case, the CPU 70 can access correct data even when the DMA transfer of the data block is not completed. The CPU 70 accesses the cache 76 or the main memory 90 via the cache unit 72 to access the requested data.
[0020]
Next, the operation of the DMA transfer control using the DMA controller 10 will be described.
[0021]
FIG. 3 shows an example of the DMA transfer control procedure. Assume that a data access request is generated from the CPU 70 (S162) after the DMA controller 10 starts the DMA transfer of the data block (S160) as shown in FIG. 1B. As shown in FIG. 1C, the address ADn of the request data DATAn is sent from the CPU 70 to the DMA controller 10 and the cache unit 72. The DMA controller 10 detects a DMA hit by the DMA hit detector 12 (S110).
[0022]
When a DMA hit is detected, the DMA controller 10 interrupts the DMA transfer of the data block being executed (S112), and performs the DMA transfer of the requested data as shown in FIG. 1D (S114). When a DMA hit is detected, the DMA controller 10 preferentially uses the system bus. When the DMA transfer is completed, the DMA controller 10 sends the requested data (DATAn) from the main memory 90 to the CPU 70 (S116) as shown in FIG. The transfer is restarted (S124).
[0023]
If a DMA hit is not detected, the DMA controller 10 suspends the DMA transfer of the data block being executed (S112). As shown in FIG. 2B, the CPU 70 accesses the cache 76 or the main memory 90 via the cache unit 72 (S118). When the access to the requested data from the CPU 70 is completed, the DMA controller 10 resumes the interrupted DMA transfer of the data block (S124).
[0024]
When all the data in the data block has been DMA-transferred (S164), the DMA controller 10 notifies the CPU 70 that the DMA transfer has been completed (S166).
[0025]
For example, as shown in FIG. 4, after the DMA transfer is started (S160) and the DMA transfer of DATA1 is completed (S180), when an access request of DATA7 is generated from the CPU 70 (S162), the DMA controller 10 executes the data being executed. The DMA transfer of the block DB is interrupted (S112), and the DMA transfer of DATA7 is performed first (S120). When the DMA transfer is interrupted, the transfer counter 84 holds “7” and the transfer address 86 holds “AD2 ′ → AD2”.
[0026]
When the DMA transfer of DATA7 is completed, the DMA controller 10 sends DATA7 to the CPU (S122), and then resumes the interrupted DMA transfer of the data block DB (S124). When the DMA transfer of DATA2 to DATA8 is completed (S182, S184, S186, S188, S190, S192, S194), the DMA controller 10 notifies the CPU 70 that the DMA transfer is completed (S166).
[0027]
In parallel with the DMA transfer of DATA2 to DATA8, the CPU 70 can execute processing using DATA7. In the example shown in FIG. 4, DATA7 is DMA-transferred again (S192), but since the CPU 70 only refers to DATA7, there is no problem even if DATA7 is DMA-transferred again. The configuration shown in FIG. 1A is a configuration that can be applied to a single processor in which a CPU 70, a cache unit 72, and a DMA controller 10 are integrated.
[0028]
As mentioned above, although one Example of this invention was described, this invention can be implemented also in another aspect. For example, as shown in FIG. 5A, the DMA hit detector 22 is connected between the CPU 70 and the system bus 80, and the DMA controller 20 is connected to the CPU 70 and the main memory 90 via the system bus 80. You can also. The DMA hit detector 22 detects a DMA hit by referring to the transfer counter 84 and the transfer address 86 of the DMA controller 20.
[0029]
When a DMA hit is detected, the DMA controller 20 causes the CPU 70 to retry accessing the requested data. The DMA controller 20 suspends the DMA transfer of the data block being executed and temporarily transfers the requested data from the time when the CPU 70 temporarily stops accessing the requested data until the CPU 70 accesses the requested data again. After the CPU 70 accesses the requested data for which the DMA transfer has been completed, the DMA controller 20 resumes the DMA transfer of the suspended data block.
[0030]
FIG. 7 shows an example of the DMA transfer control procedure. It is assumed that a data access request is generated from the CPU 70 (S162) after the DMA controller 20 starts the DMA transfer of the data block (S160) as shown in FIG. 5B. The address ADn of the request data DATAn is sent from the CPU 70 to the DMA hit detector 22 and the cache unit 72. The DMA hit detector 22 detects a DMA hit by referring to the transfer counter 84 and the transfer address 86 of the DMA controller 20.
[0031]
When a DMA hit is detected, the DMA hit detector 22 sends the address ADn of the requested data to the DMA controller 20 via the system bus 80 as shown in FIG. 5C (S130). The request data at this time is invalid data for which the DMA transfer has not been completed. The DMA controller 20 that has received the address ADn from the DMA hit detector 22 requests the CPU 70 to retry access to the requested data (ReTRY) as shown in FIG. 5D (S132). The CPU 70 that has been requested for ReTRY temporarily stops accessing the requested data, and accesses the requested data again after a predetermined time has elapsed. As shown in FIG. 6A, the DMA controller 20 suspends the DMA transfer of the data block being executed (S112) while the CPU 70 temporarily suspends the data access (S112), and DMAs the requested data DATAn. Transfer is performed (S134).
[0032]
When the CPU 70 accesses the request data again, the request data has been updated to valid data for which the DMA transfer has been completed. As shown in FIG. 6B, after the CPU 70 accesses DATAn (S136), the DMA controller 20 resumes the interrupted DMA transfer of the data block (S124). When all the data in the data block has been DMA-transferred (S164), the DMA controller 20 notifies the CPU 70 that the DMA transfer has been completed (S166).
[0033]
In FIG. 7, when a DMA hit is not detected, the CPU 70 accesses the cache 76 or the main memory 90 via the cache unit 72 as shown in FIG. At this time, the DMA controller 20 suspends the DMA transfer of the data block being executed (S112), and when the CPU 70 completes the access to the requested data (S118), resumes the DMA transfer of the suspended data block. (S124).
[0034]
Similarly to FIG. 4, after the DMA transfer is started (S160) and the DMA transfer of DATA1 is completed (S180), even if an access request to DATA7 is generated from the CPU 70 (S162), the DMA transfer of DATA7 is performed first. (S120). In parallel with the DMA transfer of DATA2 to DATA8, the CPU 70 can execute processing using DATA7. The configuration shown in FIG. 5A is a configuration that can be applied to a multiprocessor in which the CPU 70, the cache unit 72, and the DMA hit detector 22 are integrated.
[0035]
As shown in FIG. 8A, a buffer 34 can be connected to the DMA hit detector 32. As shown in FIG. 8B, the data or data block in which the DMA hit is detected is temporarily stored in the buffer 34. The data is stored in the buffer 34 after the CPU accesses the requested data. When the CPU 70 accesses the data stored in the buffer 34 again, the DMA hit detector 32 sends the data stored in the buffer 34 to the CPU 70. By providing the buffer 34, the number of retry requests (ReTRY) is reduced.
[0036]
Although the present invention has been described with reference to specific embodiments, the present invention is not limited thereto. For example, although memory-to-memory DMA transfers between memory areas of a main memory have been described herein, the present invention provides a memory-to-memory DMA transfer between any high speed memories connected to a system bus. Applicable to DMA transfer. The present invention can be implemented in various modified, modified, and modified embodiments based on the knowledge of those skilled in the art without departing from the spirit thereof. As long as the same operation or effect is produced, any of the invention-specific matters can be implemented in a form replaced with another technology. The present invention can be embodied in a form in which the integrally formed invention specifying matter is composed of a plurality of elements, or in a form in which the invention specifying matter composed of a plurality of elements is integrally formed.
[0037]
【The invention's effect】
According to the present invention, when the CPU requests access to data that has not been DMA-transferred, the data can be DMA-transferred first and the CPU can be accessed. Can be reduced.
[Brief description of the drawings]
FIGS. 1A and 1B are diagrams showing an embodiment of DMA transfer control between memory areas of a main memory according to the present invention, wherein FIG. 1A is a diagram showing an example of a configuration, and FIG. FIG. 3C is a diagram illustrating a state in which a data access request has been generated from the CPU, and FIG. 4D is a diagram illustrating a state in which a DMA hit has been detected and DMA transfer of data accessed by the CPU has been performed. FIG.
FIG. 2A is a diagram showing a state in which a DMA controller is sending data to which a DMA transfer has been completed shown in FIG. 1D to a CPU, and FIG. Is a diagram showing a state in which is accessing a cache or a main memory.
FIG. 3 is a diagram showing an example of a DMA transfer control procedure of the DMA controller shown in FIG.
FIG. 4 is a diagram showing an example of a DMA transfer procedure of a data block DB of the DMA controller shown in FIG.
5A and 5B are diagrams showing another embodiment of DMA transfer control between memory areas according to the present invention, wherein FIG. 5A is a diagram showing an example of a configuration, and FIG. 5B is a diagram showing a data transfer from a CPU during a DMA transfer. FIG. 7C is a diagram illustrating a state in which an access request has occurred, FIG. 7C is a diagram illustrating a state in which a DMA hit is detected, and the address of data to be accessed by the CPU is sent to the DMA controller, and FIG. FIG. 11 is a diagram illustrating a state in which a retry of data access is requested to the CPU.
FIG. 6A is a diagram showing a state in which DMA transfer is being performed by a DMA controller when the CPU temporarily suspends data access due to the retry request shown in FIG. 5D; FIG. 2B is a diagram illustrating a state in which the DMA controller is sending data to the CPU after the completion of the DMA transfer illustrated in FIG. 2A, and FIG. 2C is a diagram illustrating a state in which a DMA hit is not detected and the CPU transfers the data to the cache or main memory. It is a figure showing the state where it is accessing.
FIG. 7 is a diagram showing an example of a DMA transfer control procedure of the DMA controller shown in FIG.
8A and 8B are diagrams showing another embodiment of the DMA transfer control between memory areas according to the present invention, wherein FIG. 8A is a diagram showing an example of a configuration, and FIG. It is a figure which shows the state which the controller is sending to the buffer, and (c) is a figure which shows the state which the DMA hit detector is sending the data of the buffer shown in (b) to CPU.
9A and 9B are diagrams illustrating an example of a conventional DMA transfer control, FIG. 9A is a diagram illustrating an example of a configuration, FIG. 9B is a diagram illustrating a state of a DMA transfer, and FIG. FIG. 11D is a diagram illustrating a state in which the DMA controller notifies the CPU of the completion of the DMA transfer, and FIG. 9D illustrates a state in which the CPU is accessing the cache or the main memory.
10A is a diagram illustrating a configuration example of a data block in a unit for performing a DMA transfer, and FIG. 10B is a diagram illustrating a transfer counter of a DMA controller, a value of a transfer address, and a DMA transfer state of each data; FIG.
FIG. 11 is a diagram showing an example of a DMA transfer control procedure of the DMA controller shown in FIG.
FIG. 12 is a diagram illustrating an example of a DMA transfer procedure of the data block DB of the DMA controller illustrated in FIG. 9A.
[Explanation of symbols]
10, 20: DMA controller (transfer control means, DMA transfer control device)
12, 22, 32: DMA hit detector (detection means)
34: Buffer (buffer memory)
70: CPU
72: cache unit 74: tag 76: cache (cache memory)
80: system bus 82: conventional DMA controller 84: transfer counter (first register)
86: transfer address (second register)
90: Main memory

Claims (12)

A method of controlling a DMA controller for performing a memory-to-memory DMA (direct memory access) transfer in a data processing system having a main memory connected to a CPU (central processing unit) via a system bus,
A detecting step of detecting an access request from the CPU for data included in the data block during the DMA transfer;
A transfer control step of causing the CPU to access the data in which the access request is detected, prior to the DMA transfer being executed. The detecting step includes:
Judging completion / incomplete of DMA transfer of the data in which the access request is detected,
The transfer control step,
A first step of causing the CPU to access the data if the DMA transfer of the data for which the access request is detected has been completed;
And a second step of, if the DMA transfer of the data for which the access request is detected is not completed, performing the DMA transfer of the data with the highest priority, and causing a CPU to access the data for which the DMA transfer has been completed. DMA transfer control method. The DMA controller includes a first register for storing the number of data for which a DMA transfer has not been completed, and a second register for storing an address of data being DMA-transferred,
3. The method according to claim 2, wherein the detecting step includes detecting a match between an address of the data in which the access request is detected and an address of data for which DMA transfer obtained from the first register and the second register has not been completed. DMA transfer control method. The DMA controller is connected between a CPU and a system bus,
The second step includes:
Suspending the ongoing DMA transfer;
DMA-transferring data for which the DMA transfer has not been completed;
Causing the CPU to access the data for which the DMA transfer has been completed;
4. The method according to claim 2, further comprising the step of resuming the interrupted DMA transfer. The DMA controller is connected to a CPU and a main memory via a system bus,
The second step includes:
Requesting a CPU to retry access to data for which the DMA transfer has not been completed;
Suspending a DMA transfer in progress and temporarily DMA-transmitting the data between a time when the CPU temporarily stops accessing the data and a time when the CPU accesses the data again;
4. The method according to claim 2, further comprising the step of restarting the interrupted DMA transfer after the CPU accesses the data for which the DMA transfer has been completed. An apparatus for controlling a memory-to-memory DMA transfer in a data processing system having a main memory connected to a CPU via a system bus, comprising:
Detecting means for detecting an access request from the CPU for data included in the data block being DMA-transferred;
A transfer control unit for causing the CPU to access data in which the access request is detected, prior to a DMA transfer being executed. The detection means,
Means for detecting that the DMA transfer of the data for which the access request has been detected is incomplete,
The transfer control means,
Means for DMA-transferring the requested data with the highest priority;
Means for causing a CPU to access the data for which DMA transfer has been completed. The DMA transfer control device includes a first register for storing the number of data for which DMA transfer has not been completed, and a second register for storing an address of data being DMA-transferred,
8. The detection means includes means for detecting a match between the address of the data for which the access request has been detected and the address of data for which DMA transfer obtained from the first register and the second register has not been completed. DMA transfer control device. 9. The DMA transfer control device according to claim 6, wherein said detection means and transfer control means are connected between a CPU and a system bus. 9. The DMA transfer control according to claim 6, wherein said detection means is connected between a CPU and a system bus, and said transfer control means is connected to the CPU and main memory via a system bus. apparatus. 11. The DMA transfer control device according to claim 10, wherein said detection means includes a buffer memory for temporarily storing data in which the DMA transfer is detected to be incomplete. 12. The DMA transfer control device according to claim 6, wherein a cache memory is connected between the CPU and the system bus.

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