TWI259955B - DMA transfer controlling method and apparatus - Google Patents

Abstract

An object of the present invention is to allow a CPU to refer to data under DMA transfer to thereby reduce latency time of the CPU during the DMA transfer. An apparatus 10 for controlling a DMA transfer comprises means 12 for detecting whether or not a CPU requests access to data being DMA-transferred, and allows the CPU to refer co the data by suspending the DMA-transfer under execution.

Description

1253255. Α7 V. Inventions | Years from the Japanese repair (more), the Ministry of Economic Affairs, Intellectual Property Office, employee consumption cooperatives, printed inventions: The present invention relates to a device and method for controlling a direct memory access A) transfer and More specifically, it relates to apparatus and methods for controlling memory to memory DMA transfer. BACKGROUND OF THE INVENTION Figures 9(a) through 9(d) show memory-to-memory DMA transfer between memory regions implemented in a main memory. In a data processing system shown in Figures 9(a) through 9(d), a central processing unit (CPU) 70, a cache unit 72, a main memory 90 and a DMA controller 82 are provided. Connected to a system bus 80. The cache unit 72 is connected between the CPU 70 and the system bus 80 and includes a tag 74 and a cache 76. The cache 76 is a memory for temporarily storing a portion of the data stored in the main memory 90, and the tab 74 is a memory for storing the address of the data stored in the cache 76. The CPU 70 accesses the cache 76 when the cache 76 stores a target data, and the CPU accesses the main memory 90 when the cache 76 does not store the target data. The main memory 90 is a semiconductor memory such as a dynamic random access memory (RAM). The DM A controller 82 implements a memory-to-memory data transfer between the memory regions of the main memory 90 without the intervention of the CPU 70. Data transfer between memory areas means that a data is transferred from a source memory location of the primary memory 90 to a destination memory location, as shown in Figures 9(a) through 9(b). A data transfer using the DMA controller 82 (Applied to the Chinese national standard r::MS on page 4 of the next page) A specification (2l·2·; ν: (Please read the back of the note first and then fill in this page) #定. B7 V. The invention description (referred to as DMA data transfer in the text) and the processing in cpij70 can be processed in parallel. For example, when multiple instructions or groups of instructions use the same material, the original data is not Direct use, but a backup of the original data is used in many places. In the DMA transfer, the data is transferred on a data block basis. An example of a data block is shown in Figure 10(a). A data block DB contains daTAI, DATA2, DATA3, DATA4 'DATA5, DATA6, DATA7 and DATA8 in the source memory location, and the source memory locations have the address AD Γ, AD in the main memory 90 2,, AD 3 1, AD4', AD5', AD6', AD7, and AD8*. The data DATA1, DATA2, DATA3, DATA4, DATA5, DATA6, DATA7 and DATA8 are copied to the destination memory location and have the main memory. Addresses in the body 9 ADI, AD2, AD3, AD4 AD5, AD6, AD7, and AD8 智慧 Ministry of Economic Affairs Intellectual Property Officer X Consumer Cooperative Print As shown in Fig. 9(a), the DMA controller 82 includes a register 84 (hereinafter referred to as a transfer counter 84). The data used to store the DMA not transferred and a register 86 (hereinafter referred to as the transfer address 86) are used to store the address of the data under the DMA transfer. The data shown in the figure (a) In the example of the block, the transfer counter 84 stores the number of data "8" as a start value. The DMA controller 82 decrements the value of the transfer counter 84 by one every time the DMA transfer is completed. Transfer address 8 6 Store one The address of the source memory location and the address of a destination memory location. In the example of the data block shown in Figure 10(a), the address of the source location AD and the address of a destination location a D 1 is stored as a start value. The DMA controller 82 completes page 5 on each DMA transfer.

Mm T. ;W wn .ΊΓΤΤί, ·, ' ·· .... one, gas ~ «" one m. ' This paper scale applies to the Chinese national standard: ...;) / dv: (210X297 mm) 1259955 A7 B7 5. Inventor's Note () The address of the source and destination is updated. Figure 10(b) is a schematic diagram of the DMA data transfer of a data block DB. Each time the data is transferred, the transfer counter 84 and the transfer bit are transferred. The address 86 is updated and DATA1 to DATA8 are transferred one by one. When the DMA transfer of DATA8 is completed, the value of the transfer counter becomes "〇,, (not shown) and the DMA transfer of the data block DB is completed. . In the first diagram (b), AD 1, AD 1π represents the address of the source location as ad Γ and the address of a destination location is AD1. Under DMA transfer, the CPU waits until the DMA transfer is complete before it can access the data. Fig. 1 1 shows a procedure in which the CPU 70 accesses data stored in a destination memory location. As shown in FIG. 9(b), after the DMA transfer of the data block db is started (S160), the CPU 70 requests access to the data stored in the destination memory location (S162), the DMA transfer is continued (S163). . When the DMA transfer of the data block DB is completed, the DMA controller 82 sends an interrupt signal INT to inform the CPU 70 that the DMA transfer is completed (S166), as shown in Fig. 9(c). Therefore, the transferred material at the destination position can be accessed after the DMA transfer of the material block DB is completed (S168), as shown in Fig. 9(d). For example, as shown in Fig. 12, when the CPU 70 requests access to DATA7 (S162) after the DMA transfer of DATA 1 is completed (S180), the CPU 70 transfers DMA from DATA2 to DATA8 (S182, S184, S186, S188,

The DATA7 at the destination address is accessed after S 1 90 ’ S 1 92 and S 1 92) are completed (S168). Since the CPU 70 cannot access D A T A 7 during the DMA transfer of DATA2 to DATA8, a latency is generated. One object of the present invention is to enable the CPU to apply the Chinese National Standard (CNS) A4 specification (210x297 mm) on page 6 of the DMA transfer. (Please read the note on the back and fill in this page.) Machi. Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printed 1259555 A7 B7, invention description ('hunting to shorten the CPU's dive time during DM A transfer. (Please read the back note first and then fill out this page) The method for controlling the memory-to-memory DMA transfer of the invention comprises the following steps: detecting a cpu requesting access to data included in a data ghost transferred by the DMA, and preferentially allowing the CPU to save during DMA transfer execution Taking the requested data. A device for controlling a DMA transfer according to the present invention includes: detecting a CPU requesting access to a material included in a data block transferred by the DMa; and performing the transfer in the DMA In the present invention, the CPU is allowed to access the requested data. In the present invention, the CPU can access the requested data before the DMA transfer is completed, regardless of whether the requested data has been DMA or not. Therefore, the time spent in the DMA transfer can be shortened for the cpu. Simple description: The Ministry of Economic Affairs Intellectual Property Office employee consumption cooperative printed the first (a) to 1 (d) figure shows An embodiment of the DMA transfer control according to the present invention between the memory locations of a main memory. The first diagram shows an example of a system architecture, and the first (b) diagram shows a control for the DMA transfer. The signal stream, the first (c) diagram shows the access request signal stream from a cpu, and the first (d) diagram shows the signal stream sent by the DMA controller for the DMA transfer data first requested by the CPU. 1259955 A7 B7 V. INSTRUCTIONS () C Please read the precautions on the back and fill out this page.) Figure 2(a) shows that the requested information is completed after the DMA transfer shown in Figure 1(d) is completed. The DMA controller sends the main memory to the CPU, and the second (b) diagram shows the flow of the data requested by the CPU and sent from the cache or the main memory to the CPU. The figure shows a procedure for a DMA transfer of the data block DB controlled by the D Μ A controller shown in Fig. 1(a) An example of Fig. 4 shows an example of a program for transferring a data block DB by dmA by the DMA controller shown in Fig. 1(a). Figs. 5(a) to 5(d) show a master between Another embodiment of the DMA transfer control in accordance with the present invention between the memory locations of the memory. Figure 5(a) shows an example of a system architecture, and Figure 5(b) shows one from during a DMA transfer. An access request for the CPU requires a stream of signals, and Figure 5(c) shows that an address signal of the data requested by the CPU is transferred from a DMA hit detector to the DMA controller when a DMA hit is detected. And Figure 5(d) shows that a signal stream sent by a DMA controller is used to request the CPU to attempt to access the requested data again. Ministry of Economic Affairs, Intellectual Property Office, Staff Consumer Cooperative, Prints a signal stream sent by the DMA controller in Figure 6(a) for accessing the requested data as shown in Figure 5(d) When requested, it is used to instruct the main memory to transfer the requested data to a cache or main memory by temporarily stopping the access of the CPU, and Figure 6(b) shows the completion of the request. After the DMA transfer of the data, the flow of the requested data transferred by the DMA controller to the CPU via DMA transfer, and Figure 6(c) shows that when the eighth page of the paper size is applied to the Chinese national standard ( CNS) A4 specification (210x 297 mm) 1259955 A7 B7 V. Description of invention (The requested data stream from the cache or main memory to the CPU when the DM A hit is not detected. Figure 7 shows An example of a program for controlling DMA transfer performed by the DMA controller shown in Fig. 5(a). Figures 8(a) through 8(c) show memory in a main memory Another embodiment of DMA transfer control in accordance with the present invention between locations. Figure 8(a) shows an example of a system architecture, 8th ( b) the figure shows the DMA-transferred data stream sent to the buffer by the DMA controller, and Figure 8(c) shows a data stream in which the DMA hit detector will be stored in the 8(b) The data in the buffer is transferred to the CPU. Figures 9(a) through 9(d) show an embodiment of a conventional DMA transfer control. Figure 9(a) shows an example of a system architecture, page 9 (b) The figure shows the signal flow used to control a DMA transfer, and the 9th (c) diagram shows the signal flow from the DMA controller to a CPU to announce that the DMA transfer has been completed, and the 9th (d) figure shows An access between a CPU and a cache or main memory. Figure 10(a) shows an example of a data block to be transferred by DMA, and an ith (b) diagram is displayed in the DMA controller. The value of a transfer counter and the position information of a transfer address and the status data of each data. Fig. 11 shows an example of a program for controlling a DMA transfer using the DM A controller shown in Fig. 9(a). Figure 12 shows the 9th page of the implementation of a data block using the DMA controller in Figure 9(a). This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) ( Please read the notes on the back and fill out this page. Loading. -Settings · Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperatives Printed 1259555 _Li IIIIMWT1 I III ----- Mouse 5, Invention Description (A7 B7 t\mm i, a»—iM's·*·»taars «qgai·丨Μΐ«ι_·ιη 蝻........ ·ι · Example of DMA transfer program comparison: 70 Central Processing Unit (CPU) 72 Cache unit 90 Main Memory 82 DMA Controller 80 汇 汇 74 74 Tab 76 Cache 84 Transfer Counter 86 Transfer Address (Scratchpad) 10 Device (DMA Controller) 12 DMA Hit Detector 22 DMA Hit Detector 20 DMA Controller Ministry of Economic Affairs Intellectual Property Office Staff Consumption Cooperation Invention Detailed Description: Next, an embodiment of a method and apparatus for controlling memory-to-memory DMA transfer according to the present invention will be described in detail with reference to the accompanying drawings. . In the following embodiments, a memory-to-memory DMA transfer is implemented between the memory areas of a main memory. In a data processing system shown in the drawings, it is assumed that a CPU 70, a cache unit 72, a system bus 80 and a main memory 90 are similar to the conventional structure shown in Fig. 9(a). In addition, it is assumed that a data block DB to be transferred is also similar to the conventional data block shown in the figure i(a). A device (DMA controller) for controlling memory-to-memory DMA transfer shown in Figures 1(a) to 1 according to the present invention includes a DMA hit detector for detecting a CPU pair A request for access to data at a destination memory location, which may be included in a DMA transfer. Page 10 J Λ > - ~ 〇«η wraiwi _____. plus tftttir······ Rmniri: —ninn Applicable to China National Standard (CNS) A,·, :210〉: 297 mm) (Please read the note on the back 1 and fill out this page)

B7 Five 'Invention Description () (Please read the note on the back and fill in the page) The information in the moved block is updated. The role of the DMA controller i is to have the CPU access the requested data to be written to the destination location prior to the DMA transfer in progress. A DMA controller 10 including the DMA hit detector 丨2 is connected between the C P U 70 and the system bus § 。. The DMA hit detector 12 detects whether the CPU requires access to data that has not been DMA-transferred, i.e., will be written to a destination that was accessed by the cpu but not yet transferred by the DMA. When a hit is detected, the DMA controller 10 suspends the DMA transfer and then sends the requested data to the CPU 70. Printed by the Intellectual Property Office of the Ministry of Economic Affairs, the Consumer Consortium. Similarly to the conventional DMA controller, the DMA controller 1 includes a shift counter 84 and a transfer address register 86. The DMA hit detector 12 can know the destination of the data that has not been DMA transferred from the transfer counter 84 and a branch address register 86. The address of the material accessed by the CPU 70 is sent to the cache unit 72 and the DMA controller 1A. The DMA hit detector 12 compares the address of the data requested by the CPU 70 (hereinafter referred to as the requested data) with the destination address of the data that has not been transferred by the DMA to detect whether the two match. When the address of the requested material matches the destination address of the destination, the address is hereinafter referred to as "DMA hit π. When a CPU access request occurs, the destination address in the transfer address register 86 and the count in the transfer counter 84 and the address of the data requested by the CPU are represented by ADi and Ci, respectively. A DMA hit will occur at (ADi) <(ADcpu)<(ADi + Cj). It should be noted that the data block addresses within the transfer address register 86 are in order. When a DMA hit is detected, it means that the requested data is on page 11 of this paper scale applicable to China National Standard (CNS) A4 (210X297 mm) 1259955 V. DMA transfer of invention description () Not completed. The DMA controller 1 pauses the DMA transfer of a block of material in execution and performs a dma transfer of the requested material. After the DMA transfer of the requested material is completed, the DMA controller 10 sends the requested material from the source location to the CPU 70. The suspended DM A transfer is then resumed by consulting the transfer counter 84 and the transfer address register 86. When a DMA hit is not detected, the DMA transfer of the requested data has been completed. In this case, the CPU 70 can access the requested data even if the DMA transfer of a data block has not been completed. The CPU 70 accesses the cache 76 or the main memory 9 via the cache unit 72 to obtain the requested material. As a result, regardless of whether a DMA hit is detected, the CPU can access the requested data under the DMA without waiting for the completion of the DMA transfer. Next, a DMA transfer control using this DMA controller 10 will be explained. Figure 3 shows an example of a program for controlling a DMA transfer. Assuming that the DM A controller 10 starts to display the DMA transfer of a data block as shown in the first (b) (S160), the CPU 70 requests access to the data (S162). The address ADn of the requested data DATAn is then sent from the CPU 70 to the DMA controller 1 and the cache unit 72 as shown in Fig. 1(c). In the DMA controller 10, the DMA hit detector 12 checks if a DMA hit is detected (S11).

When a DMA hit is detected, the DMA controller 10 suspends the DMA transfer of the data block in execution and implements the DMA of the requested data. The 12th page of the paper scale applies the Chinese National Standard (CNS) A4 specification.袼(210X297公楚) (Please read the notes on the back and fill out this page) ^J· Ministry of Economic Affairs, Intellectual Property Office, Staff and Consumer Cooperatives Printed 1259555 A7 B7 V. Inventions () (Please read the notes on the back first) Write this page again) Transfer (S 1 1 4) as shown in Figure 1 (d). When a DMA hit is detected, the DMA controller 1 preferentially uses the system bus. After the transfer of the requested data is completed, the controller 10 sends the requested data (〇八丁八11) from the source location of the main memory 90 to CPlj7〇 (S 1 16), as in the first 2(a) shows the figure 'and then restarts the suspended DMA transfer (S 124). When a DMA hit is not detected, the dmA controller 10 suspends the DMA transfer of the data in execution (S1 13). As shown in Fig. 2(b), the CPU 70 is allowed to access the cache memory 76 or the main memory 90 via the cache unit 72 (S1 18). After the CPU 70 has accessed the requested material, the controller 10 restarts the DMA transfer of the suspended data block (S 124). When all the data contained in the data block has been transferred (8164), the 控制器8 controller 1 sends a signal to inform 11; 700% eight transfer has been completed (S166). For example, as shown in Fig. 4, assuming that a DMA transfer is started (S 160) and a DMA transfer of DATA1 is completed (S180), the CPU 70 requests access to DATA 7 (S162). The DMA controller 1 suspends the DMA transfer (SU2) of the data block in execution and preferentially implements a transfer of dATA7 (S1 20). In this example, the value of the transfer counter 84 is "7", and the transfer position of the Ministry of Economic Affairs Intellectual Property Office employee consumption cooperative print address register 86 stores the position information of the DMA transfer at the time of suspension "ad2, AD2,". After the DMA transfer of DATA7 is completed, the DMA controller 1 sends DATA7 to the CPU 70 (S122), and then restarts the DMA transfer of the suspended data block DB (S124). When a series of DMA transfers from 〇ΑΤΑ2 to DATA8 are completed (S182, S184, S186, S188, S190, S192 and 13) This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) A7

Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing 1259955 V. Invention description () S194), the DMA controller sends a signal to inform cpU7 that the DMA transfer of the data block has been completed (S166). When DATA2 to DATA8 are transferred by DMA, CPU 70 can perform an operation using DATA7. In an example shown in Fig. 4, the DMA transfer of datA7 is again implemented in step S192, which is not a problem because the CPU 70 only consults DATA7. The system shown in Fig. i can be implemented by a single processor including a CPU, a cache unit and a DMA controller. Although an embodiment of the present invention has been described, the present invention can be implemented by its E embodiment. For example, as shown in FIG. 5 (the figure, the DMA hits the debt detector 22 can be connected between the CPU 70 and the system bus 8 ,, and the dMA controller 20 can be connected to the system bus 8 〇 Between the CPU 7 and the main memory 90, the DMA hit detector 22 detects a dMa hit as a DMA by consulting the < transfer counter 84 and the transfer address register 86 in the DMA controller 20. When the hit is detected, the DMA controller 20 causes the CPU 70 to attempt to access the requested data at the destination again. The DMA controller 20 suspends the dMa transfer of an executing data block and the requested data. The DMA transfer is performed until the CPU 70 accesses the requested data again. After the CPU 70 accesses the requested data transferred via the DM A, the DMA controller 20 restarts the DMA transfer of the suspended data block. The figure shows an example of a program for controlling a dmA transfer. As shown in FIG. 5(b), when the CPU 70 starts the DMA transfer (S 160) of a data block, the CPU 70 requests access at the destination. Information on page 14 of this paper scale applies to China Standard (CNS) A4 specification (210X297 mm) (Please read the note on the back and fill out this page) Loading. - Booking · 1259 State V. Invention Description () A7 B7 'The requested information is 八八八The address of the address 11 of the eleven is sent from the € 1170 to the DMA hit detector 22 and the cache unit 72. The inquiry is made by consulting the transfer counter 84 and the transfer address register 86 in the DMA controller 20. The DMA hit is detected. When the DMA hit is detected, the detector 22 sends the requested address of the data ADn to the DMA controller 20 via the system bus 80 (S 1 30), as in the fifth (c In the example, the requested data is data that has not been transferred by DMA. After receiving the address ADn from the detector 22, the DMA controller 20 requests the CPU 70 to temporarily stop accessing the data. The requested data (S13 2) is as shown in Fig. 5(d). The CPU 70 temporarily stops accessing the requested data, and after a predetermined time, the CPU 70 re-accesses the requested data. When the access to the data is temporarily stopped, the controller A 20 suspends the d Μ A transfer of a data block being executed (S 1 1 2), such as Figure 6(a) shows and implements the DMA transfer of the requested data DAT An (S134). When the CPU 70 re-accesses the data at the destination address, the data has been updated by the DMA-transferred data. As shown in Fig. 6(b), after the CPU 70 accesses the DATAn (S136), the UI controller 20 restarts the reading of the back side.

Order

The DMA transfer of the suspended data block is printed by the employee of the Ministry of Economic Affairs, Finance and Welfare Bureau (S 124). When all the data included in the data block is transferred by DMA (S164), the DMA controller 20 sends a signal to inform the CPU 70 that the DMA transfer has been completed (S166). In Fig. 7, when the DM A hit is not detected, the CPU 70 accesses the cache 76 or the main memory 90 via the cache unit 72, as shown in Fig. 6(c). In this case, the DMA controller 20 suspends the data block being executed.

1259955 V. DMA transfer (S1 13) of the invention description () (please read the back of the note first and then fill out this page). Then, when the CPU 70 completes the access of the requested material (S1 18), the DMA transfer of the suspended data block is restarted (S124). As in the p program shown in Fig. 4, even if the CPU 70 requests access to DATA7 (S162) after a DMA transfer is started (S160) and the DM A transfer of DATA1 has been completed, the DMA transfer of DATA7 can be First implemented. Although DATA2 to DATA8 are being transferred by DMA, the CPU can use DATA7 to perform an operation. The system shown in Figure 5(a) can be implemented as a single processor including a CPU, a cache unit and a DMA controller. As shown in Figure 8(a), a buffer 34 can be coupled to the DMA hit detector 32. After the CPU 70 accesses the requested material, the data or data block detected as a DMA hit is temporarily stored in the buffer 34. When the CPU 70 re-accesses the data stored in the buffer 34, the DM A hit detector 32 sends the data stored in the buffer 34 to the CPU 70. As such, the buffer 34 can reduce the number of repetitions required. LINE INTELLIGENT INTELLECTUAL PROPERTY AGENCY WORKING COOPERATION CO., LTD. Although an embodiment of the present invention has been described, it should be understood that the present invention is not limited to the embodiments described above. For example, although memory-to-memory DMA transfer between memory regions in the main memory is described in this specification, the present invention can also be applied to any high-speed memory connected to a system bus. The transfer of memory to memory. Moreover, the requested data described with reference to Figs. 1 to 4 is sent from a source location to the system of the CPU, and step S 1 1 4 in Fig. 3 can be omitted. Many variations, modifications, and other uses and applications of the above-described embodiments can be made by those skilled in the art without departing from the scope of the invention. Page 16 This paper scale applies to China National Standard (CNS) A4 regulations (2丨0X297 mm) 1259955_

vT

• dI VI. Patent Application No. 4 (Please read the back of the note and fill in this page) 1. A control DMA (direct access memory) controller implements a memory-to-memory in a data processing system A method for DMA transfer, the data processing system includes a main memory connected to a CPU (Central Processing Unit) via a system bus. The method includes at least the following steps: a detecting step for detecting a memory Taking a cpu request including data in a data block being transferred by DMA; and an enabling step for preferentially allowing the CPU to access the requested data during execution of the DMA transfer. 2. The method of claim 1, wherein the detecting step comprises detecting whether the requested data has been transferred by DMA; and the allowing step comprises: a first step of allowing the CPU to save Taking the requested data 'if the requested data has been transferred by DMA; and a second step of suspending the DMA transfer to preferentially allow the CPU to access the requested data if the requested data Has not been transferred by DMA. Printed by the Intellectual Property Office of the Ministry of Economic Affairs, Employees' Consumer Cooperatives. 3. The method of claim 2, wherein the DMA controller comprises: a first register for storing the number of data that has not been transferred by the DM A And a second register for storing the data in the DMA storage. Page 17 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm).

Claims (1)

1259955 A8 B8 C8 D8 VI. The scope of the patent application; and the detection steps include: (Please read the note on the back and fill in the page) Compare the address of the requested information with the first and the first The address of the data obtained by the second register that has not been transferred by the DMA is used to determine whether the match is met. 4. The method of claim 2, wherein the DMA controller is coupled between the CPU and the system bus, and the second step comprises: having the DMA controller request the The data is sent to the CPU; and the DMA transfer is resumed. 5. The method of claim 2, wherein the DMA controller is connected between the CPU and the main memory via the system bus, and the second step comprises: requiring the CPU to be again Accessing the data that has not been transferred by the DMA; suspending the DMA transfer during execution to DMA transfer the requested data until the CPU accesses the data again; and after the CPU accesses the data that has not been transferred by the DMA, Restart the suspended DMA transfer. Ministry of Economic Affairs, Intellectual Property Office, Staff Consumer Cooperative, printed on a device that controls the transfer of memory to memory DM A in a data processing system, the data processing system including a main memory connected to the system via a system bus A CPU, the device comprising at least: a detection mechanism for detecting access to a paper size that is being applied to the 18th page of the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 1259955 A8 B8 C8 D8 Ministry of Economic Affairs Intellectual Property Office Employees Consumption Cooperatives Printing VI. Applying for a patent range D Μ A A CPU requirement for the data in the data block transferred; and allowing the machine component to be used in the execution of the DMA transfer, The CPU is preferentially allowed to access the requested data. 7. The device of claim 6, wherein the detecting means includes means for detecting that the requested material is data that has not been transferred by DMA, and the permitting mechanism comprises: • Priority DMA The institution that transfers the requested data; and the institution that allows the CPU to access the data that has been transferred by the DMA. 8. The device of claim 7, further comprising: a first register for storing the number of data that has not been transferred by the DM A; and a second register for storing the DM The address of the data in the storage A, wherein the detecting means includes comparing the address of the requested data with the address of the data obtained from the first and second temporary registers that has not been transferred by the DM A to determine Whether it is consistent with the institution. 9. The apparatus of any of claims 6-8, wherein the debt testing mechanism and the permitting mechanism are connected between the cpu and the system bus. 10. The device of any one of claims 6-8, wherein the integration mechanism is connected between the cpu and the system bus and on page 19 (please first read the back note) Fill in this page) # 丨定- ,线 - This paper scale applies to China National Standard (CNS) A4 specification (21〇X 297 public) Six 1259955 Μ C 8 D8 Patent application scope The allowed mechanism is connected via the system It is connected between the CPU and the main a memory. J. The device of claim 1, wherein the detection mechanism includes/buffer memory for temporarily storing data that is detected as data that has not been transferred by the DMA. The device of any one of claims 6-8, wherein one of the cache memories is connected to the CPU and the system is brewing < .....: ¥ Loading · (Please read the notes on the back and fill out this page) Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed on page 20 This paper scale applies to China National Standard (CNS) A4 specification (210x297 mm)