JPH10198644A - Synchronous control method and multi-processor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten synchronous processing time by executing cache coherence guarantee processing only between optional processors requiring synchronous processing. SOLUTION: A communication register common to plural processors is built in a storage control device 2. When the cache coherence guarantee processing of a POST instruction issuing processor 3a has been completed, control data for informing of the completion of the processing are stored in the register 22. At the time of detecting the storage of the control data in the register 22, an WAIT side processor 3b executes the cache coherence guarantee processing, and at the completion of the guarantee processing, executes an instruction following an WAIT instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system having a plurality of processors, each of which can execute a program in synchronization with each other. And a multiprocessor system.

[0002]

2. Description of the Related Art For example, a SYNC instruction is defined as a method of synchronizing processors in a shared-memory multiprocessor. This SYNC instruction performs cache coherence guarantee processing of an instruction preceding the SYNC instruction, and after completion of the cache coherence guarantee processing, SYNC
This is an instruction for performing a synchronization process among all processors constituting a multiprocessor by executing an instruction following the instruction.

[0003]

For example, in a case where synchronization processing is required only between two arbitrary processors in four multiprocessors of a shared main memory type, if the above-mentioned conventional SYNC instruction is used, the original In spite of the fact that the cache coherence assurance process between only two processors needs to be performed, the cache coherence assurance process between all processors must be executed, and as a result, the time required for the synchronization process becomes longer. There is a point.

An object of the present invention is to provide a synchronous control method and a multiprocessor system in which the synchronous processing time is shortened by performing cache coherence guarantee processing only between arbitrary processors that require synchronous processing.

[0005]

The present invention comprises a plurality of processors having a main memory and a cache memory, and a storage controller for performing data transfer between the main memory and the plurality of processors and cache coherence control between processors. In a computer system, a synchronization source processor notifies a synchronization destination processor of the completion of synchronization processing of a synchronization source processor by executing a POST instruction, and the synchronization destination processor waits for issuance of the POST instruction by executing a WAIT instruction. Program synchronization method. The present invention is characterized in that the storage control device is provided with an inter-processor shared register in order to realize the synchronization method.

When the POST-side processor and the storage controller detect the completion of the cache coherence assurance processing of the POST instruction issuing processor accompanying the POST instruction, the post-processor and the storage control device store synchronization control data for notifying the processing completion in the inter-processor shared register. When the WAIT-side processor and the storage controller detect that the POST instruction issuing processor has stored control data in the inter-processor shared register in order to notify the completion of the cache coherence assurance processing, the WAIT instruction issuing processor executes the cache coherence assurance processing of the WAIT instruction issuing processor. WAIT when the processing completion is detected
Start execution of the instruction following the instruction.

Further, a control flag stored in the shared register is provided with a cache coherence guarantee processing completion flag of the POST processor, and the flag is written when the cache coherence guarantee processing of the POST instruction issuing processor is completed. A report of the completion of the guarantee processing.

In the above-mentioned synchronous processing, a POST for executing a cache coherence assurance processing in response to a POST instruction
An instruction and a POST instruction that does not execute cache coherence assurance processing are provided, and a WAIT instruction that executes cache coherence assurance processing and a WAIT instruction that does not execute cache coherence assurance processing are provided as WAIT instructions. This makes it possible to select whether or not to execute the cache coherence assurance process.

A cache coherence assurance flag is provided in the control data. When the POST instruction for executing the cache coherence assurance processing is executed, the cache coherence assurance processing of the POST instruction issuing processor is performed, and the cache coherence assurance flag and the synchronization control data are transmitted. At the time of writing and executing the POST instruction which does not execute the cache coherence assurance processing, the POST
It is characterized in that the synchronous control data is written without performing the cache coherence guarantee processing of the instruction issuing processor and the setting of the cache coherence guarantee flag. The WAIT processor checks whether the cache coherence assurance process is performed by checking the cache coherence assurance flag without providing a WAIT instruction for executing the cache coherence assurance process and a WAIT instruction for not performing the cache coherence assurance process. Can be determined.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 1 is an overall configuration diagram of an embodiment of the present invention. In FIG. 1, 1 is a main storage device, 2 is a storage control device, and 3 is a processor. In the present embodiment, for example, four processors are provided, and 3a to 3d are processors 0 to 3, respectively. Each of the processors 3a to 3d has a cache memory 30a to 30d, respectively.
30d and storage controller interface controller 31a-
31d is provided.

The storage controller 2 includes a cache directory reference controller 20 and cache coherence controllers 21a to 21d corresponding to the processors 0 to 3, respectively.
And a communication register 22.

FIG. 1 shows a multiprocessor system of a main memory sharing type in which a plurality of processors 0 to 3 and one processor shares one main storage device 1.

FIG. 2 shows a cache coherence controller 2.
1 is shown. 2, reference numeral 210 denotes a coherence control request stack; 211, a cancel stack; 212, a processor interface control unit;
Is a cache request control unit.

FIG. 3 shows the communication register 22.
Is shown. In FIG. 3, reference numeral 220 denotes a register body,
221, a write control unit; 222, a read control unit;
Is a communication register interface control unit.

In FIG. 1, data transfer is performed by a data signal line 4 between the main storage device 1 and the cache memory 30 in the processor 3. Normally, when a STORE instruction to the main storage device 1 occurs, the storage controller interface controller 31 causes the cache coherence controller 2
1, the target address of the STORE instruction is notified, and the cache coherence processing of the block including the target address is requested by the storage controller interface signal 33. In the processor that has executed the STORE instruction, the address of the STORE instruction is compared with the address of its own cache directory.
When they match, the cache block including the address of the STORE instruction is invalidated.

The cache coherence control unit 21 requests the cache directory reference control unit 20 to issue a cache cancel request to another processor 3 through the cache directory reference control interface 23. The cache directory reference control unit 20 records the addresses of the blocks stored in the cache memories 30a to 30d in each processor.
The cache coherence control units 21a corresponding to all processors having data of the block of the same address if they are compared with and matched with the target address of the TORE instruction
Issue a cache cancel request to .about.21d.

The cache cancel requests stored in the cache coherence control section 21 are sequentially transferred to the storage controller interface control section 31 in the processor, and the cache block having the above address is invalidated to cancel the cache cancellation. Done.

<Embodiment 1> FIGS. 4A and 4B show the instruction specification of the POST / WAIT instruction of the present invention. In FIG. 1, when the four processors 3a to 3d are operating, the POST instruction of FIG.
The first embodiment will be described below in the case where the WAIT instruction is executed by the processor (1) 3b, and the two processors (0) 3a and the processor (1) 3b execute the program in synchronization with each other. .

Processor (0) is designated as the POST-side processor number in the WAIT instruction. And POS
The T-side processor (0) 3a executes ST before the POST instruction.
The ORE instruction (STA) is being executed. When the POST instruction is executed by the processor (0), the WAIT
The completion of the synchronization processing is notified to the processor (1) executing the instruction and waiting for the completion of the synchronization processing. Upon receiving this notification, the processor (1) executes the instruction following the WAIT instruction. That is, for example, the data A processed by the STORE instruction is read by executing the LD instruction (LDA), and thereby the programs are executed in synchronization between the processors.

Now, the processor (0) 3a in FIG.
When the ST instruction is decoded, the storage controller interface controller 31a notifies the cache coherence controller 21a of the POST instruction by the storage controller interface signal 33a.

The cache coherence control unit 21 shown in FIG.
a, the processor interface control unit 212 sets the PO
The notification of the ST command is sent to the coherence control request stack 210 as a POST signal 214. The coherence control request stack 210 includes the previous STOR
The address at the time of issuing the E instruction is stacked on the stack as a request. When the coherence control request stack 210 sends out all the coherence control requests in the stack to the cache directory reference control unit 20 via the cache request control unit 213 while the POST signal 214 is valid, the coherence control request stack 210 A request stack empty signal 215 is sent to the processor interface control unit 212.

Processor interface control section 212
Is the coherence control request stack empty signal 215
In response to this, it is considered that the cache coherence assurance process of the POST processor in the POST instruction has been completed, and the storage controller interface controller 31a of the processor (0) is notified of the POST processor by the storage controller interface signal 33a. Notifies the completion of the cache coherence assurance process.

Upon receiving the completion of the cache coherence assurance process, the storage controller interface controller 31a
Communication register interface signal 32a
The control data 51 shown in FIG. In the communication register 22 of FIG. 3, the control data 51 is sent from the communication register interface control unit 223 to the write control unit 221, and is written into the register 220 under the control of the write control unit 221.

Here, the control data in the register 220 is, for example, an initial value “0”, and the control data written by the POST-side processor is, for example, “1”. That is, by executing the POST instruction, the synchronization processing is completed, and the cache coherence assurance processing is completed, so that the POST-side processor 3a writes the control data “1” to the register 22.

In the processor (1) 3b that has decoded the WAIT instruction, the storage controller interface controller 31b uses the communication register interface signal 32b to communicate with the communication register 2b.
A read request is issued to No. 2. In the communication register 22 of FIG. 2, a read request is sent from the communication register interface control unit 223 to the read control unit 222, and the control data 51 in the register is read. The read control data 51 is transferred to the storage controller interface controller 31b by the communication register interface signal 32b via the read controller 222 and the communication register interface controller 223.

The storage controller interface controller 31b of the WAIT-side processor 3b decodes the read control data 51 and checks whether valid writing is being performed. If valid writing has not been performed, the above reading is repeated until valid writing is performed. Here, when the control data 51 of the register 220 changes from “0” to “1”, it is confirmed that the writing is valid.

When it is confirmed that valid writing has been performed, the storage controller interface controller 31b
Is sent to the cache coherence controller 21b by the storage controller interface signal 33b.
Notify IT command. At that time, the corresponding POST-side processor number (NO 0) specified by the WAIT instruction is also transferred.

The cache coherence controller 21 shown in FIG.
b, the processor interface control unit 212, which has received the notification of the WAIT instruction,
1 sends a WAIT signal 216 and a POST-side processor number notification signal 217. In the cancel stack 211, a cache cancel request having a POST processor number is stacked. This PO
The ST-side processor number is attached to the cache cancel request by the cache directory reference control unit 20, and sent to the cache coherence control units 21b, c, and d.

Then, the cancel stack 211 checks whether or not a cache cancel request having the same POST-side processor number as the number notified by the signal 217 exists in its own stack. If there is, a cache cancel request having the POST-side processor number is sent from the stack 211 to the processor interface control unit 212 by a signal 219. The cache storage block in the processor 3b is invalidated based on the transmitted cancel request.

When the WAIT signal 216 is valid, the cancel stack 211 completes the cache coherence assurance processing of the WAIT processor based on the fact that all cache cancel requests having the POST processor number have disappeared from the stack. And a cache coherence assurance process completion notification 218 is reported to the processor interface control unit 212.

Processor interface control section 212
Reports the completion of the above-described cache coherence assurance processing to the storage controller interface controller 31b by the storage controller interface signal 33b. Then, the processor (1) 3b, which has received the completion of the cache coherence assurance processing by the storage controller interface controller 31b, executes the subsequent instruction (LD) of the WAIT instruction.
The execution of A) is started, and the synchronization process is completed.

Second Embodiment The control data 51 of the first embodiment is data indicating both the completion of the synchronization process and the completion of the cache coherence assurance process. As shown in FIG. 5B, the data includes synchronization control data 54 indicating completion of the synchronization processing and a completion report flag 53 of the cache coherence assurance processing. Hereinafter, a second embodiment will be described.

The POST-side processor first communicates with the communication register 2 before the storage controller interface controller 31 instructs the cache coherence controller 21 to perform a series of cache coherence assurance processes.
2 is instructed to write the synchronization control data 54. Here, for example, when the synchronization processing is completed, “1” is written as the synchronization control data 54.

Next, after the cache coherence assurance process on the POST side is performed as described above, when the cache coherence assurance process is completed, writing of the cache coherence assurance process completion report flag 53 is performed in the same manner as writing of the synchronization control data 54. This is performed under the control of the communication register interface control unit 223 and the write control unit 221 in the communication register 22. Here, for example, when the guarantee processing is completed, the flag 53
Is set to "1" (valid), and if not completed, the flag is set to "0" (invalid).

In order to detect the completion of the cache coherence assurance processing of the POST processor, the WAIT processor immediately executes the synchronization control data 5 in the register 220.
4 is read, first, only the cache coherence assurance processing completion report flag 53 is read. The read cache coherence assurance processing completion report flag 53
The read control unit 222 checks whether the flag is valid, and if not valid, continues reading the flag 53 until it is valid.
At the same time, the data is sent to the storage controller interface controller 31 via the communication register interface controller 223, and thereafter, the above-mentioned WAIT instruction is processed.

<Embodiment 3> This embodiment is an embodiment for selecting whether or not to perform cache coherence assurance processing. In the present embodiment, as shown in FIG.
Coherence assurance processing to indicate whether or not to perform coherence assurance processing during instructions and WAIT instructions /
C bit indicating nothing is added. That is, C bit
When the coherence assurance process of = 1 is performed, the cache coherence assurance process is performed in the same manner as described in the first embodiment.

When the coherence assurance process of C bit = 0 is not performed, in executing the POST instruction, the storage controller interface control unit 31 performs a process related to the cache coherence assurance process on the cache coherence control unit 21. Instead, the control data 51 indicating the completion of synchronization to the communication register 22
Is written in the above-described procedure.

In the execution of a WAIT instruction that does not perform coherence assurance processing of C bit = 0, the WAI instruction
When the storage controller interface control unit 31 of the T-side processor detects that the control data 51 is written to the communication register 22 by the POST-side processor, the cache coherence control unit 21 is not controlled for the cache coherence assurance processing, and the WAIT instruction is executed. The synchronous control is performed by starting the execution of the subsequent instruction.

<Embodiment 4> In this embodiment, a cache coherence assurance flag 56 is provided in the control data 55 as shown in FIG. 5C in order to instruct whether or not to perform cache coherence assurance processing. As a result, FIG.
With regard to the WAIT instruction of (b), it is not necessary to provide a C bit indicating whether or not coherence assurance processing is performed.

When the write control unit 221 in the communication register 22 writes the control data 55 to the register 220 during execution of the POST instruction, the write control unit 221 performs cache coherence assurance processing in which C bit is “1”.
In the OST instruction, the cache coherence guarantee flag 5
6 is set to be valid and the cache coherence assurance flag 56 is invalidated in the case of the POST instruction in which the C bit is “0” and the cache coherence assurance processing is not performed.

When the WAIT instruction is executed, the control data 55 with the cache coherence assurance flag 56 is read by the read control unit 222 in the communication register 22, and the storage controller interface control unit 31 checks the cache coherence assurance flag 56. If it is valid, the cache coherence assurance process is performed. If it is invalid, the execution of the instruction following the WAIT instruction is started without performing the cache coherence assurance process.

[0042]

As described above, according to the present invention, an inter-processor shared register is provided in a storage control device, and any processor for performing synchronous control is individually set via an inter-processor shared register. Since the control data for reporting the completion of the cache coherence assurance processing is transferred, it is possible to individually perform the synchronization processing between arbitrary processors in the system.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

FIG. 2 shows a configuration of a cache coherence control unit.

FIG. 3 shows a configuration of a communication register.

FIGS. 4A and 4B are POST / WAI of the present invention.
The instruction specification of the T instruction is shown.

FIGS. 5A, 5B, and 5C show formats of control data.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main storage device 2 Storage control device 3 Processor 4 Data signal line 20 Cache directory reference control unit 21 Cache coherence control unit 22 Communication register 23 Cache directory reference control interface 30 Cache storage 31 Storage control device interface control unit 32 Communication register interface Signal 33: Storage controller interface signal

Continuation of the front page (72) Inventor Tadaaki Isobe 1 Horiyamashita, Hadano-shi, Kanagawa In the general-purpose computer division of Hitachi Corporation

Claims (5)

[Claims] 1. A main storage device, a plurality of processors each having a cache storage unit for storing a copy of a part of data in the main storage device, and data transfer between the main storage device and the plurality of processors. In a multiprocessor system including a storage controller for performing cache coherence control between processors, a synchronization
By executing the ST instruction, the synchronization destination processor is notified of the completion of the synchronization processing.
A method for controlling synchronization between processors employing a program synchronization method, in which a T instruction is executed to wait for the issuance of the POST instruction, wherein the storage control device executes the POST instruction when the synchronization source processor executes the POST instruction. Notifies the synchronization source processor of the completion of the cache coherence assurance process generated by the store instruction executed before, and the synchronization source processor sends control data indicating the completion of the synchronization process and the guarantee process to the storage control device. Write, the WA
When the synchronization destination processor that has executed the IT instruction detects the writing of the control data, it causes the storage control device to execute the cache coherence guarantee processing of the synchronization destination processor.
A synchronous control method characterized by executing an instruction following an IT instruction. 2. The control data includes first data indicating whether synchronization processing has been completed and second data indicating whether cache coherence guarantee processing of the synchronization source processor has been completed. 2. The synchronization control method according to claim 1, wherein a completion of the cache coherence assurance processing of the synchronization source processor is reported to the synchronization destination processor using the second data. 3. The POST instruction and the WAIT instruction include information indicating whether or not to perform a cache coherence assurance process. When the POST instruction and the WAIT instruction are executed, a cache coherence assurance process is performed based on the information. The method according to claim 1, wherein: 4. The POST instruction includes information indicating whether or not to perform cache coherence assurance processing, and the control data includes third data indicating whether or not synchronization processing has been completed and cache coherence assurance is valid. When the synchronization source processor executes a POST instruction for performing cache coherence guarantee processing, the fourth data includes data indicating that cache coherence guarantee is valid. Writing, when the synchronization source processor executes a POST instruction that does not perform cache coherence guarantee processing, writes data indicating that cache coherence guarantee is invalid in the fourth data, and executes the WAIT instruction,
When the fourth data is valid, a cache coherence guarantee process of the synchronization destination processor is performed, and the W
2. The method according to claim 1, wherein the instruction following the AIT instruction is executed, and when the fourth data is invalid, the instruction following the WAIT instruction is executed without performing the cache coherence guarantee processing of the synchronization destination processor. Synchronous control method described. 5. A main storage device, a plurality of processors having a cache storage unit for storing a copy of a part of data in the main storage device, data transfer between the main storage device and the plurality of processors, A storage control device for performing cache coherence control between processors, a synchronization source processor that notifies a synchronization destination processor of completion of synchronization processing by executing a POST instruction among the plurality of processors, and a WAIT instruction. A multiprocessor system in which a synchronization destination processor that waits for the issuance of the POST instruction by executing the program executes a program in synchronization with the shared register between the processors, and executes a POST instruction of the synchronization source processor. P
Means for detecting the completion of the cache coherence assurance processing generated by the store instruction executed before the OST instruction; and, upon detecting the completion of the assurance processing, predetermined data indicating the completion of the synchronization processing and the assurance processing. Means for writing to the register; means for referring to the register when the WAIT instruction of the synchronization destination processor is executed; and cache coherence of the synchronization destination processor after detecting that predetermined data is written to the register. A multiprocessor system comprising: means for detecting completion of the guarantee processing; and means for executing an instruction subsequent to the WAIT instruction after detecting completion of the guarantee processing.