JP2002541548A - Global bus synchronous transaction acknowledgment with no response detection - Google Patents

Abstract

(57) Summary An integrated multiprocessor system comprising a cluster (13 ₀ , 13 ₁ , 13 ₂ , 13 ₃ ) of processors (25) on a high-speed split transaction bus (16) requires a request from a master device on the bus. Transaction acknowledgment (TACK) by the target device in response to receipt of The master and target devices are connected to the bus via a global bus interface (17; 31B, 33B), the FIFO registers (31A, 33A) act as buffers, and the target interface is configured so that broadcast requests are addressed to the target device. And a TACK generator (FIG. 6) for inverting the state of the global bus TACK line (TACK number). The bus idle default device (BIDD) (18 in FIG. 8) generates a TACK signal when no device is on the bus and monitors the state of the TACK line to detect the absence of any TACK response (165). , Thereby providing an indication to the master device attempting to address a non-existent target device. BIDD then generates a dummy response with the flag set to invalid data for the requesting master device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] Technical Field This invention relates to integrated circuit architectures having an on-chip high-speed bus comprises a number of medium-speed device attached on-chip or off-chip, in particular, the command or data transfer between devices across the bus, A handshake method and circuit for receiving an acknowledgment by a target device of a command or data packet located on a bus.

[0002] BACKGROUND ART Typical bus systems, bus is the same speed or where slower rate than this a device to be mounted. The system bus is positioned on the printed wiring board, the processor and the memory chip module are bonded to the board, and the bus experiences capacitance and inductance delays that slow the transfer of information between the various chips across the bus. In such systems, the first bottleneck in information transfer is the bus, not the device, and latency and bandwidth calculations involve arbitration delay to gain access to the bus.

When the entire system, or most of it, is integrated on a chip, the bus itself may also be integrated on the chip. Such an on-chip bus is very fast, typically six to ten times faster than that located on a printed circuit board. 640 to 800M
An on-chip bus operating at a clock rate of 1 Hz can transfer data at a rate of about 4-5 gigabytes / second. At this speed, the bus is so fast that it is virtually transparent. The bus significantly outperforms even the fastest target device mounted on the bus. For example, DRAM has a peak sustainable transmission rate of 0.8 gigabytes / second. Even with two DRAM modules, the combined bandwidth is only 1.6 gigabytes / second, still significantly less than the bus bandwidth. This means that the speed of the system is not limited by the speed of the bus, but by the speed of the target device on the bus.

[0004] A split transaction bus may be used to avoid stalling the bus while one device waits to receive data from another device on the bus. In this way, the bus can have many transactions in progress at the same time. Each of the data read operations occurs in two steps. That is, reading starts,
Next, the reading is completed. There is a delay between the start of reading and the completion of reading. This delay is the time required for the target to decode the request, get the requested data, and send it back to the requesting device (master). During this time, neither the master device nor the target device is on the bus. Instead, the master device releases its bus after sending its data read command in the first bus cycle. Thus, while the master device waits for its read to complete, the bus can support other transactions. On the other hand, the target device processes the received request, and arbitrates the bus and sends the requested data to the master device only when the read data is ready. The transfer cycle ends when the data is transferred to the requesting device.

[0005] One possible problem with the split transaction bus is when the target device is not present. If no device receives the command, no data will be returned. However, no response can occur without being found because the split transaction bus usually has a delay between the read command and the receipt of the resulting data. The requesting device continues to wait indefinitely. What is needed is a handshake method that provides a transaction acknowledgment by the target device. It is desirable to receive an indication within two clock cycles of the master device sending the request that the target device has received the request. This essentially immediate feedback requirement does not cause the bus to stagnate for the time required to return an acknowledgment, or the target arbitrates the bus for an acknowledgment cycle separate from the data transmission cycle. It is difficult to do this on a split transaction bus without requiring it to do so.

US Pat. No. 5,666,559 to Wisor et al. Describes a system in which a peripheral device receiving data provides an acknowledgment signal to a central unit. A timeout counter is provided, and if the timeout period expires before returning an acknowledgment signal, the control unit asserts an error flag and starts an interrupt routine.

It is an object of the present invention to provide a synchronous transaction acknowledgment circuit with no response detection for a high-speed split transaction bus.

An object of Abstract The invention relates to a bus provided separate transaction acknowledgment line, the current state of the opposite state of the transaction acknowledgment line when receiving the command the target device is directed to itself This is achieved by providing a driver circuit in each of the target devices for inverting the transaction acknowledgment, and providing the bus system with an acknowledgment detection circuit that monitors whether the state of the transaction acknowledgment line is inverted. This strategy provides the requesting master device with immediate feedback that the command has been received by the specified target device. If the state of the transaction acknowledge line has not changed, it indicates that the target device is not present.

A bus idle default device (BIDD) may be provided to drive the transaction acknowledge line when no other device is driving the bus. In one embodiment, BIDD may include circuitry to detect a no response from a non-existent target device and then generate a dummy response to the requesting master device. The dummy data is flagged to indicate that it is not the requested data. Alternatively, the detection of the absence of a transaction acknowledgment may be performed by a detector at the bus interface for each master device.

[0010] With reference to best modes Figure 1 for carrying out the invention, the integrated circuit 11 to form a multiprocessor system, an input / output (I / O) a plurality of processing clusters 13 ₀ -13 ₃ as a cluster 14 (here And four SDRAM memory controllers 15, all of which are controlled by the bus interface unit 17.
6 is attached. A typical system may have a global bus 16 operating at a 640 MHz clock rate, while clusters 13-15 operate at half that clock rate, ie, 320 MHz. Global bus control unit 18 also includes a bus arbiter that regulates access to bus 16 by various clusters 13-15, and a bus idle default device (BIDD) that is used when no cluster element is driving the bus. I / O cluster 14 and SD
The RAM controller 15 communicates with off-chip devices via an I / O bus 19 and a programmable I / O subsystem 20, which has one I / O pad 21 and one It is connected to the SDRAM memory chip 22 described above. The present invention mainly focuses on the BIDD devices in the global bus 16, bus interface unit 17, and global bus control unit 18.

Referring to FIG. 2, the bus structure of the integrated circuit includes a single global bus 16 and a local bus 29 for each of a plurality of clusters 13-15 mounted on the global bus 16 as shown in FIG. Become. Each of the processing clusters 13 includes a processing element, a digital signal engine, a memory transfer control engine and associated cluster data, and a plurality of processing functions such as instruction memories, caches and registers, all mounted on the local bus 28 of the cluster 13. Is done. The same applies to the I / O cluster (14 in FIG. 1), except that the I / O transfer engine is replaced by a digital signal engine and a memory transfer control engine, and the I / O bus (19 in FIG. 1) is also connected to the local bus 29. The interface is different. Buses 16 and 29 allow various elements on the bus to transfer information (data, instructions, etc.). There are two types of bus elements. That is, they are the master 25 and the target 27. Examples of the bus master device 25 are a processing element, a digital signal engine, a memory transfer control engine, and an I / O transfer engine. Examples of bus target devices 27 are memory and registers, including cluster data and instruction memories and caches, cluster hardware registers for processing element digital signal engines and memory transfer control engines, and DRAM memory and system registers. All information transfer occurs between the master and the target, and the master initiates the transfer between the target. While all transfers within the cluster 13 take place across the local bus 29, information transfers between clusters including the I / O cluster (14 in FIG. 1) and the SDRAM controller (15 in FIG. 1) This is performed across the global bus 16 via the global bus interface 17. The global bus interface 17 comprises a master interface 31B with an associated FIFO register bank 31A and an associated FIFO register bank 31A.
And a target interface 33B having an O register bank 33B.
All write operations are direct transactions from master to target. All read operations are split transactions, where a command write from the master to the target initiates the transaction, followed by another transaction write from the target to the originating master, ending the transaction. Global bus control (
In FIG. 1, 18) arbitrates between master and target interfaces 31B and 33B for access to global bus 16 and provides clocking for data transfer between master and target FIFOs 31A and 33A. I do.

Referring to FIG. 3, the global bus interface 17 includes a master interface 31 and a target interface 33. The master interface 31 starts the transfer, and the target interface 33 responds to the transfer request received from the master interface 31. Most global bus interfaces 17 have both a master interface 31 and a target interface 33, but some devices on the global bus, such as register banks or memories, may have only one target interface 33. The bus system uses uniform addressing of a single 32-bit address for all bus elements. Any bus master element can address any other bus target element using the bus address of the target element. Therefore, each of the global bus master interfaces 31 has a unique hardware-assigned device number called “My Device Number” stored in the register 41. This number indicates a unique interface 31 to receive data in a global bus transfer. This is a hardware port number and is not generated or referenced by the programmer. Each of the target interfaces 33 also has a range of global bus addresses called "My Global Address Range", which identifies the addresses to which the target will respond. This address range is likewise the target interface 33
Is stored in the register 43.

The global bus 16 is a single transaction write, split transaction read bus. This is a 64-bit bus, with a 32-bit address and 6 bits.
4-bit data transfer. Each bus cycle specifies the transaction type (idle, command, data, last data), the bus device receiving the information, and the 64-bit command or data. The command octet includes command information (such as read / write) and a 32-bit transfer address. The destination for receiving data (either a target device for receiving write data in addition to a read or write command, or a master device for receiving data returned by the target device) may be a specific device; It may be a broadcast to all devices ("Device 0
"). The recommended global bus transfer atom is 8 words of 4 bytes each, resulting in 4 bus octets (64 bits) of 8 bytes each, with 1, 2 and 4 octet transfers being a special case. Four octet data transfers have a bus efficiency of 80% (one command octet for every four data octets). All transfers are performed on the global bus interface 17 on the bus 16
(In FIG. 3, 56, 63, 82, 85).
Addresses and data are pipelined. All data transfers on the bus are 64-bit bus octets at naturally aligned addresses. The transfer can start at any address. Data is transferred in synchronization with the bus clock, and the FIFO registers in each bus interface device 17 are mainly connected to the global bus 16 to compensate for clock speed differences and skew between the source and destination. Functions to buffer address and data information. FIFO registers have a maximum of 4 between the source and destination.
A pipeline delay of clock cycles (two clock cycles on each side) can be added.

The global bus 16 has four information transfer types. That is, data writing, data reading, control writing, and control reading. A data write operation by the bus master sends a transfer command in a first bus cycle, and then sends one, two or four data octets in a subsequent cycle. The transfer of the last data octet completes the write cycle. In the data read operation by the bus master, the transfer command
And then release the bus. The targeted device receives the command. When the read data is ready, the target arbitrates for the bus and returns the read data to the bus master indicated in the command octet. The transfer of the last data octet to the requesting master device completes the read cycle. A control write is an address variant of a data write operation and comprises a single data octet. That is, it writes data to another 32-bit control address space. The data / control bits in the command octet indicate a write to the control address space. All targets receive the command and data octets and complete the cycle. Control writes go to another data register in the interface that receives them. This avoids command rejection due to the interface being busy with data operations. The control write is used to send the base address to each of the clusters and to send the base address and configuration data to all other global bus devices, such as global registers. Control writes are also used to send global timing signals and global wake-up interrupts to all clusters. Each of the clusters receives a global bus control write of its cluster base address. Upon receiving the cluster base address, each of the clusters sends its base address to all of its processing elements and the digital signal engine, which stores this address if there is an appropriate global address on the cluster data bus. Can respond to a transfer request to an internal register. Control reading is a pair of control writing.
Control reads allow a host or configuration device to read and write base addresses and configuration registers in the global bus control address space. This is required for PCI configuration registers (eg, those that can be referenced by an external PCI device via a PCI interface).

Each of the global bus masters has only one transaction in progress at any one time. It cannot start another transaction until the current transaction is completed. The bus may have many transactions in progress, even though each of the masters can only support one transaction at a time. Each of the read operations takes place in two steps. That is, reading is started, and then reading is completed. There is a delay between the start of reading and the completion of reading. This delay is the time required for the target to decode the command, get the read data, and send it back to the master. During this time, neither the master nor the target is on the bus. While the master waits for the read to complete, the bus may support other transactions. For example, another master may perform a write transfer and another read transfer.

Each of the global bus transactions starts with a command octet written to the target device. Command octets may include the following fields: That is, a read / write transfer bit, a data / control type bit, a 2-bit transfer length field for indicating the expected transfer length in octets (1, 2, 4, or 4 or more) to the DRAM memory; A priority field and two multi-bit fields (e.g., 6 bits each), each of the two multi-bit fields being a device number of an originating master interface device for use by the target device as a destination in response to a read command. And a sub-device number specifying a particular device in the cluster, and the fields further include a 32-bit address field specifying the address of the data in the target and the target device address. Other fields may be defined if desired, or the field size may be extended if the combined command size does not exceed the one octet size established by the global bus.

Referring again to the interface structure of FIG. 3 with the timing diagram of FIG.
The data write operation in which the master device writes 1 to 4 data octets to the specified target device is started by the master device transferring a command to the master interface 31, which is performed via the local bus 29. A command buffer 53 via bus 47 and then via line 51
Transferred to The master interface device number received by the command buffer 53 from the "my device number" storage register 41 via line 52 is appended to the command in the appropriate field. The master interface 31 then requests access to the global bus, which is indicated by the global bus request line (GBR #) going low at 91 in FIG. Requests are made for command octets and also for each write of data octets. In the example shown in FIG. 4, the master request signal stays low for five clock cycles for a five octet transfer. The global bus control arbiter (18 in FIG. 1) grants access to the master interface for the number of cycles requested, which means that at 93 the grant line (GBA $) goes low for five clock cycles. It is indicated by having become. Master interface 31 then sends a write command octet and a data octet over command output line 54 in FIG. 3 and communicates via interface bus 47 and write data line 55 with a write FIFO.
It is sent to the global bus via a write data line 57 from the register bank 56. A transmission in which this write command is followed by the requested number of data octets is shown in FIG.
Octets 95-99.

A write command octet is a broadcast to all global bus target interfaces (including itself), as indicated at 100 in FIG. 4 by target device code (target device) = 0. This is a broadcast because the master does not know which global bus responds to the address contained in the command octet. The command octet includes a 32-bit global address 101 for transfer, a transfer type (write), and a transfer length (1-4 octets). This also includes the master device number, My Device Number, which is not used in write operations. Each of the target devices 33 receives a write command into the command buffer 72 of the target interface via a command input line 71 and write data into a write FIFO register 82 of the target interface via a data line 81, respectively. . This is the 32-bit address in the write command received by the comparator circuit 95 via the target address line 74 and its own global address which is the my global address received by the comparator circuit 75 via the line 76 from the storage register 43. Compare with address. If so, it receives the write data 102-105 and clocks out its write FIFO 82 across line 83. Thus, the writing operation ends. If a match is found, but the device is busy with the previous command, this sends a command reject to the bus.
If not, the target ignores the command and flushes write FIFO 82 to prepare for the next write command. Note that all writes are broadcast. Usually, only the intended target receives the broadcast write data, and other devices discard it. However,
It is possible to broadcast the write data to one or more targets if the targets are designed to decode a series of broadcast addresses.

Next, referring to FIG. 3 and FIG. 5, consider reading master data from the target. The master interface 31 includes 121, 123 and 125 in FIG.
After requesting and receiving access to the bus, transfer is initiated by sending a read command octet to the global bus, as shown in FIG. The read command octet is a broadcast to all global bus target interfaces (including itself) (as indicated by device 0 at 126 in FIG. 5). This is broadcast because the master specifies which global bus device contains the address contained in the command octet (12 in FIG. 5).
This is because it is not known whether to respond to 7). The command octet includes a 32-bit global address for transfer, a transfer type (write), and a transfer length (1-4 octets). This is also the target device uses for its response,
It also includes the my device number, which is the device number of the master. When the master has transmitted the read command octet, it activates its read FIFO 63 to receive the read data across read line 62 later. Normally at this point, the master stalls and waits for the target to send the read data to complete the read command. Each of the target interfaces 33 receives a read command octet in a buffer 72 across a command input line 71. By using the comparison circuit 75, it compares the 32-bit address in the read command with my global address, which is its own global address stored in the register 43. If there is a match, the command is transferred over lines 73 and 77 to interface bus 67 and then sent to local bus 29 to receive the requested data and to read the local bus 29, interface bus 67, read line 84 and This is transferred to the global bus 16 via the read FIFO register bank 85 and the read bus 86. After requesting and obtaining access to global bus 16 as shown at 131 and 133 in FIG. 5, it is included in the command octet as a response address, as indicated by the use of master device code 139 in FIG. The requested read data is sent to the master by using the device number of the master to be read. Thus, the read operation ends. If there is a match, but the device is busy with the previous command, this will result in a command rejection 14
Send 5 to bus 16. If they do not match, the target ignores the command.
Note that the only valid way that data 140-143 can be sent to the waiting read FIFO 63 in the master is in response to a previous read command. Only the command octet contains the device number of the master that sent the command, and this device number is embedded as hardware in the master device that sends the command (41). The device number is determined by line
8 and is checked against the stored device number (41) received over line 59 by the comparison circuit 60. Matching enables FIFO 63 via control line 61. There is no other valid way that some other device may send data to the open master read FIFO, resulting in improper completion of the open read command.

The target device receives the broadcast write and responds to the read. Alternatively, if the master device knows which device should receive the command, the master device may send its write command and data to a particular target device instead of broadcasting. By doing so, power can be saved because no other device receives the command and consequently dissipates power.

In summary, the basic write transfer sequence using a 4-octet data transfer as an example is as follows:

1. The master device requests a five octet transfer on the bus. 2. The master issues a target bus device number and a write command. If the target bus device number for writing is unknown, the target device number may be 0 (broadcast). The write command includes a write address, a write command, a command priority, a chain bit, and a master device code.

[0023] 3. It issues data octets 0-2 (transfers may take 1-4 depending on the transfer length code).
Octets).

[0024] 4. Emit data octet 3 and the last transfer type and release the bus. Bus arbitration starts again in this cycle.

A basic read transfer sequence using a 4-octet data transfer as an example is as follows:

1. The master device requests a one-octet transfer for a read command. 2. The master issues a target bus device number and a read command. If the target bus device number for reading is unknown, the target device number may be 0 (broadcast). The read command includes a read address, a read command, a command priority, a chain bit, and a master device code. The master device code is a DRAM response address.

[0027] 3. Release the bus. 4. The target device requests a 4-octet transfer for a read data response.

[0028] 5. The target issues a first octet of the target device address and read data. The master device code is a target for the read data.
The transfer can be 1-4 octets depending on the transfer length code.

[0029] 6. Emit data octets 1-2. 7. Data octet 3, issues last transfer type, releases bus. Bus arbitration starts again in this cycle.

In a system similar to the one described above that uses a split transaction bus, the present invention provides a transaction acknowledgment (TACK) signal to the bus system to indicate receipt of a command or data by at least one target device. In particular, a target device that receives each of the octets transferred on the global bus 16 will receive a transfer acknowledge (TACK) on the global bus 16.
Acknowledge the octet by activating the line. This is true for each octet, command or data transferred. TACK indicates that the target has received the command or data octet intended for it. As shown in FIG. 3, when the target device 33 receives a control read or write octet, it decodes it using a comparison circuit 75 to see if it is the intended target. If so, this generates TACK (the TACK generation circuit 7 which provides a TACK signal on line 80).
9) and activates for the TACK signal two clocks after the octet has been transferred, as shown at 106 and 144 in FIGS. The target activates TACK even if it rejects the command (as seen at 111 and 145 in FIGS. 4 and 5). If the command is a write, each of the write data octets is also acknowledged by the target (at 107-110 in FIG. 4). Similarly, the master receiving the read data activates TACK (at 146-148 in FIG. 5) for each octet read. By TACK, a state in which no device responds to the command, that is, a bus error can be detected. TACK detects this immediately without having to wait for a bus timeout. TACK is also useful for debugging. That is, it is possible to find out whether there is a device that responded. One or more devices can respond to the TACK signal without interference.

TACK has its own coding. To activate TACK, its state is changed from the preceding clock. For a continuous TACK signal, T
The ACK line is inverted every clock. Each of the target devices activates TACK every bus clock. Note that one or more devices can respond to the TACK signal. That is, all responding devices drive TACK in the same direction. FIG. 6 and FIG. 7 generate the TACK signal and
It is a block diagram of the logic for detecting a K signal. In the generator logic of FIG. 6, the last TACK flip-flop 151 records the TACK signal value for the previous cycle. The decode flip-flop 153 records a valid address decode in the preceding cycle. If the target address is valid in the previous cycle, this logic responds to the TACK signal by enabling the TACK driver 155. The TACK driver 155 is connected to the flip-flop 15
The inverted output of one is used to generate a current TACK value that is complementary to the previous TACK value. This TACK generation circuit is part of the target bus interface 33 of each of the target devices or of the cluster that includes the target devices on the global bus.

In the detector logic of FIG. 7, the last TACK flip-flop 157 records the TACK signal value for the previous cycle. If the current TACK signal value is complementary to the TACK signal in the previous cycle, the current TACK signal is valid and XOR gate 159 outputs a "true" TACK detected signal value. TA
The CK detector circuit is part of the master bus interface of the master device or of each cluster of master devices on the global bus. Instead,
A single TACK generator may form part of the bus idle default device (BIDD) of the global bus control (18 in FIG. 1). In either case, if the bus is idle, BIDD activates TACK and drives the bus to the default level. If a command is issued and no device responds, the TACK line does not change. This makes it possible to detect whether or not an address has been specified for a non-existent device. If any device is TA
If CK is not being driven, stray capacitance and bus holding logic will hold the TACK line at its previous level.

Each of the master devices on the global bus (GB) may have only one ongoing GB transfer at any one time. For a read transfer, the GB master waits for read data to be returned. For a write transfer, the master waits for the bus to acknowledge the command and for the absence of command rejection from the bus, which indicates that the write command and data have been authenticated. This results in automatic control of the transfer bandwidth between master and target. This is called self-throttling. Each of the masters waits for the target to respond. The target has received many GB transfer commands and may be in the process of processing them. These commands are typically buffered in a command FIFO. A target may have N commands from N masters in its FIFO. Once commands enter the FIFO, all N devices wait until each command is acknowledged. Even though it takes time, each of the masters waits until the transfer is completed, so that the target does not overrun.

Referring to FIGS. 8 and 9, when the global bus is idle, no active device is selected to drive the bus. If no active device is selected, the arbiter selects a default device, the bus idle default device (BIDD), to drive the bus.
Otherwise, device lines can float, causing noise and errors. BIDD drives the bus line to a valid level with the idle bus logic and bus driver 161 in response to an idle acknowledge signal from the arbiter. This sends a 0 for data words, byte enables and device addresses, and also sends a 0 for word types. That is, it is an idle command. Alternatively, the address / data lines may be held at their previous value (because of the low output), ie the byte enable is inactive and the target device number is held at all ones. This activates the TACK signal at output 163 because BIDD is a valid device and drives the bus effectively. The only time the TACK signal is not driven is when a command or data word is sent on the bus and no device responds.

BIDD also receives TACK via TACK detection logic 105 (shown in FIG. 7).
Without a response to the read command, indicating that no device responds to the read. The global bus master device can issue read and write commands to non-existent target addresses (devices 36, 15 and 27 in the example of FIG. 9). In this case, no device decodes the address, responds to the command, and does not emit a TACK signal (indicated by no TACK response in FIG. 9). The GB master that sent the command
Until the absence of ACK is detected and the command is terminated, the read data is awaited. The next question is how to abort the command. The simplest method is to provide alternative data (175-177 in FIG. 9) and set a flag to indicate that the data is not valid and run the command to a normal completion state. This means that there are no special changes to the receiving state machine (and other state machines that depend on them), but it is necessary to insert dummy data. To do this, the global bus master makes a request to the bus (request at 179 and acknowledgment at 171 shown in FIG. 9) and places dummy data on the bus for itself to receive, or 1-4. It is necessary to send a bus idle cycle. This must be done to keep the global bus off while inserting the dummy data. Otherwise, the global bus may attempt to put the data into the FIFO while the global bus master logic is inserting the dummy data.

FIG. 8 shows the microarchitecture for BIDD with TACK-less response logic. BIDD monitors the device 0 broadcast command through buffer register 167 and checks for a read command with a no TACK response. In the case of a no TACK response (183 in FIG. 9), state machine 169 makes a request to the global bus and issues a read response of 1, 2, or 4 octets of 0 data determined by the two length bits in the command. It returns a 0 data value and a 0 byte enable with the appropriate word type code for the read response. 0 byte enable indicates that the data is invalid. (The read data usually returns data in which all byte enables are set to 1.) BIDD
Also responds to the device address from the read command (183 in FIG. 9).
, Whereby the dummy data goes to the originating requesting device. BIDD is FIFO
171, before control of the bus is authenticated for a TACK-less read response,
Hold up to 5 read requests from GB.

FIG. 9 shows a timing diagram of a response without TACK. BIDD has the highest priority when requesting GB to minimize command buffering for read commands with no TACK. Command buffering is necessary because several read commands with no TACK response can occur consecutively. Due to the highest priority, only three commands need to be buffered, which correspond to the number of clocks between the detection of the state and the insertion of the dummy read data into GB. That is, one is for detecting a state, one is for sending a GB request, and one is for receiving a GB approval. The timing diagram of FIG. 9 assumes that BIDD has the highest priority over GB arbiters and that BIDD can present a DC request (179) for pulsed requests. BID
D can hold the GB request for a longer period than necessary,
This is because a response without CK does not occur frequently. Once a BIDD response request is issued, the BIDD can enter an idle cycle if the approval time is longer than required. Any number of read commands can occur consecutively for non-existent addresses, which means that BIDD must buffer these read commands. Commands must be buffered until this can gain access to GB. By making the TACK-less response logic the highest priority GB device, buffering between the time that a TACK is detected and the time that a GB acknowledge is received can be minimized to the number of clocks. This would be three commands. That is, one detects this,
One submits the request and one receives the acknowledgment. Note that only 14 bits need be saved from the command word. These are a 2-bit length code and a device and sub-device address for a 12-bit read response.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of an integrated multiprocessor system with a high-speed split transaction bus in which a synchronous transaction acknowledgment with no-response detection of the present invention is arranged.

FIG. 2 is a schematic block diagram of a processing cluster in the system of FIG. 1 with a global bus interface including a transaction acknowledgment of the present invention.

FIG. 3 is a detailed block diagram of the global bus interface 17 of FIG. 2, showing the transaction acknowledgment generator 79 at the target interface.

FIG. 4 is a timing diagram of a write transfer on the global bus 16 in FIGS. 1-3 with a transaction acknowledgment (signal TACK number) shown as an inversion of the signal state.

FIG. 5 is a timing diagram of a read transfer on the global bus 16 in FIGS. 1-3 with a transaction acknowledgment (signal TACK number) shown as an inversion of the signal state.

FIG. 6 is a block circuit diagram of transaction acknowledgment (TACK) generation logic.

FIG. 7 is a block circuit diagram of the transaction acknowledgment (TACK) detection logic.

FIG. 8 is a detailed block diagram of a bus idle default device (BIDD) that is part of the global bus control unit 18 of FIG. 1, including the TACK-less detector of FIG.

FIG. 9 is a timing chart showing a response of the BIDD of FIG. 8 to detection of no TACK.

[Procedural Amendment] Submission of translation of Article 34 Amendment

[Submission date] May 29, 2001 (2001.5.29)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Contents of correction]

[Claims]

────────────────────────────────────────────────── ─── [Continuation of summary] Then, a dummy response with the flag set to invalid data is generated for the requesting master device.

Claims (11)

[Claims] Claims: 1. An integrated circuit having a number of circuit devices mounted on an on-chip bus, a transaction comprising a no response detection indicating that a command placed on the bus has not been received by a specified target circuit device. An acknowledgment circuit, comprising: a separate transaction acknowledgment line provided on the bus; and drive circuit means associated with each of the target circuit devices, wherein the drive circuit means is designated for a particular target circuit device. Whenever a command is received by the device, the transaction acknowledgment line is inverted to the opposite state, and the absence of the command by the designated target circuit is indicated by the transaction acknowledgment line not changing. ,
Transaction acknowledgment circuit. 2. The system of claim 1 further comprising a bus idle default device mounted on said bus and connected to drive said transaction acknowledge line to its opposite state whenever said bus is idle. A transaction acknowledgment circuit according to claim 1. 3. The bus idle default device of claim 2, wherein the bus idle default device includes means for monitoring the transaction acknowledgment line and generating a dummy response whenever indicated that no command has been received. Transaction acknowledgment circuit. 4. In an integrated circuit architecture having an on-chip bus with a large number of mounted circuit devices, commands and data are transferred between said circuit devices across said bus, said bus being used for data read operations. A synchronous transaction acknowledgment (TACK) system comprising a no-response detection circuit for determining whether a designated device has received a command or data placed on said bus. Includes a TACK line associated with the on-chip bus, wherein the TACK line is
Each of the circuit devices for inverting the current state of the TACK line to the opposite state whenever the circuit device receives a command or data intended for that circuit device. Associated bus interface means; a bus idle default device (BIDD) attached to the bus to reverse the current state of the TACK line to the opposite state whenever the bus is idle; and the TACK line. No response detection means for monitoring the status of the TACK line, wherein the absence of a command or data by the designated circuit device is indicated when the TACK line remains unchanged. 5. The non-response detecting means includes means for generating dummy data in response to a non-reception of a command, and transmitting the dummy data to the circuit device which has transmitted the command. The TACK system of claim 4, wherein data indicates the unreceived state of the command. 6. The non-response detecting means is a part of the BIDD.
2. The TACK system according to 1. 7. The TACK system according to claim 4, wherein said non-response detecting means includes a detecting circuit associated with each of said circuit devices mounted on said bus. 8. The bus interface means associated with each of the circuit devices includes means for comparing an address field of any command placed on the bus with an address range to which the circuit device responds. 5. The TACK system of claim 4, wherein, whenever a match occurs, the command is transferred to the circuit device and the state of the TACK line is inverted. 9. The means for inverting the state of the TACK line comprises: a first flip-flop having an input connected to the TACK line and an inverted output; and an input connected to the address comparing means. And a second flip-flop having an output, both flip-flops being clocked by a clock to the bus, and further including a tri-state driver, wherein the tri-state driver is configured to invert the first flip-flop. 9. The TACK system of claim 8, having an input connected to an output, an enable connected to the output of the second flip-flop, and an output connected to the TACK line. 10. The non-response detecting means includes a flip-flop, the flip-flop being clocked by a clock for the bus, having an input connected to the TACK line, and an output; The exclusive-OR gate further includes a first input connected to the T input.
5. The TACK system of claim 4, wherein the TACK system is connected to an ACK line and has a second input connected to an output of the flip-flop, the output providing an indication of a lack of a command or data on the bus. 11. The integrated circuit architecture forms a multiprocessor system, wherein some of the circuit devices mounted on the on-chip bus are processing clusters, wherein the bus operates at a faster clock rate than the cluster. The TACK system according to claim 4.