JP4412852B2 - Global bus synchronous transaction acknowledgment with no response detection - Google Patents

Description

[0001]
Technical field
The present invention relates to an integrated circuit architecture having an on-chip high-speed bus with a number of medium-speed devices mounted on-chip or off-chip, and in particular, command or data transfer between devices across the bus and disposed on the bus. The present invention relates to a handshake method and circuit for receiving an acknowledgment by a target device of a command or data packet.
[0002]
Background art
In a typical bus system, the bus is at the same speed as the attached device or at a slower speed. The system bus is positioned on the printed wiring board, the processor and memory chip module are bonded to the board, and the bus is subjected to capacitance and inductance delays that slow the transfer of information across the bus between the various chips. In such systems, the first bottleneck in information transfer is the bus, not the device, and latency and bandwidth calculations involve arbitration delay to gain access to the bus.
[0003]
If the entire system, or most of it, is integrated on the chip, the bus itself can also be integrated on the chip. Such on-chip buses are very fast, typically 6 to 10 times faster than those placed on a printed circuit board. An on-chip bus operating at a clock rate of 640 to 800 MHz can transfer data at a rate of about 4 to 5 gigabytes / second. At this speed, the bus is so fast that it is virtually transparent. The bus is significantly faster in speed than even the fastest target device attached to the bus. For example, DRAM has a sustainable transmission rate with a peak of 0.8 gigabytes / second. Even with two DRAM modules, the combined bandwidth is only 1.6 gigabytes / second, still significantly less than the bus bandwidth. This means that the speed of the system is not limited by the speed of the bus, but by the speed of the target device on the bus.
[0004]
A split transaction bus may be used to avoid stagnation of the bus while one device waits to receive data from another device on the bus. In this way, the bus can proceed with many transactions simultaneously. Each data read operation occurs in two steps. That is, reading is started and then reading is completed. There is a delay between the start of reading and the completion of reading. This delay is the time required for the target to decode the request, obtain the requested data, and send it back to the requesting device (master). During this time, neither the master device nor the target device is on the bus. Rather, the master device releases the bus after sending its data read command in the first bus cycle. Thus, the bus can support other transactions while the master device waits for its read to complete. On the other hand, the target device processes the received request and only arbitrates the bus and sends the requested data to the master device when read data is ready. By transferring data to the requesting device, the read cycle ends.
[0005]
One problem that can occur with split transaction buses is when there is no target device. If no device receives the command, no data is returned. However, because the split transaction bus usually has a delay between the read command and the receipt of the resulting data, no response can occur without being found. The requesting device continues to wait indefinitely. What is needed is a handshake method that provides transaction acknowledgment by the target device. It is desirable to receive an indication that the target device has received the request within two clock cycles after the master device has sent the request. This essentially immediate feedback requirement does not stagnate the bus for the time required to return an acknowledgment or the target arbitrates the bus for an acknowledgment cycle that is separate from the data transmission cycle. It is difficult to do so on a split transaction bus without requiring it.
[0006]
U.S. Pat. No. 5,666,559 to Wisor et al. Describes a system in which a peripheral device receiving data provides an acknowledgment signal to a central unit. A time-out counter is provided, and if the time-out period expires before the acknowledgment signal is returned, the control unit asserts an error flag and starts the interrupt routine.
[0007]
An object of the present invention is to provide a synchronous transaction acknowledgment circuit with no response detection for a high speed split transaction bus.
[0008]
Summary of invention
An object of the present invention is to provide a driver circuit that provides a separate transaction acknowledgment line on the bus and reverses the current state of the transaction acknowledgment line to the opposite state when the target device receives a command directed to itself. This is accomplished by providing an acknowledgment detection circuit on each of the target devices and monitoring the bus system to see if the state of the transaction acknowledgment line has been reversed. This strategy provides immediate feedback that the command was received by the specified target device to the requesting master device. If the state of the transaction acknowledgment line has not changed, it indicates that there is no target device.
[0009]
A bus idle default device (BIDD) may be provided to drive the transaction acknowledgment line when no other device is driving the bus. In one embodiment, the BIDD may include circuitry that detects no response from a non-existing target device and then generates a dummy response to the requesting master device. The dummy data is flagged to indicate that it is not requested data. Alternatively, the absence of transaction acknowledgment may be detected by a detector at the bus interface for each master device.
[0010]
Best mode for carrying out the invention
Referring to FIG. 1, an integrated circuit 11 forming a multiprocessor system includes a plurality of processing clusters 13 as input / output (I / O) clusters 14.₀-13_Three(The number here is four) and an SDRAM memory controller 15, all of which are mounted on the on-chip high-speed global bus 16 by the bus interface unit 17. A typical system may have a global bus 16 operating at a 640 MHz clock rate, while cluster 13-15 operates at half that clock rate, ie 320 MHz. The global bus control unit 18 also includes a bus arbiter that regulates access to the bus 16 by the various clusters 13-15 and a bus idle default device (BIDD) that is used when no cluster element is driving the bus. The I / O cluster 14 and the SDRAM controller 15 communicate with off-chip devices via an I / O bus 19 and a programmable I / O subsystem 20, which is connected to the chip I / O subsystem 20. The O pad 21 and one or more SDRAM memory chips 22 are connected. The present invention mainly focuses on the BIDD devices in the global bus 16, the bus interface unit 17, and the global bus control unit 18.
[0011]
Referring to FIG. 2, the integrated circuit bus structure comprises a single global bus 16 and a local bus 29 for each of a plurality of clusters 13-15 mounted on the global bus 16 as shown in FIG. Each processing cluster 13 includes a processing element, a digital signal engine, a memory transfer control engine and associated cluster data, and multiple processing functions such as instruction memory, cache and registers, all mounted on the local bus 28 of the cluster 13. Is done. The I / O cluster (14 in FIG. 1) is similar, but the I / O transfer engine is replaced with a digital signal engine and a memory transfer control engine, and the I / O bus (19 in FIG. The interface is different. Buses 16 and 29 allow various elements on the bus to transfer information (data, instructions, etc.). There are two types of bus elements. That is, the master 25 and the target 27. Examples of the bus master device 25 are a processing element, a digital signal engine, a memory transfer control engine, and an I / O transfer engine. Examples of bus target devices 27 are memory and registers, including cluster data and instruction memory and cache, cluster hardware registers for processing element digital signal engine and memory transfer control engine, and DRAM memory and system registers. All information transfers occur between the master and target, and the master initiates transfer between the target. All transfers within the cluster 13 are performed across the local bus 29, whereas information transfer between clusters including the I / O cluster (14 in FIG. 1) and the SDRAM controller (15 in FIG. 1) is: This is done across the global bus 16 via the global bus interface 17. The global bus interface 17 includes a master interface 31B having an associated FIFO register bank 31A and a target interface 33B also having an associated FIFO register bank 33B. All write operations are direct transactions from the master to the target. All read operations are split transactions, where a command write from the master to the target starts the transaction, and then the transaction ends with another response write from the target to the originating master. Global bus control (18 in FIG. 1) arbitrates between the master and target interfaces 31B and 33B for access to the global bus 16 and transfers data between the master and target FIFOs 31A and 33A. Provide clocking.
[0012]
Referring to FIG. 3, the global bus interface 17 includes a master interface 31 and a target interface 33. The master interface 31 starts the transfer, and the target interface 33 responds to the transfer request received from the master interface 31. Most global bus interfaces 17 have both a master interface 31 and a target interface 33, but some devices on the global bus such as a register bank or memory may have only one target interface 33. The bus system uses uniform addressing of a single 32-bit address for all bus elements. Any bus master element can address any other bus target element using the bus address of the target element. Accordingly, each of the global bus master interfaces 31 has a device number assigned to its own hardware called “My Device Number” stored in the register 41. This number suggests a unique interface 31 that is to receive data in a global bus transfer. This is a hardware port number and cannot be generated or referenced by the programmer. Each of the target interfaces 33 also has a range of global bus addresses called “My Global Address Range”, which identifies the addresses to which the target will respond. This address range is similarly stored in the register 43 in the target interface 33.
[0013]
The global bus 16 is a single transaction write, split transaction read bus. This is a 64-bit bus and comprises a 32-bit address and 64-bit data transfer. Each bus cycle identifies the transaction type (idle, command, data, last data), the bus device receiving the information, and the 64-bit command or data. The command octet includes command information (read / write, etc.) and a 32-bit transfer address. The destination that receives the data (either the target device that receives the write data in addition to the read command or the write command, or the master device that receives the data returned by the target device) may be a specific device, It may be a broadcast to all devices (designated as “device 0”). The recommended global bus transfer atom is 8 words of 4 bytes each, which results in 4 bus octets (64 bits) of 8 bytes each, with 1, 2 and 4 octet transfers being special cases. A 4-octet data transfer has a bus efficiency of 80% (1 command octet for every 4 data octets). All transfers are writes to the FIFO (56, 63, 82, 85 in FIG. 3) at the global bus interface 17 on the bus 16. Addresses and data are pipelined. All data transfers on the bus are 64-bit bus octets with naturally aligned addresses. The transfer can be started at any address. Data is transferred in synchronism with the bus clock, and the FIFO register in each bus interface device 17 is primarily between the global bus 16 to compensate for clock speed differences and skew between the source and destination. Functions to buffer address and data information. The FIFO register can add a pipeline delay of up to 4 clock cycles (2 clock cycles on each side) between the source and destination.
[0014]
The global bus 16 has four information transfer types. That is, data writing, data reading, control writing, and control reading. The data write operation by the bus master sends a transfer command in the first bus cycle and then sends 1, 2 or 4 data octets in the following cycle. The transfer of the last data octet completes the write cycle. A data read operation by the bus master sends a transfer command in the first cycle and then releases the bus. The targeted device receives the command. When the read data is ready, the target arbitrates for the bus and returns the read data to the bus master indicated in the command octet. The transfer of the last data octet to the requesting master device completes the read cycle. Control writing is an address transformation of a data write operation and comprises a single data octet. That is, it writes data to another 32-bit control address space. The data / control bits in the command octet indicate writing to the control address space. All targets receive commands and data octets and complete the cycle. Control writes go to another data register in the interface that receives them. This avoids command rejection due to the interface becoming busy with data operations. Control writing is used to send a base address to each of the clusters and send the base address and configuration data to all other global bus devices such as global registers. Control writes are also used to send global timing signals and global wakeup interrupts to all clusters. Each cluster receives a global bus control write of its cluster base address. When a cluster base address is received, each cluster sends its base address to all its processing elements and the digital signal engine, which stores this address and there is an appropriate global address on the cluster data bus. To respond to the transfer request to the internal register. Control reading is a pair of control writing. Control read allows the host or configuration device to read and write base addresses and configuration registers in the global bus control address space. This is required for PCI configuration registers (eg those that can be referenced by an external PCI device via the PCI interface).
[0015]
Each global bus master has only one transaction in progress at any one time. This cannot start another transaction until the current transaction is complete. Even though each master can only support one transaction at a time, the bus can have many transactions in progress. Each read operation occurs in two steps. That is, reading is started and then reading is completed. There is a delay between the start of reading and the completion of reading. This delay is the time required for the target to decode the command, acquire the read data, and send it back to the master. During this time, neither the master nor the target is on the bus. While the master is waiting for its reading to complete, the bus may support other transactions. For example, other masters can perform write transfers and other read transfers.
[0016]
Each global bus transaction begins with a command octet written to the target device. The command octet may include the following fields: A read / write transfer bit, a data / control type bit, a 2-bit transfer length field for indicating to the DRAM memory the expected transfer length in octets (1, 2, 4 or 4 or more), and 2 bits A priority field and two multi-bit fields (eg, 6 bits each), each of the two multi-bit fields being the device number of the originating master interface device for use by the target device as a destination in response to a read command And a sub-device number that specifies a particular device within the cluster, the field further includes a 32-bit address field that specifies the address of the data in the target and the target device address. Other fields may be defined if desired, or the field size may be expanded if the total command size does not exceed the one octet size established by the global bus.
[0017]
Referring again to the interface structure of FIG. 3 together with the timing diagram of FIG. 4, a data write operation in which the master device writes 1 to 4 data octets to the designated target device causes the master device to transfer a command to the master interface 31. This is transferred to the master interface bus 47 via the local bus 29 and then to the command buffer 53 via the line 51. The device number of the master interface received by the command buffer 53 via the line 52 from the “My Device Number” storage register 41 is given to the command in the appropriate field. Next, the master interface 31 requests access to the global bus, which is indicated in FIG. 4 by reference numeral 91, where the global bus request line (GBR #) goes low. Requests are made for command octets and for each write of a data octet. In the example shown in FIG. 4, the master request signal remains low for 5 clock cycles for a 5 octet transfer. The global bus control arbiter (18 in FIG. 1) acknowledges the number of cycles requested to access the master interface, which is indicated by the reference line 93 where the acknowledge line (GBA #) goes low for 5 clock cycles. It is indicated by becoming. Master interface 31 then sends write command octets and data octets via command output line 54 in FIG. 3 from write FIFO register bank 56 which communicates via interface bus 47 and write data line 55. The data is sent to the global bus via the write data line 57. The transmission followed by the requested number of data octets after this write command is indicated by octets 95-99 in FIG.
[0018]
The write command octet is a broadcast to all global bus target interfaces (including itself) as indicated at 100 in FIG. 4 by target device code (target device) = 0. This is a broadcast because the master does not know which global bus responds to the address contained in the command octet. The command octet includes a 32-bit global address 101 for transfer, a transfer type (write), and a transfer length (1-4 octets). This also includes my device number, which is the master device number, which is not used in the write operation. Each of the target devices 33 receives a write command in the command buffer 72 of the target interface via the command input line 71 and a write data in the write FIFO register 82 of the target interface via the data line 81, respectively. . This is the 32-bit address in the write command received by the comparison circuit 95 via the target address line 74 and its own global address which is the my global address received by the comparison circuit 75 via the line 76 from the storage register 43. Compare with address. If it matches, it receives the write data 102-105 and clocks it out of its write FIFO 82 across line 83. This completes the writing operation. If there is a match but the device is busy with a previous command, this sends a command rejection to the bus. If not, the target ignores the command and flushes the write FIFO 82 to prepare for the next write command. Note that all writes are broadcast. Normally only the intended target receives the broadcast write data, and other devices discard it. However, it is possible to broadcast write data to one or more targets if the target is designed to decode a series of broadcast addresses.
[0019]
Next, with reference to FIG. 3 and FIG. 5, the master data reading from the target will be considered. The master interface 31 initiates the transfer by sending a read command octet to the global bus after requesting and receiving access to the bus, as shown at 121, 123 and 125 in FIG. The read command octet is a broadcast to all global bus target interfaces (including itself) (as indicated by device 0 at 126 in FIG. 5). This is a broadcast because the master does not know which global bus device responds to the address (127 in FIG. 5) contained in the command octet. The command octet includes a 32-bit global address for transfer, a transfer type (write), and a transfer length (1-4 octets). This also includes my device number, which is the master device number that the target device uses for its response. When the master has finished transmitting the read command octet, it activates its read FIFO 63 to receive read data across the read line 62 later. Normally, at this point, the master stalls and waits for the target to send read data and complete the read command. Each of the target interfaces 33 receives a read command octet in the buffer 72 across the command input line 71. By using the compare circuit 75, this compares the 32-bit address in the read command with the my global address, which is its own global address stored in the register 43. If there is a match, the command is transferred across line 73 and 77 to interface bus 67 and then sent to local bus 29 to receive the requested data, local bus 29, interface bus 67, read line 84 and This is transferred to the global bus 16 via 86 and the read FIFO register bank 85. After requesting and gaining access to the global bus 16 as shown at 131 and 133 in FIG. 5, it is included in the command octet as a response address as shown by the use of the master device code 139 in FIG. The requested read data is sent to the master by using the master device number. This completes the read operation. If there is a match but the device is busy with a previous command, this sends a command rejection 145 to the bus 16. If it does not match, the target ignores the command. Note that the only valid way that data 140-143 can be sent to the waiting read FIFO 63 in the master is only in response to a previous read command. Only the command octet contains the device number of the master that sent the command, and this device number is incorporated as hardware in the master device sending the command (41). The device number is read on line 58 by comparison circuit 60 and looked up against the stored device number (41) received by comparison circuit 60 across line 59. Matching enables the FIFO 63 via the control line 61. There is no other effective way that any other device can send data to the open master read FIFO, resulting in improper completion of the open read command.
[0020]
The target device receives the broadcast write and responds to the read. Alternatively, if the master device knows which device should receive the command, the master device may send the write command and data to a specific target device instead of broadcasting it. Doing this saves power because no other device receives the command and consequently dissipates power.
[0021]
In summary, the basic write transfer sequence, using 4 octet data transfer as an example, is as follows:
[0022]
1. The master device requests a 5 octet transfer on the bus.
2. The master issues a target bus device number and a write command. If the target bus device number for writing is unknown, the target device number may be 0 (broadcast). The write command includes a write address, a write command, command priority, a chain bit, and a master device code.
[0023]
3. Issue data octets 0-2 (transfer can be 1 to 4 octets depending on transfer length code).
[0024]
4). Issue data octet 3 and last transfer type to release the bus. Bus arbitration starts again in this cycle.
[0025]
The basic read transfer sequence using 4 octet data transfer as an example is as follows.
[0026]
1. The master device requests a 1 octet transfer for the read command.
2. The master issues a target bus device number and a read command. If the target bus device number for reading is unknown, the target device number may be 0 (broadcast). The read command includes a read address, a read command, command priority, a chain bit, and a master device code. The master device code is a DRAM response address.
[0027]
3. Release the bus.
4). The target device requests a 4 octet transfer for the read data response.
[0028]
5. The target issues a first octet of the target device address and read data. The master device code is a target for read data. The transfer can be 1 to 4 octets depending on the transfer length code.
[0029]
6). Issue data octets 1-2.
7). Issue data octet 3, last transfer type and release the bus. Bus arbitration begins again in this cycle.
[0030]
In a manner similar to that described above using a split transaction bus, the present invention provides a transaction acknowledgment (TACK) signal to the bus system to indicate receipt of a command or data by at least one target device. In particular, the target device receiving each octet transferred on the global bus 16 acknowledges the octet by activating the transfer acknowledge (TACK) line on the global bus 16. This is true for each octet, command or data transferred. A TACK indicates that the target has received a command or data octet intended for it. As shown in FIG. 3, when the target device 33 receives a control read or write octet, it uses a comparison circuit 75 to decode to see if it is the intended target. If so, this is a TACK (by a TACK generator circuit 79 that provides a TACK signal on line 80), and the TACK signal's two clocks after the octet is transferred, as shown at 106 and 144 in FIGS. To activate. The target activates TACK even if it rejects the command (as seen at 111 and 145 in FIGS. 4 and 5). If the command is a write, each of the write data octets is also acknowledged by the target (at 107-110 in FIG. 4). Similarly, the master receiving the read data activates TACK (at 146-148 in FIG. 5) for each octet read. By TACK, it is possible to detect a state in which no device responds to the command, that is, a bus error. TACK detects this immediately without having to wait for a bus timeout. TACK is also useful for debugging. That is, it can be found whether there is a responding device. One or more devices can respond to the TACK signal without interference.
[0031]
TACK has its own coding. In order to activate TACK, its state is changed from the preceding clock. For continuous TACK signals, the TACK line is inverted every clock. Each target device activates TACK for each bus clock. Note that one or more devices can respond to the TACK signal. That is, all responding devices drive TACK in the same direction. 6 and 7 are block diagrams of logic for generating a TACK signal and detecting the TACK signal. In the generator logic of FIG. 6, the last TACK flip-flop 151 records the TACK signal value for the previous cycle. The decode flip-flop 153 records the valid address decode in the previous cycle. If the target address is valid in the previous cycle, this logic responds to the TACK signal by enabling the TACK driver 155. The TACK driver 155 uses the inverted output of the flip-flop 151 to generate a current TACK value that is complementary to the previous TACK value. This TACK generation circuit is part of the target bus interface 33 of each target device or cluster including the target device on the global bus.
[0032]
Within the detector logic of FIG. 7, the last TACK flip-flop 157 records the TACK signal value for the previous cycle. If the current TACK signal value is complementary to the TACK signal in the previous cycle, the current TACK signal is valid and XOR gate 159 outputs a “true” TACK detected signal value. The TACK detector circuit is part of the master bus interface of each of the master devices or clusters of master devices on the global bus. Alternatively, a single TACK generator may form part of the global bus control (18 in FIG. 1) bus idle default device (BIDD). In either case, if the bus is idle, BIDD activates TACK and drives the bus to the default level. If the command is sent and no device responds, the TACK line will not change. This makes it possible to detect whether an address has been specified for a nonexistent device. If no device is driving TACK, stray capacitance and bus holding logic holds the TACK line at its previous level.
[0033]
Each master device on the global bus (GB) can have only one ongoing GB transfer at any one time. For the read transfer, the GB master waits for read data to be returned. For write transfers, the master waits for bus approval for the command and absence of command rejection from the bus, which indicates that the write command and data have been authenticated. This provides automatic control of transfer bandwidth between the master and target. This is called self-throttling. Each of the masters waits for the target to respond. The target has received many GB transfer commands and may be in the process of processing them. These commands are typically buffered in a command FIFO. A target may have N commands from N masters in its FIFO. Once a command enters the FIFO, all N devices wait until each command is acknowledged. Even if it takes time, each of the masters waits until the transfer is completed, so the target does not overrun.
[0034]
Referring to FIGS. 8 and 9, when the global bus is idle, there are no active devices selected to drive the bus. If no active device is selected, the arbiter selects the bus idle default device (BIDD), which is the default device, to drive the bus. Otherwise, the device line can float and cause noise and errors. BIDD drives the bus line to a valid level by idle bus logic and bus driver 161 in response to an idle acknowledge signal from the arbiter. This sends 0 for data words, byte enables and device addresses, and also 0 for word types. That is, it is an idle command. Alternatively, the address / data lines may be held at their previous values (for low power), i.e. the byte enable may be inactive and the target device number may be held at all ones. This activates the TACK signal at the output 163 because it is a BIDD-enabled device and drives the bus effectively. The only time that the TACK signal is not driven is only when a command or data word is sent on the bus and no device responds to it.
[0035]
BIDD also responds to the read command without TACK via TACK detection logic 105 (shown in FIG. 7), thereby indicating that no device responds to the read. The global bus master device can issue read and write commands to target addresses that do not exist (devices 36, 15 and 27 in the example of FIG. 9). In this case, no device decodes the address, responds to the command, and does not issue a TACK signal (indicated by no TACK response in FIG. 9). The GB master that sent the command finds the absence of TACK and waits for read data unless the command is aborted. The next question is how to abort the command. The simplest method is to provide alternative data (175-177 in FIG. 9) and run a command to a normal completion state with a flag indicating that the data is not valid. This means that there are no special changes to the receiving state machines (and other state machines that depend on them), but it is necessary to insert dummy data. To do this, the global bus master makes a request to the bus (request at 179 and approval at 171 shown in FIG. 9) and places dummy data on the bus to receive itself or 1-4 It is necessary to send a bus idle cycle. This is necessary to keep the global bus off while inserting dummy data. Otherwise, the global bus may attempt to put data into the FIFO while the global bus master logic is inserting dummy data.
[0036]
FIG. 8 shows the microarchitecture for BIDD with no TACK response logic. BIDD monitors device 0 broadcast commands through buffer register 167 and looks for read commands with no TACK response. In the case of a no TACK response (183 in FIG. 9), the state machine 169 makes a request to the global bus and issues a read response of 0 data of 1, 2 or 4 octets determined by the 2 length bits in the command. It returns a 0 data value and a 0 byte enable with the appropriate word type code for the read response. Zero byte enable indicates that the data is invalid. (The read data normally returns data in which all byte enables are set to 1). BIDD also responds to the device address from the read command (183 in FIG. 9), which causes the dummy data to go to the originating requesting device. BIDD uses FIFO 171 to hold up to five read requests from GB before the control of the bus is authenticated for a read response without TACK.
[0037]
FIG. 9 shows a timing diagram of a no TACK response. BIDD has the highest priority when it requires the GB to minimize command buffering for read commands with no TACK. Command buffering is necessary because a number of read commands with no TACK response can occur in succession. With superlative priority, only three commands need to be buffered, which corresponds to the number of clocks during the state detection and dummy read data in GB. That is, one is for detecting a state, one is for sending a GB request, and one is for receiving a GB approval. The timing diagram of FIG. 9 assumes that BIDD has the highest priority over the GB arbiter and that BIDD can present a DC request (179) for pulsed requests. The BIDD can hold the GB request for a longer period than necessary because the TACK-less response does not occur frequently. Once a BIDD response request is issued, the BIDD can enter an idle cycle if the approval time is longer than requested. Any number of read commands can occur consecutively for non-existent addresses, which means that the BIDD must buffer these read commands. The command must be buffered until this can gain access to the GB. By making the no-TACK response logic the highest priority GB device, the buffering between the time when the TACK is detected and the time when the GB acknowledgment is received can be minimized to the number of clocks. This would be three commands. That is, one detects this, one originates the request, and one receives the approval. Note that only 14 bits need be saved from the command word. Device and sub-device addresses for a 2-bit length code and a 12-bit read response.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram of an integrated multiprocessor system with a high speed split transaction bus in which a synchronous transaction acknowledgment with no response detection of the present invention is deployed.
FIG. 2 is a schematic block diagram of a processing cluster in the system of FIG. 1 with a global bus interface including transaction acknowledgments of the present invention.
FIG. 3 is a detailed block diagram of the global bus interface 17 of FIG. 2 showing a transaction acknowledgment generator 79 at the target interface.
FIG. 4 is a timing diagram for a write transfer on the global bus 16 in FIGS. 1-3 with a transaction acknowledgment (signal TACK number) shown as an inversion of the signal state.
FIG. 5 is a timing diagram for a read transfer on the global bus 16 in FIGS. 1-3 with a transaction acknowledgment (signal TACK number) shown as an inversion of the signal state.
FIG. 6 is a block circuit diagram of transaction acknowledgment (TACK) generation logic.
FIG. 7 is a block circuit diagram of transaction acknowledgment (TACK) detection logic.
8 is a detailed block diagram of a bus idle default device (BIDD) that is part of the global bus control unit 18 of FIG. 1, including the no TACK detector of FIG.
FIG. 9 is a timing diagram showing a response of the BIDD of FIG. 8 to detection without TACK.

Claims (8)

In an integrated circuit having a number of circuit devices mounted on an on-chip bus, a transaction acknowledgment circuit with no response detection indicating that a command placed on the bus has not been received by a specified target circuit device. And
A separate transaction acknowledgment line on the bus;
Drive circuit means associated with each of the target circuit devices, wherein the drive circuit means opposes the transaction acknowledgment line whenever a command specified for a particular target circuit device is received by that device. A command not received by the specified target circuit is indicated by the fact that the transaction acknowledge line does not change, and the transaction acknowledge is always attached to the bus and the bus is idle. Including a bus idle default device connected to drive the response line to the opposite state, the bus idle default device monitoring the transaction acknowledgment line and indicating a dummy response whenever a command is not received. Comprising means for generating a transaction acknowledgment circuit. In an integrated circuit architecture having an on-chip bus with a number of mounted circuit devices, commands and data are transferred across the bus between the circuit devices, the bus being a split transaction bus for data read operations. A synchronous transaction acknowledgment (TACK) system comprising a no response detection circuit for determining whether a specified device has received a command or data placed on the bus, comprising:
Including an associated TACK line on the on-chip bus, the TACK line having two opposite states, and whenever the circuit device receives a command or data intended for the circuit device, the current TACK line A bus interface means associated with each of the circuit devices for inverting the state of
A bus idle default device (BIDD) attached to the bus to reverse the current state of the TACK line to the opposite state whenever the bus is idle;
No response detection means for monitoring the state of the TACK line, wherein no reception of a command or data by a designated circuit device is indicated when the TACK line remains unchanged, the no response detection The means includes means for generating dummy data in response to no reception of a command and transmitting the dummy data to the circuit device that has transmitted the command, wherein the dummy data is in the unreceived state of the command A TACK system showing.   The TACK system according to claim 2, wherein the non-response detecting means is a part of the BIDD.   The TACK system according to claim 2, wherein the non-response detection means includes a detection circuit associated with each of the circuit devices mounted on the bus.   The bus interface means associated with each of the circuit devices has means for comparing the address field of any command placed on the bus with the address range to which the circuit device responds and when matching 3. The TACK system of claim 2, wherein at any time the command is transferred to the circuit device and the state of the TACK line is inverted. The means for inverting the state of the TACK line comprises:
A first flip-flop having an input connected to the TACK line and an inverted output;
A second flip-flop having an input connected to the address comparison means and an output, both flip-flops being clocked by a clock to the bus, and further comprising a tri-state driver, the tri-state driver comprising: 6. The input connected to the inverting output of the first flip-flop, an enable connected to the output of the second flip-flop, and an output connected to the TACK line. TACK system. The non-response detecting means includes
A flip-flop, the flip-flop being clocked by a clock to the bus and having an input connected to the TACK line, and an output;
The exclusive OR gate further includes a first input connected to the TACK line, a second input connected to the output of the flip-flop, and an output connected to the command or data on the bus. The TACK system of claim 2, wherein the TACK system provides an unreceived suggestion.   The integrated circuit architecture forms a multiprocessor system, wherein some of the circuit devices mounted on the on-chip bus are processing clusters, and the bus operates at a faster clock rate than the clusters. TACK system.

Images