JP6271768B2 - 共有されるデータチャネルを用いるシェーダパイプライン - Google Patents

共有されるデータチャネルを用いるシェーダパイプライン Download PDF

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Publication number
JP6271768B2
JP6271768B2 JP2016569551A JP2016569551A JP6271768B2 JP 6271768 B2 JP6271768 B2 JP 6271768B2 JP 2016569551 A JP2016569551 A JP 2016569551A JP 2016569551 A JP2016569551 A JP 2016569551A JP 6271768 B2 JP6271768 B2 JP 6271768B2
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Prior art keywords
ring buffer
graphics processing
stages
processing pipeline
data
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JP2016569551A
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Japanese (ja)
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JP2017509092A5 (enExample
JP2017509092A (ja
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メイ、チュンヒ
ゴエル、ビネート
キム、ドンヒュン
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/50—Lighting effects
    • G06T15/80—Shading

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Graphics (AREA)
  • Image Generation (AREA)
  • Image Processing (AREA)
JP2016569551A 2014-02-18 2015-01-26 共有されるデータチャネルを用いるシェーダパイプライン Expired - Fee Related JP6271768B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/182,976 US9679347B2 (en) 2014-02-18 2014-02-18 Shader pipeline with shared data channels
US14/182,976 2014-02-18
PCT/US2015/012917 WO2015126574A1 (en) 2014-02-18 2015-01-26 Shader pipeline with shared data channels

Publications (3)

Publication Number Publication Date
JP2017509092A JP2017509092A (ja) 2017-03-30
JP2017509092A5 JP2017509092A5 (enExample) 2017-08-31
JP6271768B2 true JP6271768B2 (ja) 2018-01-31

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JP2016569551A Expired - Fee Related JP6271768B2 (ja) 2014-02-18 2015-01-26 共有されるデータチャネルを用いるシェーダパイプライン

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Country Link
US (1) US9679347B2 (enExample)
EP (1) EP3108452B1 (enExample)
JP (1) JP6271768B2 (enExample)
KR (1) KR101813429B1 (enExample)
CN (1) CN106030663B (enExample)
ES (1) ES2820716T3 (enExample)
WO (1) WO2015126574A1 (enExample)

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US20180173560A1 (en) * 2016-12-21 2018-06-21 Apple Inc. Processing circuit hardware resource allocation system
GB2560709B (en) * 2017-03-14 2021-02-24 Imagination Tech Ltd Graphics processing method and system for processing sub-primitives
CN107613046B (zh) * 2017-08-22 2020-12-18 创新先进技术有限公司 滤镜管道系统、图像数据处理方法、装置以及电子设备
US11120603B2 (en) 2019-06-18 2021-09-14 Samsung Electronics Co., Ltd. Heavy-weight/light-weight GPU shader core pair architecture
US11263718B2 (en) * 2020-02-03 2022-03-01 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by pretesting against in interleaved screen regions before rendering
US11514549B2 (en) 2020-02-03 2022-11-29 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by generating information in one rendering phase for use in another rendering phase
US12112394B2 (en) 2020-02-03 2024-10-08 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by pretesting against screen regions using configurable shaders
US11508110B2 (en) 2020-02-03 2022-11-22 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by performing geometry analysis before rendering
US11416961B2 (en) 2020-05-29 2022-08-16 Samsung Electronics Co., Ltd. Variable entry transitional ring storage for efficiently accessing graphics states
US12175300B2 (en) 2021-08-11 2024-12-24 Apple Inc. Software control techniques for graphics hardware that supports logical slots and reservation of graphics hardware based on a priority threshold
US12333339B2 (en) * 2021-08-11 2025-06-17 Apple Inc. Affinity-based graphics scheduling
US12190164B2 (en) 2021-08-11 2025-01-07 Apple Inc. Kickslot manager circuitry for graphics processors
US12062126B2 (en) 2021-09-29 2024-08-13 Advanced Micro Devices, Inc. Load multiple primitives per thread in a graphics pipeline
US12169896B2 (en) * 2021-09-29 2024-12-17 Advanced Micro Devices, Inc. Graphics primitives and positions through memory buffers
US11941723B2 (en) 2021-12-29 2024-03-26 Advanced Micro Devices, Inc. Dynamic dispatch for workgroup distribution

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JP5616333B2 (ja) * 2008-05-29 2014-10-29 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ ジオメトリシェーダを用いる平面充填エンジンのためのシステム、方法及びコンピュータプログラム
US20100164954A1 (en) * 2008-12-31 2010-07-01 Sathe Rahul P Tessellator Whose Tessellation Time Grows Linearly with the Amount of Tessellation
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Also Published As

Publication number Publication date
US9679347B2 (en) 2017-06-13
CN106030663A (zh) 2016-10-12
KR101813429B1 (ko) 2017-12-28
WO2015126574A1 (en) 2015-08-27
EP3108452B1 (en) 2020-06-24
CN106030663B (zh) 2018-10-30
ES2820716T3 (es) 2021-04-22
EP3108452A1 (en) 2016-12-28
JP2017509092A (ja) 2017-03-30
KR20160123311A (ko) 2016-10-25
US20150235341A1 (en) 2015-08-20

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