KR101813429B1 - 공유 데이터 채널들을 가지는 셰이더 파이프라인 - Google Patents

공유 데이터 채널들을 가지는 셰이더 파이프라인 Download PDF

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KR101813429B1
KR101813429B1 KR1020167023022A KR20167023022A KR101813429B1 KR 101813429 B1 KR101813429 B1 KR 101813429B1 KR 1020167023022 A KR1020167023022 A KR 1020167023022A KR 20167023022 A KR20167023022 A KR 20167023022A KR 101813429 B1 KR101813429 B1 KR 101813429B1
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South Korea
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ring buffer
stages
graphics processing
processing pipeline
data
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Korean (ko)
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KR20160123311A (ko
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춘휘 메이
비니트 고엘
동현 김
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퀄컴 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/50—Lighting effects
    • G06T15/80—Shading

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Graphics (AREA)
  • Image Generation (AREA)
  • Image Processing (AREA)
KR1020167023022A 2014-02-18 2015-01-26 공유 데이터 채널들을 가지는 셰이더 파이프라인 Expired - Fee Related KR101813429B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/182,976 2014-02-18
US14/182,976 US9679347B2 (en) 2014-02-18 2014-02-18 Shader pipeline with shared data channels
PCT/US2015/012917 WO2015126574A1 (en) 2014-02-18 2015-01-26 Shader pipeline with shared data channels

Publications (2)

Publication Number Publication Date
KR20160123311A KR20160123311A (ko) 2016-10-25
KR101813429B1 true KR101813429B1 (ko) 2017-12-28

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KR1020167023022A Expired - Fee Related KR101813429B1 (ko) 2014-02-18 2015-01-26 공유 데이터 채널들을 가지는 셰이더 파이프라인

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US (1) US9679347B2 (enExample)
EP (1) EP3108452B1 (enExample)
JP (1) JP6271768B2 (enExample)
KR (1) KR101813429B1 (enExample)
CN (1) CN106030663B (enExample)
ES (1) ES2820716T3 (enExample)
WO (1) WO2015126574A1 (enExample)

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US11120603B2 (en) 2019-06-18 2021-09-14 Samsung Electronics Co., Ltd. Heavy-weight/light-weight GPU shader core pair architecture
US12112394B2 (en) 2020-02-03 2024-10-08 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by pretesting against screen regions using configurable shaders
US11514549B2 (en) 2020-02-03 2022-11-29 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by generating information in one rendering phase for use in another rendering phase
US11263718B2 (en) * 2020-02-03 2022-03-01 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by pretesting against in interleaved screen regions before rendering
US11508110B2 (en) 2020-02-03 2022-11-22 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by performing geometry analysis before rendering
US11416961B2 (en) 2020-05-29 2022-08-16 Samsung Electronics Co., Ltd. Variable entry transitional ring storage for efficiently accessing graphics states
US12190164B2 (en) 2021-08-11 2025-01-07 Apple Inc. Kickslot manager circuitry for graphics processors
US12175300B2 (en) 2021-08-11 2024-12-24 Apple Inc. Software control techniques for graphics hardware that supports logical slots and reservation of graphics hardware based on a priority threshold
US12333339B2 (en) * 2021-08-11 2025-06-17 Apple Inc. Affinity-based graphics scheduling
US12169896B2 (en) * 2021-09-29 2024-12-17 Advanced Micro Devices, Inc. Graphics primitives and positions through memory buffers
US12062126B2 (en) 2021-09-29 2024-08-13 Advanced Micro Devices, Inc. Load multiple primitives per thread in a graphics pipeline
US11941723B2 (en) 2021-12-29 2024-03-26 Advanced Micro Devices, Inc. Dynamic dispatch for workgroup distribution

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US20030050725A1 (en) 2001-09-11 2003-03-13 Siemens Aktiengesellschaft Method for reliable high-performance recording of process data with numerically controlled industrial processing machines
US20060070079A1 (en) 2004-09-08 2006-03-30 Franchuk Brian A Discarding a partially received message from a data queue
US20130155080A1 (en) 2011-12-15 2013-06-20 Qualcomm Incorporated Graphics processing unit with command processor
WO2013112692A1 (en) * 2012-01-27 2013-08-01 Qualcomm Incorporated Buffer management for graphics parallel processing unit

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US20060070079A1 (en) 2004-09-08 2006-03-30 Franchuk Brian A Discarding a partially received message from a data queue
US20130155080A1 (en) 2011-12-15 2013-06-20 Qualcomm Incorporated Graphics processing unit with command processor
WO2013112692A1 (en) * 2012-01-27 2013-08-01 Qualcomm Incorporated Buffer management for graphics parallel processing unit

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Publication number Publication date
KR20160123311A (ko) 2016-10-25
EP3108452B1 (en) 2020-06-24
JP6271768B2 (ja) 2018-01-31
EP3108452A1 (en) 2016-12-28
CN106030663A (zh) 2016-10-12
US9679347B2 (en) 2017-06-13
JP2017509092A (ja) 2017-03-30
US20150235341A1 (en) 2015-08-20
CN106030663B (zh) 2018-10-30
ES2820716T3 (es) 2021-04-22
WO2015126574A1 (en) 2015-08-27

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