JP2017509092A5 - - Google Patents

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Publication number
JP2017509092A5
JP2017509092A5 JP2016569551A JP2016569551A JP2017509092A5 JP 2017509092 A5 JP2017509092 A5 JP 2017509092A5 JP 2016569551 A JP2016569551 A JP 2016569551A JP 2016569551 A JP2016569551 A JP 2016569551A JP 2017509092 A5 JP2017509092 A5 JP 2017509092A5
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JP
Japan
Prior art keywords
ring buffer
graphics processing
stages
processing pipeline
data
Prior art date
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Application number
JP2016569551A
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English (en)
Japanese (ja)
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JP6271768B2 (ja
JP2017509092A (ja
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Publication date
Priority claimed from US14/182,976 external-priority patent/US9679347B2/en
Application filed filed Critical
Publication of JP2017509092A publication Critical patent/JP2017509092A/ja
Publication of JP2017509092A5 publication Critical patent/JP2017509092A5/ja
Application granted granted Critical
Publication of JP6271768B2 publication Critical patent/JP6271768B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2016569551A 2014-02-18 2015-01-26 共有されるデータチャネルを用いるシェーダパイプライン Expired - Fee Related JP6271768B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/182,976 US9679347B2 (en) 2014-02-18 2014-02-18 Shader pipeline with shared data channels
US14/182,976 2014-02-18
PCT/US2015/012917 WO2015126574A1 (en) 2014-02-18 2015-01-26 Shader pipeline with shared data channels

Publications (3)

Publication Number Publication Date
JP2017509092A JP2017509092A (ja) 2017-03-30
JP2017509092A5 true JP2017509092A5 (enExample) 2017-08-31
JP6271768B2 JP6271768B2 (ja) 2018-01-31

Family

ID=52469922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016569551A Expired - Fee Related JP6271768B2 (ja) 2014-02-18 2015-01-26 共有されるデータチャネルを用いるシェーダパイプライン

Country Status (7)

Country Link
US (1) US9679347B2 (enExample)
EP (1) EP3108452B1 (enExample)
JP (1) JP6271768B2 (enExample)
KR (1) KR101813429B1 (enExample)
CN (1) CN106030663B (enExample)
ES (1) ES2820716T3 (enExample)
WO (1) WO2015126574A1 (enExample)

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US11514549B2 (en) 2020-02-03 2022-11-29 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by generating information in one rendering phase for use in another rendering phase
US11263718B2 (en) * 2020-02-03 2022-03-01 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by pretesting against in interleaved screen regions before rendering
US11508110B2 (en) 2020-02-03 2022-11-22 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by performing geometry analysis before rendering
US12112394B2 (en) 2020-02-03 2024-10-08 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by pretesting against screen regions using configurable shaders
US11416961B2 (en) 2020-05-29 2022-08-16 Samsung Electronics Co., Ltd. Variable entry transitional ring storage for efficiently accessing graphics states
US12175300B2 (en) 2021-08-11 2024-12-24 Apple Inc. Software control techniques for graphics hardware that supports logical slots and reservation of graphics hardware based on a priority threshold
US12333339B2 (en) * 2021-08-11 2025-06-17 Apple Inc. Affinity-based graphics scheduling
US12190164B2 (en) 2021-08-11 2025-01-07 Apple Inc. Kickslot manager circuitry for graphics processors
US12062126B2 (en) 2021-09-29 2024-08-13 Advanced Micro Devices, Inc. Load multiple primitives per thread in a graphics pipeline
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