JP6268007B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP6268007B2
JP6268007B2 JP2014051812A JP2014051812A JP6268007B2 JP 6268007 B2 JP6268007 B2 JP 6268007B2 JP 2014051812 A JP2014051812 A JP 2014051812A JP 2014051812 A JP2014051812 A JP 2014051812A JP 6268007 B2 JP6268007 B2 JP 6268007B2
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semiconductor layer
electrode
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JP2015176991A (en
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尚史 齋藤
尚史 齋藤
雅彦 蔵口
雅彦 蔵口
四戸　孝
孝 四戸
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Toshiba Corp
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151—Compositional structures
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

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Description

本発明の実施形態は、半導体装置に関する。   Embodiments described herein relate generally to a semiconductor device.

半導体装置の高耐圧、低オン抵抗を実現するには、高い臨界電界を有する材料を用いるのが有効である。窒化物半導体は高い臨界電界強度を有することから、この窒化物半導体を用いることにより、高耐圧、低オン抵抗を実現する半導体装置が得られる。   In order to realize a high breakdown voltage and low on-resistance of a semiconductor device, it is effective to use a material having a high critical electric field. Since a nitride semiconductor has a high critical electric field strength, a semiconductor device that realizes a high breakdown voltage and a low on-resistance can be obtained by using this nitride semiconductor.

窒化物半導体装置では、電界がゲート電極の端部、あるいはフィールドプレート電極の端部に集中する場合があり、窒化物半導体が本来持つ高い耐性が有効に活用されていない場合がある。   In the nitride semiconductor device, the electric field may concentrate on the end of the gate electrode or the end of the field plate electrode, and the high resistance inherent in the nitride semiconductor may not be effectively utilized.

特開２０１３−２０７１６６号公報JP2013-207166A

本発明が解決しようとする課題は、高耐圧の半導体装置を提供することである。   The problem to be solved by the present invention is to provide a high breakdown voltage semiconductor device.

実施形態の半導体装置は、窒化物半導体を有する第１半導体層と、前記第１半導体層上に設けられ、前記第１半導体層よりも禁止帯幅が大きく、窒化物半導体を有する第２半導体層と、前記第２半導体層上に設けられ、前記第２半導体層よりも禁止帯幅が小さく、窒化物半導体を有する第３半導体層と、前記第２半導体層上に設けられ、前記第３半導体層に接する第１電極と、前記第２半導体層上に設けられ、前記第３半導体層に接する第２電極と、前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、の間に設けられ、前記第３半導体層上には設けられていない第３電極と、前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第３電極と、の間の第１部分、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、前記第３電極との間の第２部分、並びに、前記第１半導体層と前記第３電極との間の第３部分と、を含む絶縁膜と、を備える。前記第３電極は、前記第１部分の上には設けられておらず、前記第２部分の上にも設けられておらず、前記第３電極の下端は、前記第１半導体層の上端よりも下である。前記第１半導体層は、ｐ形の第１半導体領域と、前記第１半導体領域と前記第２半導体層との間の第２半導体領域と、を含み、前記第２半導体領域におけるｐ形不純物濃度は、前記第１半導体領域のｐ形不純物濃度よりも低い。前記第１半導体領域は、ｐ形ＧａＮを含み、前記第２半導体領域は、アンドープのＧａＮを含む。
実施形態の半導体装置は、窒化物半導体を有する第１半導体層と、前記第１半導体層上に設けられ、前記第１半導体層よりも禁止帯幅が大きく、窒化物半導体を有する第２半導体層と、前記第２半導体層上に設けられ、前記第２半導体層よりも禁止帯幅が小さく、窒化物半導体を有する第３半導体層と、前記第２半導体層上に設けられ、前記第３半導体層に接する第１電極と、前記第２半導体層上に設けられ、前記第３半導体層に接する第２電極と、前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、の間に設けられ、前記第３半導体層上には設けられていない第３電極と、前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第３電極と、の間の第１部分、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、前記第３電極との間の第２部分、並びに、前記第１半導体層と前記第３電極との間の第３部分と、を含む絶縁膜と、を備える。前記第３電極は、前記第１部分の上には設けられておらず、前記第２部分の上にも設けられておらず、前記第３電極の下端は、前記第１半導体層の上端よりも下である。前記第１半導体層は、ｐ形の第１半導体領域と、前記第１半導体領域と前記第２半導体層との間の第２半導体領域と、を含む。前記第２半導体領域は、超接合構造を有している。
実施形態の半導体装置は、窒化物半導体を有する第１半導体層と、前記第１半導体層上に設けられ、前記第１半導体層よりも禁止帯幅が大きく、窒化物半導体を有する第２半導体層と、前記第２半導体層上に設けられ、前記第２半導体層よりも禁止帯幅が小さく、窒化物半導体を有する第３半導体層と、前記第２半導体層上に設けられ、前記第３半導体層に接する第１電極と、前記第２半導体層上に設けられ、前記第３半導体層に接する第２電極と、前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、の間に設けられ、前記第３半導体層上には設けられていない第３電極と、前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第３電極と、の間の第１部分、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、前記第３電極との間の第２部分、並びに、前記第１半導体層と前記第３電極との間の第３部分と、を含む絶縁膜と、を備える。前記第３電極は、前記第１部分の上には設けられておらず、前記第２部分の上にも設けられておらず、前記第３電極の下端は、前記第１半導体層の上端よりも下である。前記第１半導体層は、ｐ形の第１半導体領域と、前記第１半導体領域と前記第２半導体層との間の第２半導体領域と、を含む。前記第２半導体領域は、前記第１半導体層から前記第３半導体層に向かう方向において、ｎ形ＧａＮ含有層とｐ形ＧａＮ含有層とが交互に配列された構造を有する。
実施形態の半導体装置は、窒化物半導体を有する第１半導体層と、前記第１半導体層上に設けられ、前記第１半導体層よりも禁止帯幅が大きく、窒化物半導体を有する第２半導体層と、前記第２半導体層上に設けられ、前記第２半導体層よりも禁止帯幅が小さく、窒化物半導体を有する第３半導体層と、前記第２半導体層上に設けられ、前記第３半導体層に接する第１電極と、前記第２半導体層上に設けられ、前記第３半導体層に接する第２電極と、前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、の間に設けられ、前記第３半導体層上には設けられていない第３電極と、前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第３電極と、の間の第１部分、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、前記第３電極との間の第２部分、並びに、前記第１半導体層と前記第３電極との間の第３部分と、を含む絶縁膜と、を備える。前記第３電極は、前記第１部分の上には設けられておらず、前記第２部分の上にも設けられておらず、前記第３電極の下端は、前記第１半導体層の上端よりも下である。前記第１半導体層は、ｐ形の第１半導体領域と、前記第１半導体領域と前記第２半導体層との間の第２半導体領域と、を含む。前記第２半導体領域は、前記第１半導体層から前記第３半導体層に向かう方向において、ｎ形ＡｌＧａＮ含有層とｐ形ＡｌＧａＮ含有層とが交互に配列された構造を有する。
実施形態の半導体装置は、窒化物半導体を有する第１半導体層と、前記第１半導体層上に設けられ、前記第１半導体層よりも禁止帯幅が大きく、窒化物半導体を有する第２半導体層と、前記第２半導体層上に設けられ、前記第２半導体層よりも禁止帯幅が小さく、窒化物半導体を有する第３半導体層と、前記第２半導体層上に設けられ、前記第３半導体層に接する第１電極と、前記第２半導体層上に設けられ、前記第３半導体層に接する第２電極と、前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、の間に設けられ、前記第３半導体層上には設けられていない第３電極と、前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第３電極と、の間の第１部分、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、前記第３電極との間の第２部分、並びに、前記第１半導体層と前記第３電極との間の第３部分と、を含む絶縁膜と、を備える。前記第３電極は、前記第１部分の上には設けられておらず、前記第２部分の上にも設けられておらず、前記第３電極の下端は、前記第１半導体層の上端よりも下である。前記第２半導体領域は、前記第１半導体層から前記第３半導体層に向かう方向において、ＡｌＧａＮ含有層とＧａＮ含有層とが交互に配列された構造を有する。
別の実施形態の半導体装置は、窒化物半導体を有する第１半導体層と、前記第１半導体層上に設けられ、前記第１半導体層よりも禁止帯幅が大きく、窒化物半導体を有する第２半導体層と、前記第２半導体層上に設けられ、前記第２半導体層よりも禁止帯幅が小さく、窒化物半導体を有する第３半導体層と、前記第２半導体層上に設けられ、前記第３半導体層に接する第１電極と、前記第２半導体層上に設けられ、前記第３半導体層に接する第２電極と、前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、の間に設けられ、絶縁膜を介して前記第３半導体層、前記第２半導体層、および前記第１半導体層に対向し、前記第１電極から第２電極に向かう方向に対して交差する方向に配列され、前記第３半導体層上には設けられていない複数の第３電極と、隣り合う前記第３電極の間に設けられ、前記第３半導体層、前記第２半導体層、および前記第１半導体層に繋がり、窒化物半導体を有する第５半導体層と、を備える。前記第１半導体層は、ｐ形ＧａＮと、前記ｐ形ＧａＮと前記第２半導体層との間のＧａＮと、を含む。前記第５半導体層は、前記ｐ形ＧａＮよりも高抵抗のＧａＮを含む。
The semiconductor device according to the embodiment includes a first semiconductor layer having a nitride semiconductor, and a second semiconductor layer provided on the first semiconductor layer and having a forbidden bandwidth larger than that of the first semiconductor layer and having a nitride semiconductor. A third semiconductor layer provided on the second semiconductor layer and having a forbidden band width smaller than that of the second semiconductor layer and having a nitride semiconductor; and the third semiconductor layer provided on the second semiconductor layer. A first electrode in contact with a layer; a second electrode provided on the second semiconductor layer and in contact with the third semiconductor layer; the third semiconductor layer in contact with the first electrode; and the first electrode immediately below the first electrode. Two semiconductor layers, the first semiconductor layer immediately below the first electrode, the third semiconductor layer in contact with the second electrode, the second semiconductor layer immediately below the second electrode, and the immediately below the second electrode And a third semiconductor layer provided between the first semiconductor layer and the third semiconductor layer. A third electrode not provided on the body layer; the third semiconductor layer in contact with the first electrode; the second semiconductor layer immediately below the first electrode; and the first semiconductor layer immediately below the first electrode A first portion between the first electrode, the third semiconductor layer in contact with the second electrode, the second semiconductor layer immediately below the second electrode, and the first semiconductor immediately below the second electrode And an insulating film including a second portion between the layer and the third electrode, and a third portion between the first semiconductor layer and the third electrode. The third electrode is not provided on the first portion and is not provided on the second portion, and the lower end of the third electrode is lower than the upper end of the first semiconductor layer. Is also below. The first semiconductor layer includes a p-type first semiconductor region and a second semiconductor region between the first semiconductor region and the second semiconductor layer, and the p-type impurity concentration in the second semiconductor region Is lower than the p-type impurity concentration of the first semiconductor region. The first semiconductor region includes p-type GaN, and the second semiconductor region includes undoped GaN.
The semiconductor device according to the embodiment includes a first semiconductor layer having a nitride semiconductor, and a second semiconductor layer provided on the first semiconductor layer and having a forbidden bandwidth larger than that of the first semiconductor layer and having a nitride semiconductor. A third semiconductor layer provided on the second semiconductor layer and having a forbidden band width smaller than that of the second semiconductor layer and having a nitride semiconductor; and the third semiconductor layer provided on the second semiconductor layer. A first electrode in contact with a layer; a second electrode provided on the second semiconductor layer and in contact with the third semiconductor layer; the third semiconductor layer in contact with the first electrode; and the first electrode immediately below the first electrode. Two semiconductor layers, the first semiconductor layer immediately below the first electrode, the third semiconductor layer in contact with the second electrode, the second semiconductor layer immediately below the second electrode, and the immediately below the second electrode And a third semiconductor layer provided between the first semiconductor layer and the third semiconductor layer. A third electrode not provided on the body layer; the third semiconductor layer in contact with the first electrode; the second semiconductor layer immediately below the first electrode; and the first semiconductor layer immediately below the first electrode A first portion between the first electrode, the third semiconductor layer in contact with the second electrode, the second semiconductor layer immediately below the second electrode, and the first semiconductor immediately below the second electrode And an insulating film including a second portion between the layer and the third electrode, and a third portion between the first semiconductor layer and the third electrode. The third electrode is not provided on the first portion and is not provided on the second portion, and the lower end of the third electrode is lower than the upper end of the first semiconductor layer. Is also below. The first semiconductor layer includes a p-type first semiconductor region and a second semiconductor region between the first semiconductor region and the second semiconductor layer. The second semiconductor region has a superjunction structure.
The semiconductor device according to the embodiment includes a first semiconductor layer having a nitride semiconductor, and a second semiconductor layer provided on the first semiconductor layer and having a forbidden bandwidth larger than that of the first semiconductor layer and having a nitride semiconductor. A third semiconductor layer provided on the second semiconductor layer and having a forbidden band width smaller than that of the second semiconductor layer and having a nitride semiconductor; and the third semiconductor layer provided on the second semiconductor layer. A first electrode in contact with a layer; a second electrode provided on the second semiconductor layer and in contact with the third semiconductor layer; the third semiconductor layer in contact with the first electrode; and the first electrode immediately below the first electrode. Two semiconductor layers, the first semiconductor layer immediately below the first electrode, the third semiconductor layer in contact with the second electrode, the second semiconductor layer immediately below the second electrode, and the immediately below the second electrode And a third semiconductor layer provided between the first semiconductor layer and the third semiconductor layer. A third electrode not provided on the body layer; the third semiconductor layer in contact with the first electrode; the second semiconductor layer immediately below the first electrode; and the first semiconductor layer immediately below the first electrode A first portion between the first electrode, the third semiconductor layer in contact with the second electrode, the second semiconductor layer immediately below the second electrode, and the first semiconductor immediately below the second electrode And an insulating film including a second portion between the layer and the third electrode, and a third portion between the first semiconductor layer and the third electrode. The third electrode is not provided on the first portion and is not provided on the second portion, and the lower end of the third electrode is lower than the upper end of the first semiconductor layer. Is also below. The first semiconductor layer includes a p-type first semiconductor region and a second semiconductor region between the first semiconductor region and the second semiconductor layer. The second semiconductor region has a structure in which n-type GaN-containing layers and p-type GaN-containing layers are alternately arranged in a direction from the first semiconductor layer to the third semiconductor layer.
The semiconductor device according to the embodiment includes a first semiconductor layer having a nitride semiconductor, and a second semiconductor layer provided on the first semiconductor layer and having a forbidden bandwidth larger than that of the first semiconductor layer and having a nitride semiconductor. A third semiconductor layer provided on the second semiconductor layer and having a forbidden band width smaller than that of the second semiconductor layer and having a nitride semiconductor; and the third semiconductor layer provided on the second semiconductor layer. A first electrode in contact with a layer; a second electrode provided on the second semiconductor layer and in contact with the third semiconductor layer; the third semiconductor layer in contact with the first electrode; and the first electrode immediately below the first electrode. Two semiconductor layers, the first semiconductor layer immediately below the first electrode, the third semiconductor layer in contact with the second electrode, the second semiconductor layer immediately below the second electrode, and the immediately below the second electrode And a third semiconductor layer provided between the first semiconductor layer and the third semiconductor layer. A third electrode not provided on the body layer; the third semiconductor layer in contact with the first electrode; the second semiconductor layer immediately below the first electrode; and the first semiconductor layer immediately below the first electrode A first portion between the first electrode, the third semiconductor layer in contact with the second electrode, the second semiconductor layer immediately below the second electrode, and the first semiconductor immediately below the second electrode And an insulating film including a second portion between the layer and the third electrode, and a third portion between the first semiconductor layer and the third electrode. The third electrode is not provided on the first portion and is not provided on the second portion, and the lower end of the third electrode is lower than the upper end of the first semiconductor layer. Is also below. The first semiconductor layer includes a p-type first semiconductor region and a second semiconductor region between the first semiconductor region and the second semiconductor layer. The second semiconductor region has a structure in which n-type AlGaN-containing layers and p-type AlGaN-containing layers are alternately arranged in a direction from the first semiconductor layer to the third semiconductor layer.
The semiconductor device according to the embodiment includes a first semiconductor layer having a nitride semiconductor, and a second semiconductor layer provided on the first semiconductor layer and having a forbidden bandwidth larger than that of the first semiconductor layer and having a nitride semiconductor. A third semiconductor layer provided on the second semiconductor layer and having a forbidden band width smaller than that of the second semiconductor layer and having a nitride semiconductor; and the third semiconductor layer provided on the second semiconductor layer. A first electrode in contact with a layer; a second electrode provided on the second semiconductor layer and in contact with the third semiconductor layer; the third semiconductor layer in contact with the first electrode; and the first electrode immediately below the first electrode. Two semiconductor layers, the first semiconductor layer immediately below the first electrode, the third semiconductor layer in contact with the second electrode, the second semiconductor layer immediately below the second electrode, and the immediately below the second electrode And a third semiconductor layer provided between the first semiconductor layer and the third semiconductor layer. A third electrode not provided on the body layer; the third semiconductor layer in contact with the first electrode; the second semiconductor layer immediately below the first electrode; and the first semiconductor layer immediately below the first electrode A first portion between the first electrode, the third semiconductor layer in contact with the second electrode, the second semiconductor layer immediately below the second electrode, and the first semiconductor immediately below the second electrode And an insulating film including a second portion between the layer and the third electrode, and a third portion between the first semiconductor layer and the third electrode. The third electrode is not provided on the first portion and is not provided on the second portion, and the lower end of the third electrode is lower than the upper end of the first semiconductor layer. Is also below. The second semiconductor region has a structure in which AlGaN-containing layers and GaN-containing layers are alternately arranged in a direction from the first semiconductor layer toward the third semiconductor layer.
A semiconductor device according to another embodiment includes a first semiconductor layer having a nitride semiconductor, a second semiconductor layer provided on the first semiconductor layer, having a forbidden band larger than that of the first semiconductor layer, and having a nitride semiconductor. A semiconductor layer, a third semiconductor layer provided on the second semiconductor layer, having a forbidden band width smaller than that of the second semiconductor layer and having a nitride semiconductor; and provided on the second semiconductor layer; A first electrode in contact with three semiconductor layers; a second electrode provided on the second semiconductor layer and in contact with the third semiconductor layer; the third semiconductor layer in contact with the first electrode; and immediately below the first electrode. The second semiconductor layer, the first semiconductor layer immediately below the first electrode, the third semiconductor layer in contact with the second electrode, the second semiconductor layer immediately below the second electrode, and immediately below the second electrode An insulating film provided between the first semiconductor layer and the first semiconductor layer Via the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer, and arranged in a direction intersecting a direction from the first electrode to the second electrode, A plurality of third electrodes that are not provided above and the adjacent third electrodes are connected to the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer, and are nitride semiconductors And a fifth semiconductor layer. The first semiconductor layer includes p-type GaN and GaN between the p-type GaN and the second semiconductor layer. The fifth semiconductor layer includes GaN having a higher resistance than the p-type GaN .

図１（ａ）は、第１実施形態に係る半導体装置を表す模式的平面図であり、図１（ｂ）は、第１実施形態に係る半導体装置を表す模式的断面図である。FIG. 1A is a schematic plan view illustrating the semiconductor device according to the first embodiment, and FIG. 1B is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. 図２（ａ）は、参考例に係る半導体装置を表す模式的平面図であり、図２（ｂ）は、参考例に係る半導体装置の電界強度を表す図である。FIG. 2A is a schematic plan view illustrating a semiconductor device according to a reference example, and FIG. 2B is a diagram illustrating electric field strength of the semiconductor device according to the reference example. 図３（ａ）、（ｃ）は、第１実施形態に係る半導体装置の動作を表す模式的断面図であり、図３（ｂ）は、第１実施形態に係る半導体装置の電界強度を表す図である。3A and 3C are schematic cross-sectional views illustrating the operation of the semiconductor device according to the first embodiment, and FIG. 3B illustrates the electric field strength of the semiconductor device according to the first embodiment. FIG. 図４（ａ）は、第２実施形態に係る半導体装置を表す模式的断面図であり、図４（ｂ）は、第２実施形態に係る半導体装置の動作を表す図である。FIG. 4A is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment, and FIG. 4B is a diagram illustrating the operation of the semiconductor device according to the second embodiment. 図５（ａ）は、第３実施形態に係る半導体装置を表す模式的断面図であり、図５（ｂ）は、第３実施形態に係る半導体装置のエネルギーバンドを表す図である。FIG. 5A is a schematic cross-sectional view illustrating a semiconductor device according to the third embodiment, and FIG. 5B is a diagram illustrating an energy band of the semiconductor device according to the third embodiment. 図６は、第４実施形態に係る半導体装置を表す模式的断面図である。FIG. 6 is a schematic cross-sectional view showing a semiconductor device according to the fourth embodiment. 図７（ａ）は、第５実施形態に係る半導体装置を表す模式的断面図であり、図７（ｂ）は、ＧａＮ結晶の結晶構造を表す図である。FIG. 7A is a schematic cross-sectional view showing a semiconductor device according to the fifth embodiment, and FIG. 7B is a view showing a crystal structure of a GaN crystal. 図８（ａ）は、第６実施形態に係る半導体装置を表す模式的平面図であり、図８（ｂ）、（ｃ）は、第６実施形態に係る半導体装置を表す模式的平面図である。FIG. 8A is a schematic plan view showing a semiconductor device according to the sixth embodiment, and FIGS. 8B and 8C are schematic plan views showing the semiconductor device according to the sixth embodiment. is there. 図９は、第８実施形態に係る半導体装置を表す模式的断面図である。FIG. 9 is a schematic cross-sectional view showing a semiconductor device according to the eighth embodiment.

以下、図面を参照しつつ、実施形態について説明する。以下の説明では、同一の部材には同一の符号を付し、一度説明した部材については適宜その説明を省略する。   Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same members are denoted by the same reference numerals, and the description of the members once described is omitted as appropriate.

（第１実施形態）
図１（ａ）は、第１実施形態に係る半導体装置を表す模式的平面図であり、図１（ｂ）は、第１実施形態に係る半導体装置を表す模式的断面図である。 (First embodiment)
FIG. 1A is a schematic plan view illustrating the semiconductor device according to the first embodiment, and FIG. 1B is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.

図１（ａ）、（ｂ）では、ソース電極３０からドレイン電極３１に向かう方向を、例えば、Ｙ方向としている。また、半導体基板１０から半導体層２２に向かう方向を、例えば、Ｚ方方向としている。そして、Ｘ方向、Ｙ方向、およびＺ方向のそれぞれは、交差している。   In FIGS. 1A and 1B, the direction from the source electrode 30 to the drain electrode 31 is, for example, the Y direction. The direction from the semiconductor substrate 10 toward the semiconductor layer 22 is, for example, the Z direction. Each of the X direction, the Y direction, and the Z direction intersects.

図１（ｂ）には、図１（ａ）のＡ−Ａ’線における断面が表されている。   FIG. 1B shows a cross section taken along the line A-A ′ of FIG.

第１実施形態に係る半導体装置１は、半導体基板１０と、バッファ層１１と、半導体層２０（第１半導体層）と、半導体層２１（第２半導体層）と、半導体層２２（第３半導体層）と、ソース電極３０（第１電極）と、ドレイン電極３１（第２電極）と、ゲート電極４０（第３電極）と、ゲート絶縁膜４１（絶縁膜）と、を備える。   The semiconductor device 1 according to the first embodiment includes a semiconductor substrate 10, a buffer layer 11, a semiconductor layer 20 (first semiconductor layer), a semiconductor layer 21 (second semiconductor layer), and a semiconductor layer 22 (third semiconductor). Layer), a source electrode 30 (first electrode), a drain electrode 31 (second electrode), a gate electrode 40 (third electrode), and a gate insulating film 41 (insulating film).

半導体基板１０は、例えば、シリコン基板である。半導体層２０は、窒化物半導体（例えば、ＧａＮ）を有する。半導体層２０は、半導体領域２０ｕと、半導体領域２０ｐと、を有する。半導体領域２０ｕは、半導体領域２０ｐの上に設けられている。半導体領域２０ｕは、アンドープ（undoped）の窒化物半導体（例えば、ＧａＮ）を有する。半導体領域２０ｐは、窒化物半導体を有する。一例として、半導体領域２０ｐは、ｐ形ＧａＮであるが、必ずしもｐ形である必要はない。半導体基板１０と半導体層２０との間には、バッファ層１１が設けられている。バッファ層１１は、窒化物半導体（例えば、ＧａＮ）を有する。   The semiconductor substrate 10 is a silicon substrate, for example. The semiconductor layer 20 includes a nitride semiconductor (for example, GaN). The semiconductor layer 20 includes a semiconductor region 20u and a semiconductor region 20p. The semiconductor region 20u is provided on the semiconductor region 20p. The semiconductor region 20u includes an undoped nitride semiconductor (for example, GaN). The semiconductor region 20p includes a nitride semiconductor. As an example, the semiconductor region 20p is p-type GaN, but is not necessarily p-type. A buffer layer 11 is provided between the semiconductor substrate 10 and the semiconductor layer 20. The buffer layer 11 includes a nitride semiconductor (for example, GaN).

半導体層２１は、半導体層２０上に設けられている。半導体層２１の禁止帯幅は、半導体層２０の禁止帯幅よりも大きい。半導体層２１は、アンドープの窒化物半導体（例えば、ＡｌＧａＮ）を有する。   The semiconductor layer 21 is provided on the semiconductor layer 20. The forbidden band width of the semiconductor layer 21 is larger than the forbidden band width of the semiconductor layer 20. The semiconductor layer 21 includes an undoped nitride semiconductor (for example, AlGaN).

半導体層２２は、半導体層２１上に設けられている。半導体層２２の禁止帯幅は、半導体層２１の禁止帯幅よりも小さい。半導体層２２は、窒化物半導体を有する。一例として、半導体層２２は、ｎ形ＧａＮであるが、必ずしもｎ形である必要はない。   The semiconductor layer 22 is provided on the semiconductor layer 21. The forbidden band width of the semiconductor layer 22 is smaller than the forbidden band width of the semiconductor layer 21. The semiconductor layer 22 includes a nitride semiconductor. As an example, the semiconductor layer 22 is n-type GaN, but is not necessarily n-type.

ソース電極３０は、半導体層２１上に設けられている。ソース電極３０は、半導体層２２に接している。ドレイン電極３１は、半導体層２１上に設けられている。ドレイン電極３１は、半導体層２２に接している。ソース電極３０とドレイン電極３１とは互いに離れている。   The source electrode 30 is provided on the semiconductor layer 21. The source electrode 30 is in contact with the semiconductor layer 22. The drain electrode 31 is provided on the semiconductor layer 21. The drain electrode 31 is in contact with the semiconductor layer 22. The source electrode 30 and the drain electrode 31 are separated from each other.

ゲート電極４０は、ソース電極３０が接する半導体層２２、ソース電極３０直下の半導体層２１、およびソース電極３０直下の半導体層２０と、ドレイン電極３１が接する半導体層２２、ドレイン電極３１直下の半導体層２１、およびドレイン電極３１直下の半導体層２０と、の間に設けられている。ゲート電極４０は、ゲート絶縁膜４１を介して半導体層２０、半導体層２１、および半導体層２２に接している。ここで、ゲート電極４０は、半導体層２２上には設けられていない。ソース電極３０、ドレイン電極３１、およびゲート電極４０は、Ｘ方向に延在している。また、ゲート絶縁膜４１は、半導体層２２上にも設けられている。ゲート電極４０の上およびゲート絶縁膜４１の上には、絶縁層５０が設けられている。   The gate electrode 40 includes a semiconductor layer 22 in contact with the source electrode 30, a semiconductor layer 21 immediately below the source electrode 30, a semiconductor layer 20 immediately below the source electrode 30, a semiconductor layer 22 in contact with the drain electrode 31, and a semiconductor layer immediately below the drain electrode 31. 21 and the semiconductor layer 20 immediately below the drain electrode 31. The gate electrode 40 is in contact with the semiconductor layer 20, the semiconductor layer 21, and the semiconductor layer 22 through the gate insulating film 41. Here, the gate electrode 40 is not provided on the semiconductor layer 22. The source electrode 30, the drain electrode 31, and the gate electrode 40 extend in the X direction. The gate insulating film 41 is also provided on the semiconductor layer 22. An insulating layer 50 is provided on the gate electrode 40 and the gate insulating film 41.

窒化物半導体に含まれるｎ形不純物元素は、例えば、Ｓｉ等であり、ｐ形不純物元素は、例えば、Ｍｇ等である。   The n-type impurity element contained in the nitride semiconductor is, for example, Si, and the p-type impurity element is, for example, Mg.

半導体装置１において、半導体層２０と半導体層２１とはヘテロ接合をしており、半導体層２０と半導体層２１との界面付近に２次元電子ガス（２ＤＥＧ）が発生する。ここで、半導体層２１の厚さを５ｎｍ以上とすることにより、半導体層２０と半導体層２１との界面付近で分極が生じ、２次元電子ガスが生成する。また、半導体層２１の膜厚の上限値は、エピタキシャル成長の限界膜厚（例えば、５０ｎｍ）とする。   In the semiconductor device 1, the semiconductor layer 20 and the semiconductor layer 21 are in a heterojunction, and a two-dimensional electron gas (2DEG) is generated near the interface between the semiconductor layer 20 and the semiconductor layer 21. Here, by setting the thickness of the semiconductor layer 21 to 5 nm or more, polarization occurs near the interface between the semiconductor layer 20 and the semiconductor layer 21, and a two-dimensional electron gas is generated. In addition, the upper limit value of the film thickness of the semiconductor layer 21 is set to a limit film thickness (for example, 50 nm) for epitaxial growth.

半導体装置１においては、２次元電子ガスがゲート電極４０とゲート絶縁膜４１とによって構成されるトレンチ構造によって分断されている。このため、半導体装置１はいわゆるノーマリーオフの半導体装置になっている。   In the semiconductor device 1, the two-dimensional electron gas is divided by a trench structure constituted by the gate electrode 40 and the gate insulating film 41. Therefore, the semiconductor device 1 is a so-called normally-off semiconductor device.

半導体装置１の動作を説明する前に参考例に係る半導体装置の動作について説明する。   Before describing the operation of the semiconductor device 1, the operation of the semiconductor device according to the reference example will be described.

図２（ａ）は、参考例に係る半導体装置を表す模式的平面図であり、図２（ｂ）は、参考例に係る半導体装置の電界強度を表す図である。   FIG. 2A is a schematic plan view illustrating a semiconductor device according to a reference example, and FIG. 2B is a diagram illustrating electric field strength of the semiconductor device according to the reference example.

図２（ｂ）の横軸は、長さ（Ｌ）であり、縦軸は、電界強度（Ｉ）である。   The horizontal axis in FIG. 2B is the length (L), and the vertical axis is the electric field strength (I).

参考例に係る半導体装置１００においては、半導体基板１０上にバッファ層２２０を介してＧａＮ層２００が設けられている。また、ＧａＮ層２００の上にＡｌＧａＮ層２１０が設けられている。ＧａＮ層２００とＡｌＧａＮ層２１０とはヘテロ接合をしている。これにより、ＧａＮ層２００とＡｌＧａＮ層２１０との界面付近に２次元電子ガス（２ＤＥＧ）が発生する。   In the semiconductor device 100 according to the reference example, the GaN layer 200 is provided on the semiconductor substrate 10 via the buffer layer 220. An AlGaN layer 210 is provided on the GaN layer 200. The GaN layer 200 and the AlGaN layer 210 are in a heterojunction. As a result, a two-dimensional electron gas (2DEG) is generated near the interface between the GaN layer 200 and the AlGaN layer 210.

また、半導体装置１００においては、ＡｌＧａＮ層２１０上に、ソース電極３００とドレイン電極３１０とが設けられている。また、ゲート電極４００は、ソース電極３００とドレイン電極３１０との間に設けられている。ゲート電極４００は、ゲート絶縁膜４１０を介してＧａＮ層２００とＡｌＧａＮ層２１０とに接している。   In the semiconductor device 100, the source electrode 300 and the drain electrode 310 are provided on the AlGaN layer 210. The gate electrode 400 is provided between the source electrode 300 and the drain electrode 310. The gate electrode 400 is in contact with the GaN layer 200 and the AlGaN layer 210 through the gate insulating film 410.

また、半導体装置１００においては、オフ時における電流コラプス現象を防止する対策として、ゲート電極４００の上方に、フィールドプレート電極４００ＦＰが設けている。フィールドプレート電極４００ＦＰは、ゲート電極４００に電気的に接続されている。さらに、フィールドプレート電極４００ＦＰの上方には、フィールドプレート電極３００ＦＰが設けられている。フィールドプレート電極３００ＦＰは、ソース電極３００に電気的に接続されている。そして、半導体装置１００においては、ゲート電極４００、フィールドプレート電極４００ＦＰ、およびフィールドプレート電極３００ＦＰのそれぞれがドレイン電極３１０側に張り出す張り出し構造を有している（矢印Ａで示す部分）。   Further, in the semiconductor device 100, the field plate electrode 400FP is provided above the gate electrode 400 as a measure for preventing the current collapse phenomenon at the off time. The field plate electrode 400FP is electrically connected to the gate electrode 400. Further, a field plate electrode 300FP is provided above the field plate electrode 400FP. The field plate electrode 300FP is electrically connected to the source electrode 300. In the semiconductor device 100, each of the gate electrode 400, the field plate electrode 400FP, and the field plate electrode 300FP has an overhang structure that projects toward the drain electrode 310 (part indicated by an arrow A).

半導体装置１００においては、ソース・ドレイン間に電圧を印加し、ゲート電極４００に閾値電圧（Ｖｔｈ）以上の電位を印加することにより、ソース電極３００とドレイン電極３１０との間に電流が流れる。   In the semiconductor device 100, a current flows between the source electrode 300 and the drain electrode 310 by applying a voltage between the source and drain and applying a potential equal to or higher than the threshold voltage (Vth) to the gate electrode 400.

但し、半導体装置１００においては、上述した張り出し構造によって、オフ時には、ゲート電極４００の端部４００Ｅ、フィールドプレート電極４００ＦＰの端部４００ＦＰＥ、フィールドプレート電極３００ＦＰの端部３００ＦＰＥで電界が集中してしまう。   However, in the semiconductor device 100, the electric field concentrates at the end portion 400E of the gate electrode 400, the end portion 400FPE of the field plate electrode 400FP, and the end portion 300FPE of the field plate electrode 300FP due to the above-described projecting structure.

従って、図２（ｂ）に示すように、ゲート電極４００の端部４００Ｅ、フィールドプレート電極４００ＦＰの端部４００ＦＰＥ、およびフィールドプレート電極３００ＦＰの端部３００ＦＰＥで、電界強度はピークを持つことになる。   Therefore, as shown in FIG. 2B, the electric field strength has a peak at the end portion 400E of the gate electrode 400, the end portion 400FPE of the field plate electrode 400FP, and the end portion 300FPE of the field plate electrode 300FP.

ここで、ＧａＮ結晶の耐圧限界は、例えば、３ＭＶ（メガボルト）／ｃｍ以上であると言われている。ところが、ゲート・ドレイン間で局所的に電界が強くなると、ゲート・ドレイン間の耐圧が１００Ｖ／μｍ以下にまで下がる場合がある。つまり、参考例のように、張り出し構造を持つ半導体装置では、本来持っているＧａＮ結晶の耐圧特性が十分に生かしきれていない可能性がある。   Here, it is said that the breakdown voltage limit of the GaN crystal is, for example, 3 MV (megavolt) / cm or more. However, when the electric field is locally increased between the gate and the drain, the breakdown voltage between the gate and the drain may be lowered to 100 V / μm or less. That is, as in the reference example, in a semiconductor device having an overhang structure, there is a possibility that the breakdown voltage characteristic of the inherent GaN crystal is not fully utilized.

図３（ａ）、（ｃ）は、第１実施形態に係る半導体装置の動作を表す模式的断面図であり、図３（ｂ）は、第１実施形態に係る半導体装置の電界強度を表す図である。   3A and 3C are schematic cross-sectional views illustrating the operation of the semiconductor device according to the first embodiment, and FIG. 3B illustrates the electric field strength of the semiconductor device according to the first embodiment. FIG.

半導体装置１の動作について説明する。
図３（ａ）には、ドレイン電極３１にソース電極３０よりも高い電位を印加し、ゲート電極４０に閾値電圧（Ｖｔｈ）よりも小さい電位（第１の電位）を印加したときの状態が表されている。この場合、ソース電極３０とドレイン電極３１との間には電流が流れない。つまり、オフ状態では、２次元電子ガス（２ＤＥＧ）はトレンチ構造によって分断されたままである。 The operation of the semiconductor device 1 will be described.
FIG. 3A shows a state when a potential higher than that of the source electrode 30 is applied to the drain electrode 31 and a potential (first potential) smaller than the threshold voltage (Vth) is applied to the gate electrode 40. Has been. In this case, no current flows between the source electrode 30 and the drain electrode 31. That is, in the off state, the two-dimensional electron gas (2DEG) remains separated by the trench structure.

半導体装置１は、上述した張り出し構造を有していない。このため、ドレイン電極３１からゲート電極４０に向かう電界Ｅは、図中の矢印で示すように、Ｚ方向において均一に分散される。   The semiconductor device 1 does not have the above-described overhang structure. For this reason, the electric field E directed from the drain electrode 31 to the gate electrode 40 is uniformly dispersed in the Z direction as indicated by arrows in the drawing.

ここで、オフ状態のときの電界強度を、図３（ｂ）に表す。つまり、半導体装置１では、張り出し構造がないために、電極端部への電界集中が緩和されている。このため、半導体装置１の電界強度は、局所的に強くなるピークを持たず、電界強度分布が参考例に比べてより平坦になる。このように、電界強度分布がより平坦になることから、半導体装置１の耐圧は、ＧａＮ結晶の物性限界で決まるようになる。つまり、参考例に比べて、半導体装置の耐圧は向上する。   Here, the electric field strength in the OFF state is shown in FIG. That is, in the semiconductor device 1, since there is no overhang structure, the electric field concentration at the electrode end is reduced. For this reason, the electric field strength of the semiconductor device 1 does not have a locally strong peak, and the electric field strength distribution becomes flatter than that of the reference example. As described above, since the electric field intensity distribution becomes flatter, the breakdown voltage of the semiconductor device 1 is determined by the physical property limit of the GaN crystal. That is, the breakdown voltage of the semiconductor device is improved as compared with the reference example.

次いで、図３（ｃ）に表すように、ドレイン電極３１にソース電極３０よりも高い電位を印加したまま、ゲート電極４０に閾値電圧（Ｖｔｈ）以上の電位（第２の電位）を印加する。この場合、ゲート絶縁膜４１と半導体層２０との界面に沿って電子が誘起される。つまり、ゲート絶縁膜４１と半導体層２０との界面に沿って、チャネル領域が形成される。   Next, as shown in FIG. 3C, a potential (second potential) equal to or higher than the threshold voltage (Vth) is applied to the gate electrode 40 while a potential higher than that of the source electrode 30 is applied to the drain electrode 31. In this case, electrons are induced along the interface between the gate insulating film 41 and the semiconductor layer 20. That is, a channel region is formed along the interface between the gate insulating film 41 and the semiconductor layer 20.

従って、ゲートによって分断された２次元電子ガスと、誘起された電子と、が繋がって、ソース電極３０とドレイン電極３１との間に電子電流経路ＥＲＴが形成される。これにより、ソース電極３０とドレイン電極３１との間に電流が流れる。   Therefore, the two-dimensional electron gas divided by the gate and the induced electrons are connected to form an electron current path ERT between the source electrode 30 and the drain electrode 31. Thereby, a current flows between the source electrode 30 and the drain electrode 31.

また、半導体装置１では、その耐圧が高くなることに伴い、Ｙ方向におけるソース電極３０、ゲート電極４０、およびドレイン電極３１のそれぞれの間隔を縮めることができる。これにより、半導体装置の小型化を図ることができる。また、ソース・ドレイン間を縮めることにより、半導体装置のオン抵抗が低減する。   Further, in the semiconductor device 1, as the withstand voltage increases, the intervals between the source electrode 30, the gate electrode 40, and the drain electrode 31 in the Y direction can be reduced. As a result, the semiconductor device can be miniaturized. Further, by reducing the distance between the source and the drain, the on-resistance of the semiconductor device is reduced.

また、半導体装置１によれば、ゲート電極４０がゲート絶縁膜４１を介して接する半導体層２０の一部（半導体領域２０ｐ）の導電形がｐ形になっている。従って、半導体装置１では、半導体層２０の全てがノンドープ層である半導体装置に比べて、ゲート電極４０の閾値電圧（Ｖｔｈ）が上昇する。つまり、第１実施形態では、確実にノーマリーオフとなる半導体装置が実現する。   Further, according to the semiconductor device 1, the conductivity type of a part of the semiconductor layer 20 (semiconductor region 20 p) with which the gate electrode 40 is in contact via the gate insulating film 41 is p-type. Therefore, in the semiconductor device 1, the threshold voltage (Vth) of the gate electrode 40 increases as compared with a semiconductor device in which all of the semiconductor layer 20 is a non-doped layer. That is, in the first embodiment, a semiconductor device that is normally normally off is realized.

（第２実施形態）
図４（ａ）は、第２実施形態に係る半導体装置を表す模式的断面図であり、図４（ｂ）は、第２実施形態に係る半導体装置の動作を表す図である。 (Second Embodiment)
FIG. 4A is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment, and FIG. 4B is a diagram illustrating the operation of the semiconductor device according to the second embodiment.

図４（ａ）に表す半導体装置２においては、図中に表す領域２ｎの導電形がｎ＋形になっている。領域２ｎは、ソース電極３０直下の半導体層２１および半導体層２０と、ソース電極３０直下の半導体層２１および半導体層２０とゲート電極４０との間の半導体層２１および半導体層２０と、ゲート電極４０直下の半導体層２０と、を含む。このような領域２ｎは、例えば、ｎ形不純物元素を領域２ｎに局所的に注入することにより形成される。 In the semiconductor device 2 shown in FIG. 4A, the conductivity type of the region 2n shown in the drawing is an n + type . The region 2n includes the semiconductor layer 21 and the semiconductor layer 20 immediately below the source electrode 30, the semiconductor layer 21 and the semiconductor layer 20 between the semiconductor layer 20 and the gate electrode 40 immediately below the source electrode 30, and the gate electrode 40. And a semiconductor layer 20 immediately below. Such a region 2n is formed, for example, by locally injecting an n-type impurity element into the region 2n.

ｎ＋形の領域２ｎは、電子にとって低抵抗な領域となる。また、電子電流経路ＥＲＴの一部は、領域２ｎを通過している。つまり、半導体装置２では、半導体装置１に比べてオン抵抗がさらに低減する。
また、図４（ａ）には、一例として、領域２ｎのみを示したが、ソース電極３０とゲート電極４０との間の半導体層２２がｎ＋形であってもよい。このような領域がｎ＋形になることにより、電子電流経路ＥＲＴの抵抗がさらに低減し、オン抵抗がさらに低くなる。 The n + -type region 2n is a region having low resistance for electrons. A part of the electron current path ERT passes through the region 2n. That is, in the semiconductor device 2, the on-resistance is further reduced as compared with the semiconductor device 1.
FIG. 4A shows only the region 2n as an example, but the semiconductor layer 22 between the source electrode 30 and the gate electrode 40 may be an n + type . When such a region becomes an n + type , the resistance of the electron current path ERT is further reduced, and the on-resistance is further reduced.

なお、半導体装置２では、領域２ｎにおいては反転層が形成されず、領域２ｎ以外のゲート絶縁膜４１と半導体層２０との界面に沿ってチャネル（図中のチャネルＣＨ）が形成される。これにより、チャネル領域ＣＨがドレイン電極３１に向き合う構造となり、ドレイン電極３１からチャネル領域ＣＨに向かう電界がチャネル領域ＣＨで分散される。従って、局所的な電界がチャネル領域ＣＨに印加され難くなり、オフリーク電流が確実に抑えられる。   In the semiconductor device 2, an inversion layer is not formed in the region 2n, and a channel (channel CH in the drawing) is formed along the interface between the gate insulating film 41 and the semiconductor layer 20 other than the region 2n. As a result, the channel region CH faces the drain electrode 31, and the electric field from the drain electrode 31 toward the channel region CH is dispersed in the channel region CH. Therefore, it becomes difficult for a local electric field to be applied to the channel region CH, and the off-leakage current is reliably suppressed.

（第３実施形態）
図５（ａ）は、第３実施形態に係る半導体装置を表す模式的断面図であり、図５（ｂ）は、第３実施形態に係る半導体装置のエネルギーバンドを表す図である。 (Third embodiment)
FIG. 5A is a schematic cross-sectional view illustrating a semiconductor device according to the third embodiment, and FIG. 5B is a diagram illustrating an energy band of the semiconductor device according to the third embodiment.

図５（ａ）には、ゲート電極４０近傍の構造が表されている。図５（ｂ）には、オン時におけるゲート電極４０近傍のエネルギーバンドが表されている。   FIG. 5A shows the structure near the gate electrode 40. FIG. 5B shows an energy band in the vicinity of the gate electrode 40 at the on time.

図５（ａ）に表す半導体装置３においては、ゲート絶縁膜４１と半導体層２０との間に、半導体層２５（第４半導体層）が設けられている。半導体層２５は、窒化物半導体（例えば、ＡｌＧａＮ）を有する。半導体層２５の禁止帯幅は、半導体層２０の禁止帯幅よりも大きい。半導体層２５は、例えば、エピタキシャル成長によって形成される。   In the semiconductor device 3 illustrated in FIG. 5A, a semiconductor layer 25 (fourth semiconductor layer) is provided between the gate insulating film 41 and the semiconductor layer 20. The semiconductor layer 25 includes a nitride semiconductor (for example, AlGaN). The forbidden band width of the semiconductor layer 25 is larger than the forbidden band width of the semiconductor layer 20. The semiconductor layer 25 is formed by, for example, epitaxial growth.

半導体装置３によれば、チャネル領域においてもヘテロ接合が形成され、チャネル領域にも２次元電子ガス（２ＤＥＧ）が発生する。そして、オン時には、ゲート絶縁膜４１と半導体層２５との界面近傍、あるいは半導体層２０と半導体層２５との界面近傍に電子が誘起される。   According to the semiconductor device 3, a heterojunction is formed also in the channel region, and two-dimensional electron gas (2DEG) is generated also in the channel region. When the switch is turned on, electrons are induced near the interface between the gate insulating film 41 and the semiconductor layer 25 or near the interface between the semiconductor layer 20 and the semiconductor layer 25.

半導体装置３によれば、チャネル領域における２次元電子ガス（２ＤＥＧ）が発生により、チャネル領域における電子の閉じ込め効果が半導体装置１、２に比べて増す。これにより、チャネル抵抗がさらに低減し、チャネル領域における電子の移動度がさらに増加する。   According to the semiconductor device 3, the two-dimensional electron gas (2DEG) in the channel region is generated, so that the electron confinement effect in the channel region is increased as compared with the semiconductor devices 1 and 2. Thereby, the channel resistance is further reduced, and the mobility of electrons in the channel region is further increased.

（第４実施形態）
図６は、第４実施形態に係る半導体装置を表す模式的断面図である。 (Fourth embodiment)
FIG. 6 is a schematic cross-sectional view showing a semiconductor device according to the fourth embodiment.

第４実施形態に係る半導体装置４においては、半導体層２０の半導体領域２０ｐ以外の部分が超接合構造（スーパージャンクション構造）を有している。   In the semiconductor device 4 according to the fourth embodiment, a portion other than the semiconductor region 20p of the semiconductor layer 20 has a super junction structure (super junction structure).

例えば、半導体層２０の上側の半導体領域２０ｕは、半導体層２０から半導体層２２に向かう方向（Ｚ方向）において、半導体領域２０ｕｎと半導体領域２０ｕｐとが交互に配列された構造を有する。   For example, the semiconductor region 20u on the upper side of the semiconductor layer 20 has a structure in which the semiconductor regions 20un and the semiconductor regions 20up are alternately arranged in the direction from the semiconductor layer 20 toward the semiconductor layer 22 (Z direction).

ここで、半導体領域２０ｕｎは、ｎ形ＧａＮ含有層であり、半導体領域２０ｕｐは、ｐ形ＧａＮ含有層である。あるいは、半導体領域２０ｕｎは、ｎ形ＡｌＧａＮ含有層であり、半導体領域２０ｕｐは、ｐ形ＡｌＧａＮ含有層でもよい。   Here, the semiconductor region 20un is an n-type GaN-containing layer, and the semiconductor region 20up is a p-type GaN-containing layer. Alternatively, the semiconductor region 20un may be an n-type AlGaN-containing layer, and the semiconductor region 20up may be a p-type AlGaN-containing layer.

また、半導体領域２０ｕｎは、ＧａＮ含有層であり、半導体領域２０ｕｐは、ＡｌＧａＮ含有層であってもよい。この場合、ＧａＮ含有層およびＡｌＧａＮ含有層には、不純物元素が導入されていない。しかし、ＧａＮ含有層とＡｌＧａＮ含有層とのヘテロ接合によって、一方が負に帯電し、他方が正に帯電する。つまり、不純物元素を導入せずとも、擬似的にｎ形領域とｐ形領域とがＺ方向に交互に配列されたことになる。   Further, the semiconductor region 20un may be a GaN-containing layer, and the semiconductor region 20up may be an AlGaN-containing layer. In this case, no impurity element is introduced into the GaN-containing layer and the AlGaN-containing layer. However, due to the heterojunction of the GaN-containing layer and the AlGaN-containing layer, one is negatively charged and the other is positively charged. That is, the n-type region and the p-type region are alternately arranged in the Z direction in a pseudo manner without introducing an impurity element.

このような超接合構造が設けられることにより、オフ時には、半導体領域２０ｕｎと半導体領域２０ｕｐとの接合部から半導体領域２０ｕｎと半導体領域２０ｕｐとの双方に空乏層が延びる。そして、延びた空乏層が半導体領域２０ｕｎ内および半導体領域２０ｕｐ内で繋がって、半導体領域２０ｕ全域が空乏化する。つまり、オフ時には、ゲート・ドレイン間に電気的な中性な半導体領域２０ｕが安定して存在することになり、半導体装置４の耐圧は、半導体装置１〜３の耐圧に比べてさらに増加する。   By providing such a superjunction structure, a depletion layer extends from the junction between the semiconductor region 20un and the semiconductor region 20up to both the semiconductor region 20un and the semiconductor region 20up when off. Then, the extended depletion layer is connected in the semiconductor region 20un and the semiconductor region 20up, and the entire semiconductor region 20u is depleted. That is, at the time of OFF, the electrically neutral semiconductor region 20u exists stably between the gate and the drain, and the breakdown voltage of the semiconductor device 4 further increases as compared with the breakdown voltage of the semiconductor devices 1 to 3.

なお、超接合構造におけるｎ形ＡｌＧａＮ含有層、ｐ形ＡｌＧａＮ含有層、およびＡｌＧａＮ含有層のそれぞれの厚さは、例えば、５ｎｍ以上５０ｎｍ以下とする。また、図６では、４層構造の半導体領域２０ｕが表されているが、この層数に限られるものではない。   Note that the thicknesses of the n-type AlGaN-containing layer, the p-type AlGaN-containing layer, and the AlGaN-containing layer in the superjunction structure are, for example, not less than 5 nm and not more than 50 nm. In FIG. 6, the semiconductor region 20u having a four-layer structure is shown, but the number of layers is not limited thereto.

（第５実施形態）
図７（ａ）は、第５実施形態に係る半導体装置を表す模式的断面図であり、図７（ｂ）は、ＧａＮ結晶の結晶構造を表す図である。 (Fifth embodiment)
FIG. 7A is a schematic cross-sectional view showing a semiconductor device according to the fifth embodiment, and FIG. 7B is a view showing a crystal structure of a GaN crystal.

第５実施形態に係る半導体装置５においては、半導体層２０に含まれるＧａＮ結晶のＣ軸が半導体層２０から半導体層２２に向かう方向（Ｚ方向）に向いている。さらに、ゲート電極４０がゲート絶縁膜４１を介して接するＧａＮ結晶の面がＧａＮ結晶のｍ面になっている。   In the semiconductor device 5 according to the fifth embodiment, the C-axis of the GaN crystal included in the semiconductor layer 20 is oriented in the direction from the semiconductor layer 20 toward the semiconductor layer 22 (Z direction). Furthermore, the surface of the GaN crystal with which the gate electrode 40 is in contact via the gate insulating film 41 is the m-plane of the GaN crystal.

ここで、ＧａＮ結晶のｍ面は、非極性面である。従って、ｍ面とゲート絶縁膜４１との界面近傍には２次元電子ガス（２ＤＥＧ）が発生し難いことから、オフリーク電流を確実に抑制できる。   Here, the m-plane of the GaN crystal is a nonpolar plane. Accordingly, since the two-dimensional electron gas (2DEG) is hardly generated in the vicinity of the interface between the m-plane and the gate insulating film 41, the off-leak current can be reliably suppressed.

（第６実施形態）
図８（ａ）は、第６実施形態に係る半導体装置を表す模式的平面図であり、図８（ｂ）、（ｃ）は、第６実施形態に係る半導体装置を表す模式的平面図である。 (Sixth embodiment)
FIG. 8A is a schematic plan view showing a semiconductor device according to the sixth embodiment, and FIGS. 8B and 8C are schematic plan views showing the semiconductor device according to the sixth embodiment. is there.

図８（ａ）には、図８（ｂ）、（ｃ）のＣ−Ｃ’線における断面が表され、図８（ｂ）には、図８（ａ）のＡ−Ａ’線における断面が表され、図８（ｃ）には、図８（ａ）のＢ−Ｂ’線における断面が表されている。   8A shows a cross section taken along the line CC ′ of FIGS. 8B and 8C, and FIG. 8B shows a cross section taken along the line AA ′ of FIG. 8A. FIG. 8C shows a cross section taken along line BB ′ of FIG.

第６実施形態に係る半導体装置６においては、複数のゲート電極４０がＸ方向に配列されている。隣り合うゲート電極４０の間には、半導体層２７（第５半導体層）が設けられている。半導体層２７は、窒化物半導体（例えば、ＧａＮ）を有する。半導体層２７は、半導体層２２、半導体層２１、および半導体層２０に繋がっている。   In the semiconductor device 6 according to the sixth embodiment, a plurality of gate electrodes 40 are arranged in the X direction. A semiconductor layer 27 (fifth semiconductor layer) is provided between the adjacent gate electrodes 40. The semiconductor layer 27 includes a nitride semiconductor (for example, GaN). The semiconductor layer 27 is connected to the semiconductor layer 22, the semiconductor layer 21, and the semiconductor layer 20.

半導体装置６によれば、ソース・ドレイン間を流れる電子電流が半導体層２７を経由しても流れる。これにより、オン抵抗がさらに低減する。   According to the semiconductor device 6, the electron current flowing between the source and the drain also flows through the semiconductor layer 27. Thereby, the on-resistance is further reduced.

（第７実施形態）
ゲート電極４０の材料は、ポリシリコンのほか、仕事関数がより大きくなる金属材料、仕事関数がより大きくなるダイヤモンド等を選択してもよい。これにより、ゲート電極４０の閾値電圧（Ｖｔｈ）がさらに上昇し、より確実にノーマリーオフとなる半導体装置が実現する。また、半導体層２１は、ＩｎＡｌＧａＮを含んでもよい。ＩｎＡｌＧａＮは、ＡｌＧａＮに比べて分極定数が高い。すなわち、ＩｎＡｌＧａＮを用いれば、半導体層２０と半導体層２１との界面近傍に、より多くの２次元電子ガスが発生する。これにより、オン抵抗がより低減する。 (Seventh embodiment)
As a material of the gate electrode 40, in addition to polysilicon, a metal material having a higher work function, diamond having a higher work function, or the like may be selected. As a result, the threshold voltage (Vth) of the gate electrode 40 is further increased, and a semiconductor device that is normally off more reliably is realized. Further, the semiconductor layer 21 may include InAlGaN. InAlGaN has a higher polarization constant than AlGaN. That is, when InAlGaN is used, more two-dimensional electron gas is generated near the interface between the semiconductor layer 20 and the semiconductor layer 21. Thereby, the on-resistance is further reduced.

（第８実施形態）
図９は、第８実施形態に係る半導体装置の模式的断面図である。 (Eighth embodiment)
FIG. 9 is a schematic cross-sectional view of a semiconductor device according to the eighth embodiment.

図９に示す半導体装置７においては、ソース電極３０とドレイン電極３１とが半導体層２１、２２に接しているが、図９のように、ソース電極３０とドレイン電極３１とは、半導体層２２の上に設けられてもよい。ゲート電極４０は、ソース電極３０直下の半導体層２２、半導体層２１、および半導体層２０と、ドレイン電極３１直下の半導体層２２、半導体層２１、および半導体層２０と、の間に設けられている。ゲート電極４０は、ゲート絶縁膜４１を介して半導体層２０、半導体層２１、および半導体層２２に接している。このような構造は、上述した半導体装置２〜６にも適用される。   In the semiconductor device 7 shown in FIG. 9, the source electrode 30 and the drain electrode 31 are in contact with the semiconductor layers 21 and 22, but the source electrode 30 and the drain electrode 31 are formed on the semiconductor layer 22 as shown in FIG. 9. It may be provided above. The gate electrode 40 is provided between the semiconductor layer 22, the semiconductor layer 21, and the semiconductor layer 20 immediately below the source electrode 30, and the semiconductor layer 22, the semiconductor layer 21, and the semiconductor layer 20 immediately below the drain electrode 31. . The gate electrode 40 is in contact with the semiconductor layer 20, the semiconductor layer 21, and the semiconductor layer 22 through the gate insulating film 41. Such a structure is also applied to the semiconductor devices 2 to 6 described above.

また、半導体装置においては、半導体装置２のような領域２ｎを形成し、ソース電極３０直下の半導体層２２と、ソース電極３０直下の半導体層２２とゲート電極４０との間の半導体層２２と、をさらにｎ＋形にしてもよい。 In the semiconductor device, a region 2n like the semiconductor device 2 is formed, the semiconductor layer 22 immediately below the source electrode 30, and the semiconductor layer 22 between the semiconductor layer 22 and the gate electrode 40 immediately below the source electrode 30; May be further in the n + form.

上記の実施形態では、「部位Ａは部位Ｂの上に設けられている」と表現された場合の「の上に」とは、部位Ａが部位Ｂに接触して、部位Ａが部位Ｂの上に設けられている場合の他に、部位Ａが部位Ｂに接触せず、部位Ａが部位Ｂの上方に設けられている場合との意味で用いられる場合がある。また、「部位Ａは部位Ｂの上に設けられている」は、部位Ａと部位Ｂとを反転させて部位Ａが部位Ｂの下に位置した場合や、部位Ａと部位Ｂとが横に並んだ場合にも適用される場合がある。これは、実施形態に係る半導体装置を回転しても、回転前後において半導体装置の構造は変わらないからである。   In the above embodiment, “above” in the case where “the part A is provided on the part B” means that the part A is in contact with the part B and the part A is the part B. In addition to the case where it is provided above, it may be used to mean that the part A does not contact the part B and the part A is provided above the part B. In addition, “part A is provided on part B” means that part A and part B are reversed and part A is located below part B, or part A and part B are placed sideways. It may also apply when lined up. This is because even if the semiconductor device according to the embodiment is rotated, the structure of the semiconductor device is not changed before and after the rotation.

以上、具体例を参照しつつ実施形態について説明した。しかし、実施形態はこれらの具体例に限定されるものではない。すなわち、これら具体例に、当業者が適宜設計変更を加えたものも、実施形態の特徴を備えている限り、実施形態の範囲に包含される。前述した各具体例が備える各要素およびその配置、材料、条件、形状、サイズなどは、例示したものに限定されるわけではなく適宜変更することができる。   The embodiment has been described above with reference to specific examples. However, the embodiments are not limited to these specific examples. In other words, those specific examples that have been appropriately modified by those skilled in the art are also included in the scope of the embodiments as long as they include the features of the embodiments. Each element included in each of the specific examples described above and their arrangement, material, condition, shape, size, and the like are not limited to those illustrated, and can be appropriately changed.

また、前述した各実施形態が備える各要素は、技術的に可能な限りにおいて複合させることができ、これらを組み合わせたものも実施形態の特徴を含む限り実施形態の範囲に包含される。その他、実施形態の思想の範疇において、当業者であれば、各種の変更例および修正例に想到し得るものであり、それら変更例および修正例についても実施形態の範囲に属するものと了解される。   In addition, each element included in each of the above-described embodiments can be combined as long as technically possible, and combinations thereof are also included in the scope of the embodiment as long as they include the features of the embodiment. In addition, in the category of the idea of the embodiment, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the embodiment. .

本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。   Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

１、２、３、４、５、６、７、１００ 半導体装置、 ２ｎ 領域、 １０ 半導体基板、 １１ バッファ層、 ２０、２１、２２、２５、２７ 半導体層、 ２０ｐ、２０ｕ、２０ｕｎ、２０ｕｐ 半導体領域、 ３０ ソース電極、 ３１ ドレイン電極、 ４０ ゲート電極、 ４１ ゲート絶縁膜、 ５０ 絶縁層、 ２００ ＧａＮ層、 ２１０ ＡｌＧａＮ層、 ３００ ソース電極、 ３００ＦＰ フィールドプレート電極、 ３００ＦＰＥ、４００Ｅ、４００ＦＰＥ 端部、 ３１０ ドレイン電極、 ４００ ゲート電極、 ４００ＦＰ フィールドプレート電極、 ４１０ ゲート絶縁膜、 ＥＲＴ 電子電流経路   1, 2, 3, 4, 5, 6, 7, 100 semiconductor device, 2n region, 10 semiconductor substrate, 11 buffer layer, 20, 21, 22, 25, 27 semiconductor layer, 20p, 20u, 20un, 20up semiconductor region 30 source electrode, 31 drain electrode, 40 gate electrode, 41 gate insulating film, 50 insulating layer, 200 GaN layer, 210 AlGaN layer, 300 source electrode, 300FP field plate electrode, 300 FPE, 400E, 400 FPE end, 310 drain electrode 400 gate electrode, 400FP field plate electrode, 410 gate insulating film, ERT electron current path

Claims (12)

窒化物半導体を有する第１半導体層と、
前記第１半導体層上に設けられ、前記第１半導体層よりも禁止帯幅が大きく、窒化物半導体を有する第２半導体層と、
前記第２半導体層上に設けられ、前記第２半導体層よりも禁止帯幅が小さく、窒化物半導体を有する第３半導体層と、
前記第２半導体層上に設けられ、前記第３半導体層に接する第１電極と、
前記第２半導体層上に設けられ、前記第３半導体層に接する第２電極と、
前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、の間に設けられ、前記第３半導体層上には設けられていない第３電極と、
前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第３電極と、の間の第１部分、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、前記第３電極との間の第２部分、並びに、前記第１半導体層と前記第３電極との間の第３部分と、を含む絶縁膜と、
を備え、
前記第３電極は、前記第１部分の上には設けられておらず、前記第２部分の上にも設けられておらず、
前記第３電極の下端は、前記第１半導体層の上端よりも下であり、
前記第１半導体層は、ｐ形の第１半導体領域と、前記第１半導体領域と前記第２半導体層との間の第２半導体領域と、を含み、前記第２半導体領域におけるｐ形不純物濃度は、前記第１半導体領域のｐ形不純物濃度よりも低く、
前記第１半導体領域は、ｐ形ＧａＮを含み、
前記第２半導体領域は、アンドープのＧａＮを含む、半導体装置。 A first semiconductor layer having a nitride semiconductor;
A second semiconductor layer provided on the first semiconductor layer and having a forbidden band larger than the first semiconductor layer and having a nitride semiconductor;
A third semiconductor layer provided on the second semiconductor layer, having a forbidden bandwidth smaller than that of the second semiconductor layer and having a nitride semiconductor;
A first electrode provided on the second semiconductor layer and in contact with the third semiconductor layer;
A second electrode provided on the second semiconductor layer and in contact with the third semiconductor layer;
The third semiconductor layer in contact with the first electrode, the second semiconductor layer immediately below the first electrode, the first semiconductor layer immediately below the first electrode, and the third semiconductor layer in contact with the second electrode; A third electrode provided between the second semiconductor layer immediately below the second electrode and the first semiconductor layer immediately below the second electrode, and not provided on the third semiconductor layer;
A first portion between the third semiconductor layer, the third semiconductor layer in contact with the first electrode, the second semiconductor layer immediately below the first electrode, the first semiconductor layer immediately below the first electrode, and the third electrode , The third semiconductor layer in contact with the second electrode, the second semiconductor layer immediately below the second electrode, the first semiconductor layer immediately below the second electrode, and a second portion between the third electrode And an insulating film including a third portion between the first semiconductor layer and the third electrode;
With
The third electrode is not provided on the first part and is not provided on the second part,
The lower end of the third electrode, Ri Oh below the upper end of the first semiconductor layer,
The first semiconductor layer includes a p-type first semiconductor region and a second semiconductor region between the first semiconductor region and the second semiconductor layer, and the p-type impurity concentration in the second semiconductor region Is lower than the p-type impurity concentration of the first semiconductor region,
The first semiconductor region includes p-type GaN,
The semiconductor device , wherein the second semiconductor region includes undoped GaN . 前記第２半導体層は、ＡｌＧａＮを含み、
前記第３半導体層は、ＧａＮを含む、請求項１記載の半導体装置。 Before Stories second semiconductor layer comprises AlGaN,
The third semiconductor layer includes GaN, claim 1 Symbol mounting semiconductor device. 前記第２電極直下の前記第１半導体層は、ＧａＮ結晶を含み、
前記ＧａＮ結晶の、前記第３電極と対向する面は、ＧａＮ結晶のｍ面である請求項１記載の半導体装置。 The first semiconductor layer directly under the second electrode includes a GaN crystal,
Wherein the GaN crystal, the third electrode and the opposing surfaces is, claim 1 Symbol mounting a semiconductor device of which an m-plane of the GaN crystal. 窒化物半導体を有する第１半導体層と、
前記第１半導体層上に設けられ、前記第１半導体層よりも禁止帯幅が大きく、窒化物半導体を有する第２半導体層と、
前記第２半導体層上に設けられ、前記第２半導体層よりも禁止帯幅が小さく、窒化物半導体を有する第３半導体層と、
前記第２半導体層上に設けられ、前記第３半導体層に接する第１電極と、
前記第２半導体層上に設けられ、前記第３半導体層に接する第２電極と、
前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、の間に設けられ、前記第３半導体層上には設けられていない第３電極と、
前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第３電極と、の間の第１部分、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、前記第３電極との間の第２部分、並びに、前記第１半導体層と前記第３電極との間の第３部分と、を含む絶縁膜と、
を備え、
前記第３電極は、前記第１部分の上には設けられておらず、前記第２部分の上にも設けられておらず、
前記第３電極の下端は、前記第１半導体層の上端よりも下であり、
前記第１半導体層は、ｐ形の第１半導体領域と、前記第１半導体領域と前記第２半導体層との間の第２半導体領域と、を含み、
前記第２半導体領域は、超接合構造を有している、半導体装置。 A first semiconductor layer having a nitride semiconductor;
A second semiconductor layer provided on the first semiconductor layer and having a forbidden band larger than the first semiconductor layer and having a nitride semiconductor;
A third semiconductor layer provided on the second semiconductor layer, having a forbidden bandwidth smaller than that of the second semiconductor layer and having a nitride semiconductor;
A first electrode provided on the second semiconductor layer and in contact with the third semiconductor layer;
A second electrode provided on the second semiconductor layer and in contact with the third semiconductor layer;
The third semiconductor layer in contact with the first electrode, the second semiconductor layer immediately below the first electrode, the first semiconductor layer immediately below the first electrode, and the third semiconductor layer in contact with the second electrode; A third electrode provided between the second semiconductor layer immediately below the second electrode and the first semiconductor layer immediately below the second electrode, and not provided on the third semiconductor layer;
A first portion between the third semiconductor layer, the third semiconductor layer in contact with the first electrode, the second semiconductor layer immediately below the first electrode, the first semiconductor layer immediately below the first electrode, and the third electrode , The third semiconductor layer in contact with the second electrode, the second semiconductor layer immediately below the second electrode, the first semiconductor layer immediately below the second electrode, and a second portion between the third electrode And an insulating film including a third portion between the first semiconductor layer and the third electrode;
With
The third electrode is not provided on the first part and is not provided on the second part,
The lower end of the third electrode, Ri Oh below the upper end of the first semiconductor layer,
The first semiconductor layer includes a p-type first semiconductor region, and a second semiconductor region between the first semiconductor region and the second semiconductor layer,
The semiconductor device, wherein the second semiconductor region has a superjunction structure . 窒化物半導体を有する第１半導体層と、
前記第１半導体層上に設けられ、前記第１半導体層よりも禁止帯幅が大きく、窒化物半導体を有する第２半導体層と、
前記第２半導体層上に設けられ、前記第２半導体層よりも禁止帯幅が小さく、窒化物半導体を有する第３半導体層と、
前記第２半導体層上に設けられ、前記第３半導体層に接する第１電極と、
前記第２半導体層上に設けられ、前記第３半導体層に接する第２電極と、
前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、の間に設けられ、前記第３半導体層上には設けられていない第３電極と、
前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第３電極と、の間の第１部分、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、前記第３電極との間の第２部分、並びに、前記第１半導体層と前記第３電極との間の第３部分と、を含む絶縁膜と、
を備え、
前記第３電極は、前記第１部分の上には設けられておらず、前記第２部分の上にも設けられておらず、
前記第３電極の下端は、前記第１半導体層の上端よりも下であり、
前記第１半導体層は、ｐ形の第１半導体領域と、前記第１半導体領域と前記第２半導体層との間の第２半導体領域と、を含み、
前記第２半導体領域は、前記第１半導体層から前記第３半導体層に向かう方向において、ｎ形ＧａＮ含有層とｐ形ＧａＮ含有層とが交互に配列された構造を有する、半導体装置。 A first semiconductor layer having a nitride semiconductor;
A second semiconductor layer provided on the first semiconductor layer and having a forbidden band larger than the first semiconductor layer and having a nitride semiconductor;
A third semiconductor layer provided on the second semiconductor layer, having a forbidden bandwidth smaller than that of the second semiconductor layer and having a nitride semiconductor;
A first electrode provided on the second semiconductor layer and in contact with the third semiconductor layer;
A second electrode provided on the second semiconductor layer and in contact with the third semiconductor layer;
The third semiconductor layer in contact with the first electrode, the second semiconductor layer immediately below the first electrode, the first semiconductor layer immediately below the first electrode, and the third semiconductor layer in contact with the second electrode; A third electrode provided between the second semiconductor layer immediately below the second electrode and the first semiconductor layer immediately below the second electrode, and not provided on the third semiconductor layer;
A first portion between the third semiconductor layer, the third semiconductor layer in contact with the first electrode, the second semiconductor layer immediately below the first electrode, the first semiconductor layer immediately below the first electrode, and the third electrode , The third semiconductor layer in contact with the second electrode, the second semiconductor layer immediately below the second electrode, the first semiconductor layer immediately below the second electrode, and a second portion between the third electrode And an insulating film including a third portion between the first semiconductor layer and the third electrode;
With
The third electrode is not provided on the first part and is not provided on the second part,
The lower end of the third electrode, Ri Oh below the upper end of the first semiconductor layer,
The first semiconductor layer includes a p-type first semiconductor region, and a second semiconductor region between the first semiconductor region and the second semiconductor layer,
The second semiconductor region has a structure in which n-type GaN-containing layers and p-type GaN-containing layers are alternately arranged in a direction from the first semiconductor layer to the third semiconductor layer . 窒化物半導体を有する第１半導体層と、
前記第１半導体層上に設けられ、前記第１半導体層よりも禁止帯幅が大きく、窒化物半導体を有する第２半導体層と、
前記第２半導体層上に設けられ、前記第２半導体層よりも禁止帯幅が小さく、窒化物半導体を有する第３半導体層と、
前記第２半導体層上に設けられ、前記第３半導体層に接する第１電極と、
前記第２半導体層上に設けられ、前記第３半導体層に接する第２電極と、
前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、の間に設けられ、前記第３半導体層上には設けられていない第３電極と、
前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第３電極と、の間の第１部分、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、前記第３電極との間の第２部分、並びに、前記第１半導体層と前記第３電極との間の第３部分と、を含む絶縁膜と、
を備え、
前記第３電極は、前記第１部分の上には設けられておらず、前記第２部分の上にも設けられておらず、
前記第３電極の下端は、前記第１半導体層の上端よりも下であり、
前記第１半導体層は、ｐ形の第１半導体領域と、前記第１半導体領域と前記第２半導体層との間の第２半導体領域と、を含み、
前記第２半導体領域は、前記第１半導体層から前記第３半導体層に向かう方向において、ｎ形ＡｌＧａＮ含有層とｐ形ＡｌＧａＮ含有層とが交互に配列された構造を有する、半導体装置。 A first semiconductor layer having a nitride semiconductor;
A second semiconductor layer provided on the first semiconductor layer and having a forbidden band larger than the first semiconductor layer and having a nitride semiconductor;
A third semiconductor layer provided on the second semiconductor layer, having a forbidden bandwidth smaller than that of the second semiconductor layer and having a nitride semiconductor;
A first electrode provided on the second semiconductor layer and in contact with the third semiconductor layer;
A second electrode provided on the second semiconductor layer and in contact with the third semiconductor layer;
The third semiconductor layer in contact with the first electrode, the second semiconductor layer immediately below the first electrode, the first semiconductor layer immediately below the first electrode, and the third semiconductor layer in contact with the second electrode; A third electrode provided between the second semiconductor layer immediately below the second electrode and the first semiconductor layer immediately below the second electrode, and not provided on the third semiconductor layer;
A first portion between the third semiconductor layer, the third semiconductor layer in contact with the first electrode, the second semiconductor layer immediately below the first electrode, the first semiconductor layer immediately below the first electrode, and the third electrode , The third semiconductor layer in contact with the second electrode, the second semiconductor layer immediately below the second electrode, the first semiconductor layer immediately below the second electrode, and a second portion between the third electrode And an insulating film including a third portion between the first semiconductor layer and the third electrode;
With
The third electrode is not provided on the first part and is not provided on the second part,
The lower end of the third electrode, Ri Oh below the upper end of the first semiconductor layer,
The first semiconductor layer includes a p-type first semiconductor region, and a second semiconductor region between the first semiconductor region and the second semiconductor layer,
The semiconductor device, wherein the second semiconductor region has a structure in which n-type AlGaN-containing layers and p-type AlGaN-containing layers are alternately arranged in a direction from the first semiconductor layer to the third semiconductor layer . 窒化物半導体を有する第１半導体層と、
前記第１半導体層上に設けられ、前記第１半導体層よりも禁止帯幅が大きく、窒化物半導体を有する第２半導体層と、
前記第２半導体層上に設けられ、前記第２半導体層よりも禁止帯幅が小さく、窒化物半導体を有する第３半導体層と、
前記第２半導体層上に設けられ、前記第３半導体層に接する第１電極と、
前記第２半導体層上に設けられ、前記第３半導体層に接する第２電極と、
前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、の間に設けられ、前記第３半導体層上には設けられていない第３電極と、
前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第３電極と、の間の第１部分、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、前記第３電極との間の第２部分、並びに、前記第１半導体層と前記第３電極との間の第３部分と、を含む絶縁膜と、
を備え、
前記第３電極は、前記第１部分の上には設けられておらず、前記第２部分の上にも設けられておらず、
前記第３電極の下端は、前記第１半導体層の上端よりも下であり、
前記第２半導体領域は、前記第１半導体層から前記第３半導体層に向かう方向において、ＡｌＧａＮ含有層とＧａＮ含有層とが交互に配列された構造を有する、半導体装置。 A first semiconductor layer having a nitride semiconductor;
A second semiconductor layer provided on the first semiconductor layer and having a forbidden band larger than the first semiconductor layer and having a nitride semiconductor;
A third semiconductor layer provided on the second semiconductor layer, having a forbidden bandwidth smaller than that of the second semiconductor layer and having a nitride semiconductor;
A first electrode provided on the second semiconductor layer and in contact with the third semiconductor layer;
A second electrode provided on the second semiconductor layer and in contact with the third semiconductor layer;
The third semiconductor layer in contact with the first electrode, the second semiconductor layer immediately below the first electrode, the first semiconductor layer immediately below the first electrode, and the third semiconductor layer in contact with the second electrode; A third electrode provided between the second semiconductor layer immediately below the second electrode and the first semiconductor layer immediately below the second electrode, and not provided on the third semiconductor layer;
A first portion between the third semiconductor layer, the third semiconductor layer in contact with the first electrode, the second semiconductor layer immediately below the first electrode, the first semiconductor layer immediately below the first electrode, and the third electrode , The third semiconductor layer in contact with the second electrode, the second semiconductor layer immediately below the second electrode, the first semiconductor layer immediately below the second electrode, and a second portion between the third electrode And an insulating film including a third portion between the first semiconductor layer and the third electrode;
With
The third electrode is not provided on the first part and is not provided on the second part,
The lower end of the third electrode, Ri Oh below the upper end of the first semiconductor layer,
The semiconductor device, wherein the second semiconductor region has a structure in which AlGaN-containing layers and GaN-containing layers are alternately arranged in a direction from the first semiconductor layer to the third semiconductor layer . 前記第２電極に前記第１電極よりも高い電位を印加し、前記第３電極に、第１の電位を印加したときには、前記第１電極と前記第２電極との間が通電せず、前記第３電極に、前記第１の電位よりも高い第２の電位を印加したときは、前記第１電極と第２電極との間が通電可能な請求項１〜７のいずれか１つに記載の半導体装置。 When a potential higher than that of the first electrode is applied to the second electrode and a first potential is applied to the third electrode, no current is passed between the first electrode and the second electrode, the third electrode, the first at the time of applying a second potential higher than the potential is, according to the any one of claims 1-7 capable energization between the first electrode and the second electrode Semiconductor device. 前記第１電極と、前記第３電極と、の間の前記第３半導体層の導電形がｎ形である請求項１〜８のいずれか１つに記載の半導体装置。 Wherein a first electrode, a semiconductor device according to any one of the third electrode and the claim 1-8 conductivity type of the third semiconductor layer is an n-type between. 前記絶縁膜と前記第１半導体層との間に設けられ、前記第１半導体層よりも禁止帯幅が大きく、窒化物半導体を有する第４半導体層をさらに備えた請求項１〜９のいずれか１つに記載の半導体装置。 Wherein provided between the insulating film and the first semiconductor layer, said large band gap than the first semiconductor layer, any of claims 1 to 9 comprising further a fourth semiconductor layer having a nitride semiconductor The semiconductor device according to one. 前記第２半導体層の厚さは、５ｎｍ以上５０ｎｍ以下である請求項１〜１０のいずれか１つに記載の半導体装置。 The thickness of the second semiconductor layer, the semiconductor device according to any one of claims 1 to 1 0 is 5nm or more 50nm or less. 窒化物半導体を有する第１半導体層と、
前記第１半導体層上に設けられ、前記第１半導体層よりも禁止帯幅が大きく、窒化物半導体を有する第２半導体層と、
前記第２半導体層上に設けられ、前記第２半導体層よりも禁止帯幅が小さく、窒化物半導体を有する第３半導体層と、
前記第２半導体層上に設けられ、前記第３半導体層に接する第１電極と、
前記第２半導体層上に設けられ、前記第３半導体層に接する第２電極と、
前記第１電極に接する前記第３半導体層、前記第１電極直下の前記第２半導体層、および前記第１電極直下の前記第１半導体層と、前記第２電極に接する前記第３半導体層、前記第２電極直下の前記第２半導体層、および前記第２電極直下の前記第１半導体層と、の間に設けられ、絶縁膜を介して前記第３半導体層、前記第２半導体層、および前記第１半導体層に対向し、前記第１電極から第２電極に向かう方向に対して交差する方向に配列され、前記第３半導体層上には設けられていない複数の第３電極と、
隣り合う前記第３電極の間に設けられ、前記第３半導体層、前記第２半導体層、および前記第１半導体層に繋がり、窒化物半導体を有する第５半導体層と、
を備え、
前記第１半導体層は、ｐ形ＧａＮと、前記ｐ形ＧａＮと前記第２半導体層との間のＧａＮと、を含み、
前記第５半導体層は、前記ｐ形ＧａＮよりも高抵抗のＧａＮを含む、半導体装置。 A first semiconductor layer having a nitride semiconductor;
A second semiconductor layer provided on the first semiconductor layer and having a forbidden band larger than the first semiconductor layer and having a nitride semiconductor;
A third semiconductor layer provided on the second semiconductor layer, having a forbidden bandwidth smaller than that of the second semiconductor layer and having a nitride semiconductor;
A first electrode provided on the second semiconductor layer and in contact with the third semiconductor layer;
A second electrode provided on the second semiconductor layer and in contact with the third semiconductor layer;
The third semiconductor layer in contact with the first electrode, the second semiconductor layer immediately below the first electrode, the first semiconductor layer immediately below the first electrode, and the third semiconductor layer in contact with the second electrode; The third semiconductor layer, the second semiconductor layer, and the second semiconductor layer immediately below the second electrode and the first semiconductor layer directly below the second electrode, with an insulating film interposed therebetween, A plurality of third electrodes opposed to the first semiconductor layer and arranged in a direction intersecting with a direction from the first electrode toward the second electrode, and not provided on the third semiconductor layer;
A fifth semiconductor layer provided between the adjacent third electrodes, connected to the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer and having a nitride semiconductor;
With
The first semiconductor layer includes p-type GaN and GaN between the p-type GaN and the second semiconductor layer,
The semiconductor device, wherein the fifth semiconductor layer includes GaN having higher resistance than the p-type GaN.
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