JP2008263140A - Nitride semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride semiconductor device having a stable high breakdown voltage and high reliability. <P>SOLUTION: In a GaN-HFET (Heterostructure Field-Effect Transistor), an undoped or n-type AlGaN layer 2 is formed on an undoped GaN layer 1, and a source electrode 3 and a drain electrode 4, both connected to the AlGaN layer 2, are formed on the AlGaN layer 2, while a gate electrode 5 is formed between the source and drain electrodes. A p-layer 6 is formed in a region in an upper layer part of the GaN layer 1 and in the AlGaN layer 2, wherein the region includes a part of the region directly underneath the source electrode 3 and a part of the region directly underneath the gate electrode 5, and the p-layer 6 is connected to the source electrode 3 and to the gate electrode 5. Furthermore, a field insulating film 7 is formed covering the gate electrode 5. A source FP (Field-Plate) electrode 8, which is connected to the source electrode 3, is formed on a region of the field insulating film 7, wherein the region includes the region directly above the gate electrode 5, and the distance between the source FP electrode 8 and the drain electrode 4 is longer than the distance between the p-layer 6 and the drain electrode 4. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nitride semiconductor device, and more particularly to a lateral power nitride semiconductor device.

  Since gallium nitride (GaN) has a larger band gap than silicon (Si), a semiconductor device using GaN has a higher critical electric field than a semiconductor device using Si, and it is easy to realize a small and high breakdown voltage device. For this reason, if a semiconductor element for power control is produced using GaN, an element with low on-resistance and low loss can be realized. In particular, a field effect transistor (HFET) using an AlGaN / GaN heterostructure can be expected to have good characteristics with a simple element structure. In such an HFET, an AlGaN layer is formed on a GaN layer, and a source electrode, a gate electrode, and a drain electrode are provided thereon. Then, a current can flow between the drain electrode and the source electrode using the two-dimensional electron gas (2DEG) generated near the interface with the AlGaN layer in the GaN layer as a carrier.

  In such a horizontal power control semiconductor element, in order to prevent electric field concentration at the end of the gate electrode, a field insulating film is provided so as to cover the gate electrode, and inside or above the field insulating film, A field plate electrode connected to the source electrode or the gate electrode may be provided (see, for example, Patent Document 1). Thereby, the concentration point of the electric field can be distributed between the end portion of the gate electrode and the end portion of the field plate electrode. At this time, the electric field concentrated on the end of the gate electrode is applied to the semiconductor layer, that is, the AlGaN layer and the GaN layer. On the other hand, the electric field concentrated on the end of the field plate electrode is applied to the field insulating film.

  However, the conventional HFET has the following problems. The critical electric field of GaN is as high as 10 times or more the critical electric field of Si, which is about the same as the breakdown electric field of the insulating film. For this reason, it is possible to apply the same electric field to the semiconductor layer and the insulating film. However, the breakdown voltage of the element is determined by the breakdown electric field of the field insulating film. The breakdown electric field of the insulating film varies depending on the film formation method, and is more likely to vary than the critical electric field of the single crystal semiconductor. For this reason, the element breakdown voltage varies due to variations in the breakdown electric field of the field insulating film, and the breakdown voltage stability is low.

  Further, even if the electric field strength applied to the field insulating film is less than the strength of the breakdown electric field, the insulating film is deteriorated and gradually increases the leakage current by continuing to be applied for a long period of time. In some cases, the insulating film is eventually destroyed. For this reason, when the electric field is strongly concentrated on the end portion of the field plate electrode, there is a risk that the long-term reliability of the element is impaired.

JP 2005-93864 A

  An object of the present invention is to provide a nitride semiconductor device having a stable high breakdown voltage and high reliability.

According to one embodiment of the present invention, a first semiconductor layer made of undoped Al _x Ga _1-x N (0 ≦ x <1) and an undoped or n-type Al _y provided on the first semiconductor layer. A second semiconductor layer made of Ga _1-y N (0 <y ≦ 1, x <y), and a p-type third semiconductor layer selectively formed on at least the upper surface of the second semiconductor layer; A source electrode connected to the second semiconductor layer and the third semiconductor layer, a drain electrode connected to the second semiconductor layer, and a gate electrode provided on the second semiconductor layer; A field plate provided on the second semiconductor layer and covering the gate electrode; and a field plate provided in a region including a region immediately above the gate electrode on the field insulating film and connected to the source electrode An electrode; and The distance between the de plate electrode and the drain electrode, a nitride semiconductor device according to claim longer than the distance between the drain electrode and the third semiconductor layer is provided.

  According to the present invention, a nitride semiconductor device having a stable and high breakdown voltage and high reliability can be realized.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same or corresponding part in drawing.

(First embodiment)
FIG. 1 is a cross-sectional view schematically illustrating the configuration of a nitride semiconductor device according to the first embodiment of the present invention, and the horizontal axis indicates the current direction position of the device, and the vertical axis indicates the electric field strength. It is a graph which illustrates electric field distribution in an element.
The nitride semiconductor device according to this embodiment is a lateral HFET using an AlGaN / GaN heterostructure (hereinafter referred to as “GaN-HFET”), and is used, for example, for output control of a high voltage current. .

As shown in FIG. 1, in the GaN-HFET according to the present embodiment, an undoped Al _x Ga _1-x N (0 ≦ x <1) is formed as a first semiconductor layer on a substrate (not shown). For example, a GaN layer 1 made of GaN is provided. On the GaN layer 1, as a second semiconductor layer, an undoped or n-type Al _y Ga _1-y N (0 <y ≦ 1, x <y), for example, an AlGaN layer made of undoped AlGaN. 2 is provided. Furthermore, a source electrode 3 and a drain electrode 4 are provided on the AlGaN layer 2 so as to be separated from each other, and a gate electrode 5 is provided between the source electrode 3 and the drain electrode 4.

  A two-dimensional electron gas (2DEG) is generated in the vicinity of the interface between the GaN layer 1 and the AlGaN layer 2 (hereinafter also referred to as “AlGaN / GaN heterointerface”). Ohmic connected to 2DEG. The gate electrode 5 forms a Schottky junction with the AlGaN layer 2. In one example, the source electrode 3 and the drain electrode 4 are made of titanium (Ti) having a low contact resistivity with respect to 2DEG, and the gate electrode 5 is made of nickel (Ni) having a high barrier height at the Schottky junction. Yes.

  A p-type p layer 6 is selectively formed as a third semiconductor layer in the upper layer portion of the GaN layer 1 and the AlGaN layer 2. The p layer 6 is formed, for example, by selectively doping a p-type impurity such as fluorine (F) or magnesium (Mg) with respect to the upper layer portion of the GaN layer 1 and the AlGaN layer 2. The p layer 6 is formed in a region including a part of the region directly under the source electrode 3 and a part of the region directly under the gate electrode 5, and is connected to the source electrode 3 and the gate electrode 5. That is, the source electrode 3 is connected to the AlGaN layer 2 and the p layer 6. Note that the p-layer 6 is not necessarily formed in the GaN layer 1, and may be formed at least on the upper surface of the AlGaN layer 2.

  Further, a field insulating film 7 is provided on the AlGaN layer 2 so as to cover the gate electrode 5. A source field plate electrode (hereinafter referred to as “source FP”) connected to the source electrode 3 is formed on the field insulating film 7. 8) is provided. On the field insulating film 7, the source FP electrode 8 extends from a region directly above the source electrode 3 to a region directly above the gate electrode 5 and to a region immediately above the drain electrode 4. That is, the source FP electrode 8 is provided in a region including the region directly above the gate electrode 5 on the field insulating film 7.

  In the GaN-HFET according to this embodiment, the distance between the source FP electrode 8 and the drain electrode 4 is longer than the distance between the p layer 6 and the drain electrode 4. For example, when viewed from above, that is, from a direction perpendicular to the upper surface of the AlGaN layer 2 (hereinafter referred to as “in plan view”), the p layer 6 protrudes from the source FP electrode 8 to the drain electrode 4 side. .

Next, the effect of this embodiment is demonstrated.
In the GaN-HFET according to the present embodiment, a voltage is applied between the source electrode 3 and the drain electrode 4 (hereinafter also referred to as “between the source and drain”), and is generated at the AlGaN / GaN hetero interface. A current can be passed between the source electrode 3 and the drain electrode 4 using 2DEG as a carrier. Further, by applying a negative potential to the gate electrode 5, a depletion layer can be formed immediately below the gate electrode 5 at the AlGaN / GaN hetero interface, thereby interrupting the current.

  At this time, when a high voltage is applied between the source electrode 3 and the drain electrode 4, the electric field concentrates at the end of the gate electrode 5 on the drain electrode 4 side. And if the intensity of this electric field exceeds the limit, avalanche breakdown occurs. The voltage at which this avalanche breakdown occurs is the breakdown voltage of the device (GaN-HFET). Therefore, in order to increase the breakdown voltage of the element, it is necessary to suppress the concentration of the electric field at the end of the gate electrode 5.

  For this reason, in this GaN-HFET, the source FP electrode 8 is provided in a region including the region directly above the gate electrode 5. Thereby, the concentration of the electric field at the end of the gate electrode 5 can be relaxed, and the breakdown voltage of the element can be improved. Further, by relaxing the electric field concentration at the end of the gate electrode 5, it is possible to suppress the 2DEG from being accelerated in the electric field when a high voltage is applied between the source and the drain. As a result, it is possible to suppress trapping of electrons accelerated by the electric field at the interface between the field insulating film 7 and the AlGaN layer 2 and crystal defects in the GaN layer 1, and the concentration of 2DEG is increased by the trapped electrons. It is possible to suppress the reduction, and it is possible to suppress an increase in on-resistance due to a 2DEG concentration reduction. As a result, it is possible to realize a GaN-HFET with a high breakdown voltage and low on-resistance.

  However, the provision of the source FP electrode 8 reduces the electric field at the end of the gate electrode 5, that is, the electric field in the AlGaN layer 2 and the GaN layer 1, but the end of the source FP electrode 8 on the drain electrode 4 side. The electric field in the portion, that is, the electric field in the field insulating film 7 increases. That is, as indicated by the broken line in the graph of FIG. 1, in the comparative example in which the p layer 6 is not formed, the electric field is concentrated on the end of the source FP electrode 8 on the drain electrode 4 side. As a result, a strong electric field is applied to the field insulating film 7.

  The critical electric field of GaN is about 3.3 MV / cm, which is more than 10 times the critical electric field of Si used in conventional power devices, but is almost the same as the breakdown electric field of the insulating film. . That is, the breakdown electric field of the insulating film is not significantly higher than the critical electric field of GaN. For this reason, even if the electric field in GaN is weakened, if the electric field in the insulating film is increased, dielectric breakdown occurs and the element is destroyed. That is, the breakdown voltage of the element is determined by the breakdown electric field of the field insulating film.

  The magnitude of the breakdown electric field of the field insulating film depends on the film forming method and the film forming conditions, and varies more than the critical electric field of the single crystal semiconductor. Therefore, when the breakdown voltage of the element is determined by the breakdown electric field of the field insulating film, the breakdown voltage of the element becomes unstable. Further, when a strong electric field is applied to the field insulating film over a long period of time, the field insulating film is deteriorated, and the reliability of the element is lowered.

  Therefore, in the GaN-HFET according to the present embodiment, the p layer 6 is formed to a position closer to the drain electrode 4 than to the source FP electrode 8. Thereby, the electric field concentration at the end of the source FP electrode 8 can be relaxed, and the dielectric breakdown of the field insulating film 7 can be prevented. Specifically, when a high voltage is applied between the source and the drain, the depletion layer spreads over the entire p layer 6. As a result, as indicated by the solid line in the graph of FIG. 1, the electric field strength at the end of the p layer 6 on the drain electrode 4 side increases, and the electric field strength at the end of the source FP electrode 8 on the drain electrode 4 side decreases. To do. Thereby, the dielectric breakdown of the field insulating film 7 can be prevented.

  In addition, since the p layer 6 is connected to the source electrode 3, when the GaN-HFET is switched by applying a voltage to the gate electrode 5, the p layer 6 is charged and discharged quickly. Can do. Thereby, the operating speed of the GaN-HFET can be increased.

  As described above, according to the present embodiment, the p layer 6 connected to the source electrode 3 is formed at least on the upper surface of the AlGaN layer 2, and this p layer 6 is formed at the portion where the electric field is strongest in the field insulating film 7. It extends to a position closer to the drain electrode 4 than the end of a certain field plate electrode. Thereby, the electric field concentration in the field insulating film 7 can be relaxed, and the element breakdown voltage can be determined not by the breakdown electric field of the insulating film but by the critical electric field of the semiconductor. As a result, the breakdown voltage of the element can be increased and stabilized. In addition, since the electric field in the field insulating film is reduced, deterioration of the insulating film due to application of the electric field can be prevented, and high reliability can be obtained. That is, according to the present embodiment, a nitride semiconductor device having a stable high breakdown voltage and high reliability can be realized.

Hereinafter, the configuration of the p layer 6 in the present embodiment will be described more specifically.
First, the impurity concentration of the p layer 6 will be described.
FIG. 2 is a cross-sectional view schematically illustrating the configuration of the GaN-HFET according to the present embodiment, and the sheet impurity of the p layer with the horizontal axis indicating the position in the current direction and the vertical axis indicating the electric field strength. It is a graph which illustrates the influence which density | concentration has on electric field distribution in an element.
Note that the graph of FIG. 2, the electric field distribution when the sheet impurity concentration N _p of the p-layer 6 is lower than the sheet concentration N _2DEG of the 2DEG shown in solid lines indicate the electric field distribution when both concentrations are equal by a broken line shows the electric field distribution when density N _p is higher than the concentration N _2DEG by a one-dot chain line.

As shown in FIG. 2, the electric field distribution in the device depends on the relationship between the sheet concentration _{N 2DEG} sheet impurity concentration _{N p} and the 2DEG p layer 6. The sheet impurity concentration here is the sheet concentration of activated impurities. As shown by the solid line in FIG. 2, the sheet impurity concentration N _p of the p-layer 6 is lower than the sheet concentration N _2DEG of 2DEG, the electric field strength at the ends of the p layer 6 the field strength at the end of the source FP electrode 8 Higher than. On the other hand, as indicated by a broken line in FIG. 2, when the concentration N _p is equal to the concentration N _2DEG , the electric field strength at the end of the source FP electrode 8 becomes substantially equal to the electric field strength at the end of the p layer 6. Further, as shown by a chain line in FIG. 2, when the concentration N _p is higher than the concentration N _2DEG, the electric field strength at the ends of the source FP electrode 8 is lower than the electric field strength at the ends of the p layer 6. Therefore, in order to suppress the electric field at the end portions of the source FP electrode 8 is desirably sheet impurity concentration _{N p} of the p-layer 6 is less sheet concentration _{N 2DEG} of the 2DEG, lower than the sheet concentration _{N 2DEG} of the 2DEG It is more desirable. Even when the AlGaN layer 2 is n-type doped, it is desirable that the sheet impurity concentration of the p layer 6 be lower than the sheet concentration of 2DEG, as in the case of undoped. In this case, the sheet impurity concentration of the p layer 6 may be made lower than the 2DEG sheet concentration obtained by combining 2DEG generated by n-type doping and 2DEG generated by polarization.

Next, the planar shape of the p layer 6 will be described.
FIG. 3A is a plan view illustrating a GaN-HFET according to this embodiment, FIG. 3B is a cross-sectional view taken along the line AA ′ shown in FIG. 3A, and FIG. It is sectional drawing by the BB 'line shown.
Note that the content of FIG. 3B is the same as the content of the cross-sectional view of FIG. In FIG. 3A, the gate electrode 5 is drawn with a two-dot chain line, and the field insulating film 7 and the source FP electrode 8 are not shown. Further, among the components shown in FIG. 3, the same or corresponding components as those shown in FIG. 1 are denoted by the same reference numerals as those in FIG. The same applies to other figures described later.

  As shown in FIGS. 3A to 3C, the shape of the p layer 6 extends in a direction from the source electrode 3 toward the drain electrode 4 in a plan view, and is intermittent along a direction orthogonal to this direction. This is a stripe pattern arranged in a pattern. For example, the p layer 6 is periodically formed along the arrangement direction. The source electrode 3, the drain electrode 4, and the gate electrode 5 extend in a stripe shape along the arrangement direction of the p layer 6. Therefore, in plan view, the p layer 6 and the gate electrode 5 intersect each other, and in the region immediately below the gate electrode 5, the portion where the p layer 6 exists and the portion where the p layer 6 does not exist are alternately arranged. ing.

  Thus, by forming the p layer 6 in a stripe shape, the ratio of the region where 2DEG disappears in the region between the source electrode 3 and the drain electrode 4 can be reduced, and the on-resistance can be reduced. On the other hand, when the p layer 6 is formed over the entire region between the source and the drain, all 2DEG in this region disappears and the on-resistance increases. Even if the p-layer 6 is formed in a stripe shape, the depletion layer extends to the end of the p-layer 6 on the drain electrode 4 side when a high voltage is applied, so that the electric field at the end of the source FP electrode 8 can be reduced. Is possible.

(First modification of the first embodiment)
4A is a plan view illustrating a GaN-HFET according to a first modification of the first embodiment, and FIG. 4B is a cross-sectional view taken along the line AA ′ shown in FIG. (C) is sectional drawing by the BB 'line shown to (a).
In FIG. 4A, the gate electrode 5 is drawn with a two-dot chain line, and the field insulating film 7 and the source FP electrode 8 are not shown.
As shown in FIGS. 4A to 4C, in the GaN-HFET according to this modification, the drain electrode 4 side of the p layer 6 from the edge of the gate electrode 5 on the drain electrode 4 side is seen in plan view. When the distance to the edge is a and the arrangement period of the p layer 6 is b, the arrangement period b is shorter than the distance a. That is, a> b.

  In the GaN-HFET according to the first embodiment described above, the lower the arrangement density of the p layers 6, the lower the ratio of the region where 2DEG disappears between the source and the drain. On the other hand, the effect of suppressing the electric field concentration at the end of the source FP electrode 8 is also reduced. Therefore, in this modification, the p layer 6 is formed periodically and this period is shortened. This ensures a certain proportion of the region where the p-layer 6 is not formed in the region between the source and drain, thereby reducing the distance between the adjacent p-layers 6 while suppressing an increase in on-resistance. By making the depletion layers extending from the matching p layer 6 easy to connect, the electric field at the end of the source FP electrode 8 can be reduced. In order to reliably obtain this effect, it is desirable that the arrangement period b of the p layer 6 is shorter than the distance a. Configurations and operational effects other than those described above in the present modification are the same as those in the first embodiment.

(Second modification of the first embodiment)
FIG. 5 is a plan view illustrating a GaN-HFET according to a second modification of the first embodiment.
As shown in FIG. 5, in the GaN-HFET according to the present modification, the end of the p layer 6 on the drain electrode 4 side protrudes on both sides in the arrangement direction of the p layer 6 in a plan view. It has a shape. Thereby, the depletion layers extending from the adjacent p layers 6 are more easily connected in the vicinity of the region immediately below the source FP electrode 8. Configurations and operational effects other than those described above in the present modification are the same as those in the first embodiment.

(Second Embodiment)
FIG. 6 is a cross-sectional view schematically illustrating the structure of a GaN-HFET according to the second embodiment of the invention.
As shown in FIG. 6, in the GaN-HFET according to the present embodiment, in addition to the configuration of the GaN-HFET according to the first embodiment (see FIG. 1), the gate FP connected to the gate electrode 5 is used. An electrode 9 is provided. The gate FP electrode 9 is embedded in the field insulating film 7 and insulated from the source FP electrode 8 by the field insulating film 7. Further, the gate FP electrode 9 protrudes from the region directly above the gate electrode 5 toward the region directly above the drain electrode 4.

  In the present embodiment, since the gate FP electrode 9 is provided in addition to the source FP electrode 8, electric field concentration at the end of the gate electrode 5 is more effective as compared with the case where only the source FP electrode 8 is provided. Can be suppressed. As a result, it is possible to more effectively suppress the phenomenon in which 2DEG is accelerated by the electric field and trapped at the interface and crystal defects to increase the on-resistance. Configurations and operational effects other than those described above in the present embodiment are the same as those in the first embodiment described above.

(Third embodiment)
FIG. 7 is a cross-sectional view schematically illustrating the structure of a GaN-HFET according to the third embodiment of the invention.
As shown in FIG. 7, in the GaN-HFET according to the present embodiment, in addition to the configuration of the GaN-HFET according to the second embodiment (see FIG. 6), the upper layer portion of the GaN layer 1 and the AlGaN layer. 2, a p-type p ⁺ layer 10 is formed as a fourth semiconductor layer immediately below the gate electrode 5. For example, the p ⁺ layer 10 is formed in a stripe shape over the entire length immediately below the gate electrode 5, and the depth thereof is deeper than the depth of the p layer 6. Further, the sheet concentration of p-type impurities in the p ⁺ layer 10 is higher than the sheet concentration of p-type impurities in the p layer 6, for example, higher than the sheet concentration of 2DEG. The p ⁺ layer 10 can be formed by selectively doping the upper layer portion of the GaN layer 1 and the AlGaN layer 2 with p-type impurities.

In the present embodiment, since the p ⁺ layer 10 is selectively formed only in the region immediately below the gate electrode 5, 2DEG can be completely disabled and the gate threshold voltage can be shifted to the plus side. In particular, if the sheet concentration of the p-type impurity in the p ⁺ layer 10 is made higher than the 2DEG sheet concentration, the threshold voltage becomes 0 V or more. That is, it is possible to realize a normally-off operation. Configurations and operational effects other than those described above in the present embodiment are the same as those in the first embodiment described above.

(Modification of the third embodiment)
FIG. 8 is a cross-sectional view schematically illustrating the structure of a GaN-HFET according to a modification of the third embodiment.
As shown in FIG. 8, in the GaN-HFET according to this modification, in addition to the configuration of the GaN-HFET according to the third embodiment (see FIG. 7), the p ⁺ layer 10 and the gate electrode 5 For example, the gate insulating film 11 is provided in the entire region between the source electrode 3 and the drain electrode 4 on the AlGaN layer 2.

  According to this modification, the gate leakage current can be reduced by providing the gate insulating film 11. As a result, a large positive voltage can be applied to the gate electrode 5 and the channel resistance can be reduced. As a result, the on-resistance of the element can be reduced. Configurations and operational effects other than those described above in the present modification are the same as those in the third embodiment described above.

(Fourth embodiment)
FIG. 9 is a cross-sectional view schematically illustrating the structure of a GaN-HFET according to the fourth embodiment of the invention.
As shown in FIG. 9, in the GaN-HFET according to this embodiment, in addition to the configuration of the GaN-HFET according to the first embodiment (see FIG. 1), the upper layer portion of the GaN layer 1 and the AlGaN layer. 2, a p-type p ⁺ contact layer 12 is formed in a part of the region immediately below the source electrode 3. For example, the p ⁺ contact layer 12 is formed only in a region in contact with the p layer 6 in the region immediately below the source electrode 3, and is connected to both the p layer 6 and the source electrode 3. Further, the sheet concentration of p-type impurities in the p ⁺ contact layer 12 is higher than the sheet concentration of p-type impurities in the p layer 6. The p ⁺ contact layer 12 can be formed, for example, by selectively doping p-type impurities into the upper layer portion of the GaN layer 1 and the AlGaN layer 2.

As described in the first embodiment, in order to make the electric field distribution in the element uniform, the sheet impurity concentration of the p layer 6 is preferably lower than the sheet concentration of 2DEG. When the sheet impurity concentration of the p layer 6 is lowered, the contact resistivity between the p layer 6 and the source electrode 3 is increased, and it becomes difficult to quickly charge and discharge holes in the p layer 6. Therefore, in the present embodiment, by forming the p ⁺ contact layer 12, the resistance between the p layer 6 and the source electrode 3 is reduced while the sheet impurity concentration of the p layer 6 is kept low, and the p layer 6 can quickly charge and discharge holes. This makes it possible to increase the speed of the element. Configurations and operational effects other than those described above in the present embodiment are the same as those in the first embodiment described above.

(Modification of the fourth embodiment)
FIG. 10 is a cross-sectional view schematically illustrating the structure of a GaN-HFET according to a modification of the fourth embodiment.
As shown in FIG. 10, the GaN-HFET according to the present modification has a source electrode 3 having n contact portions 3 a and p as compared with the GaN-HFET according to the fourth embodiment (see FIG. 9). The difference is that it is composed of the contact portion 3b. That is, the portion of the source electrode 3 on the side far from the drain electrode 4 is an n-contact portion 3a, and the portion near the drain electrode 4 is a p-contact portion 3b.

The n contact portion 3a is in contact with a portion of the upper surface of the AlGaN layer 2 where the p layer 6 or the p ⁺ contact layer 12 is not formed, that is, an n-type or undoped semiconductor portion. The n contact portion 3a is made of a metal having a low contact resistivity with respect to the n-type semiconductor, and is made of, for example, titanium (Ti). On the other hand, the p contact portion 3b is in contact with the p layer 6 and the p ⁺ contact layer 12, that is, the p-type semiconductor portion. The p contact portion 3b is made of a metal having a low contact resistivity with respect to a p-type semiconductor, and is made of, for example, platinum (Pt).

  According to this modification, the source electrode 3 is provided with the n-contact portion 3a and the p-contact portion 3b, which are formed of a material having a low contact resistivity with respect to the n-type semiconductor and the p-type semiconductor. Can be connected to both 2DEG and the p-layer 6 with low resistance. Along with the arrangement direction of the p layer 6, the p contact portion 3 b is periodically provided only at a position in contact with the p layer 6 in the source electrode 3, and the other portion is formed by the n contact portion 3 a. Also good. Configurations and operational effects other than those described above in the present modification are the same as those in the fourth embodiment described above.

  The present invention has been described above with reference to the first to fourth embodiments and their modifications. However, the present invention is not limited to these examples. For example, the present invention is not limited to the above-described embodiments and modifications. Those in which those skilled in the art have appropriately added, deleted, and changed the design are also included in the scope of the present invention as long as they have the gist of the present invention. Moreover, the above-described embodiments and modifications can be implemented in combination with each other. For example, also in the above-described second to fourth embodiments, it is desirable to form the p layer 6 in a stripe shape as in the first embodiment.

  In each of the above-described embodiments and modification examples, the GaN layer 1 is formed of undoped GaN. However, the GaN layer 1 may be formed of undoped AlGaN. In each of the above-described embodiments and modification examples, the AlGaN layer 2 is formed of undoped AlGaN. However, the AlGaN layer 2 may be formed of n-type AlGaN. Alternatively, the AlGaN layer 2 may be formed of AlN. That is, in each of the above-described embodiments and modifications, an example in which an AlGaN / GaN heterostructure is formed has been shown, but the present invention is not limited to this, and AlN / AlGaN heterostructures such as AlN / AlGaN heterostructures. A heterostructure in which the composition ratio of Ga and Ga is arbitrarily set may be formed.

  Furthermore, the present invention is not limited by the material of the support substrate for forming the GaN layer 1 and the AlGaN layer 2, and the support substrate is a SiC substrate, a sapphire substrate, a Si substrate, or a GaN substrate. Can do. A buffer layer may be provided between the support substrate and the GaN layer 1. The structure and material of the buffer layer are not particularly limited, and for example, an AlN layer, an AlGaN layer, or a stacked structure of an AlN layer and a GaN layer can be used.

Furthermore, in each of the above-described embodiments and modifications, an example in which the gate portion has a planar Schottky gate structure has been shown. However, the present invention is not limited thereto, and a recess gate structure or a structure in which a GaN cap layer is formed. Other gate structures can also be implemented. Furthermore, the effects of the present invention are not limited by the material of the insulating film such as the gate insulating film and the field insulating film. The materials of these insulating films, for example, _SiN, etc. SiO 2, _Al 2 _{O 3} or HfO _2, may be any insulating material that can be used in semiconductor processing.

  Furthermore, since the gate-drain between the gates and drains of the HFETs shown in the above embodiments and modifications is a heterostructure Schottky barrier diode (HSBD), the gate electrode is replaced with an anode electrode, and the drain electrode is replaced with a cathode electrode. Thus, an HSBD having a high breakdown voltage and a low on-voltage can be realized.

Sectional drawing which illustrates GaN-HFET which concerns on the 1st Embodiment of this invention, and the graph which illustrates the electric field intensity in an element by taking the position of the current direction in this element on a horizontal axis, and taking the electric field strength on a vertical axis | shaft FIG. The cross-sectional view illustrating the GaN-HFET according to this embodiment, and the horizontal axis indicates the current direction position in the device, the vertical axis indicates the electric field strength, and the p-layer sheet impurity concentration affects the electric field distribution in the device. It is a graph which illustrates an influence. (A) is a top view which illustrates GaN-HFET concerning this embodiment, (b) is sectional drawing by the AA 'line shown to (a), (c) is B shown to (a). It is sectional drawing by -B 'line. (A) is a top view which illustrates GaN-HFET which concerns on the 1st modification of 1st Embodiment, (b) is sectional drawing by the AA 'line shown to (a), (c) ) Is a cross-sectional view taken along line BB ′ shown in FIG. It is a top view which illustrates GaN-HFET concerning the 2nd modification of a 1st embodiment. It is sectional drawing which illustrates GaN-HFET concerning the 2nd Embodiment of this invention. It is sectional drawing which illustrates GaN-HFET concerning the 3rd Embodiment of this invention. It is sectional drawing which illustrates GaN-HFET which concerns on the modification of 3rd Embodiment. It is sectional drawing which illustrates GaN-HFET concerning the 4th Embodiment of this invention. It is sectional drawing which illustrates GaN-HFET which concerns on the modification of 4th Embodiment.

Explanation of symbols

1 GaN layer, 2 AlGaN layer, 3 source electrode, 3 an contact part, 3 b p contact part, 4 drain electrode, 5 gate electrode, 6 p layer, 7 field insulating film, 8 source FP electrode, 9 gate FP electrode 10 p ⁺ layer, 11 gate insulating film, 12 p ⁺ contact layer

Claims (5)

A first semiconductor layer made of undoped Al _x Ga _1-x N (0 ≦ x <1);
A second semiconductor layer provided on the first semiconductor layer and made of undoped or n-type Al _y Ga _1-y N (0 <y ≦ 1, x <y);
A p-type third semiconductor layer selectively formed on at least the upper surface of the second semiconductor layer;
A source electrode connected to the second semiconductor layer and the third semiconductor layer;
A drain electrode connected to the second semiconductor layer;
A gate electrode provided on the second semiconductor layer;
A field insulating film provided on the second semiconductor layer and covering the gate electrode;
A field plate electrode provided in a region including the region directly above the gate electrode on the field insulating film, and connected to the source electrode;
With
The nitride semiconductor device, wherein a distance between the field plate electrode and the drain electrode is longer than a distance between the third semiconductor layer and the drain electrode.   When viewed from a direction perpendicular to the top surface of the second semiconductor layer, the shape of the third semiconductor layer extends from the source electrode toward the drain electrode and is orthogonal to the direction toward the drain electrode. The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device is a stripe pattern that is intermittently arranged along a direction in which the nitride semiconductor device is aligned. The third semiconductor layers are arranged periodically;
The distance between a portion corresponding to a region immediately below the gate electrode in the third semiconductor layer and an end on the drain electrode side is longer than an arrangement period of the third semiconductor layer. Item 3. The nitride semiconductor device according to Item 2.   The nitride semiconductor device according to claim 1, further comprising another field plate electrode connected to the gate electrode. A p-type fourth semiconductor layer selectively formed in a region directly below the gate electrode on the upper surface of the third semiconductor layer;
A gate insulating film provided between the fourth semiconductor layer and the gate electrode;
The nitride semiconductor device according to claim 1, further comprising:

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