JP2010109086A - Nitride semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a normally-off type nitride semiconductor element which has a low on-resistance. <P>SOLUTION: One embodiment of the invention provides the nitride semiconductor element including: a first semiconductor layer of a p-type nitride semiconductor; a second semiconductor layer of an undoped nitride semiconductor formed on the first semiconductor layer; a third semiconductor layer of an undoped or n-type nitride semiconductor formed selectively on the second semiconductor layer; a first main electrode formed on the third semiconductor layer; a second main electrode formed on the third semiconductor layer; an insulating film formed on the second semiconductor layer; and a control electrode formed on the insulating film, wherein the third semiconductor layer has a larger band gap than the second semiconductor layer has, and the control electrode is positioned between the first main electrode and the second main electrode. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nitride semiconductor device, and more particularly to a nitride semiconductor device used for power control.

Power semiconductor elements such as switching elements and diodes are used in circuits such as switching power supplies and inverters. A power semiconductor element is required to have a high breakdown voltage and a low on-resistance.
However, the relationship between breakdown voltage and on-resistance has a trade-off relationship determined by the element material. Due to the progress of technological development so far, low on-resistance of power semiconductor elements has been realized to the limit of silicon, which is the main element material. In order to further reduce the on-resistance, it is necessary to change the element material.

By using a nitride semiconductor such as GaN or AlGaN or a wide band gap semiconductor such as silicon carbide (SiC) as a switching element material, the trade-off relationship determined by the material can be improved, and the on-resistance can be drastically reduced. (For example, refer nonpatent literature 1).
W. Huang, Z. Li, TP Chow, Y. Niiyama, T. nomura and S. Yoshida, Proc. International Symposium on Power Semiconductor Devices &IC's, pp.295-298, 2008

  As an element using a nitride semiconductor such as GaN or AlGaN and having a low on-resistance, an HFET (Heterojunction Field Effect Transistor) using an AlGaN / GaN heterostructure can be cited. This HFET realizes a low on-resistance due to the high mobility of the heterointerface channel and the high electron concentration generated by piezoelectric polarization.

  In this HFET, electrons are generated by polarization, so that high concentration electrons are uniformly generated not only between the gate and source and between the gate and drain but also under the gate electrode. Therefore, the HFET is a normally-on type element that is turned on without applying a voltage to the gate electrode.

  In order to realize a normally-off operation in which the element is turned off when no gate voltage is applied, a structure in which the AlGaN layer is not selectively formed only under the gate electrode is effective. If there is no AlGaN layer under the gate electrode, there is no polarization and no electrons are generated. Therefore, an MISFET operation can be realized by forming a gate insulating film under the gate electrode so that an AlGaN layer is not formed and a gate leakage current does not flow.

  If the GaN layer under the gate electrode is p-type doped, the gate threshold voltage can be increased. However, when the p-type doping concentration is low, a leak current flows between the source and the drain due to the short channel effect. When the p-type doping concentration is increased, the channel mobility is lowered and the on-resistance is increased.

  The present invention provides a normally-off type nitride semiconductor device with low on-resistance.

  According to one aspect of the present invention, a first semiconductor layer of a p-type nitride semiconductor, a second semiconductor layer of an undoped nitride semiconductor provided on the first semiconductor layer, and the second semiconductor A third semiconductor layer of an undoped or n-type nitride semiconductor selectively provided on the layer, a first main electrode provided on the third semiconductor layer, and on the third semiconductor layer A second main electrode provided; an insulating film provided on the second semiconductor layer; and a control electrode provided on the insulating film, wherein the band gap of the third semiconductor layer is A nitride semiconductor device is provided, wherein the nitride semiconductor device is larger than a band gap of the second semiconductor layer, and the control electrode is located between the first main electrode and the second main electrode. The

  According to another aspect of the present invention, a first semiconductor layer of a p-type nitride semiconductor, a second semiconductor layer of an undoped nitride semiconductor provided on the first semiconductor layer, A third semiconductor layer of an undoped or n-type nitride semiconductor selectively provided on the second semiconductor layer; and a first main layer provided on the third semiconductor layer and extending in the first direction. An insulating film provided on the electrode, the second main electrode provided on the third semiconductor layer and extending in the first direction, and the second semiconductor layer and the third semiconductor layer And a first direction provided on the second semiconductor layer and a part of the third semiconductor layer with the insulating film interposed therebetween and spaced apart from the first main electrode and the second main electrode. A band gap of the second semiconductor layer is set to a band gap of the second semiconductor layer. Greater than the control electrode, a nitride semiconductor element being located between said first main electrode and the second main electrode.

  According to the present invention, a normally-off type nitride semiconductor device with low on-resistance is provided.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
FIG. 1 is a schematic cross-sectional view illustrating the configuration of a nitride semiconductor device according to the first embodiment of the invention.
The nitride semiconductor device 50a shown in FIG. 1 is a GaN-HFET.

  The nitride semiconductor element 50a uses an undoped GaN layer formed on the p-GaN layer 1 (first semiconductor layer), that is, an i-GaN layer 2 (second semiconductor layer) as a channel layer. An undoped AlGaN layer, that is, an i-AlGaN layer 3 (third semiconductor layer) is formed thereon as a barrier layer. A source electrode 4 (first main electrode) and a drain electrode 5 (second main electrode) are formed on the i-AlGaN layer 3.

  A region where the i-AlGaN layer 3 (third semiconductor layer) is not formed exists between the source electrode 4 (first main electrode) and the drain electrode 5 (second main electrode). A gate insulating film 6 (insulating film) is formed on the i-GaN layer 2. A gate electrode 7 (control electrode) is formed on the gate insulating film 6 (insulating film).

  Two-dimensional electron gas (2DEG) is generated at the i-AlGaN / i-GaN hetero interface by polarization. Thereby, the resistance of the offset region between the gate and the source and between the gate and the drain can be reduced. 2DEG is electrically connected to the source electrode 4 (first main electrode) and the drain electrode 5 (second main electrode) on the i-AlGaN layer 3 to form an ohmic contact. Since i-AlGaN layer 3 (third semiconductor layer) is not formed under gate electrode 7 (control electrode), 2DEG is not generated by polarization. Further, since the i-GaN layer 2 (second semiconductor layer) is undoped, electrons are not present at the interface with the gate insulating film 6 (insulating film) unless a voltage is applied to the gate electrode 7 (control electrode). It is not present and a normally-off operation can be realized.

  In order to control the gate threshold voltage, the doping concentration of the channel layer may be changed. However, when the channel layer in the vicinity of the gate insulating film forming the inversion channel is doped, the channel mobility is lowered and the channel resistance is increased. As a result, the on-resistance increases.

  Therefore, in the nitride semiconductor element 50a, the p-GaN layer 1 (first semiconductor layer) is formed under the i-GaN layer 2 (second semiconductor layer) that is the channel layer. The p-GaN layer 1 (first semiconductor layer) serves as a back barrier, and the gate threshold voltage can be controlled by changing the potential distribution of the channel layer by changing the doping concentration. Further, since the doped layer is far from the MIS channel interface, the channel mobility can be kept high. Thereby, it is possible to realize both the gate threshold voltage control of the normally-off operation and the low on-resistance.

  Such a structure can be implemented by selectively growing the i-AlGaN layer 3 (third semiconductor layer) or removing it by etching.

FIG. 2 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention.
The nitride semiconductor device 50b shown in FIG. 2 is a GaN-HFET.

  In this nitride semiconductor element 50b, an i-AlGaN layer 3 (third semiconductor layer) is formed between the source electrode 4 (first main electrode) and the drain electrode 5 (second main electrode). A gate insulating film 6 (insulating film) is formed on the i-GaN layer 2 and the i-AlGaN layer 3 (third semiconductor layer) that are not formed. A gate electrode 7 (control electrode) is formed on the gate insulating film 6 (insulating film) so as to be in contact with the i-AlGaN layer 3 (third semiconductor layer) through the gate insulating film 6 (insulating film). Yes. The rest is the same as the nitride semiconductor element 50a shown in FIG.

  By making such a gate electrode 7 (control electrode) overlap with the i-AlGaN layer 3 (third semiconductor layer), the inversion channel of the MIS gate structure and the i-AlGaN / i-GaN heterointerface Thus, the electrical connection resistance of the 2DEG channel is reduced, and a low on-resistance can be realized.

FIG. 3 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention.
The nitride semiconductor device 50c shown in FIG. 3 is a GaN-HFET.

  In the nitride semiconductor device 50 c, the p-GaN layer 1 (first semiconductor layer) is electrically connected to the source electrode 4 (first main electrode) via the contact plug 24. The rest is the same as the nitride semiconductor device 50b shown in FIG.

  As described above, the p-GaN layer 1 (first semiconductor layer) is electrically connected to the source electrode 4 (first main electrode), thereby realizing high avalanche resistance and high reliability. Can do. When an avalanche breakdown occurs when a high voltage is applied, a large amount of electrons and holes are generated. Electrons are discharged from the drain electrode 5 (second main electrode), and holes are discharged from the source electrode 4 (first main electrode). By connecting the p-GaN layer 1 (first semiconductor layer) to the source electrode 4 (first main electrode), holes can be discharged from the p-GaN layer 1 (first semiconductor layer). , The discharge resistance becomes smaller. As a result, even if an avalanche breakdown occurs, the device is not easily destroyed, and a high avalanche resistance can be realized.

  When the p-GaN layer 1 (first semiconductor layer) is connected to the source electrode 4 (first main electrode), holes generated by impact ionization when a high voltage is applied are formed in the gate insulating film 6 (insulating film). ) Or a passivation film (not shown) and flow into the p-GaN layer 1 (first semiconductor layer). Thereby, the insulating property of the gate insulating film 6 (insulating film) is maintained, and high reliability can be obtained.

  In FIG. 3, a structure in which the p-GaN layer 1 (first semiconductor layer) and the source electrode 4 (first main electrode) are connected by etching from the surface is shown. The same effect can be obtained if it is connected to.

FIG. 4 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention.
The nitride semiconductor device 50d shown in FIG. 4 is a GaN-HFET.

  In this nitride semiconductor device 50d, a trench gate in which a trench groove is formed so that a portion where the gate electrode 7 (control electrode) is formed reaches the i-GaN layer 2 (second semiconductor layer). It has a structure. The rest is the same as the nitride semiconductor device 50b shown in FIG. With the trench gate structure, the distance between the gate electrode 7 (control electrode) and the p-GaN layer 1 (first semiconductor layer) can be controlled by the trench groove depth (etching depth).

  For example, as shown in FIG. 5, the short channel effect is hardly caused by increasing the etching depth b, so that the gate length a can be shortened. Thereby, channel resistance can be reduced. The effective channel length is a length a + 2b obtained by adding the etching depth b and the gate length a. However, the short channel effect is reduced by shortening the etching depth b rather than shortening the gate length a. Since it becomes remarkable, it is desirable that the etching depth b is larger than the channel length a.

  Compared with the trench side wall, the trench bottom is easily damaged by etching, and the mobility is likely to decrease. On the other hand, the side wall is less damaged, and a flat surface can be easily obtained by wet treatment, and higher mobility than the bottom can be easily obtained. For this reason, even if the etching depth b is increased, the on-resistance becomes lower as the gate length a is shortened.

  As shown in FIG. 5, a plane parallel to the main surface of the p-GaN layer 1 (first semiconductor layer) is defined as an XY plane, and a direction perpendicular to the XY plane is defined as Z. Axis. A direction from the source electrode 4 (first main electrode) to the drain electrode 5 (second main electrode) is defined as an X direction, and a direction perpendicular to the Z axis and the X axis is defined as a Y axis. At this time, in the nitride semiconductor element 50d, the trench depth b is constant in the Y-axis direction.

FIG. 6 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention.
The nitride semiconductor device 50e shown in FIG. 6 is a GaN-HFET.

As shown in FIG. 6, a plane parallel to the main surface of the p-GaN layer 1 (first semiconductor layer) is defined as an XY plane, and a direction perpendicular to the XY plane is defined as a Z axis. To do. Also, the direction from the back of the paper to the front is the X axis, and the direction perpendicular to the Z axis and the X axis is the Y axis.
The cross section taken along line AA ′ of the nitride semiconductor device 50e shown in FIG. 6 is the same as the cross section of the nitride semiconductor device 50d shown in FIG.

  The nitride semiconductor element 50e has a trench gate structure similar to the nitride semiconductor element 50d shown in FIG. However, unevenness is provided by changing the trench depth in the Y direction. The rest is the same as the nitride semiconductor device 50d shown in FIG.

  If the flatness is poor, the mobility of the trench sidewall may be lowered. For this reason, in the nitride semiconductor device 50e, it is possible to increase the channel width by adding irregularities by changing the trench depth in the Y direction. Thereby, channel resistance can be reduced and low on-resistance can be realized. If the i-AlGaN / i-GaN hetero interface is also formed under the gate electrode 7 (control electrode), 2DEG is generated. Therefore, in order to maintain a normally-off operation, the mesa width c is narrowed. Therefore, the mesa width c is preferably smaller than the trench depth b so as to be depleted.

FIG. 7 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention.
The nitride semiconductor device 50f shown in FIG. 7 is a GaN-HFET.

  In the nitride semiconductor element 50f, the i-AlGaN layer 3 (third semiconductor layer) is not formed under the gate electrode 7 (control electrode). The rest is the same as the nitride semiconductor device 50e shown in FIG.

  In the nitride semiconductor device 50f, since the i-AlGaN / i-GaN hetero interface is not formed under the gate electrode 7 (control electrode), 2DEG is not generated, and the normally-off operation is maintained. There is no restriction between the mesa width c and the trench depth b. The trench depth b and mesa width c can be freely set.

FIG. 8 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention.
The nitride semiconductor device 50g shown in FIG. 8 is a GaN-HFET.
In the nitride semiconductor device 50g, the back barrier layer is formed of the p-InGaN layer 8 (first semiconductor layer). The rest is the same as the nitride semiconductor device 50b shown in FIG.

In the nitride semiconductor device 50g, the p-InGaN layer 8 (first semiconductor layer) is used as the back barrier layer, so that the dopant activation rate can be increased, and the resistance of the p layer is reduced. easy. Further, since the p-InGaN layer 8 (first semiconductor layer) has a narrower band gap than the i-GaN layer 2 (second semiconductor layer), the holes are quickly formed into the p-InGaN layer 8 (first semiconductor layer). The discharge resistance can be reduced, and a high avalanche resistance and high reliability can be obtained.
By connecting the p-InGaN layer 8 (first semiconductor layer) to the source electrode 4 (first main electrode), holes can be quickly discharged. Thereby, a high avalanche resistance can be realized.

FIG. 9 is a schematic view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention.
4A is a schematic cross-sectional view, and FIGS. 2B and 2C are conceptual diagrams showing changes in the depth direction of the impurity concentration.
In FIGS. 5B and 5C, the vertical axis represents depth and the horizontal axis represents impurity concentration.
The nitride semiconductor device 50h shown in FIG. 5A is a GaN-HFET.

  In the nitride semiconductor element 50h, the impurity concentration of the p-GaN layer 1 (first semiconductor layer) varies in the depth direction, as shown in FIGS. The rest is the same as the nitride semiconductor device 50b shown in FIG.

  If the concentration is high near the i-GaN layer 2 (second semiconductor layer), the channel mobility tends to decrease. Therefore, the concentration is low at the portion close to the channel, and the concentration is increased by increasing the concentration at a distant portion. The average concentration of the p-GaN layer 1 (first semiconductor layer) can be increased while keeping the degree high. As a result, the range in which the gate threshold voltage can be controlled is widened, and the hole discharge resistance can be reduced.

  The impurity profile can be implemented even if it changes continuously as shown in FIG. 5B or changes stepwise as shown in FIG. Impurity dopants can be implemented by using dopants such as Mg, Mn, C, and Zn.

FIG. 10 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention.
The nitride semiconductor device 50i shown in FIG. 10 is a GaN-HFET.

In the nitride semiconductor device 50 i, an i-AlGaN / i-GaN heterostructure is formed on the p-Si substrate 10 via the AlN / GaN buffer layer 9. The rest is the same as the nitride semiconductor device 50b shown in FIG.
By using the p-Si substrate 10 as a support substrate, it is possible to create an element with a large diameter.

FIG. 11 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention.
The nitride semiconductor device 50j shown in FIG. 11 is a GaN-HFET.

  In the nitride semiconductor element 50j, an i-AlGaN / i-GaN heterostructure is formed on the p-Si substrate 10 via the AlN / GaN buffer layer 9. Further, a back electrode 11 is formed on the p-Si substrate 10 on the surface opposite to the AlN / GaN buffer layer 9. The back electrode 11 is electrically connected to the source electrode 4 (first main electrode). The rest is the same as the nitride semiconductor element 50i shown in FIG.

  By using the p-Si substrate 10 as a support substrate, it is possible to create an element with a large diameter. Further, since the back electrode 11 is electrically connected to the source electrode 4 (first main electrode), holes can be discharged through the p-Si substrate 10. Further, by connecting the p-Si substrate 10 to the source electrode 4 (first main electrode) via the back electrode 11, it becomes a field plate (FP) electrode, and an electric field between the gate and the drain is obtained. The distribution approaches flat. Thereby, high breakdown voltage and high reliability can be obtained.

  Also, a high avalanche resistance can be realized by positively causing an avalanche breakdown between the drain electrode 5 and the p-Si substrate 10 and allowing the holes to flow into the p-Si substrate 10 promptly. .

  In addition, as shown in FIG. 12, the sum t of the thicknesses of the p-GaN layer 1 (first semiconductor layer) and the i-GaN layer 2 (second semiconductor layer) is expressed as a gate-drain distance L. By making it smaller than this, an avalanche breakdown occurs between the drain electrode 5 (second main electrode) and the p-Si substrate 10, and a high avalanche resistance can be realized.

FIG. 13 is a schematic plan view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention.
The nitride semiconductor device 50k shown in FIG. 13 is a GaN-HFET.

  As shown in the figure, the plane of the paper is an XY plane, and the direction parallel to the source electrode 4 (first main electrode), the drain electrode 5 (second main electrode), and the gate electrode 7 (control electrode) is set. The direction from the back of the sheet perpendicular to the Y axis and the XY plane to the front is the Z axis, and the direction perpendicular to the Y axis and the Z axis is the X axis.

In the nitride semiconductor device 50k, the planar shape of the gate electrode 7 (control electrode) is a comb shape. The rest is the same as the nitride semiconductor device 50b shown in FIG.
By making the planar shape of the gate electrode 7 (control electrode) comb, the short channel effect can be suppressed, the gate length can be shortened, and a low on-resistance can be realized. By lengthening the comb tooth portion in the X direction, the shielding effect is enhanced and the gate length is easily shortened. For this reason, as shown in FIG. 14, it is desirable that the tooth length e in the X direction is larger than the tooth distance d in the Y direction.

FIG. 15 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention.
The nitride semiconductor device 50l shown in FIG. 15 is a GaN-HFET.

  In the nitride semiconductor device 50l, the gate insulating film 26 (insulating film) has a two-layer structure of a SiNx film 26b and an AlOx film 26a. The rest is the same as the nitride semiconductor device 50b shown in FIG.

  The gate insulating film 26 (insulating film) having a two-layer structure of the SiNx film 26b and the AlOx film 26a can reduce the gate leakage current while keeping the interface state density low. By forming an interface with the nitride film instead of the oxide film on the i-AlGaN layer 3 or the GaN layer 2, the interface state density can be lowered. By forming the AlOx film 26a having a large band gap, it becomes difficult for electrons to flow into the gate electrode 7 (control electrode), and the gate leakage current can be reduced. Although FIG. 15 shows the case where SiNx is used, the present invention can also be implemented using other nitride films such as AlN.

FIG. 16 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention.
The nitride semiconductor device 50m shown in FIG. 16 is a GaN-HFET.

  In the nitride semiconductor device 50m, the gate insulating film 26 (insulating film) has a three-layer structure in which an HfOx film 26c is further sandwiched between the SiNx film 26b and the AlOx film 26a. The rest is the same as the nitride semiconductor device 50b shown in FIG.

By using the high dielectric HfOx film 26c, the gate capacitance can be increased and the electron density of the inversion channel generated at the MIS gate interface can be increased. Thereby, channel resistance can be reduced and low on-resistance can be realized.
Although the high dielectric film has a small band gap, the gate leakage current can be kept low because the AlOx film 26a is formed. In the drawing, the case where HfOx is used is shown, but the present invention can also be implemented using other high dielectric films such as ZrO and TaOx.

Here, returning to FIG. 2 again, the nitride semiconductor device 50b shown in FIG. 2 will be described.
In the nitride semiconductor device 50b, the gate length and the thickness of the i-GaN layer 2 (second semiconductor layer) can be selected.
For example, as shown in FIG. 17, the thickness f of the i-GaN layer 2 (second semiconductor layer) can be made smaller than the gate length a. Thereby, a low on-resistance can be realized by suppressing the short channel effect and shortening the gate length a.

  Further, the nitride semiconductor device 50d having the trench gate structure shown in FIG. 5 will be described. As shown in FIG. 18, the thickness h of the i-GaN layer 2 (second semiconductor layer) remaining after the etching is as follows. It is desirable to be smaller than the gate length a. Thereby, a low on-resistance can be realized by suppressing the short channel effect and shortening the gate length a.

FIG. 19 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention.
The nitride semiconductor device 50n shown in FIG. 19 is a GaN-HFET.

  In nitride semiconductor device 50n, field insulating film 12 is formed on gate insulating film 6 (insulating film), and gate field plate (FP) electrode electrically connected to gate electrode 7 (control electrode) thereon. 13 is formed. The rest is the same as the nitride semiconductor device 50b shown in FIG.

  By adopting such a structure, the nitride semiconductor device 50n can have high breakdown voltage, low on-resistance, and high reliability. Further, by forming the gate FP electrode 13, electric field concentration at the end of the gate electrode 7 (control electrode) can be suppressed by the shielding effect. Thereby, a high withstand voltage is obtained by approaching a flat electric field distribution.

When a high voltage is applied, a current collapse phenomenon occurs in which the on-resistance increases because electrons accelerated by the electric field at the gate end are trapped at the passivation interface or crystal defects. For this reason, by forming the gate FP electrode 13, the electric field at the gate end is reduced, and the current collapse phenomenon does not occur, thereby realizing a low on-resistance.
Further, since the impact ionization is difficult to occur by suppressing the electric field, there is a problem that the insulating property is deteriorated by the holes generated by the impact ionization jumping into the gate insulating film 6 (insulating film) or the field insulating film 12. And high reliability is obtained.

FIG. 20 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention.
The nitride semiconductor device 50o illustrated in FIG. 20 is a GaN-HFET.

  In nitride semiconductor device 50o, field insulating film 14 is formed on field insulating film 12, and a source electrically connected to source electrode 4 (first main electrode) so as to cover gate FP electrode 13 is further provided. An FP electrode 15 is formed. The rest is the same as the nitride semiconductor device 50n shown in FIG.

  By adopting such a structure, the nitride semiconductor device 50o has a further flat electric field distribution, and an element having higher breakdown voltage, lower on-resistance, and higher reliability can be realized.

FIG. 21 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention.
The nitride semiconductor device 50p shown in FIG. 21 is a GaN-HFET.

  In the nitride semiconductor element 50p, the buried p-GaN layer 16 is selectively formed in the i-GaN layer 2 (second semiconductor layer) under the gate electrode 7 (control electrode). The rest is the same as the nitride semiconductor device 50b shown in FIG.

By adopting such a structure, in the nitride semiconductor device 50p, the short channel effect is suppressed and a low on-resistance can be obtained as in the case where the trench gate structure is formed. And since it becomes a flat channel without using etching, high channel mobility is easy to be obtained.
The buried p-GaN layer 16 can be formed by selective growth after etching or ion implantation.

(Second Embodiment)
FIG. 22 is a schematic cross-sectional view illustrating the configuration of a nitride semiconductor device according to the second embodiment of the invention.
The nitride semiconductor device 60a shown in FIG. 22 is a GaN-HSBD (heterojunction Schottky barrier diode).

  In the nitride semiconductor device 60a, the i-GaN layer 2 is formed on the p-GaN layer 1, and the i-AlGaN layer 3 is selectively formed thereon. Furthermore, an insulating film 22 is formed so as to cover a part of the i-AlGaN layer 3 and the i-GaN layer 2. In addition, the anode electrode 17 is provided so as to cover the i-GaN layer 2 in a region where the i-AlGaN layer 3 is not formed, the insulating film 22, and a part of the i-AlGaN layer 3 via the insulating film 22. Is formed. A cathode electrode 18 is formed on the i-AlGaN layer 3.

The anode electrode 17 forms a Schottky junction 19 at a portion in contact with the i-GaN layer 2. The cathode electrode 18 forms an ohmic contact with the i-AlGaN layer 3. Since the i-AlGaN layer 3 is formed between the anode electrode 17 and the cathode electrode 18, 2DEG is generated and low resistance is obtained.
By forming the p-GaN layer 1 under the i-GaN layer 2, the potential distribution in the Schottky junction can be controlled and the reverse leakage current can be reduced.

FIG. 23 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the second embodiment of the invention.
The nitride semiconductor device 60b shown in FIG. 23 is GaN-HSBD.

  In the nitride semiconductor element 60b, the anode electrode 17 is electrically connected to the p-GaN layer 1 through the contact plug 27. The rest is the same as the nitride semiconductor device 60a shown in FIG.

The anode electrode 17 (contact plug 27) forms a Schottky junction 19 at a portion in contact with the i-GaN layer 2. With such a structure, a high avalanche breakdown voltage can be realized in the nitride semiconductor element 60b.
FIG. 23 shows a structure in which the p-GaN layer 1 and the anode electrode 17 are connected by etching from the surface, but the same effect can be obtained if they are electrically connected anywhere in the device.

Although the description has been made with the combination of AlGaN / GaN, the present invention can also be implemented with a combination of GaN / InGaN or AlN / AlGaN.
Although the substrate material for forming the AlGaN / GaN heterostructure is not particularly described, the present invention does not depend on the substrate material such as the sapphire substrate, the SiC substrate, or the Si substrate, and is not limited to conductivity or insulation. It can be implemented.
Although the embodiments of the present invention have been described using a simple AlGaN / GaN heterostructure, a lateral HFET such as a GaN / AlGaN / GaN heterostructure or an AlGaN / AlN / GaN heterostructure is configured. It can be implemented in the device.
Moreover, although it demonstrated using undoped AlGaN, it can implement also using n-type doped AlGaN.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples, and all other modifications that can be easily considered by those skilled in the art can be applied. For example, as to the specific configuration of each element constituting the nitride semiconductor element, the present invention is similarly implemented by appropriately selecting from a well-known range by those skilled in the art, as long as the same effect can be obtained. It is included in the scope of the invention.
Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, all nitride semiconductor elements that can be implemented by those skilled in the art based on the nitride semiconductor elements described above as the embodiments of the present invention are included in the present invention as long as they include the gist of the present invention. Belongs to the range.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

1 is a schematic cross-sectional view illustrating the configuration of a nitride semiconductor device according to a first embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention. FIG. 5 is a schematic cross-sectional view illustrating the configuration of the nitride semiconductor device illustrated in FIG. 4. FIG. 6 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention. FIG. 5 is a schematic view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention. FIG. 12 is a schematic cross-sectional view illustrating the configuration of the nitride semiconductor device illustrated in FIG. 11. FIG. 6 is a schematic plan view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention. FIG. 14 is a schematic plan view illustrating the configuration of the nitride semiconductor device illustrated in FIG. 13. FIG. 6 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention. FIG. 3 is a schematic cross-sectional view illustrating the configuration of the nitride semiconductor element illustrated in FIG. 2. FIG. 6 is a schematic cross-sectional view illustrating the configuration of the nitride semiconductor device illustrated in FIG. 5. FIG. 6 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor device according to the first embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating the configuration of a nitride semiconductor device according to a second embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating another configuration of the nitride semiconductor element according to the second embodiment of the invention.

Explanation of symbols

1 p-GaN layer (first semiconductor layer)
2 i-GaN layer (second semiconductor layer)
3 i-AlGaN layer (third semiconductor layer)
4 Source electrode (first main electrode)
5 Drain electrode (second main electrode)
6 Gate insulating film (insulating film)
7 Gate electrode (control electrode)
8 p-InGaN layer 9 AlN / GaN buffer layer 10 p-Si substrate 11 Back electrode 12 First field insulating film 13 Gate field plate (FP) electrode 14 Second field insulating film 15 Source field plate (FP) electrode 16 Embedded p-GaN layer 17 Anode electrode 18 Cathode electrode 19 Schottky junction 22 Insulating film 24, 27 Contact plug 26 Gate insulating film (insulating film)
26a AlOx film 26b SiNx film 26c HfOx film 50a-50p GaN-HFET (nitride semiconductor device)
60a, 60b GaN-HSBD (nitride semiconductor device)

Claims (5)

a first semiconductor layer of a p-type nitride semiconductor;
A second semiconductor layer of an undoped nitride semiconductor provided on the first semiconductor layer;
A third semiconductor layer of an undoped or n-type nitride semiconductor selectively provided on the second semiconductor layer;
A first main electrode provided on the third semiconductor layer;
A second main electrode provided on the third semiconductor layer;
An insulating film provided on the second semiconductor layer;
A control electrode provided on the insulating film;
With
The band gap of the third semiconductor layer is larger than the band gap of the second semiconductor layer,
The nitride semiconductor device, wherein the control electrode is located between the first main electrode and the second main electrode. a first semiconductor layer of a p-type nitride semiconductor;
A second semiconductor layer of an undoped nitride semiconductor provided on the first semiconductor layer;
A third semiconductor layer of an undoped or n-type nitride semiconductor selectively provided on the second semiconductor layer;
A first main electrode provided on the third semiconductor layer and extending in a first direction;
A second main electrode provided on the third semiconductor layer and extending in a first direction;
An insulating film provided on the second semiconductor layer and the third semiconductor layer;
The first main electrode and the second main electrode are provided on the second semiconductor layer and a part of the third semiconductor layer with the insulating film interposed therebetween so as to be separated from the first main electrode and the second main electrode and extend in the first direction. Existing control electrodes;
With
The band gap of the third semiconductor layer is larger than the band gap of the second semiconductor layer,
The nitride semiconductor device, wherein the control electrode is located between the first main electrode and the second main electrode.   The nitride semiconductor element according to claim 1, wherein the first semiconductor layer is electrically connected to the first main electrode. a first semiconductor layer of a p-type nitride semiconductor;
A second semiconductor layer of an undoped nitride semiconductor provided on the first semiconductor layer;
A third semiconductor layer of an undoped or n-type nitride semiconductor selectively provided on the second semiconductor layer;
A first main electrode provided on the third semiconductor layer and extending in a first direction;
A second main electrode provided on the third semiconductor layer and extending in a first direction;
A trench groove provided in the surface of the second semiconductor layer;
An insulating film provided in the trench and on the third semiconductor layer;
The first main electrode and the second main electrode are provided on the second semiconductor layer and a part of the third semiconductor layer with the insulating film interposed therebetween so as to be separated from the first main electrode and the second main electrode. A control electrode extending in the direction;
With
The band gap of the third semiconductor layer is larger than the band gap of the second semiconductor layer,
The nitride semiconductor device, wherein the control electrode is located between the first main electrode and the second main electrode.   The depth of the trench groove in the second direction perpendicular to the main surface of the first semiconductor layer is greater than the width of the trench groove in the first direction and the third direction perpendicular to the second direction. The nitride semiconductor device according to claim 4, wherein the nitride semiconductor device is also large.

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