WO2013008414A1 - Rectifier device - Google Patents

Rectifier device Download PDF

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Publication number
WO2013008414A1
WO2013008414A1 PCT/JP2012/004319 JP2012004319W WO2013008414A1 WO 2013008414 A1 WO2013008414 A1 WO 2013008414A1 JP 2012004319 W JP2012004319 W JP 2012004319W WO 2013008414 A1 WO2013008414 A1 WO 2013008414A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor layer
substrate
electrode
nitride semiconductor
anode
Prior art date
Application number
PCT/JP2012/004319
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French (fr)
Japanese (ja)
Inventor
文智 井腰
真吾 橋詰
優人 山際
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パナソニック株式会社
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Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Publication of WO2013008414A1 publication Critical patent/WO2013008414A1/en

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Definitions

  • the present invention relates to a rectifier using a nitride semiconductor, and more particularly to a rectifier applicable to a power device used in a power supply circuit or the like.
  • a nitride semiconductor typified by gallium nitride (GaN) is a wide gap semiconductor.
  • GaN gallium nitride
  • AlN aluminum nitride
  • Nitride semiconductors have a feature that a breakdown electric field is large and a saturation drift velocity of electrons is large compared to a compound semiconductor such as gallium arsenide (GaAs) or a silicon (Si) semiconductor.
  • GaAs gallium arsenide
  • Si silicon
  • the sheet carrier concentration of 2DEG is 1 ⁇ 10 13 cm ⁇ 2 or more even when undoped.
  • a diode and a heterojunction field effect transistor (HFET) having a large current density are used. Can be realized.
  • HFET heterojunction field effect transistor
  • One of the diodes used as power devices is a Schottky diode.
  • Schottky diodes using an AlGaN / GaN heterostructure have been developed as GaN-based diodes. Since the Schottky diode using the AlGaN / GaN heterostructure uses 2DEG generated at the interface between the undoped AlGaN layer and the undoped GaN layer as a channel, it can operate with a low resistance and a large current.
  • FIG. 4 is a conceptual diagram showing a configuration of a field effect transistor (GaN-HFET) which is a nitride semiconductor element described in Patent Document 1.
  • GaN-HFET field effect transistor
  • an AlN buffer layer 302 a P-type GaN layer 303, an undoped GaN layer 304, and an AlGaN layer 305 are stacked in this order on an N + type SiC substrate 301.
  • a source electrode 306, a drain electrode 307, and a gate electrode 308 are formed on the AlGaN layer 305. Then, the source electrode 306 penetrates to the N + type SiC substrate 301, whereby the P type GaN layer 303 and the N + type SiC substrate 301 are connected to the source electrode 306.
  • Patent Document 1 for reducing the current collapse of a transistor is a method related to a GaN-based field effect transistor.
  • a field effect transistor having a rectifying action by a PN junction current is transported mainly by minority carriers.
  • the Schottky diode has a feature that the forward voltage drop is low and the switching speed is fast, while the reverse leakage current is large and the reverse withstand voltage is low.
  • GaN-based field effect transistors and GaN-based Schottky diodes are different devices
  • rectification using GaN-based field-effect transistors is a method for reducing current collapse of rectifiers using GaN-based Schottky diodes.
  • the method of reducing the current collapse of the device cannot be used as it is, and another method has to be studied.
  • An object of the present invention is to solve the above-described problem and to realize a rectifier with reduced current collapse.
  • a rectifier includes a first nitride semiconductor layer formed over a main surface of a substrate, and the first nitride semiconductor layer formed over the first nitride semiconductor layer. And a second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer, and having a channel in which electrons travel in a direction parallel to the main surface of the substrate.
  • a cathode electrode that is in ohmic contact with the body and a substrate electrode formed on the back surface of the substrate are provided, and the substrate electrode is grounded to a potential of 0 V or more.
  • the present inventors have found that a plurality of substrate grounding methods are effective for reducing current collapse in a GaN-based Schottky diode. According to this configuration, it is possible to alleviate electric field concentration to the anode electrode end by spatially expanding how the electric field is applied from the cathode electrode to the anode electrode end. In the rectifier using a GaN-based Schottky diode, A rectifier with reduced current collapse can be realized.
  • the substrate electrode is preferably connected so as to have substantially the same potential as the anode electrode.
  • a GaN-based Schottky diode it is effective not only to directly contact the anode electrode with the substrate by the anode recess structure, but also to connect the anode electrode to the substrate by wiring or the like in order to reduce current collapse. According to this configuration, it is possible to provide a rectifier with reduced current collapse, because the anode electrode and the substrate electrode have the same potential.
  • the substrate electrode is preferably connected so as to have substantially the same potential as the cathode electrode.
  • a GaN-based Schottky diode it is effective not only to directly contact the cathode electrode with the substrate by the cathode recess structure, but also to connect the cathode electrode to the substrate by wiring or the like in order to reduce current collapse.
  • the cathode electrode and the substrate electrode have the same potential, so that a rectifier with reduced current collapse can be provided.
  • the substrate electrode is preferably connected so as to have substantially the same potential as the ground. Thereby, the current collapse is reduced by grounding the substrate electrode.
  • the substrate electrode may be a lead frame.
  • the substrate electrode formed on the back surface of the substrate is completed simply by die-bonding a chip provided with a rectifier to the lead frame.
  • the semiconductor layer stack is preferably formed by alternately stacking a plurality of the first nitride semiconductor layers and the second nitride semiconductor layers.
  • the rectifier with reduced current collapse can be realized.
  • a rectifier with reduced current collapse can be realized.
  • FIG. 1A is a plan view showing a configuration of a rectifier according to the first embodiment.
  • FIG. 1B is a cross-sectional view illustrating the configuration of the rectifier according to the first embodiment.
  • FIG. 1C is a plan view showing the configuration of the rectifier according to the first embodiment.
  • FIG. 1D is a cross-sectional view illustrating the configuration of the rectifier according to the first embodiment.
  • FIG. 1E is a plan view showing the configuration of the rectifier according to the first embodiment.
  • FIG. 1F is a plan view showing the configuration of the rectifier according to the first embodiment.
  • FIG. 2A is a plan view showing a configuration of a rectifier according to the second embodiment.
  • FIG. 2B is a cross-sectional view illustrating a configuration of a rectifier according to the second embodiment.
  • FIG. 2C is a plan view showing the configuration of the rectifier according to the second embodiment.
  • FIG. 2D is a cross-sectional view illustrating a configuration of a rectifier according to the second embodiment.
  • FIG. 2E is a plan view showing the configuration of the rectifier according to the second embodiment.
  • FIG. 2F is a plan view showing the configuration of the rectifier according to the second embodiment.
  • FIG. 3A is a plan view illustrating a configuration of a rectifying device according to a third embodiment.
  • FIG. 3B is a cross-sectional view showing the configuration of the rectifier according to the third embodiment.
  • FIG. 3C is a plan view showing the configuration of the rectifier according to the third embodiment.
  • FIG. 3D is a cross-sectional view illustrating a configuration of a rectifier according to the third embodiment.
  • FIG. 3E is a plan view showing the configuration of the rectifier according to the third embodiment.
  • FIG. 4 is a cross-sectional view showing a configuration of a nitride semiconductor device according to the prior art.
  • FIG. 1A to 1F are conceptual diagrams showing the configuration of the rectifier according to the first embodiment.
  • FIG. 1A and FIG. 1B are conceptual diagrams showing the configuration of a single semiconductor layer laminate and an anode grounded rectifier.
  • FIGS. 1C and 1D are a plurality of semiconductor layer laminates and an anode grounded rectifier.
  • FIG. 1E is a plan view showing the configuration of a rectifier that is anode-grounded by wiring
  • FIG. 1F is a plan view showing the configuration of the rectifier that is anode-grounded by a lead frame.
  • anode grounding means that in the rectifier, the anode electrode is connected so as to have substantially the same potential as the substrate (or substrate electrode).
  • “connected so as to have substantially the same potential” means that they are connected with a conductive material such as a copper wire, an aluminum wire, or a conductive adhesive.
  • a rectifying device 100 includes a chip 101 of a rectifying device composed of one semiconductor layer stack, a plurality of anode electrodes 102a, a plurality of cathode electrodes 103a, and an anode pad. 104, a cathode pad 105, and a protective film 106 are provided.
  • the anode pad 104 and the cathode pad 105 are connected to the anode electrode 102a and the cathode electrode 103a, respectively.
  • a protective film 106 is formed on the chip surface so as to cover the chip 101, the anode electrode 102a, the cathode electrode 103a, the anode pad 104, and the cathode pad 105.
  • FIG. 1B is a cross-sectional view taken along line A-A ′ of rectifier 100 shown in FIG. 1A.
  • a buffer layer 108, a first nitride semiconductor layer 109, and a second nitride semiconductor layer 110 are sequentially formed on the substrate 107.
  • a channel (not shown) made of 2DEG is formed in the vicinity of the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110.
  • the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 correspond to a semiconductor layer stack according to the present invention.
  • a substrate electrode (not shown) (for example, a lead frame described later) is formed on the back surface of the substrate 107, and the substrate electrode is grounded to a potential of 0 V or more (for example, ground).
  • a potential of 0 V or more for example, ground.
  • “grounded to a potential of 0 V or higher” means being connected to a potential that can be substantially called ground.
  • “grounded” not only means “grounded” but also means “grounded” for the first time when the rectifier is used as an electronic component.
  • a plurality of anode electrodes 102a and cathode electrodes 103a are alternately arranged at intervals. Yes.
  • the anode electrode 102 a is formed to a predetermined depth of the substrate 107 through the second nitride semiconductor layer 110, the first nitride semiconductor layer 109, and the buffer layer 108.
  • the cathode electrode 103 a is formed to penetrate the second nitride semiconductor layer 110 to a predetermined depth of the first nitride semiconductor layer 109.
  • the anode electrode 102a and the cathode electrode 103a may not be plural but one each.
  • the surface of the anode electrode 102a, the surface of the cathode electrode 103a, and the surface of the second nitride semiconductor layer 110 between the anode electrode 102a and the cathode electrode 103a are protected from silicon nitride (SiN) or the like.
  • the film 106 is covered.
  • the anode electrode 102 a is formed in an anode recess that reaches the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer 109. And Schottky contact with the second nitride semiconductor layer 110 (channel). Thereby, the anode electrode 102a is in direct contact with the substrate 107, and anode grounding is realized in which the anode electrode 102a and the substrate 107 have substantially the same potential.
  • the anode electrode 102a may be a stacked body made of nickel (Ni) and gold (Au).
  • the cathode electrode 103a is formed in a cathode recess that does not reach the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer. 109 and the second nitride semiconductor layer 110 (channel) are in ohmic contact.
  • the cathode electrode 103a may be formed of a material containing titanium (Ti) or aluminum (Al) that is easily in ohmic contact with 2DEG. For example, an alloy of Ti and Al may be used.
  • the rectifying device 100 of this embodiment may be configured by a chip 111 of a rectifying device including a plurality of semiconductor layer stacks instead of one semiconductor layer stack.
  • the rectifying device 100 includes a plurality of semiconductor layer stacks, an anode electrode 102a, a plurality of cathode electrodes 103a, an anode pad 104, a cathode pad 105, and a protective film 106.
  • the anode pad 104 and the cathode pad 105 are connected to the anode electrode 102a and the cathode electrode 103a, respectively.
  • a protective film 106 is formed on the chip surface so as to cover the chip 101, the anode electrode 102a, the cathode electrode 103a, the anode pad 104, and the cathode pad 105.
  • the plurality of semiconductor layer stacks have a configuration in which the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 are stacked in three cycles.
  • FIG. 1D is a cross-sectional view taken along line B-B ′ of the rectifier 100 shown in FIG. 1C.
  • a buffer layer 108, a first nitride semiconductor layer 109, and a second nitride semiconductor layer 110 are alternately and sequentially formed on the substrate 107 in three cycles.
  • a channel (not shown) made of 2DEG is formed in the vicinity of the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110.
  • a substrate electrode (not shown) (for example, a lead frame described later) is formed on the back surface of the substrate 107, and the substrate electrode is grounded to a potential of 0 V or more (for example, ground).
  • anode electrode 102a and cathode electrodes 103a are alternately arranged at intervals.
  • the anode electrode 102a is formed to a predetermined depth of the substrate 107 through the second nitride semiconductor layer 110, the first nitride semiconductor layer 109, and the buffer layer 108, which are formed by repeating three cycles. Yes. Thereby, the anode electrode 102a is in direct contact with the substrate 107, and anode grounding is realized in which the anode electrode 102a and the substrate 107 have substantially the same potential.
  • the cathode electrode 103 a is formed to penetrate the second nitride semiconductor layer 110 to a predetermined depth of the first nitride semiconductor layer 109. Note that the anode electrode 102a and the cathode electrode 103a may not be plural but one each.
  • the surface of the anode electrode 102a, the surface of the cathode electrode 103a, and the surface of the second nitride semiconductor layer 110 between the anode electrode 102a and the cathode electrode 103a are protected from silicon nitride (SiN) or the like.
  • the film 106 is covered.
  • the anode electrode 102 a is formed in an anode recess that reaches the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer 109. And Schottky contact with the second nitride semiconductor layer 110 (channel).
  • the anode electrode 102a may be a laminate made of nickel (Ni) and gold (Au).
  • the cathode electrode 103a is formed in a cathode recess that does not reach the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer. 109 and the second nitride semiconductor layer 110 (channel) are in ohmic contact.
  • the cathode electrode 103a may be formed of a material containing titanium (Ti) or aluminum (Al) that is easily in ohmic contact with 2DEG. For example, an alloy of Ti and Al may be used.
  • the anode electrode 102a and the substrate 107 can be set to the same potential, and the application of an electric field from the cathode electrode 103a to the end of the anode electrode 102a is spatially widened to thereby increase the anode electrode.
  • the electric field concentration up to the end of 102a can be relaxed, and the current collapse of the rectifier 100 can be reduced.
  • the anode electrode 102a is formed in the anode recess reaching the substrate 107, whereby the anode electrode 102a and the substrate 107 are directly connected.
  • the configuration may be such that the anode pad 104 and the anode terminal 114 a formed on the substrate 107 are connected to the substrate 107.
  • a chip 101 provided with a rectifier constituted by a single semiconductor layer stack (or a chip 111 provided with a rectifier constituted by a plurality of semiconductor layer laminates), for example, a TO- A die frame is bonded to a lead frame 112 made of a 220 type package.
  • the lead frame 112 corresponds to a substrate electrode according to the present invention, that is, an electrode formed on the back surface of the substrate 107.
  • the lead frame 112 is formed with anode terminals 114a and 114b and a cathode terminal 115a.
  • the anode pad 104 and the anode terminal 114a are connected by a wire 113a made of Al, and the cathode pad 105 and the cathode terminal 115a are connected by a wire 113b.
  • the anode terminal 114 a is in contact with the back surface of the substrate 107 and is also a substrate electrode formed on the back surface of the substrate 107.
  • the anode pad 104 and the substrate 107 may be short-circuited by wiring.
  • the anode electrode 102a can be set to the same potential as the anode terminal 114a (that is, the substrate electrode) via the anode pad 104, and the application of an electric field from the cathode electrode 103a to the end of the anode electrode 102a is spatially applied. It is possible to alleviate the electric field concentration up to the end of the anode electrode 102a, and the current collapse of the rectifier 100 can be reduced.
  • a chip 101 including a rectifier configured by one semiconductor layer stack (or a chip 111 including a rectifier configured by a plurality of semiconductor layer stacks), for example, A die bond is made to the lead frame 112 made of a TO-220 type package.
  • the lead frame 112 corresponds to a substrate electrode according to the present invention.
  • the lead frame 112 is formed with anode terminals 114a and 114b and a cathode terminal 115a.
  • the anode terminals 114a and 114b are integrally formed and are electrically connected.
  • the anode pad 104 and the anode terminal 114b are connected by a wire 113c made of Al, and the cathode pad 105 and the cathode terminal 115a are connected by a wire 113b.
  • the anode terminals 114 a and 114 b are in contact with the back surface of the substrate 107 as the lead frame 112, and are also substrate electrodes formed on the back surface of the substrate 107.
  • the anode pad 104 and the substrate 107 may be short-circuited by the lead frame 112.
  • the anode electrode 102a can be set to the same potential as the lead frame 112 (that is, the substrate electrode) via the anode pad 104 and the anode terminal 114b, and an electric field is applied from the cathode electrode 103a to the end of the anode electrode 102a.
  • the electric field concentration to the end of the anode electrode 102a can be relaxed, and the current collapse of the rectifying device 100 can be further reduced.
  • the rectifier according to this embodiment is different from the rectifier according to the first embodiment in that the potential of the substrate (or substrate electrode) is substantially the same as the potential of the cathode electrode, not the potential of the anode electrode. There is a point.
  • FIGS. 2A to 2F are conceptual diagrams showing the configuration of the rectifier according to the second embodiment.
  • FIGS. 2A and 2B are conceptual diagrams showing the configuration of a rectifier with a single semiconductor layer stack and a cathode ground
  • FIGS. 2C and 2D are rectifiers with a plurality of semiconductor layer stacks and a cathode ground.
  • FIG. 2E is a plan view showing the configuration of a rectifier that is cathode-grounded by wiring
  • FIG. 2F is a plan view showing the configuration of the rectifier that is cathode-grounded by a lead frame.
  • the cathode ground means that in the rectifier, the cathode electrode is connected so as to have substantially the same potential as the substrate (or substrate electrode).
  • the rectifying device 100 includes a rectifying device chip 101 composed of one semiconductor layer stack, a plurality of anode electrodes 102b, a plurality of cathode electrodes 103b, and an anode pad. 104, a cathode pad 105, and a protective film 106 are provided.
  • the anode pad 104 and the cathode pad 105 are connected to the anode electrode 102b and the cathode electrode 103b, respectively.
  • a protective film 106 is formed on the chip surface so as to cover the chip 101, the anode electrode 102b, the cathode electrode 103b, the anode pad 104, and the cathode pad 105.
  • FIG. 2B is a cross-sectional view taken along line C-C ′ of the rectifier 100 shown in FIG. 2A.
  • a buffer layer 108, a first nitride semiconductor layer 109, and a second nitride semiconductor layer 110 are sequentially formed on the substrate 107.
  • a channel (not shown) made of 2DEG is formed in the vicinity of the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110.
  • the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 correspond to a semiconductor layer stack according to the present invention.
  • a substrate electrode (not shown) (for example, a lead frame described later) is formed on the back surface of the substrate 107, and the substrate electrode is grounded to a potential of 0 V or more (for example, ground).
  • a plurality of anode electrodes 102b and cathode electrodes 103b are alternately arranged at intervals. Yes.
  • the anode electrode 102 b is formed to penetrate the second nitride semiconductor layer 110 to a predetermined depth of the first nitride semiconductor layer 109.
  • the cathode electrode 103 b is formed to a predetermined depth of the substrate 107 through the second nitride semiconductor layer 110, the first nitride semiconductor layer 109, and the buffer layer 108.
  • the anode electrode 102b and the cathode electrode 103b may not be plural but one each.
  • the surface of the anode electrode 102b, the surface of the cathode electrode 103b, and the surface of the second nitride semiconductor layer 110 between the anode electrode 102b and the cathode electrode 103b are protected from silicon nitride (SiN) or the like.
  • the film 106 is covered.
  • the anode electrode 102b is formed in an anode recess that does not reach the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 (channel) are in Schottky contact.
  • the anode electrode 102b may be a laminate made of nickel (Ni) and gold (Au).
  • the cathode electrode 103 b is formed in a cathode recess that reaches the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer 109. And in ohmic contact with the second nitride semiconductor layer 110 (channel). As a result, the cathode electrode 103b is in direct contact with the substrate 107, and cathode grounding is realized in which the cathode electrode 103b and the substrate 107 have substantially the same potential.
  • the cathode electrode 103b may be formed of a material containing titanium (Ti) or aluminum (Al) that is easily in ohmic contact with 2DEG, for example, an alloy of Ti and Al.
  • the rectifying device 100 of the present embodiment may be configured by a chip 111 of a rectifying device including a plurality of semiconductor layer stacks instead of one semiconductor layer stack.
  • the rectifying device 100 includes a plurality of semiconductor layer stacks, a plurality of anode electrodes 102b, a plurality of cathode electrodes 103b, an anode pad 104, a cathode pad 105, and a protective film 106. .
  • the anode pad 104 and the cathode pad 105 are connected to the anode electrode 102b and the cathode electrode 103b, respectively.
  • a protective film 106 is formed on the chip surface so as to cover the chip 101, the anode electrode 102b, the cathode electrode 103b, the anode pad 104, and the cathode pad 105.
  • the plurality of semiconductor layer stacks have a configuration in which the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 are stacked in three cycles.
  • FIG. 2D is a cross-sectional view taken along the line D-D ′ of the rectifier 100 shown in FIG. 2C.
  • the buffer layer 108, the first nitride semiconductor layer 109, and the second nitride semiconductor layer 110 are alternately and sequentially formed on the substrate 107 in three cycles.
  • a channel (not shown) made of 2DEG is formed in the vicinity of the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110.
  • a substrate electrode (not shown) (for example, a lead frame described later) is formed on the back surface of the substrate 107, and the substrate electrode is grounded to a potential of 0 V or more (for example, ground).
  • a plurality of anode electrodes 102b and cathode electrodes 103b are alternately arranged at intervals.
  • the anode electrode 102 b is formed to penetrate the second nitride semiconductor layer 110 to a predetermined depth of the first nitride semiconductor layer 109.
  • the cathode electrode 103b is formed to a predetermined depth of the substrate 107 through the second nitride semiconductor layer 110, the first nitride semiconductor layer 109, and the buffer layer 108, which are formed by repeating three cycles. Yes.
  • the cathode electrode 103b is in direct contact with the substrate 107, and cathode grounding is realized in which the cathode electrode 103b and the substrate 107 have substantially the same potential.
  • the anode electrode 102b and the cathode electrode 103b may not be plural but one each.
  • the surface of the anode electrode 102b, the surface of the cathode electrode 103b, and the surface of the second nitride semiconductor layer 110 between the anode electrode 102b and the cathode electrode 103b are protected from silicon nitride (SiN) or the like.
  • the film 106 is covered.
  • the anode electrode 102b is formed in an anode recess that does not reach the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 (channel) are in Schottky contact.
  • the anode electrode 102b may be a laminate made of nickel (Ni) and gold (Au).
  • the cathode electrode 103 b is formed in a cathode recess that reaches the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer 109. And in ohmic contact with the second nitride semiconductor layer 110 (channel).
  • the cathode electrode 103b may be formed of a material containing titanium (Ti), aluminum (Al), or the like that is easily in ohmic contact with 2DEG, for example, an alloy of Ti and Al.
  • the cathode electrode 103b and the substrate 107 can be set to the same potential, and the application of an electric field from the cathode electrode 103a to the end of the anode electrode 102a is spatially widened to thereby increase the anode electrode.
  • the electric field concentration up to the end of 102a can be relaxed, and the current collapse of the rectifier 100 can be reduced.
  • the cathode electrode 103b is formed in the cathode recess reaching the substrate 107, so that the cathode electrode 103b and the substrate 107 are directly connected.
  • the configuration may be such that the cathode pad 105 and the cathode terminal 115 b formed on the substrate 107 are connected to the substrate 107.
  • a chip 101 including a rectifier configured by one semiconductor layer stack is, for example, TO- A die frame is bonded to a lead frame 112 made of a 220 type package.
  • the lead frame 112 corresponds to a substrate electrode according to the present invention, that is, an electrode formed on the back surface of the substrate 107.
  • the lead frame 112 is formed with an anode terminal 114c and cathode terminals 115b and 115c.
  • the anode pad 104 and the anode terminal 114c are connected by a wire 113d made of Al, and the cathode pad 105 and the cathode terminal 115b are connected by a wire 113e.
  • the cathode terminal 115 b is in contact with the back surface of the substrate 107 and is also a substrate electrode formed on the back surface of the substrate 107.
  • the cathode pad 105 and the substrate 107 may be short-circuited by wiring.
  • the cathode electrode 103b can be set to the same potential as the cathode terminal 115b (that is, the substrate electrode) via the cathode pad 105, and the application of an electric field from the cathode electrode 103b to the end of the anode electrode 102b is spatially determined. It is possible to alleviate the electric field concentration up to the end of the anode electrode 102b, and the current collapse of the rectifier 100 can be reduced.
  • a chip 101 including a rectifier configured by one semiconductor layer stack (or a chip 111 including a rectifier configured by a plurality of semiconductor layer stacks) is used, for example.
  • a die bond is made to the lead frame 112 made of a TO-220 type package.
  • the lead frame 112 corresponds to a substrate electrode according to the present invention.
  • the lead frame 112 is formed with an anode terminal 114c and cathode terminals 115b and 115c.
  • the cathode terminals 115b and 115c are integrally formed and electrically connected.
  • the anode pad 104 and the anode terminal 114c are connected by a wire 113d made of Al, and the cathode pad 105 and the cathode terminal 115c are connected by a wire 113f.
  • the cathode terminals 115 b and 115 c are in contact with the back surface of the substrate 107 as the lead frame 112, and are also substrate electrodes formed on the back surface of the substrate 107.
  • the cathode pad 105 and the substrate 107 may be short-circuited by the lead frame.
  • the cathode electrode 103b can be set to the same potential as the lead frame 112 (that is, the substrate electrode) via the cathode pad 105 and the cathode terminal 115c, and an electric field is applied from the cathode electrode 103b to the end of the anode electrode 102b.
  • the cathode electrode 103b By expanding the direction spatially, it becomes possible to alleviate the electric field concentration to the end of the anode electrode 102b, and the current collapse of the rectifier 100 can be further reduced.
  • the rectifier according to this embodiment is different from the rectifier according to the first and second embodiments in that the substrate (or substrate electrode) is connected so that the potential of the substrate (or substrate electrode) is substantially the same as the ground. It is a point to be done. Note that “connected so that the potential of the substrate (or the substrate electrode) is substantially the same potential as the ground” does not only mean such a state of being “connected”, but also a rectifier. This means the state of being “connected” for the first time when the is used as an electronic component.
  • FIG. 3A to 3E are conceptual diagrams showing the configuration of the rectifier according to the third embodiment.
  • FIG. 3A and FIG. 3B are conceptual diagrams showing the configuration of a rectifier with one semiconductor layer stack and grounded.
  • FIGS. 3C and 3D are rectifiers with a plurality of semiconductor layer stacks and grounded.
  • the conceptual diagram which shows the structure of an apparatus FIG. 3E is a top view which shows the structure of the rectifier which was earth
  • the rectifier 100 includes a chip 101 of a rectifier constituted by one semiconductor layer stack, a plurality of anode electrodes 102c, a plurality of cathode electrodes 103c, and an anode pad. 104, a cathode pad 105, and a protective film 106 are provided.
  • the anode pad 104 and the cathode pad 105 are connected to the anode electrode 102c and the cathode electrode 103c, respectively.
  • a protective film 106 is formed on the chip surface so as to cover the chip 101, the anode electrode 102c, the cathode electrode 103c, the anode pad 104, and the cathode pad 105.
  • FIG. 3B is a cross-sectional view taken along line E-E ′ of rectifier 100 shown in FIG. 3A.
  • a buffer layer 108, a first nitride semiconductor layer 109, and a second nitride semiconductor layer 110 are sequentially formed on the substrate 107.
  • a channel (not shown) made of 2DEG is formed in the vicinity of the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110.
  • the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 correspond to a semiconductor layer stack according to the present invention.
  • a substrate electrode (not shown) (for example, a lead frame described later) is formed on the back surface of the substrate 107, and the substrate electrode is grounded to a potential of 0 V or more (for example, ground).
  • a plurality of anode electrodes 102c and cathode electrodes 103c are alternately arranged at intervals. Yes.
  • the anode electrode 102 c and the cathode electrode 103 c are formed to penetrate the second nitride semiconductor layer 110 to a predetermined depth of the first nitride semiconductor layer 109.
  • the anode electrode 102c and the cathode electrode 103c may not be plural but one each.
  • the surface of the anode electrode 102c, the surface of the cathode electrode 103c, and the surface of the second nitride semiconductor layer 110 between the anode electrode 102c and the cathode electrode 103c are protected from silicon nitride (SiN) or the like.
  • the film 106 is covered.
  • the anode electrode 102c is formed in an anode recess that does not reach the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 (channel) are in Schottky contact.
  • the anode electrode 102c may be a laminate made of nickel (Ni) and gold (Au).
  • the cathode electrode 103c is formed in a cathode recess that does not reach the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer. 109 and the second nitride semiconductor layer 110 (channel) are in ohmic contact.
  • the cathode electrode 103c may be formed of a material containing titanium (Ti) or aluminum (Al) that is easily in ohmic contact with 2DEG. For example, an alloy of Ti and Al may be used.
  • the rectifying device 100 of the present embodiment may be configured by a chip 111 of a rectifying device including a plurality of semiconductor layer stacks instead of one semiconductor layer stack.
  • the rectifying device 100 includes a plurality of semiconductor layer stacks, a plurality of anode electrodes 102c, a plurality of cathode electrodes 103c, an anode pad 104, a cathode pad 105, and a protective film 106. .
  • the anode pad 104 and the cathode pad 105 are connected to the anode electrode 102c and the cathode electrode 103c, respectively.
  • a protective film 106 is formed on the chip surface so as to cover the chip 101, the anode electrode 102c, the cathode electrode 103c, the anode pad 104, and the cathode pad 105.
  • the plurality of semiconductor layer stacks have a configuration in which the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 are stacked in three cycles.
  • FIG. 3D is a cross-sectional view taken along line F-F ′ of the rectifier 100 shown in FIG. 3C.
  • a buffer layer 108, a first nitride semiconductor layer 109, and a second nitride semiconductor layer 110 are alternately and sequentially formed on the substrate 107 in three cycles.
  • a channel (not shown) made of 2DEG is formed in the vicinity of the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110.
  • a substrate electrode (not shown) (for example, a lead frame described later) is formed on the back surface of the substrate 107, and the substrate electrode is grounded to a potential of 0 V or more (for example, ground).
  • a plurality of anode electrodes 102c and cathode electrodes 103c are alternately arranged at intervals. Yes.
  • the anode electrode 102 c and the cathode electrode 103 c penetrate the second nitride semiconductor layer 110 and are formed to a predetermined depth of the first nitride semiconductor layer 109.
  • the anode electrode 102c and the cathode electrode 103c may not be plural but one each.
  • the surface of the anode electrode 102c, the surface of the cathode electrode 103c, and the surface of the second nitride semiconductor layer 110 between the anode electrode 102c and the cathode electrode 103c are protected from silicon nitride (SiN) or the like.
  • the film 106 is covered.
  • the anode electrode 102c is formed in an anode recess that does not reach the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 (channel) are in Schottky contact.
  • the anode electrode 102c may be a laminate made of nickel (Ni) and gold (Au).
  • the cathode electrode 103c is formed in a cathode recess that does not reach the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer. 109 and the second nitride semiconductor layer 110 (channel) are in ohmic contact.
  • the cathode electrode 103c may be formed of a material containing titanium (Ti) or aluminum (Al) that is easily in ohmic contact with 2DEG. For example, an alloy of Ti and Al may be used.
  • the substrate electrode is grounded to a potential of 0 V or more (for example, ground). Therefore, by spatially expanding the manner in which the electric field is applied from the cathode electrode 103a to the end of the anode electrode 102a. Electric field concentration to the end of the anode electrode 102a can be relaxed, and current collapse of the rectifier 100 can be reduced.
  • a chip 101 provided with a rectifier constituted by one semiconductor layer stack is, for example, TO- A die frame is bonded to a lead frame 112 made of a 220 type package.
  • the lead frame 112 is formed with an anode terminal 114d, a cathode terminal 115d, and a ground terminal 116.
  • the ground terminal 116 is in contact with the back surface of the substrate 107 as the lead frame 112 and corresponds to the substrate electrode according to the present invention formed on the back surface of the substrate 107.
  • the anode pad 104 and the anode terminal 114d are connected by a wire 113g made of Al, and the cathode pad 105 and the cathode terminal 115d are connected by a wire 113h.
  • the substrate 107 is connected to the ground terminal 116 as an independent terminal, so that when the ground terminal 116 is grounded, an electric field is applied from the cathode electrode 103c to the anode electrode 102c end.
  • the electric field concentration to the end of the anode electrode 102c can be relaxed, and the current collapse of the rectifier 100 can be further reduced.
  • any material may be used for the anode electrode as long as it is in Schottky contact with the channel.
  • the cathode electrode may be made of any material as long as it is in ohmic contact with the channel.
  • the rectifier according to the present invention includes other embodiments realized by combining arbitrary components in the above-described embodiments, and various types conceived by those skilled in the art without departing from the gist of the present invention with respect to the embodiments. Modifications obtained by applying modifications and various devices including the rectifier according to the present invention are also included in the present invention.
  • a power supply circuit including the rectifier according to the present invention, a power device including the power supply circuit, and the like are also included in the present invention.
  • the rectifier according to the present invention is useful as a power device used for a switching power supply circuit or the like.

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Abstract

The present invention fabricates a rectifier device in which current collapse is reduced. A rectifier device (100) provided with: a semiconductor layer laminate having a first nitride semiconductor layer (109) formed on the main surface of a substrate (107), a second nitride semiconductor layer (110) formed on the first nitride semiconductor layer (109) and having a larger band gap than the first nitride semiconductor layer (109), and a channel in which electrons travel in the direction that is parallel to the main surface of the substrate (107); an anode electrode (102a) formed on the semiconductor layer laminate and coming into Schottky contact with the semiconductor layer laminate; a plurality of cathode electrodes (103a) formed on the semiconductor layer laminate with a predetermined distance from the anode electrode (102a) and coming into ohmic contact with the semiconductor layer laminate; and a substrate electrode (lead frame (112)) formed on the rear surface of the substrate (107). The substrate electrode is grounded to a potential of 0V or more.

Description

整流装置Rectifier
　本発明は、窒化物半導体を用いた整流装置に関し、特に電源回路等に用いられるパワーデバイスに適用できる整流装置に関する。 The present invention relates to a rectifier using a nitride semiconductor, and more particularly to a rectifier applicable to a power device used in a power supply circuit or the like.
　窒化ガリウム（ＧａＮ）に代表される窒化物半導体はワイドギャップ半導体であり、例えば、ＧａＮ及び窒化アルミニウム（ＡｌＮ）の室温におけるバンドギャップはそれぞれ３．４ｅＶ及び６．２ｅＶである。窒化物半導体は、絶縁破壊電界が大きいという特徴や、電子の飽和ドリフト速度が砒化ガリウム（ＧａＡｓ）等の化合物半導体又はシリコン（Ｓｉ）半導体等と比べて大きいという特長を有している。ＡｌＧａＮ／ＧａＮへテロ構造においては（０００１）面上にて自発分極及びピエゾ分極によりヘテロ界面に２次元電子ガス（２ＤＥＧ：２　Ｄｉｍｅｎｓｉｏｎａｌ　Ｅｌｅｃｔｒｏｎ　Ｇａｓ）が生じる。２ＤＥＧのシートキャリア濃度は、アンドープ時においても１×１０１３ｃｍ－２以上であり、２ＤＥＧを利用することにより、電流密度が大きいダイオード及びヘテロ接合電界効果トランジスタ（ＨＦＥＴ：Ｈｅｔｅｒｏ－ｊｕｎｃｔｉｏｎ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）を実現できる。このように、高出力化及び高耐圧化に有利な窒化物半導体を用いたパワーデバイスの研究開発が現在活発に行われている。 A nitride semiconductor typified by gallium nitride (GaN) is a wide gap semiconductor. For example, the band gaps of GaN and aluminum nitride (AlN) at room temperature are 3.4 eV and 6.2 eV, respectively. Nitride semiconductors have a feature that a breakdown electric field is large and a saturation drift velocity of electrons is large compared to a compound semiconductor such as gallium arsenide (GaAs) or a silicon (Si) semiconductor. In the AlGaN / GaN heterostructure, two-dimensional electron gas (2DEG: 2 Dimensional Electron Gas) is generated at the heterointerface due to spontaneous polarization and piezoelectric polarization on the (0001) plane. The sheet carrier concentration of 2DEG is 1 × 10 13 cm −2 or more even when undoped. By using 2DEG, a diode and a heterojunction field effect transistor (HFET) having a large current density are used. Can be realized. Thus, research and development of power devices using nitride semiconductors that are advantageous for high output and high breakdown voltage are being actively conducted.
　パワーデバイスとして用いるダイオードの１つにショットキーダイオードがある。ＧａＮ系のダイオードとしてＡｌＧａＮ／ＧａＮへテロ構造を用いたショットキーダイオードが開発されている。ＡｌＧａＮ／ＧａＮへテロ構造を用いたショットキーダイオードは、アンドープＡｌＧａＮ層とアンドープＧａＮ層との界面に発生する２ＤＥＧをチャネルとして用いるため低抵抗で且つ大電流動作が可能である。 One of the diodes used as power devices is a Schottky diode. Schottky diodes using an AlGaN / GaN heterostructure have been developed as GaN-based diodes. Since the Schottky diode using the AlGaN / GaN heterostructure uses 2DEG generated at the interface between the undoped AlGaN layer and the undoped GaN layer as a channel, it can operate with a low resistance and a large current.
　前記従来のＧａＮ系ショットキーダイオードを本発明者らが実際に作製したところ、所謂電流コラプスという現象が生じる問題があることを見出した。具体的には、高い逆方向電圧を印加した直後に順方向電圧を印加すると、逆方向電圧を印加しない場合と比較して順方向電圧が増加しオン抵抗が増大する。電流コラプスによるオン抵抗の増大は、高い逆方向電圧が印加されるＧａＮ系ショットキーダイオードにおいては重大な問題となる。この電流コラプスを抑制する技術として、例えば、ＧａＮ系電界効果トランジスタのソース電極を、導電性を有するｎ＋ＳｉＣ基板まで貫通させることで、ドレイン電極から見たときの裏面からのフィールドプレート効果により電流コラプスを低減する（低オン抵抗を実現する）という報告もある（例えば、特許文献１を参照）。 When the present inventors actually fabricated the conventional GaN-based Schottky diode, it was found that there is a problem that a phenomenon called so-called current collapse occurs. Specifically, when a forward voltage is applied immediately after a high reverse voltage is applied, the forward voltage is increased and the on-resistance is increased as compared with the case where no reverse voltage is applied. An increase in on-resistance due to current collapse becomes a serious problem in a GaN-based Schottky diode to which a high reverse voltage is applied. As a technique for suppressing this current collapse, for example, by passing the source electrode of a GaN-based field effect transistor to a conductive n + SiC substrate, the current collapse is caused by the field plate effect from the back surface when viewed from the drain electrode. There is also a report of reducing (realizing low on-resistance) (see, for example, Patent Document 1).
　図４は、特許文献１に記載の窒化物半導体素子である電界効果トランジスタ（ＧａＮ－ＨＦＥＴ）の構成を示す概念図である。図４に示すように、電界効果トランジスタ３００は、Ｎ＋型ＳｉＣ基板３０１上に、ＡｌＮバッファ層３０２、Ｐ型ＧａＮ層３０３、アンドープＧａＮ層３０４及びＡｌＧａＮ層３０５がこの順に積層されている。また、ＡｌＧａＮ層３０５上に、ソース電極３０６と、ドレイン電極３０７と、ゲート電極３０８とが形成されている。そして、ソース電極３０６がＮ＋型ＳｉＣ基板３０１まで貫通されることにより、Ｐ型ＧａＮ層３０３とＮ＋型ＳｉＣ基板３０１がソース電極３０６に接続される。 FIG. 4 is a conceptual diagram showing a configuration of a field effect transistor (GaN-HFET) which is a nitride semiconductor element described in Patent Document 1. As shown in FIG. 4, in the field effect transistor 300, an AlN buffer layer 302, a P-type GaN layer 303, an undoped GaN layer 304, and an AlGaN layer 305 are stacked in this order on an N + type SiC substrate 301. A source electrode 306, a drain electrode 307, and a gate electrode 308 are formed on the AlGaN layer 305. Then, the source electrode 306 penetrates to the N + type SiC substrate 301, whereby the P type GaN layer 303 and the N + type SiC substrate 301 are connected to the source electrode 306.
特開２００８－２５８４１９号公報JP 2008-258419 A
　特許文献１に記載された、トランジスタの電流コラプスを低減する方法は、ＧａＮ系電界効果トランジスタに関する方法である。ＰＮ接合により整流作用を有する電界効果トランジスタでは、主に少数キャリアにより電流の輸送が行われる。 The method described in Patent Document 1 for reducing the current collapse of a transistor is a method related to a GaN-based field effect transistor. In a field effect transistor having a rectifying action by a PN junction, current is transported mainly by minority carriers.
　これに対し、ショットキー接合により整流作用を有するショットキーダイオードでは、主に多数キャリアにより電流の輸送が行われる。そのため、ショットキーダイオードは、順方向の電圧降下が低くスイッチング速度が速いという特長を有する一方で、逆方向漏れ電流が大きく、逆方向耐電圧が低いという欠点を有する。 On the other hand, in a Schottky diode having a rectifying action by a Schottky junction, current is mainly transported by majority carriers. For this reason, the Schottky diode has a feature that the forward voltage drop is low and the switching speed is fast, while the reverse leakage current is large and the reverse withstand voltage is low.
　このように、ＧａＮ系電界効果トランジスタとＧａＮ系ショットキーダイオードとはデバイスが異なるため、ＧａＮ系ショットキーダイオードを用いた整流装置の電流コラプスを低減する方法として、ＧａＮ系電界効果トランジスタを用いた整流装置の電流コラプスを低減する方法をそのまま用いることはできず、別の方法を検討する必要があった。 As described above, since GaN-based field effect transistors and GaN-based Schottky diodes are different devices, rectification using GaN-based field-effect transistors is a method for reducing current collapse of rectifiers using GaN-based Schottky diodes. The method of reducing the current collapse of the device cannot be used as it is, and another method has to be studied.
　本発明は、上記の問題を解決し、電流コラプスを低減した整流装置を実現することを目的とする。 An object of the present invention is to solve the above-described problem and to realize a rectifier with reduced current collapse.
　上記課題を解決するために、本発明の一態様に係る整流装置は、基板の主面の上に形成された第１の窒化物半導体層と、該第１の窒化物半導体層の上に形成され、かつ、前記第１の窒化物半導体層に比べてバンドギャップが大きい第２の窒化物半導体層とを有し、前記基板の主面と平行な方向に電子が走行するチャネルを有する半導体層積層体と、前記半導体層積層体に形成され、前記半導体層積層体とショットキー接触するアノード電極と、前記半導体層積層体に前記アノード電極と所定の間隔をおいて形成され、前記半導体層積層体とオーミック接触するカソード電極と、前記基板の裏面に形成された基板電極とを備え、基板電極は０Ｖ以上の電位に接地される。 In order to solve the above-described problem, a rectifier according to one embodiment of the present invention includes a first nitride semiconductor layer formed over a main surface of a substrate, and the first nitride semiconductor layer formed over the first nitride semiconductor layer. And a second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer, and having a channel in which electrons travel in a direction parallel to the main surface of the substrate A laminated body, an anode electrode formed in the semiconductor layer laminated body and in Schottky contact with the semiconductor layer laminated body, and formed in the semiconductor layer laminated body at a predetermined interval from the anode electrode. A cathode electrode that is in ohmic contact with the body and a substrate electrode formed on the back surface of the substrate are provided, and the substrate electrode is grounded to a potential of 0 V or more.
　本発明者らは、ＧａＮ系ショットキーダイオードにおいて、複数の基板接地方法が電流コラプスを低減するために有効であることを見出した。この構成によれば、カソード電極からアノード電極端までの電界のかかり方を空間的に広げることでアノード電極端までの電界集中を緩和することが可能となり、ＧａＮ系ショットキーダイオードによる整流装置において、電流コラプスを低減した整流装置を実現することができる。 The present inventors have found that a plurality of substrate grounding methods are effective for reducing current collapse in a GaN-based Schottky diode. According to this configuration, it is possible to alleviate electric field concentration to the anode electrode end by spatially expanding how the electric field is applied from the cathode electrode to the anode electrode end. In the rectifier using a GaN-based Schottky diode, A rectifier with reduced current collapse can be realized.
　また、前記基板電極は、前記アノード電極と実質的に同電位となるように接続されていることが好ましい。 The substrate electrode is preferably connected so as to have substantially the same potential as the anode electrode.
　ＧａＮ系ショットキーダイオードにおいて、アノードリセスの構造によりアノード電極を基板と直接接触させるだけでなく、さらに、アノード電極をワイヤリング等により基板に接続させることが、電流コラプスを低減するために有効である。この構成によれば、アノード電極と基板電極とが同電位になることにより、電流コラプスを低減した整流装置を提供することができる。 In a GaN-based Schottky diode, it is effective not only to directly contact the anode electrode with the substrate by the anode recess structure, but also to connect the anode electrode to the substrate by wiring or the like in order to reduce current collapse. According to this configuration, it is possible to provide a rectifier with reduced current collapse, because the anode electrode and the substrate electrode have the same potential.
　また、前記基板電極は、前記カソード電極と実質的に同電位となるように接続されていることが好ましい。 The substrate electrode is preferably connected so as to have substantially the same potential as the cathode electrode.
　ＧａＮ系ショットキーダイオードにおいて、カソードリセスの構造によりカソード電極を基板と直接接触させるだけでなく、さらに、カソード電極をワイヤリング等により基板に接続させることが、電流コラプスを低減するために有効である。この構成によれば、カソード電極と基板電極とが同電位になることにより、電流コラプスを低減した整流装置を提供することができる。 In a GaN-based Schottky diode, it is effective not only to directly contact the cathode electrode with the substrate by the cathode recess structure, but also to connect the cathode electrode to the substrate by wiring or the like in order to reduce current collapse. According to this configuration, the cathode electrode and the substrate electrode have the same potential, so that a rectifier with reduced current collapse can be provided.
　また、前記基板電極は、グランドと実質的に同電位となるように接続されることが好ましい。これにより、基板電極を接地することで、電流コラプスが低減される。 The substrate electrode is preferably connected so as to have substantially the same potential as the ground. Thereby, the current collapse is reduced by grounding the substrate electrode.
　また、前記基板電極は、リードフレームであってもよい。 Further, the substrate electrode may be a lead frame.
　この構成によれば、整流装置を備えたチップをリードフレームにダイボンドするだけで、基板の裏面に形成された基板電極が完成される。 According to this configuration, the substrate electrode formed on the back surface of the substrate is completed simply by die-bonding a chip provided with a rectifier to the lead frame.
　また、前記半導体層積層体は、前記第１の窒化物半導体層と前記第２の窒化物半導体層とを交互に複数層積層して形成されていることが好ましい。 The semiconductor layer stack is preferably formed by alternately stacking a plurality of the first nitride semiconductor layers and the second nitride semiconductor layers.
　この構成によれば、半導体層積層体が第１の窒化物半導体層と第２の窒化物半導体層とを交互に複数層積層して形成されている整流装置において、電流コラプスを低減した整流装置を実現することができる。 According to this configuration, in the rectifier in which the semiconductor layer stack is formed by alternately stacking a plurality of first nitride semiconductor layers and second nitride semiconductor layers, the rectifier with reduced current collapse Can be realized.
　本発明により、電流コラプスを低減した整流装置を実現できる。 According to the present invention, a rectifier with reduced current collapse can be realized.
図１Ａは、第１の実施形態に係る整流装置の構成を示す平面図である。FIG. 1A is a plan view showing a configuration of a rectifier according to the first embodiment. 図１Ｂは、第１の実施形態に係る整流装置の構成を示す断面図である。FIG. 1B is a cross-sectional view illustrating the configuration of the rectifier according to the first embodiment. 図１Ｃは、第１の実施形態に係る整流装置の構成を示す平面図である。FIG. 1C is a plan view showing the configuration of the rectifier according to the first embodiment. 図１Ｄは、第１の実施形態に係る整流装置の構成を示す断面図である。FIG. 1D is a cross-sectional view illustrating the configuration of the rectifier according to the first embodiment. 図１Ｅは、第１の実施形態に係る整流装置の構成を示す平面図である。FIG. 1E is a plan view showing the configuration of the rectifier according to the first embodiment. 図１Ｆは、第１の実施形態に係る整流装置の構成を示す平面図である。FIG. 1F is a plan view showing the configuration of the rectifier according to the first embodiment. 図２Ａは、第２の実施形態に係る整流装置の構成を示す平面図である。FIG. 2A is a plan view showing a configuration of a rectifier according to the second embodiment. 図２Ｂは、第２の実施形態に係る整流装置の構成を示す断面図である。FIG. 2B is a cross-sectional view illustrating a configuration of a rectifier according to the second embodiment. 図２Ｃは、第２の実施形態に係る整流装置の構成を示す平面図である。FIG. 2C is a plan view showing the configuration of the rectifier according to the second embodiment. 図２Ｄは、第２の実施形態に係る整流装置の構成を示す断面図である。FIG. 2D is a cross-sectional view illustrating a configuration of a rectifier according to the second embodiment. 図２Ｅは、第２の実施形態に係る整流装置の構成を示す平面図である。FIG. 2E is a plan view showing the configuration of the rectifier according to the second embodiment. 図２Ｆは、第２の実施形態に係る整流装置の構成を示す平面図である。FIG. 2F is a plan view showing the configuration of the rectifier according to the second embodiment. 図３Ａは、第３の実施形態に係る整流装置の構成を示す平面図である。FIG. 3A is a plan view illustrating a configuration of a rectifying device according to a third embodiment. 図３Ｂは、第３の実施形態に係る整流装置の構成を示す断面図である。FIG. 3B is a cross-sectional view showing the configuration of the rectifier according to the third embodiment. 図３Ｃは、第３の実施形態に係る整流装置の構成を示す平面図である。FIG. 3C is a plan view showing the configuration of the rectifier according to the third embodiment. 図３Ｄは、第３の実施形態に係る整流装置の構成を示す断面図である。FIG. 3D is a cross-sectional view illustrating a configuration of a rectifier according to the third embodiment. 図３Ｅは、第３の実施形態に係る整流装置の構成を示す平面図である。FIG. 3E is a plan view showing the configuration of the rectifier according to the third embodiment. 図４は、従来技術に係る窒化物半導体素子の構成を示す断面図である。FIG. 4 is a cross-sectional view showing a configuration of a nitride semiconductor device according to the prior art.
　以下、本発明に係る整流装置の実施形態について説明する。なお、本発明について、以下の実施形態及び添付の図面を用いて説明を行うが、これは例示を目的としており、本発明がこれらに限定されることを意図しない。つまり、以下で説明する実施形態は、いずれも本発明の好ましい一具体例を示すものである。以下の実施形態で示される数値、形状、材料、構成要素、構成要素の配置位置及び接続形態などは、一例であり、本発明を限定する主旨ではない。本発明は、請求の範囲だけによって限定される。よって、以下の実施の形態における構成要素のうち、本発明の最上位概念を示す独立請求項に記載されていない構成要素については、本発明の課題を達成するのに必ずしも必要ではないが、より好ましい形態を構成するものとして説明される。 Hereinafter, embodiments of the rectifier according to the present invention will be described. In addition, although this invention is demonstrated using the following embodiment and attached drawing, this is for the purpose of illustration and this invention is not intended to be limited to these. That is, each of the embodiments described below shows a preferred specific example of the present invention. Numerical values, shapes, materials, constituent elements, arrangement positions and connection forms of constituent elements, and the like shown in the following embodiments are merely examples, and are not intended to limit the present invention. The present invention is limited only by the claims. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept of the present invention are not necessarily required to achieve the object of the present invention. It will be described as constituting a preferred form.
　（第１の実施形態）
　はじめに、本発明に係る第１の実施形態について説明する。 (First embodiment)
First, a first embodiment according to the present invention will be described.
　図１Ａ～図１Ｆは、第１の実施形態に係る整流装置の構成を示す概念図である。図１Ａ及び図１Ｂは１つの半導体層積層体で、かつ、アノード接地された整流装置の構成を示す概念図、図１Ｃ及び図１Ｄは複数の半導体層積層体で、かつ、アノード接地された整流装置の構成を示す概念図、図１Ｅはワイヤリングにてアノード接地された整流装置の構成を示す平面図、図１Ｆはリードフレームにてアノード接地された整流装置の構成を示す平面図である。ここで、アノード接地とは、整流装置において、アノード電極が基板（あるいは、基板電極）と実質的に同電位となるように接続されることをいう。また、「実質的に同電位となるように接続される」とは、銅線、アルミニウム線、導電性接着剤等の導電性材料で接続されることをいう。 1A to 1F are conceptual diagrams showing the configuration of the rectifier according to the first embodiment. FIG. 1A and FIG. 1B are conceptual diagrams showing the configuration of a single semiconductor layer laminate and an anode grounded rectifier. FIGS. 1C and 1D are a plurality of semiconductor layer laminates and an anode grounded rectifier. FIG. 1E is a plan view showing the configuration of a rectifier that is anode-grounded by wiring, and FIG. 1F is a plan view showing the configuration of the rectifier that is anode-grounded by a lead frame. Here, anode grounding means that in the rectifier, the anode electrode is connected so as to have substantially the same potential as the substrate (or substrate electrode). In addition, “connected so as to have substantially the same potential” means that they are connected with a conductive material such as a copper wire, an aluminum wire, or a conductive adhesive.
　図１Ａに示すように、本実施形態に係る整流装置１００は、１つの半導体層積層体で構成される整流装置のチップ１０１と、複数のアノード電極１０２ａと、複数のカソード電極１０３ａと、アノードパッド１０４と、カソードパッド１０５と、保護膜１０６とを備えている。 As shown in FIG. 1A, a rectifying device 100 according to this embodiment includes a chip 101 of a rectifying device composed of one semiconductor layer stack, a plurality of anode electrodes 102a, a plurality of cathode electrodes 103a, and an anode pad. 104, a cathode pad 105, and a protective film 106 are provided.
　アノードパッド１０４及びカソードパッド１０５は、それぞれアノード電極１０２ａ及びカソード電極１０３ａと接続されている。また、チップ表面には、チップ１０１、アノード電極１０２ａ、カソード電極１０３ａ、アノードパッド１０４、カソードパッド１０５を覆うように保護膜１０６が形成されている。 The anode pad 104 and the cathode pad 105 are connected to the anode electrode 102a and the cathode electrode 103a, respectively. A protective film 106 is formed on the chip surface so as to cover the chip 101, the anode electrode 102a, the cathode electrode 103a, the anode pad 104, and the cathode pad 105.
　図１Ｂは、図１Ａに示した整流装置１００のＡ－Ａ’線における断面図である。図１Ｂに示すように、基板１０７の上には、バッファ層１０８と、第１の窒化物半導体層１０９と、第２の窒化物半導体層１１０とが順次形成されている。第１の窒化物半導体層１０９の第２の窒化物半導体層１１０との界面近傍には、２ＤＥＧからなるチャネル（図示せず）が形成されている。ここで、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０は、本発明に係る半導体層積層体に相当する。なお、基板１０７の裏面には、図示されない基板電極（例えば、後述するリードフレーム）が形成され、その基板電極は、０Ｖ以上の電位（例えば、グランド）に接地される。ここで、「０Ｖ以上の電位に接地される」とは、実質的にグランドと呼べる電位に接続されることをいう。また、「接地される」とは、「接地されている」状態を意味するだけでなく、整流装置を電子部品として使用したときに初めて「接地される」状態も意味する。 FIG. 1B is a cross-sectional view taken along line A-A ′ of rectifier 100 shown in FIG. 1A. As shown in FIG. 1B, a buffer layer 108, a first nitride semiconductor layer 109, and a second nitride semiconductor layer 110 are sequentially formed on the substrate 107. A channel (not shown) made of 2DEG is formed in the vicinity of the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110. Here, the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 correspond to a semiconductor layer stack according to the present invention. A substrate electrode (not shown) (for example, a lead frame described later) is formed on the back surface of the substrate 107, and the substrate electrode is grounded to a potential of 0 V or more (for example, ground). Here, “grounded to a potential of 0 V or higher” means being connected to a potential that can be substantially called ground. Further, “grounded” not only means “grounded” but also means “grounded” for the first time when the rectifier is used as an electronic component.
　また、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０には、図１Ａに示すように、アノード電極１０２ａとカソード電極１０３ａとが、互いに間隔をおいて交互に複数配置されている。アノード電極１０２ａは、第２の窒化物半導体層１１０と、第１の窒化物半導体層１０９と、バッファ層１０８とを貫通して、基板１０７の所定の深さまで形成されている。カソード電極１０３ａは、第２の窒化物半導体層１１０を貫通して、第１の窒化物半導体層１０９の所定の深さまで形成されている。なお、アノード電極１０２ａ及びカソード電極１０３ａは、複数でなくても１つずつであってもよい。 In addition, in the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, as shown in FIG. 1A, a plurality of anode electrodes 102a and cathode electrodes 103a are alternately arranged at intervals. Yes. The anode electrode 102 a is formed to a predetermined depth of the substrate 107 through the second nitride semiconductor layer 110, the first nitride semiconductor layer 109, and the buffer layer 108. The cathode electrode 103 a is formed to penetrate the second nitride semiconductor layer 110 to a predetermined depth of the first nitride semiconductor layer 109. Note that the anode electrode 102a and the cathode electrode 103a may not be plural but one each.
　また、アノード電極１０２ａの表面と、カソード電極１０３ａの表面と、アノード電極１０２ａとカソード電極１０３ａとの間の部分の第２の窒化物半導体層１１０の表面は、窒化シリコン（ＳｉＮ）等からなる保護膜１０６に覆われている。 Further, the surface of the anode electrode 102a, the surface of the cathode electrode 103a, and the surface of the second nitride semiconductor layer 110 between the anode electrode 102a and the cathode electrode 103a are protected from silicon nitride (SiN) or the like. The film 106 is covered.
　アノード電極１０２ａは、第１の窒化物半導体層１０９と第２の窒化物半導体層１１０との界面よりも下側で基板１０７に達するアノードリセスに形成されており、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０（チャネル）とショットキー接触している。これにより、アノード電極１０２ａが直接、基板１０７に接し、アノード電極１０２ａと基板１０７とが実質的に同電位となるアノード接地が実現される。なお、アノード電極１０２ａはニッケル（Ｎｉ）、金（Ａｕ）からなる積層体とすればよい。 The anode electrode 102 a is formed in an anode recess that reaches the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer 109. And Schottky contact with the second nitride semiconductor layer 110 (channel). Thereby, the anode electrode 102a is in direct contact with the substrate 107, and anode grounding is realized in which the anode electrode 102a and the substrate 107 have substantially the same potential. Note that the anode electrode 102a may be a stacked body made of nickel (Ni) and gold (Au).
　カソード電極１０３ａは、第１の窒化物半導体層１０９と第２の窒化物半導体層１１０との界面よりも下側で基板１０７に達しないカソードリセスに形成されており、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０（チャネル）とオーミック接触している。カソード電極１０３ａは、２ＤＥＧと容易にオーミック接触するチタン（Ｔｉ）又はアルミニウム（Ａｌ）等を含む材料により形成すればよく、例えば、ＴｉとＡｌとの合金等とすればよい。 The cathode electrode 103a is formed in a cathode recess that does not reach the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer. 109 and the second nitride semiconductor layer 110 (channel) are in ohmic contact. The cathode electrode 103a may be formed of a material containing titanium (Ti) or aluminum (Al) that is easily in ohmic contact with 2DEG. For example, an alloy of Ti and Al may be used.
　また、図１Ｃに示すように、本実施形態の整流装置１００は、１つの半導体層積層体に代えて、複数の半導体層積層体で構成される整流装置のチップ１１１からなる構成であってもよい。具体的には、整流装置１００は、複数の半導体層積層体と、アノード電極１０２ａと、複数のカソード電極１０３ａと、アノードパッド１０４と、カソードパッド１０５と、保護膜１０６とを備えている。 Further, as shown in FIG. 1C, the rectifying device 100 of this embodiment may be configured by a chip 111 of a rectifying device including a plurality of semiconductor layer stacks instead of one semiconductor layer stack. Good. Specifically, the rectifying device 100 includes a plurality of semiconductor layer stacks, an anode electrode 102a, a plurality of cathode electrodes 103a, an anode pad 104, a cathode pad 105, and a protective film 106.
　アノードパッド１０４及びカソードパッド１０５は、それぞれアノード電極１０２ａ及びカソード電極１０３ａと接続されている。また、チップ表面には、チップ１０１、アノード電極１０２ａ、カソード電極１０３ａ、アノードパッド１０４、カソードパッド１０５を覆うように保護膜１０６が形成されている。複数の半導体層積層体は、本実施形態では、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０が３周期積層された構成である。 The anode pad 104 and the cathode pad 105 are connected to the anode electrode 102a and the cathode electrode 103a, respectively. A protective film 106 is formed on the chip surface so as to cover the chip 101, the anode electrode 102a, the cathode electrode 103a, the anode pad 104, and the cathode pad 105. In the present embodiment, the plurality of semiconductor layer stacks have a configuration in which the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 are stacked in three cycles.
　図１Ｄは、図１Ｃに示した整流装置１００のＢ－Ｂ’線における断面図である。図１Ｄに示すように、基板１０７の上には、バッファ層１０８と、第１の窒化物半導体層１０９と、第２の窒化物半導体層１１０とが３周期繰り返して交互に順次形成されている。第１の窒化物半導体層１０９の第２の窒化物半導体層１１０との界面近傍には、２ＤＥＧからなるチャネル（図示せず）が形成されている。なお、基板１０７の裏面には、図示されない基板電極（例えば、後述するリードフレーム）が形成され、その基板電極は、０Ｖ以上の電位（例えば、グランド）に接地される。 FIG. 1D is a cross-sectional view taken along line B-B ′ of the rectifier 100 shown in FIG. 1C. As shown in FIG. 1D, a buffer layer 108, a first nitride semiconductor layer 109, and a second nitride semiconductor layer 110 are alternately and sequentially formed on the substrate 107 in three cycles. . A channel (not shown) made of 2DEG is formed in the vicinity of the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110. A substrate electrode (not shown) (for example, a lead frame described later) is formed on the back surface of the substrate 107, and the substrate electrode is grounded to a potential of 0 V or more (for example, ground).
　また、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０には、図１Ｃに示すように、アノード電極１０２ａとカソード電極１０３ａとが、互いに間隔をおいて交互に複数配置されている。アノード電極１０２ａは、３周期繰り返して形成された第２の窒化物半導体層１１０及び第１の窒化物半導体層１０９と、バッファ層１０８とを貫通して、基板１０７の所定の深さまで形成されている。これにより、アノード電極１０２ａが直接、基板１０７に接し、アノード電極１０２ａと基板１０７とが実質的に同電位となるアノード接地が実現される。 Further, in the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, as shown in FIG. 1C, a plurality of anode electrodes 102a and cathode electrodes 103a are alternately arranged at intervals. Yes. The anode electrode 102a is formed to a predetermined depth of the substrate 107 through the second nitride semiconductor layer 110, the first nitride semiconductor layer 109, and the buffer layer 108, which are formed by repeating three cycles. Yes. Thereby, the anode electrode 102a is in direct contact with the substrate 107, and anode grounding is realized in which the anode electrode 102a and the substrate 107 have substantially the same potential.
　カソード電極１０３ａは、第２の窒化物半導体層１１０を貫通して、第１の窒化物半導体層１０９の所定の深さまで形成されている。なお、アノード電極１０２ａ及びカソード電極１０３ａは、複数でなくても１つずつであってもよい。 The cathode electrode 103 a is formed to penetrate the second nitride semiconductor layer 110 to a predetermined depth of the first nitride semiconductor layer 109. Note that the anode electrode 102a and the cathode electrode 103a may not be plural but one each.
　また、アノード電極１０２ａの表面と、カソード電極１０３ａの表面と、アノード電極１０２ａとカソード電極１０３ａとの間の部分の第２の窒化物半導体層１１０の表面は、窒化シリコン（ＳｉＮ）等からなる保護膜１０６に覆われている。 Further, the surface of the anode electrode 102a, the surface of the cathode electrode 103a, and the surface of the second nitride semiconductor layer 110 between the anode electrode 102a and the cathode electrode 103a are protected from silicon nitride (SiN) or the like. The film 106 is covered.
　アノード電極１０２ａは、第１の窒化物半導体層１０９と第２の窒化物半導体層１１０との界面よりも下側で基板１０７に達するアノードリセスに形成されており、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０（チャネル）とショットキー接触している。アノード電極１０２ａはニッケル（Ｎｉ）、金（Ａｕ）からなる積層体とすればよい。 The anode electrode 102 a is formed in an anode recess that reaches the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer 109. And Schottky contact with the second nitride semiconductor layer 110 (channel). The anode electrode 102a may be a laminate made of nickel (Ni) and gold (Au).
　カソード電極１０３ａは、第１の窒化物半導体層１０９と第２の窒化物半導体層１１０との界面よりも下側で基板１０７に達しないカソードリセスに形成されており、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０（チャネル）とオーミック接触している。カソード電極１０３ａは、２ＤＥＧと容易にオーミック接触するチタン（Ｔｉ）又はアルミニウム（Ａｌ）等を含む材料により形成すればよく、例えば、ＴｉとＡｌとの合金等とすればよい。 The cathode electrode 103a is formed in a cathode recess that does not reach the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer. 109 and the second nitride semiconductor layer 110 (channel) are in ohmic contact. The cathode electrode 103a may be formed of a material containing titanium (Ti) or aluminum (Al) that is easily in ohmic contact with 2DEG. For example, an alloy of Ti and Al may be used.
　このように、本実施形態によれば、アノード電極１０２ａと基板１０７とを同電位にすることができ、カソード電極１０３ａからアノード電極１０２ａ端までの電界のかかり方を空間的に広げることでアノード電極１０２ａ端までの電界集中を緩和することが可能となり、整流装置１００の電流コラプスを低減することができる。 As described above, according to the present embodiment, the anode electrode 102a and the substrate 107 can be set to the same potential, and the application of an electric field from the cathode electrode 103a to the end of the anode electrode 102a is spatially widened to thereby increase the anode electrode. The electric field concentration up to the end of 102a can be relaxed, and the current collapse of the rectifier 100 can be reduced.
　（第１の実施形態の変形例）
　次に、第１の実施形態の変形例について説明する。上記した整流装置１００では、アノード電極１０２ａが基板１０７に達するアノードリセスに形成されることにより、アノード電極１０２ａと基板１０７とが直接接続されている構成であったが、アノード電極１０２ａは、さらに、アノードパッド１０４と、基板１０７に形成されたアノード端子１１４ａとを介して基板１０７に接続される構成であってもよい。 (Modification of the first embodiment)
Next, a modification of the first embodiment will be described. In the rectifier 100 described above, the anode electrode 102a is formed in the anode recess reaching the substrate 107, whereby the anode electrode 102a and the substrate 107 are directly connected. The configuration may be such that the anode pad 104 and the anode terminal 114 a formed on the substrate 107 are connected to the substrate 107.
　図１Ｅに示すように、１つの半導体層積層体で構成された整流装置を備えたチップ１０１（あるいは複数の半導体層積層体で構成された整流装置を備えたチップ１１１）を、例えば、ＴＯ－２２０型パッケージからなるリードフレーム１１２にダイボンドする。ここで、リードフレーム１１２は、本発明に係る基板電極、つまり、基板１０７の裏面に形成された電極に相当する。 As shown in FIG. 1E, a chip 101 provided with a rectifier constituted by a single semiconductor layer stack (or a chip 111 provided with a rectifier constituted by a plurality of semiconductor layer laminates), for example, a TO- A die frame is bonded to a lead frame 112 made of a 220 type package. Here, the lead frame 112 corresponds to a substrate electrode according to the present invention, that is, an electrode formed on the back surface of the substrate 107.
　リードフレーム１１２には、アノード端子１１４ａ及び１１４ｂと、カソード端子１１５ａとが形成されている。 The lead frame 112 is formed with anode terminals 114a and 114b and a cathode terminal 115a.
　図１Ｅに示すように、アノードパッド１０４とアノード端子１１４ａとは、Ａｌからなるワイヤ１１３ａで接続され、また、カソードパッド１０５とカソード端子１１５ａとは、ワイヤ１１３ｂで接続されている。ここで、アノード端子１１４ａは、基板１０７の裏面と接触しており、基板１０７の裏面に形成された基板電極でもある。このように、ワイヤリングによりアノードパッド１０４と基板１０７とが短絡されても良い。これにより、アノード電極１０２ａを、アノードパッド１０４を介して、アノード端子１１４ａ（つまり、基板電極）と同電位にすることができ、カソード電極１０３ａからアノード電極１０２ａ端までの電界のかかり方を空間的に広げることでアノード電極１０２ａ端までの電界集中を緩和することが可能となり、整流装置１００の電流コラプスを低減することができる。 As shown in FIG. 1E, the anode pad 104 and the anode terminal 114a are connected by a wire 113a made of Al, and the cathode pad 105 and the cathode terminal 115a are connected by a wire 113b. Here, the anode terminal 114 a is in contact with the back surface of the substrate 107 and is also a substrate electrode formed on the back surface of the substrate 107. Thus, the anode pad 104 and the substrate 107 may be short-circuited by wiring. As a result, the anode electrode 102a can be set to the same potential as the anode terminal 114a (that is, the substrate electrode) via the anode pad 104, and the application of an electric field from the cathode electrode 103a to the end of the anode electrode 102a is spatially applied. It is possible to alleviate the electric field concentration up to the end of the anode electrode 102a, and the current collapse of the rectifier 100 can be reduced.
　また、図１Ｆに示すように、１つの半導体層積層体で構成される整流装置を備えたチップ１０１（あるいは複数の半導体層積層体で構成される整流装置を備えたチップ１１１）を、例えば、ＴＯ－２２０型パッケージからなるリードフレーム１１２にダイボンドする。ここで、リードフレーム１１２は、本発明に係る基板電極に相当する。 Further, as shown in FIG. 1F, a chip 101 including a rectifier configured by one semiconductor layer stack (or a chip 111 including a rectifier configured by a plurality of semiconductor layer stacks), for example, A die bond is made to the lead frame 112 made of a TO-220 type package. Here, the lead frame 112 corresponds to a substrate electrode according to the present invention.
　リードフレーム１１２には、アノード端子１１４ａ及び１１４ｂと、カソード端子１１５ａとが形成されている。アノード端子１１４ａ及び１１４ｂは、一体形成され、電気的に接続されている。 The lead frame 112 is formed with anode terminals 114a and 114b and a cathode terminal 115a. The anode terminals 114a and 114b are integrally formed and are electrically connected.
　図１Ｆに示すように、アノードパッド１０４とアノード端子１１４ｂとは、Ａｌからなるワイヤ１１３ｃで接続され、また、カソードパッド１０５とカソード端子１１５ａとは、ワイヤ１１３ｂで接続されている。ここで、アノード端子１１４ａ及び１１４ｂは、リードフレーム１１２として、基板１０７の裏面と接触しており、基板１０７の裏面に形成された基板電極でもある。このように、リードフレーム１１２によりアノードパッド１０４と基板１０７とが短絡されても良い。これにより、アノード電極１０２ａを、アノードパッド１０４及びアノード端子１１４ｂを介して、リードフレーム１１２（つまり、基板電極）と同電位にすることができ、カソード電極１０３ａからアノード電極１０２ａ端までの電界のかかり方を空間的に広げることでアノード電極１０２ａ端までの電界集中を緩和することが可能となり、整流装置１００の電流コラプスをより低減することができる。 As shown in FIG. 1F, the anode pad 104 and the anode terminal 114b are connected by a wire 113c made of Al, and the cathode pad 105 and the cathode terminal 115a are connected by a wire 113b. Here, the anode terminals 114 a and 114 b are in contact with the back surface of the substrate 107 as the lead frame 112, and are also substrate electrodes formed on the back surface of the substrate 107. As described above, the anode pad 104 and the substrate 107 may be short-circuited by the lead frame 112. Thus, the anode electrode 102a can be set to the same potential as the lead frame 112 (that is, the substrate electrode) via the anode pad 104 and the anode terminal 114b, and an electric field is applied from the cathode electrode 103a to the end of the anode electrode 102a. By expanding the direction spatially, the electric field concentration to the end of the anode electrode 102a can be relaxed, and the current collapse of the rectifying device 100 can be further reduced.
　（第２の実施形態）
　次に、本発明に係る第２の実施形態について説明する。本実施形態に係る整流装置が第１の実施形態に係る整流装置と異なる点は、基板（あるいは、基板電極）の電位が、アノード電極の電位ではなくカソード電極の電位と実質的に同じ電位である点である。 (Second Embodiment)
Next, a second embodiment according to the present invention will be described. The rectifier according to this embodiment is different from the rectifier according to the first embodiment in that the potential of the substrate (or substrate electrode) is substantially the same as the potential of the cathode electrode, not the potential of the anode electrode. There is a point.
　図２Ａ～図２Ｆは、第２の実施形態に係る整流装置の構成を示す概念図である。図２Ａ及び図２Ｂは１つの半導体層積層体で、かつ、カソード接地された整流装置の構成を示す概念図、図２Ｃ及び図２Ｄは複数の半導体層積層体で、かつ、カソード接地された整流装置の構成を示す概念図、図２Ｅはワイヤリングにてカソード接地された整流装置の構成を示す平面図、図２Ｆはリードフレームにてカソード接地された整流装置の構成を示す平面図である。ここで、カソード接地とは、整流装置において、カソード電極が基板（あるいは、基板電極）と実質的に同電位となるように接続されることをいう。 2A to 2F are conceptual diagrams showing the configuration of the rectifier according to the second embodiment. FIGS. 2A and 2B are conceptual diagrams showing the configuration of a rectifier with a single semiconductor layer stack and a cathode ground, and FIGS. 2C and 2D are rectifiers with a plurality of semiconductor layer stacks and a cathode ground. FIG. 2E is a plan view showing the configuration of a rectifier that is cathode-grounded by wiring, and FIG. 2F is a plan view showing the configuration of the rectifier that is cathode-grounded by a lead frame. Here, the cathode ground means that in the rectifier, the cathode electrode is connected so as to have substantially the same potential as the substrate (or substrate electrode).
　図２Ａに示すように、本実施形態に係る整流装置１００は、１つの半導体層積層体で構成される整流装置のチップ１０１と、複数のアノード電極１０２ｂと、複数のカソード電極１０３ｂと、アノードパッド１０４と、カソードパッド１０５と、保護膜１０６とを備えている。 As shown in FIG. 2A, the rectifying device 100 according to the present embodiment includes a rectifying device chip 101 composed of one semiconductor layer stack, a plurality of anode electrodes 102b, a plurality of cathode electrodes 103b, and an anode pad. 104, a cathode pad 105, and a protective film 106 are provided.
　アノードパッド１０４及びカソードパッド１０５は、それぞれアノード電極１０２ｂ、カソード電極１０３ｂと接続されている。また、チップ表面には、チップ１０１、アノード電極１０２ｂ、カソード電極１０３ｂ、アノードパッド１０４、カソードパッド１０５を覆うように保護膜１０６が形成されている。 The anode pad 104 and the cathode pad 105 are connected to the anode electrode 102b and the cathode electrode 103b, respectively. A protective film 106 is formed on the chip surface so as to cover the chip 101, the anode electrode 102b, the cathode electrode 103b, the anode pad 104, and the cathode pad 105.
　図２Ｂは、図２Ａに示した整流装置１００のＣ－Ｃ’線における断面図である。図２Ｂに示すように、基板１０７の上には、バッファ層１０８と、第１の窒化物半導体層１０９と、第２の窒化物半導体層１１０とが順次形成されている。第１の窒化物半導体層１０９の第２の窒化物半導体層１１０との界面近傍には、２ＤＥＧからなるチャネル（図示せず）が形成されている。ここで、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０は、本発明に係る半導体層積層体に相当する。なお、基板１０７の裏面には、図示されない基板電極（例えば、後述するリードフレーム）が形成され、その基板電極は、０Ｖ以上の電位（例えば、グランド）に接地される。 FIG. 2B is a cross-sectional view taken along line C-C ′ of the rectifier 100 shown in FIG. 2A. As shown in FIG. 2B, a buffer layer 108, a first nitride semiconductor layer 109, and a second nitride semiconductor layer 110 are sequentially formed on the substrate 107. A channel (not shown) made of 2DEG is formed in the vicinity of the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110. Here, the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 correspond to a semiconductor layer stack according to the present invention. A substrate electrode (not shown) (for example, a lead frame described later) is formed on the back surface of the substrate 107, and the substrate electrode is grounded to a potential of 0 V or more (for example, ground).
　また、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０には、図２Ａに示すように、アノード電極１０２ｂとカソード電極１０３ｂとが、互いに間隔をおいて交互に複数配置されている。アノード電極１０２ｂは、第２の窒化物半導体層１１０を貫通して第１の窒化物半導体層１０９の所定の深さまで形成されている。カソード電極１０３ｂは、第２の窒化物半導体層１１０、第１の窒化物半導体層１０９、バッファ層１０８を貫通して基板１０７の所定の深さまで形成されている。なお、アノード電極１０２ｂ及びカソード電極１０３ｂは、複数でなくても１つずつであってもよい。 In addition, in the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, as shown in FIG. 2A, a plurality of anode electrodes 102b and cathode electrodes 103b are alternately arranged at intervals. Yes. The anode electrode 102 b is formed to penetrate the second nitride semiconductor layer 110 to a predetermined depth of the first nitride semiconductor layer 109. The cathode electrode 103 b is formed to a predetermined depth of the substrate 107 through the second nitride semiconductor layer 110, the first nitride semiconductor layer 109, and the buffer layer 108. Note that the anode electrode 102b and the cathode electrode 103b may not be plural but one each.
　また、アノード電極１０２ｂの表面と、カソード電極１０３ｂの表面と、アノード電極１０２ｂとカソード電極１０３ｂとの間の部分の第２の窒化物半導体層１１０の表面は、窒化シリコン（ＳｉＮ）等からなる保護膜１０６に覆われている。 Further, the surface of the anode electrode 102b, the surface of the cathode electrode 103b, and the surface of the second nitride semiconductor layer 110 between the anode electrode 102b and the cathode electrode 103b are protected from silicon nitride (SiN) or the like. The film 106 is covered.
　アノード電極１０２ｂは、第１の窒化物半導体層１０９と第２の窒化物半導体層１１０との界面よりも下側で基板１０７に達しないアノードリセスに形成されており、第１の窒化物半導体層１０９および第２の窒化物半導体層１１０（チャネル）とショットキー接触している。アノード電極１０２ｂはニッケル（Ｎｉ）、金（Ａｕ）からなる積層体とすればよい。 The anode electrode 102b is formed in an anode recess that does not reach the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 (channel) are in Schottky contact. The anode electrode 102b may be a laminate made of nickel (Ni) and gold (Au).
　カソード電極１０３ｂは、第１の窒化物半導体層１０９と第２の窒化物半導体層１１０との界面よりも下側で基板１０７に達するカソードリセスに形成されており、第１の窒化物半導体層１０９および第２の窒化物半導体層１１０（チャネル）とオーミック接触している。これにより、カソード電極１０３ｂが直接、基板１０７に接し、カソード電極１０３ｂと基板１０７とが実質的に同電位となるカソード接地が実現される。なお、カソード電極１０３ｂは、２ＤＥＧと容易にオーミック接触するチタン（Ｔｉ）又はアルミニウム（Ａｌ）等を含む材料により形成すればよく、例えば、ＴｉとＡｌとの合金等とすればよい。 The cathode electrode 103 b is formed in a cathode recess that reaches the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer 109. And in ohmic contact with the second nitride semiconductor layer 110 (channel). As a result, the cathode electrode 103b is in direct contact with the substrate 107, and cathode grounding is realized in which the cathode electrode 103b and the substrate 107 have substantially the same potential. Note that the cathode electrode 103b may be formed of a material containing titanium (Ti) or aluminum (Al) that is easily in ohmic contact with 2DEG, for example, an alloy of Ti and Al.
　また、図２Ｃに示すように、本実施形態の整流装置１００は、１つの半導体層積層体に代えて、複数の半導体層積層体で構成される整流装置のチップ１１１からなる構成であってもよい。具体的には、整流装置１００は、複数の半導体層積層体と、複数のアノード電極１０２ｂと、複数のカソード電極１０３ｂと、アノードパッド１０４と、カソードパッド１０５と、保護膜１０６とを備えている。 Further, as shown in FIG. 2C, the rectifying device 100 of the present embodiment may be configured by a chip 111 of a rectifying device including a plurality of semiconductor layer stacks instead of one semiconductor layer stack. Good. Specifically, the rectifying device 100 includes a plurality of semiconductor layer stacks, a plurality of anode electrodes 102b, a plurality of cathode electrodes 103b, an anode pad 104, a cathode pad 105, and a protective film 106. .
　アノードパッド１０４及びカソードパッド１０５は、それぞれアノード電極１０２ｂ、カソード電極１０３ｂと接続されている。また、チップ表面には、チップ１０１、アノード電極１０２ｂ、カソード電極１０３ｂ、アノードパッド１０４、カソードパッド１０５を覆うように保護膜１０６が形成されている。複数の半導体層積層体は、本実施形態では、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０が３周期積層された構成である。 The anode pad 104 and the cathode pad 105 are connected to the anode electrode 102b and the cathode electrode 103b, respectively. A protective film 106 is formed on the chip surface so as to cover the chip 101, the anode electrode 102b, the cathode electrode 103b, the anode pad 104, and the cathode pad 105. In the present embodiment, the plurality of semiconductor layer stacks have a configuration in which the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 are stacked in three cycles.
　図２Ｄは、図２Ｃに示した整流装置１００のＤ－Ｄ’線における断面図である。図２Ｄに示すように、基板１０７の上には、バッファ層１０８と、第１の窒化物半導体層１０９と、第２の窒化物半導体層１１０とが３周期繰り返して交互に順次形成されている。第１の窒化物半導体層１０９の第２の窒化物半導体層１１０との界面近傍には、２ＤＥＧからなるチャネル（図示せず）が形成されている。なお、基板１０７の裏面には、図示されない基板電極（例えば、後述するリードフレーム）が形成され、その基板電極は、０Ｖ以上の電位（例えば、グランド）に接地される。 FIG. 2D is a cross-sectional view taken along the line D-D ′ of the rectifier 100 shown in FIG. 2C. As shown in FIG. 2D, the buffer layer 108, the first nitride semiconductor layer 109, and the second nitride semiconductor layer 110 are alternately and sequentially formed on the substrate 107 in three cycles. . A channel (not shown) made of 2DEG is formed in the vicinity of the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110. A substrate electrode (not shown) (for example, a lead frame described later) is formed on the back surface of the substrate 107, and the substrate electrode is grounded to a potential of 0 V or more (for example, ground).
　また、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０には、図２Ｃに示すように、アノード電極１０２ｂとカソード電極１０３ｂとが、互いに間隔をおいて交互に複数配置されている。アノード電極１０２ｂは、第２の窒化物半導体層１１０を貫通して、第１の窒化物半導体層１０９の所定の深さまで形成されている。カソード電極１０３ｂは、３周期繰り返して形成された第２の窒化物半導体層１１０及び第１の窒化物半導体層１０９と、バッファ層１０８とを貫通して、基板１０７の所定の深さまで形成されている。これにより、カソード電極１０３ｂが直接、基板１０７に接し、カソード電極１０３ｂと基板１０７とが実質的に同電位となるカソード接地が実現される。なお、アノード電極１０２ｂ及びカソード電極１０３ｂは、複数でなくても１つずつであってもよい。 In addition, in the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, as shown in FIG. 2C, a plurality of anode electrodes 102b and cathode electrodes 103b are alternately arranged at intervals. Yes. The anode electrode 102 b is formed to penetrate the second nitride semiconductor layer 110 to a predetermined depth of the first nitride semiconductor layer 109. The cathode electrode 103b is formed to a predetermined depth of the substrate 107 through the second nitride semiconductor layer 110, the first nitride semiconductor layer 109, and the buffer layer 108, which are formed by repeating three cycles. Yes. As a result, the cathode electrode 103b is in direct contact with the substrate 107, and cathode grounding is realized in which the cathode electrode 103b and the substrate 107 have substantially the same potential. Note that the anode electrode 102b and the cathode electrode 103b may not be plural but one each.
　また、アノード電極１０２ｂの表面と、カソード電極１０３ｂの表面と、アノード電極１０２ｂとカソード電極１０３ｂとの間の部分の第２の窒化物半導体層１１０の表面は、窒化シリコン（ＳｉＮ）等からなる保護膜１０６に覆われている。 Further, the surface of the anode electrode 102b, the surface of the cathode electrode 103b, and the surface of the second nitride semiconductor layer 110 between the anode electrode 102b and the cathode electrode 103b are protected from silicon nitride (SiN) or the like. The film 106 is covered.
　アノード電極１０２ｂは、第１の窒化物半導体層１０９と第２の窒化物半導体層１１０との界面よりも下側で基板１０７に達しないアノードリセスに形成されており、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０（チャネル）とショットキー接触している。アノード電極１０２ｂはニッケル（Ｎｉ）、金（Ａｕ）からなる積層体とすればよい。 The anode electrode 102b is formed in an anode recess that does not reach the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 (channel) are in Schottky contact. The anode electrode 102b may be a laminate made of nickel (Ni) and gold (Au).
　カソード電極１０３ｂは、第１の窒化物半導体層１０９と第２の窒化物半導体層１１０との界面よりも下側で基板１０７に達するカソードリセスに形成されており、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０（チャネル）とオーミック接触している。カソード電極１０３ｂは、２ＤＥＧと容易にオーミック接触するチタン（Ｔｉ）又はアルミニウム（Ａｌ）等を含む材料により形成すればよく、例えば、ＴｉとＡｌとの合金等とすればよい。 The cathode electrode 103 b is formed in a cathode recess that reaches the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer 109. And in ohmic contact with the second nitride semiconductor layer 110 (channel). The cathode electrode 103b may be formed of a material containing titanium (Ti), aluminum (Al), or the like that is easily in ohmic contact with 2DEG, for example, an alloy of Ti and Al.
　このように、本実施形態によれば、カソード電極１０３ｂと基板１０７とを同電位にすることができ、カソード電極１０３ａからアノード電極１０２ａ端までの電界のかかり方を空間的に広げることでアノード電極１０２ａ端までの電界集中を緩和することが可能となり、整流装置１００の電流コラプスを低減することができる。 As described above, according to the present embodiment, the cathode electrode 103b and the substrate 107 can be set to the same potential, and the application of an electric field from the cathode electrode 103a to the end of the anode electrode 102a is spatially widened to thereby increase the anode electrode. The electric field concentration up to the end of 102a can be relaxed, and the current collapse of the rectifier 100 can be reduced.
　（第２の実施形態の変形例）
　次に、第２の実施形態の変形例について説明する。上記した整流装置１００では、カソード電極１０３ｂが基板１０７に達するカソードリセスに形成されることにより、カソード電極１０３ｂと基板１０７とが直接接続されている構成であったが、カソード電極１０３ｂは、さらに、カソードパッド１０５と、基板１０７に形成されたカソード端子１１５ｂとを介して基板１０７に接続される構成であってもよい。 (Modification of the second embodiment)
Next, a modification of the second embodiment will be described. In the rectifier 100 described above, the cathode electrode 103b is formed in the cathode recess reaching the substrate 107, so that the cathode electrode 103b and the substrate 107 are directly connected. The configuration may be such that the cathode pad 105 and the cathode terminal 115 b formed on the substrate 107 are connected to the substrate 107.
　図２Ｅに示すように、１つの半導体層積層体で構成される整流装置を備えたチップ１０１（あるいは複数の半導体層積層体で構成された整流装置を備えたチップ１１１）を、例えば、ＴＯ－２２０型パッケージからなるリードフレーム１１２にダイボンドする。ここで、リードフレーム１１２は、本発明に係る基板電極、つまり、基板１０７の裏面に形成された電極に相当する。 As shown in FIG. 2E, a chip 101 including a rectifier configured by one semiconductor layer stack (or a chip 111 including a rectifier configured by a plurality of semiconductor layer stacks) is, for example, TO- A die frame is bonded to a lead frame 112 made of a 220 type package. Here, the lead frame 112 corresponds to a substrate electrode according to the present invention, that is, an electrode formed on the back surface of the substrate 107.
　リードフレーム１１２には、アノード端子１１４ｃと、カソード端子１１５ｂ及び１１５ｃとが形成されている。 The lead frame 112 is formed with an anode terminal 114c and cathode terminals 115b and 115c.
　図２Ｅに示すように、アノードパッド１０４とアノード端子１１４ｃとは、Ａｌからなるワイヤ１１３ｄで接続され、また、カソードパッド１０５とカソード端子１１５ｂとは、ワイヤ１１３ｅで接続されている。ここで、カソード端子１１５ｂは、基板１０７の裏面と接触しており、基板１０７の裏面に形成された基板電極でもある。このように、ワイヤリングによりカソードパッド１０５と基板１０７とが短絡されても良い。これにより、カソード電極１０３ｂを、カソードパッド１０５を介して、カソード端子１１５ｂ（つまり、基板電極）と同電位にすることができ、カソード電極１０３ｂからアノード電極１０２ｂ端までの電界のかかり方を空間的に広げることでアノード電極１０２ｂ端までの電界集中を緩和することが可能となり、整流装置１００の電流コラプスを低減することができる。 As shown in FIG. 2E, the anode pad 104 and the anode terminal 114c are connected by a wire 113d made of Al, and the cathode pad 105 and the cathode terminal 115b are connected by a wire 113e. Here, the cathode terminal 115 b is in contact with the back surface of the substrate 107 and is also a substrate electrode formed on the back surface of the substrate 107. Thus, the cathode pad 105 and the substrate 107 may be short-circuited by wiring. Thus, the cathode electrode 103b can be set to the same potential as the cathode terminal 115b (that is, the substrate electrode) via the cathode pad 105, and the application of an electric field from the cathode electrode 103b to the end of the anode electrode 102b is spatially determined. It is possible to alleviate the electric field concentration up to the end of the anode electrode 102b, and the current collapse of the rectifier 100 can be reduced.
　また、図２Ｆに示すように、１つの半導体層積層体で構成される整流装置を備えたチップ１０１（あるいは複数の半導体層積層体で構成される整流装置を備えたチップ１１１）を、例えば、ＴＯ－２２０型パッケージからなるリードフレーム１１２にダイボンドする。ここで、リードフレーム１１２は、本発明に係る基板電極に相当する。 Further, as shown in FIG. 2F, for example, a chip 101 including a rectifier configured by one semiconductor layer stack (or a chip 111 including a rectifier configured by a plurality of semiconductor layer stacks) is used, for example. A die bond is made to the lead frame 112 made of a TO-220 type package. Here, the lead frame 112 corresponds to a substrate electrode according to the present invention.
　リードフレーム１１２には、アノード端子１１４ｃと、カソード端子１１５ｂ及び１１５ｃとが形成されている。カソード端子１１５ｂ及び１１５ｃは、一体形成され、電気的に接続されている。 The lead frame 112 is formed with an anode terminal 114c and cathode terminals 115b and 115c. The cathode terminals 115b and 115c are integrally formed and electrically connected.
　図２Ｆに示すように、アノードパッド１０４とアノード端子１１４ｃとは、Ａｌからなるワイヤ１１３ｄで接続され、また、カソードパッド１０５とカソード端子１１５ｃとは、ワイヤ１１３ｆで接続されている。ここで、カソード端子１１５ｂ及び１１５ｃは、リードフレーム１１２として、基板１０７の裏面と接触しており、基板１０７の裏面に形成された基板電極でもある。このように、リードフレームによりカソードパッド１０５と基板１０７とが短絡されても良い。これにより、カソード電極１０３ｂを、カソードパッド１０５及びカソード端子１１５ｃを介して、リードフレーム１１２（つまり、基板電極）と同電位にすることができ、カソード電極１０３ｂからアノード電極１０２ｂ端までの電界のかかり方を空間的に広げることでアノード電極１０２ｂ端までの電界集中を緩和することが可能となり、整流装置１００の電流コラプスをより低減することができる。 As shown in FIG. 2F, the anode pad 104 and the anode terminal 114c are connected by a wire 113d made of Al, and the cathode pad 105 and the cathode terminal 115c are connected by a wire 113f. Here, the cathode terminals 115 b and 115 c are in contact with the back surface of the substrate 107 as the lead frame 112, and are also substrate electrodes formed on the back surface of the substrate 107. Thus, the cathode pad 105 and the substrate 107 may be short-circuited by the lead frame. Thus, the cathode electrode 103b can be set to the same potential as the lead frame 112 (that is, the substrate electrode) via the cathode pad 105 and the cathode terminal 115c, and an electric field is applied from the cathode electrode 103b to the end of the anode electrode 102b. By expanding the direction spatially, it becomes possible to alleviate the electric field concentration to the end of the anode electrode 102b, and the current collapse of the rectifier 100 can be further reduced.
　（第３の実施形態）
　次に、本発明に係る第３の実施形態について説明する。本実施形態に係る整流装置が第１の実施形態及び第２の実施形態に係る整流装置と異なる点は、基板（あるいは、基板電極）の電位がグランドと実質的に同じ電位となるように接続される点である。なお、「基板（あるいは、基板電極）の電位がグランドと実質的に同じ電位となるように接続される」とは、そのように「接続されている」状態を意味するだけでなく、整流装置を電子部品として使用したときに初めてそのように「接続される」状態も意味する。 (Third embodiment)
Next, a third embodiment according to the present invention will be described. The rectifier according to this embodiment is different from the rectifier according to the first and second embodiments in that the substrate (or substrate electrode) is connected so that the potential of the substrate (or substrate electrode) is substantially the same as the ground. It is a point to be done. Note that “connected so that the potential of the substrate (or the substrate electrode) is substantially the same potential as the ground” does not only mean such a state of being “connected”, but also a rectifier. This means the state of being “connected” for the first time when the is used as an electronic component.
　図３Ａ～図３Ｅは、第３の実施形態に係る整流装置の構成を示す概念図である。図３Ａ及び図３Ｂは１つの半導体層積層体で、かつ、グランド接地された整流装置の構成を示す概念図、図３Ｃ及び図３Ｄは複数の半導体層積層体で、かつ、グランド接地された整流装置の構成を示す概念図、図３Ｅは実装にてグランド接地された整流装置の構成を示す平面図である。以下、それぞれ説明する。 3A to 3E are conceptual diagrams showing the configuration of the rectifier according to the third embodiment. FIG. 3A and FIG. 3B are conceptual diagrams showing the configuration of a rectifier with one semiconductor layer stack and grounded. FIGS. 3C and 3D are rectifiers with a plurality of semiconductor layer stacks and grounded. The conceptual diagram which shows the structure of an apparatus, FIG. 3E is a top view which shows the structure of the rectifier which was earth | grounded by mounting. Each will be described below.
　図３Ａに示すように、本実施形態に係る整流装置１００は、１つの半導体層積層体で構成される整流装置のチップ１０１と、複数のアノード電極１０２ｃと、複数のカソード電極１０３ｃと、アノードパッド１０４と、カソードパッド１０５と、保護膜１０６とを備えている。 As shown in FIG. 3A, the rectifier 100 according to the present embodiment includes a chip 101 of a rectifier constituted by one semiconductor layer stack, a plurality of anode electrodes 102c, a plurality of cathode electrodes 103c, and an anode pad. 104, a cathode pad 105, and a protective film 106 are provided.
　アノードパッド１０４及びカソードパッド１０５は、それぞれアノード電極１０２ｃ及びカソード電極１０３ｃと接続されている。また、チップ表面には、チップ１０１、アノード電極１０２ｃ、カソード電極１０３ｃ、アノードパッド１０４、カソードパッド１０５を覆うように保護膜１０６が形成されている。 The anode pad 104 and the cathode pad 105 are connected to the anode electrode 102c and the cathode electrode 103c, respectively. A protective film 106 is formed on the chip surface so as to cover the chip 101, the anode electrode 102c, the cathode electrode 103c, the anode pad 104, and the cathode pad 105.
　図３Ｂは、図３Ａに示した整流装置１００のＥ－Ｅ’線における断面図である。図３Ｂに示すように、基板１０７の上には、バッファ層１０８と、第１の窒化物半導体層１０９と、第２の窒化物半導体層１１０とが順次形成されている。第１の窒化物半導体層１０９の第２の窒化物半導体層１１０との界面近傍には、２ＤＥＧからなるチャネル（図示せず）が形成されている。ここで、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０は、本発明に係る半導体層積層体に相当する。なお、基板１０７の裏面には、図示されない基板電極（例えば、後述するリードフレーム）が形成され、その基板電極は、０Ｖ以上の電位（例えば、グランド）に接地される。 FIG. 3B is a cross-sectional view taken along line E-E ′ of rectifier 100 shown in FIG. 3A. As shown in FIG. 3B, a buffer layer 108, a first nitride semiconductor layer 109, and a second nitride semiconductor layer 110 are sequentially formed on the substrate 107. A channel (not shown) made of 2DEG is formed in the vicinity of the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110. Here, the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 correspond to a semiconductor layer stack according to the present invention. A substrate electrode (not shown) (for example, a lead frame described later) is formed on the back surface of the substrate 107, and the substrate electrode is grounded to a potential of 0 V or more (for example, ground).
　また、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０には、図３Ａに示すように、アノード電極１０２ｃとカソード電極１０３ｃとが、互いに間隔をおいて交互に複数配置されている。アノード電極１０２ｃとカソード電極１０３ｃとは、第２の窒化物半導体層１１０を貫通して第１の窒化物半導体層１０９の所定の深さまで形成されている。なお、アノード電極１０２ｃ及びカソード電極１０３ｃは、複数でなくても１つずつであってもよい。 In addition, in the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, as shown in FIG. 3A, a plurality of anode electrodes 102c and cathode electrodes 103c are alternately arranged at intervals. Yes. The anode electrode 102 c and the cathode electrode 103 c are formed to penetrate the second nitride semiconductor layer 110 to a predetermined depth of the first nitride semiconductor layer 109. In addition, the anode electrode 102c and the cathode electrode 103c may not be plural but one each.
　また、アノード電極１０２ｃの表面と、カソード電極１０３ｃの表面と、アノード電極１０２ｃとカソード電極１０３ｃとの間の部分の第２の窒化物半導体層１１０の表面は、窒化シリコン（ＳｉＮ）等からなる保護膜１０６に覆われている。 Further, the surface of the anode electrode 102c, the surface of the cathode electrode 103c, and the surface of the second nitride semiconductor layer 110 between the anode electrode 102c and the cathode electrode 103c are protected from silicon nitride (SiN) or the like. The film 106 is covered.
　アノード電極１０２ｃは、第１の窒化物半導体層１０９と第２の窒化物半導体層１１０との界面よりも下側で基板１０７に達しないアノードリセスに形成されており、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０（チャネル）とショットキー接触している。アノード電極１０２ｃはニッケル（Ｎｉ）、金（Ａｕ）からなる積層体とすればよい。 The anode electrode 102c is formed in an anode recess that does not reach the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 (channel) are in Schottky contact. The anode electrode 102c may be a laminate made of nickel (Ni) and gold (Au).
　カソード電極１０３ｃは、第１の窒化物半導体層１０９と第２の窒化物半導体層１１０との界面よりも下側で基板１０７に達しないカソードリセスに形成されており、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０（チャネル）とオーミック接触している。カソード電極１０３ｃは、２ＤＥＧと容易にオーミック接触するチタン（Ｔｉ）又はアルミニウム（Ａｌ）等を含む材料により形成すればよく、例えば、ＴｉとＡｌとの合金等とすればよい。 The cathode electrode 103c is formed in a cathode recess that does not reach the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer. 109 and the second nitride semiconductor layer 110 (channel) are in ohmic contact. The cathode electrode 103c may be formed of a material containing titanium (Ti) or aluminum (Al) that is easily in ohmic contact with 2DEG. For example, an alloy of Ti and Al may be used.
　また、図３Ｃに示すように、本実施形態の整流装置１００は、１つの半導体層積層体に代えて、複数の半導体層積層体で構成される整流装置のチップ１１１からなる構成であってもよい。具体的には、整流装置１００は、複数の半導体層積層体と、複数のアノード電極１０２ｃと、複数のカソード電極１０３ｃと、アノードパッド１０４と、カソードパッド１０５と、保護膜１０６とを備えている。 Further, as shown in FIG. 3C, the rectifying device 100 of the present embodiment may be configured by a chip 111 of a rectifying device including a plurality of semiconductor layer stacks instead of one semiconductor layer stack. Good. Specifically, the rectifying device 100 includes a plurality of semiconductor layer stacks, a plurality of anode electrodes 102c, a plurality of cathode electrodes 103c, an anode pad 104, a cathode pad 105, and a protective film 106. .
　アノードパッド１０４及びカソードパッド１０５は、それぞれアノード電極１０２ｃ及びカソード電極１０３ｃと接続されている。また、チップ表面には、チップ１０１、アノード電極１０２ｃ、カソード電極１０３ｃ、アノードパッド１０４、カソードパッド１０５を覆うように保護膜１０６が形成されている。複数の半導体層積層体は、本実施形態では、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０が３周期積層された構成である。 The anode pad 104 and the cathode pad 105 are connected to the anode electrode 102c and the cathode electrode 103c, respectively. A protective film 106 is formed on the chip surface so as to cover the chip 101, the anode electrode 102c, the cathode electrode 103c, the anode pad 104, and the cathode pad 105. In the present embodiment, the plurality of semiconductor layer stacks have a configuration in which the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 are stacked in three cycles.
　図３Ｄは、図３Ｃに示した整流装置１００のＦ－Ｆ’線における断面図である。図３Ｄに示すように、基板１０７の上には、バッファ層１０８と、第１の窒化物半導体層１０９と、第２の窒化物半導体層１１０とが３周期繰り返して交互に順次形成されている。第１の窒化物半導体層１０９の第２の窒化物半導体層１１０との界面近傍には、２ＤＥＧからなるチャネル（図示せず）が形成されている。なお、基板１０７の裏面には、図示されない基板電極（例えば、後述するリードフレーム）が形成され、その基板電極は、０Ｖ以上の電位（例えば、グランド）に接地される。 FIG. 3D is a cross-sectional view taken along line F-F ′ of the rectifier 100 shown in FIG. 3C. As shown in FIG. 3D, a buffer layer 108, a first nitride semiconductor layer 109, and a second nitride semiconductor layer 110 are alternately and sequentially formed on the substrate 107 in three cycles. . A channel (not shown) made of 2DEG is formed in the vicinity of the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110. A substrate electrode (not shown) (for example, a lead frame described later) is formed on the back surface of the substrate 107, and the substrate electrode is grounded to a potential of 0 V or more (for example, ground).
　また、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０には、図３Ｃに示すように、アノード電極１０２ｃとカソード電極１０３ｃとが、互いに間隔をおいて交互に複数配置されている。アノード電極１０２ｃ及びカソード電極１０３ｃは、第２の窒化物半導体層１１０を貫通して、第１の窒化物半導体層１０９の所定の深さまで形成されている。なお、アノード電極１０２ｃ及びカソード電極１０３ｃは、複数でなくても１つずつであってもよい。 In addition, in the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, as shown in FIG. 3C, a plurality of anode electrodes 102c and cathode electrodes 103c are alternately arranged at intervals. Yes. The anode electrode 102 c and the cathode electrode 103 c penetrate the second nitride semiconductor layer 110 and are formed to a predetermined depth of the first nitride semiconductor layer 109. In addition, the anode electrode 102c and the cathode electrode 103c may not be plural but one each.
　また、アノード電極１０２ｃの表面と、カソード電極１０３ｃの表面と、アノード電極１０２ｃとカソード電極１０３ｃとの間の部分の第２の窒化物半導体層１１０の表面は、窒化シリコン（ＳｉＮ）等からなる保護膜１０６に覆われている。 Further, the surface of the anode electrode 102c, the surface of the cathode electrode 103c, and the surface of the second nitride semiconductor layer 110 between the anode electrode 102c and the cathode electrode 103c are protected from silicon nitride (SiN) or the like. The film 106 is covered.
　アノード電極１０２ｃは、第１の窒化物半導体層１０９と第２の窒化物半導体層１１０との界面よりも下側で基板１０７に達しないアノードリセスに形成されており、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０（チャネル）とショットキー接触している。アノード電極１０２ｃはニッケル（Ｎｉ）、金（Ａｕ）からなる積層体とすればよい。 The anode electrode 102c is formed in an anode recess that does not reach the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110 (channel) are in Schottky contact. The anode electrode 102c may be a laminate made of nickel (Ni) and gold (Au).
　カソード電極１０３ｃは、第１の窒化物半導体層１０９と第２の窒化物半導体層１１０との界面よりも下側で基板１０７に達しないカソードリセスに形成されており、第１の窒化物半導体層１０９及び第２の窒化物半導体層１１０（チャネル）とオーミック接触している。カソード電極１０３ｃは、２ＤＥＧと容易にオーミック接触するチタン（Ｔｉ）又はアルミニウム（Ａｌ）等を含む材料により形成すればよく、例えば、ＴｉとＡｌとの合金等とすればよい。 The cathode electrode 103c is formed in a cathode recess that does not reach the substrate 107 below the interface between the first nitride semiconductor layer 109 and the second nitride semiconductor layer 110, and the first nitride semiconductor layer. 109 and the second nitride semiconductor layer 110 (channel) are in ohmic contact. The cathode electrode 103c may be formed of a material containing titanium (Ti) or aluminum (Al) that is easily in ohmic contact with 2DEG. For example, an alloy of Ti and Al may be used.
　このように、本実施形態によれば、基板電極が０Ｖ以上の電位（例えば、グランド）に接地されるので、カソード電極１０３ａからアノード電極１０２ａ端までの電界のかかり方を空間的に広げることでアノード電極１０２ａ端までの電界集中を緩和することが可能となり、整流装置１００の電流コラプスを低減することができる。 As described above, according to the present embodiment, the substrate electrode is grounded to a potential of 0 V or more (for example, ground). Therefore, by spatially expanding the manner in which the electric field is applied from the cathode electrode 103a to the end of the anode electrode 102a. Electric field concentration to the end of the anode electrode 102a can be relaxed, and current collapse of the rectifier 100 can be reduced.
　（第３の実施形態の変形例）
　次に、第３の実施形態の変形例について説明する。本変形例では、基板１０７が実装によりグランドに接地される（より厳密には、基板１０７が、接地用のグランド端子に接続されている）構成について説明する。 (Modification of the third embodiment)
Next, a modification of the third embodiment will be described. In this modification, a configuration in which the substrate 107 is grounded by mounting (more strictly speaking, the substrate 107 is connected to a ground terminal for grounding) will be described.
　図３Ｅに示すように、１つの半導体層積層体で構成される整流装置を備えたチップ１０１（あるいは複数の半導体層積層体で構成される整流装置を備えたチップ１１１）を、例えば、ＴＯ－２２０型パッケージからなるリードフレーム１１２にダイボンドする。 As shown in FIG. 3E, a chip 101 provided with a rectifier constituted by one semiconductor layer stack (or a chip 111 provided with a rectifier constituted by a plurality of semiconductor layer laminates) is, for example, TO- A die frame is bonded to a lead frame 112 made of a 220 type package.
　リードフレーム１１２には、アノード端子１１４ｄと、カソード端子１１５ｄと、グランド端子１１６とが形成されている。ここで、グランド端子１１６は、リードフレーム１１２として、基板１０７の裏面と接触しており、基板１０７の裏面に形成された本発明に係る基板電極に相当する。アノードパッド１０４とアノード端子１１４ｄとは、Ａｌからなるワイヤ１１３ｇで接続され、また、カソードパッド１０５とカソード端子１１５ｄとは、ワイヤ１１３ｈで接続されている。基板１０７を、独立端子としてのグランド端子１１６に接続しておくことで、基板１０７をグランド接地することが可能になる。 The lead frame 112 is formed with an anode terminal 114d, a cathode terminal 115d, and a ground terminal 116. Here, the ground terminal 116 is in contact with the back surface of the substrate 107 as the lead frame 112 and corresponds to the substrate electrode according to the present invention formed on the back surface of the substrate 107. The anode pad 104 and the anode terminal 114d are connected by a wire 113g made of Al, and the cathode pad 105 and the cathode terminal 115d are connected by a wire 113h. By connecting the substrate 107 to the ground terminal 116 as an independent terminal, the substrate 107 can be grounded.
　このような構成により、基板１０７を、独立端子としてのグランド端子１１６に接続しておくことで、グランド端子１１６が接地された場合に、カソード電極１０３ｃからアノード電極１０２ｃ端までの電界のかかり方を空間的に広げることでアノード電極１０２ｃ端までの電界集中を緩和することが可能となり、整流装置１００の電流コラプスをより低減することができる。 With such a configuration, the substrate 107 is connected to the ground terminal 116 as an independent terminal, so that when the ground terminal 116 is grounded, an electric field is applied from the cathode electrode 103c to the anode electrode 102c end. By spatially expanding, the electric field concentration to the end of the anode electrode 102c can be relaxed, and the current collapse of the rectifier 100 can be further reduced.
　なお、本発明は、上記した実施の形態に限定されるものではなく、本発明の要旨を逸脱しない範囲内で種々の改良、変形を行ってもよい。 Note that the present invention is not limited to the above-described embodiment, and various improvements and modifications may be made without departing from the gist of the present invention.
　例えば、上記した整流装置において、アノード電極は、チャネルとショットキー接触するのであれば、どのような材料を用いてもよい。また、カソード電極は、チャネルとオーミック接触するのであれば、どのような材料を用いてもよい。 For example, in the rectifier described above, any material may be used for the anode electrode as long as it is in Schottky contact with the channel. The cathode electrode may be made of any material as long as it is in ohmic contact with the channel.
　また、本発明に係る整流装置には、上記実施形態における任意の構成要素を組み合わせて実現される別の実施形態や、実施形態に対して本発明の主旨を逸脱しない範囲で当業者が思いつく各種変形を施して得られる変形例や、本発明に係る整流装置を備えた各種デバイスなども本発明に含まれる。例えば、本発明に係る整流装置を備えた電源回路、電源回路を備えたパワーデバイス等も本発明に含まれる。 In addition, the rectifier according to the present invention includes other embodiments realized by combining arbitrary components in the above-described embodiments, and various types conceived by those skilled in the art without departing from the gist of the present invention with respect to the embodiments. Modifications obtained by applying modifications and various devices including the rectifier according to the present invention are also included in the present invention. For example, a power supply circuit including the rectifier according to the present invention, a power device including the power supply circuit, and the like are also included in the present invention.
　本発明に係る整流装置は、スイッチング電源回路等に用いるパワーデバイスとして有用である。 The rectifier according to the present invention is useful as a power device used for a switching power supply circuit or the like.
１００　整流装置
１０１、１１１　チップ
１０２ａ、１０２ｂ、１０２ｃ　アノード電極
１０３ａ、１０３ｂ、１０３ｃ　カソード電極
１０４　アノードパッド
１０５　カソードパッド
１０６　保護膜
１０７　基板
１０８　バッファ層
１０９　第１の窒化物半導体層
１１０　第２の窒化物半導体層
１１２　リードフレーム（基板電極）
１１３ａ、１１３ｂ、１１３ｃ、１１３ｄ、１１３ｅ、１１３ｆ、１１３ｇ、１１３ｈ　ワイヤ
１１４ａ、１１４ｂ、１１４ｃ、１１４ｄ　アノード端子
１１５ａ、１１５ｂ、１１５ｃ、１１５ｄ　カソード端子
１１６　グランド端子 100 Rectifier 101, 111 Chips 102a, 102b, 102c Anode electrodes 103a, 103b, 103c Cathode electrode 104 Anode pad 105 Cathode pad 106 Protective film 107 Substrate 108 Buffer layer 109 First nitride semiconductor layer 110 Second nitride semiconductor Layer 112 Lead frame (substrate electrode)
113a, 113b, 113c, 113d, 113e, 113f, 113g, 113h Wire 114a, 114b, 114c, 114d Anode terminal 115a, 115b, 115c, 115d Cathode terminal 116 Ground terminal

Claims (6)

  1. 　基板の主面の上に形成された第１の窒化物半導体層と、該第１の窒化物半導体層の上に形成され、かつ、前記第１の窒化物半導体層に比べてバンドギャップが大きい第２の窒化物半導体層とを有し、前記基板の主面と平行な方向に電子が走行するチャネルを有する半導体層積層体と、
    　前記半導体層積層体に形成され、前記半導体層積層体とショットキー接触するアノード電極と、
    　前記半導体層積層体に前記アノード電極と所定の間隔をおいて形成され、前記半導体層積層体とオーミック接触するカソード電極と、
    　前記基板の裏面に形成された基板電極とを備え、
    　前記基板電極は０Ｖ以上の電位に接地される
    整流装置。     A first nitride semiconductor layer formed on the main surface of the substrate, and formed on the first nitride semiconductor layer, and has a larger band gap than the first nitride semiconductor layer A semiconductor layer stack including a second nitride semiconductor layer and a channel in which electrons travel in a direction parallel to the main surface of the substrate;
    An anode electrode formed in the semiconductor layer stack and in Schottky contact with the semiconductor layer stack;
    A cathode electrode formed in the semiconductor layer stack at a predetermined interval from the anode electrode and in ohmic contact with the semiconductor layer stack;
    A substrate electrode formed on the back surface of the substrate,
    A rectifier in which the substrate electrode is grounded to a potential of 0V or higher.
  2. 　前記基板電極は、前記アノード電極と実質的に同電位となるように接続されている
    請求項１に記載の整流装置。     The rectifier according to claim 1, wherein the substrate electrode is connected so as to have substantially the same potential as the anode electrode.
  3. 　前記基板電極は、前記カソード電極と実質的に同電位となるように接続されている
    請求項１に記載の整流装置。     The rectifier according to claim 1, wherein the substrate electrode is connected so as to have substantially the same potential as the cathode electrode.
  4. 　前記基板電極は、グランドと実質的に同電位となるように接続される
    請求項１に記載の整流装置。     The rectifier according to claim 1, wherein the substrate electrode is connected so as to have substantially the same potential as the ground.
  5. 　前記基板電極は、リードフレームである
    請求項１に記載の整流装置。     The rectifier according to claim 1, wherein the substrate electrode is a lead frame.
  6. 　前記半導体層積層体は、前記第１の窒化物半導体層と前記第２の窒化物半導体層とを交互に複数層積層して形成されている
    請求項１～５のいずれか１項に記載の整流装置。      6. The semiconductor layer stack according to claim 1, wherein the semiconductor layer stack is formed by alternately stacking a plurality of the first nitride semiconductor layers and the second nitride semiconductor layers. Rectifier.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021217875A1 (en) * 2020-04-27 2021-11-04 华南理工大学 Gan/two-dimensional ain heterojunction rectifier on silicon substrate and preparation method therefor

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62193175A (en) * 1986-02-19 1987-08-25 Sanyo Electric Co Ltd Schottky barrier semiconductor device
JP2009117485A (en) * 2007-11-02 2009-05-28 Panasonic Corp Nitride semiconductor device
JP2010109086A (en) * 2008-10-29 2010-05-13 Toshiba Corp Nitride semiconductor element
WO2011010419A1 (en) * 2009-07-23 2011-01-27 パナソニック株式会社 Nitride semiconductor device
WO2011027490A1 (en) * 2009-09-03 2011-03-10 パナソニック株式会社 Nitride semiconductor device
JP2011124258A (en) * 2009-12-08 2011-06-23 Furukawa Electric Co Ltd:The Nitride-based diode

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62193175A (en) * 1986-02-19 1987-08-25 Sanyo Electric Co Ltd Schottky barrier semiconductor device
JP2009117485A (en) * 2007-11-02 2009-05-28 Panasonic Corp Nitride semiconductor device
JP2010109086A (en) * 2008-10-29 2010-05-13 Toshiba Corp Nitride semiconductor element
WO2011010419A1 (en) * 2009-07-23 2011-01-27 パナソニック株式会社 Nitride semiconductor device
WO2011027490A1 (en) * 2009-09-03 2011-03-10 パナソニック株式会社 Nitride semiconductor device
JP2011124258A (en) * 2009-12-08 2011-06-23 Furukawa Electric Co Ltd:The Nitride-based diode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021217875A1 (en) * 2020-04-27 2021-11-04 华南理工大学 Gan/two-dimensional ain heterojunction rectifier on silicon substrate and preparation method therefor

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