JP5841624B2 - Nitride semiconductor device - Google Patents

Description

  The present invention relates to a nitride semiconductor device, for example, a nitride semiconductor device that has a heterojunction of a nitride semiconductor and is used for power control switching.

  Switching elements used for power control are required to have a low on-resistance and a high breakdown voltage. On the other hand, the semiconductor switching element has a trade-off in which the breakdown voltage is lowered when the on-resistance is lowered, and there is a withstand voltage limit specific to the semiconductor material used for a desired on-resistance.

Since a nitride semiconductor such as GaN has a larger band gap than Si, the trade-off between the on-resistance and withstand voltage inherent to the material can be dramatically improved. Therefore, a switching element made of a nitride semiconductor is expected to realize a high breakdown voltage with a low on-resistance compared to a conventional switching element made of Si. Then, as a switching element made of a nitride semiconductor, a field effect transistor (HFET) using a heterojunction of n-AlGaN and i-GaN, or a Schottky Barrier Diode (SBD) using GaN. ) Is promising. (Patent Document 1, Non-Patent Documents 1 and 2)
On the other hand, an element used for power control can withstand the application of a high voltage, and of course, when an overvoltage occurs due to noise superimposed on the applied voltage, the voltage applied to the subsequent circuit is large. It is necessary to clamp the voltage so that it does not become too much, and to protect passive elements and other switching elements in the circuit. That is, a function of clamping a voltage by passing a certain amount of current against an overvoltage is indispensable.

  However, a switching element using a nitride semiconductor as a material has a problem that when an avalanche breakdown occurs when a high voltage is applied, an overcurrent immediately leading to destruction of the element flows. That is, there is a problem that a voltage clamping function using a current generated by avalanche breakdown cannot be provided.

JP 2007-180143 A

Japanese Journal of Applied Physics Vol.44, No.9A, 2005, pp.6385-6388 Proceeding of 2004 International Symposiumon Power Semiconductor Devices & ICs, pp.319-322

  In view of the above problems, an object of the present invention is to provide a nitride semiconductor device having a voltage clamping function.

According to one aspect of the present invention, a first layer made of a first nitride semiconductor and a second layer provided on the first layer and having a band gap larger than that of the first nitride semiconductor. A second layer made of a nitride semiconductor; a first electrode electrically connected to the second layer and extending in a first direction; and the second electrode spaced apart from the first electrode. A plurality of second electrodes provided on the layer and provided in the first direction, and provided between the second electrodes on the second layer and directed toward the first electrode. A floating electrode having a portion protruding from the second electrode, the second electrode, and a third electrode provided on the second layer so as to be separated from the floating electrode. A nitride semiconductor device is provided.

  According to the present invention, a nitride semiconductor device having a voltage clamping function can be realized.

FIG. 2 is an electrode pattern diagram and a cross-sectional view schematically showing the configuration of the nitride semiconductor SBD according to the first embodiment of the present invention. It is the electrode pattern figure and sectional view which show typically the composition of the nitride semiconductor HFET according to the 2nd embodiment of the present invention. It is an electrode pattern figure of nitride semiconductor HFET according to a 2nd embodiment of the present invention. It is the electrode pattern figure and sectional view which show typically the composition of the nitride semiconductor HFET according to the 2nd embodiment of the present invention. It is the electrode pattern figure and sectional view which show typically the composition of the nitride semiconductor HFET according to the 3rd embodiment of the present invention. It is the electrode pattern figure and sectional drawing which show typically the structure of the nitride semiconductor HFET according to the 4th Embodiment of this invention. It is the electrode pattern figure and sectional view which show typically the composition of the nitride semiconductor HFET according to the 5th embodiment of the present invention. It is the electrode pattern figure and sectional view which show typically the composition of the nitride semiconductor HFET according to the 5th embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same parts in the drawings are denoted by the same reference numerals, detailed description thereof will be omitted as appropriate, and different parts will be described as appropriate.

(First embodiment)
FIG. 1 is a schematic diagram showing a configuration of a nitride semiconductor SBD according to the first embodiment of the present invention. FIG. 1A is a schematic diagram showing an electrode pattern of an SBD, and FIGS. 1B and 1C are schematic diagrams showing an AA section and a BB section of the SBD, respectively.

  The nitride semiconductor SBD according to the present embodiment is provided on the i-GaN layer 1 that is the first layer made of the first nitride semiconductor and the i-GaN layer 1, and has a larger band gap than GaN. An i-AlGaN layer 2 that is a second layer made of the second nitride semiconductor, a cathode electrode 14 that is a first electrode electrically connected to the i-AlGaN layer 2, and an i-AlGaN layer. An anode electrode 13 which is a second electrode provided in parallel with the cathode electrode 14 in the first direction and a floating electrode 6 provided on the i-AlGaN layer 2 are provided.

  Furthermore, the floating electrode 6 has a portion 6a sandwiched between the anode electrodes 13 in a second direction orthogonal to the first direction, and a portion 6b protruding from the anode electrode 13 toward the cathode electrode 14. ing. In FIG. 1A, the first direction means the horizontal direction in the figure, and the second direction means the vertical direction.

  Next, the detail of said structure is demonstrated. The cathode electrode 14 formed on the nitride semiconductor substrate 21 in which the i-GaN layer 1 and the i-AlGaN layer 2 are stacked is electrically connected to the upper surface of the i-AlGaN layer 2. That is, an ohmic contact is formed between the cathode electrode 14 and the i-AlGaN layer 2. On the other hand, the anode electrode 13 provided at a position facing the cathode electrode 14 forms a Schottky contact with the i-AlGaN layer 2.

  The i-GaN layer 1 and the i-AlGaN layer 2 according to the present embodiment are undoped high-resistance layers, but the i-AlGaN layer 2 can be implemented as an n-AlGaN layer that is n-type doped. Further, an i-AlGaN layer having a band gap smaller than that of the i-AlGaN layer 2 can be used instead of the i-GaN layer 1.

  When the SBD is turned on, the Schottky contact of the anode electrode 13 is forward-biased, and the anode electrode 13 to the cathode electrode 14 pass through the channel 23 formed at the heterointerface between the i-GaN layer 1 and the i-AlGaN layer 2. Current flows to On the other hand, at the heterointerface between the i-GaN layer 1 and the i-AlGaN layer 2, electrons are supplied from the i-AlGaN layer 2 functioning as a barrier layer to the i-GaN layer side to form a high-concentration two-dimensional electron gas. Has been. Thereby, the resistance of the channel 23 is reduced, and a low on-resistance can be realized.

  Furthermore, as shown in the electrode pattern of FIG. 1A, the anode electrode 13 has a short electrode portion 22 in which the electrode length in the direction facing the cathode electrode 14 is relatively shortened. Further, the floating electrode 6 is provided at a position close to the short electrode portion 22 between the anode electrode 13 and the cathode electrode 14. When a reverse bias is applied between the anode electrode 13 and the cathode electrode 14 during the SBD off operation, the floating potential of the floating electrode 6 having the portion 6b protruding from the anode electrode 13 toward the cathode electrode 14 is It changes according to the bias voltage. At this time, when a certain high voltage lower than the breakdown voltage of the Schottky contact of the anode electrode 13 is applied, the potential barrier under the anode electrode 13 close to the floating electrode 6 is pushed down, current flows, and the voltage is clamped. Is done. That is, by forming the floating electrode 6, it is possible to realize a function of clamping the voltage at a voltage lower than the withstand voltage of the SBD. In order to ensure the effect of depressing the potential barrier of the anode electrode 13 due to the change in the potential of the floating electrode 6, the distance d between the floating electrode 6 and the anode electrode 13 is set to be longer than the electrode length Lg of the short electrode portion 22. It is desirable to shorten the length. The floating electrode 6 is preferably a Schottky contact with the i-AlGaN layer 2 so as not to be a leakage current path.

  Further, as shown in FIG. 1A, the anode electrode 13 is formed in a comb shape having the short electrode portion 22 as a recess. On the other hand, the floating electrode 6 has a portion 6 a that is nested in the recess and is sandwiched between the anode electrodes 13. As a result, when the potential of the floating electrode 6 changes, only the potential barrier of the short electrode portion 22 is pushed down, so that the current path at the time of voltage clamping is limited to the periphery of the short electrode portion 22 and the element is destroyed. Excessive current can be prevented. That is, the distance d between the floating electrode 6 and the anode electrode 13 (short electrode portion 22) is preferably shorter than the recess width ΔLg of the recess of the anode electrode 13.

(Second Embodiment)
FIG. 2 is an electrode pattern diagram and a cross-sectional view schematically showing the configuration of a nitride semiconductor HFET according to the second embodiment of the present invention. 2A is a schematic diagram showing an electrode pattern of the HFET, and FIGS. 2B and 2C are schematic diagrams showing an AA cross section and a BB cross section of the HFET, respectively.

  In the nitride semiconductor HFET shown in FIG. 2, a source electrode 3 and a drain electrode 4 electrically connected to the i-AlGaN layer 2 as a barrier layer, and a gate electrode 5 in Schottky contact with the i-AlGaN layer 2 are formed. ing. The source electrode 3 is a third electrode and is juxtaposed with the drain electrode 4 which is the first electrode in the first direction. The gate electrode 5 as the second electrode is provided between the source electrode 3 and the drain electrode 4. The gate length of the gate electrode 5 changes so as to have the short electrode portion 22 having a short gate length. On the other hand, the floating electrode 6 is provided close to the short electrode portion 22, and has a portion 6 a sandwiched between the gate electrodes 5 and a portion 6 b protruding toward the drain electrode 4 in the second direction. In FIG. 2A, the first direction means the horizontal direction in the figure, and the second direction means the vertical direction.

  If the voltage applied between the gate electrode 5 and the source electrode 3 is less than or equal to the gate threshold voltage, the channel 23 under the gate electrode 5 is depleted and the HFET is off. At this time, when a voltage is applied between the source electrode 3 and the drain electrode 4, the potential of the floating electrode 6 changes according to the drain voltage. When a certain high voltage lower than the breakdown voltage between the source and drain is applied, the potential of the floating electrode 6 is changed, the potential barrier of the short electrode portion 22 is lowered, and a two-dimensional electron gas is formed in the channel 23 to cause a current. Begins to flow. Thereby, a voltage clamp function can be provided.

  By simply forming a portion having a short gate length (short electrode portion 22) in the gate electrode 5, it is possible to provide a function of flowing a current when a high voltage is applied due to the short channel effect. However, in order to make the voltage clamp function effectively, it is necessary to make a large difference in the gate length between the portion causing the short channel effect and the portion not causing the short channel effect. On the other hand, in the structure of this embodiment shown in FIG. 2, the portion 6 b of the floating electrode 6 that protrudes from the gate electrode 5 toward the drain electrode 4 is close to the drain electrode 4, so that the potential of the floating electrode 6 is concentrated. And the voltage clamp can function effectively. That is, since the clamp voltage can be designed by changing the length of the floating electrode 6, the degree of design freedom can be increased. Furthermore, it becomes possible to shorten the gate length in a portion where the short channel effect is not caused, and the on-resistance can be lowered. In addition, by shortening the gate length, the gate capacitance can be reduced, and the effect of enabling high-speed switching can be obtained.

  Further, when a voltage is applied to the drain electrode 4, the electric field is concentrated at the end of the gate electrode 5 facing the drain electrode 4, but the electric field is also concentrated at the end of the floating electrode 6 facing the drain electrode 4. Thereby, the location where the electric field concentrates is dispersed, and the peak value of the concentrated electric field is reduced. As a result, an increase in on-resistance due to current collapse peculiar to the nitride semiconductor HFET is less likely to occur, and characteristic variations such as a change in gate threshold voltage and an increase in gate leakage current are less likely to occur, thereby improving reliability. it can.

  The comb-shaped electrode pattern shown in FIGS. 1 and 2 has a rectangular stepped form. For example, as shown in FIG. 3, the gate length is continuously increased by tapering a portion having a long gate length. Even changing modes can be implemented. In the electrode pattern shown in FIG. 3, the floating electrode 6 has a tapered shape corresponding to the shape of the gate electrode 5. As a result, the coupling through the stray capacitance is strengthened by the wide end portion 6c facing the drain electrode 4, while the narrow end portion 6d is opposed to the gate electrode 5 and the current at the time of voltage clamping is increased. Can be limited. That is, in the embodiment shown in FIG. 2, when the current at the time of voltage clamping flows too much, the current flowing at the time of voltage clamping can be reduced while maintaining the coupling with the drain electrode 4.

  FIG. 4 is an electrode pattern diagram and a cross-sectional view schematically showing the configuration of a nitride semiconductor HFET according to a modification of the second embodiment. 4A is a schematic diagram showing an electrode pattern of an HFET, and FIGS. 4B and 4C are schematic diagrams showing an AA cross section and a BB cross section of the HFET, respectively.

  As shown in FIG. 4A, in the present embodiment, a plurality of gate electrodes 5 are provided apart from each other between the source electrode 3 and the drain electrode 4. The floating electrode 6 has a portion 6 a sandwiched between the gate electrodes 5 and a portion 6 b protruding from the gate electrode 5 toward the drain electrode 4. The plurality of gate electrodes 5 are connected by a wiring (not shown), and a common gate voltage is applied during the operation of the HFET. By using such an electrode pattern, the gate capacitance can be reduced, and high-speed switching characteristics can be obtained.

  On the other hand, as shown in FIGS. 4B and 4C, a recess 25 is formed in the i-AlGaN layer 2 below the gate electrode 5 and the floating electrode 6. With such a recess structure, the channel 23 is depleted by the built-in potential of the Schottky barrier of the gate electrode 5 and the floating electrode 6, and a normally-off operation is realized.

  In the HFET shown in FIG. 4, when a voltage is applied between the source and drain with the gate bias being 0 V, the potential of the floating electrode 6 provided between the gate electrodes 5 changes according to the drain voltage. . As described above, when a certain drain voltage is applied, the potential of the gate electrode 5 is lowered by the potential of the floating electrode 6, and a two-dimensional electron gas is formed in the depleted channel 23 so that current flows. become. In this embodiment, current flows at the end of the gate electrode 5 adjacent to the portion 6a sandwiched between the gate electrodes 5, and the voltage between the source and drain is clamped. That is, even in this embodiment in which the gate electrode 5 is not provided between the floating electrode 6 and the source electrode 3, it is possible to provide a voltage clamping function. In addition to the recess structure described above, it is also possible to realize a normally-off operation of the HFET by using a configuration in which a p-type layer is selectively provided under the gate electrode 5, and even in that case, the above embodiment is implemented. can do.

  In a conventional nitride semiconductor HFET that does not include the floating electrode 6, when a high voltage is applied between the source and drain, the channel 23 becomes a high electric field and avalanche breakdown occurs. When avalanche breakdown occurs, electron-hole pairs are generated, and electrons accelerated by the electric field flow into the drain electrode 4. On the other hand, although the holes move to the source electrode 3 side, the resistance of the source contact formed in the i-AlGaN layer 2 or the n-AlGaN layer is high, so that the holes cannot quickly flow into the source electrode 3 and enter the channel 23. Accumulated in. In the channel 23 in which holes are accumulated, a higher electric field is generated, the avalanche breakdown becomes stronger, and further electron / hole pairs are generated. Due to such a feedback action, the element is destroyed even when an instantaneous high voltage is applied. As a method for avoiding such destruction, it is conceivable to provide a p-layer for discharging holes and connect it to the source electrode 3. However, the device structure becomes complicated and design becomes difficult. Therefore, it is effective to provide a function of clamping the voltage by the embodiment in which the floating electrode 6 shown in FIGS. 2 to 4 is added.

(Third embodiment)
FIG. 5 is an electrode pattern diagram and a cross-sectional view schematically showing the configuration of the nitride semiconductor HFET according to the third embodiment of the present invention. FIG. 5A is a schematic diagram showing an electrode pattern of an HFET, and FIGS. 5B and 5C are schematic diagrams showing an AA section and a BB section of the HFET, respectively.

  In the nitride semiconductor HFET according to this embodiment, as shown in FIGS. 5A and 5C, the gate electrode 5 as the second electrode covers a part of the floating electrode 6 through the insulating film 7. It is formed as follows. On the other hand, as shown in FIG. 5B, the portion of the gate electrode 5 that does not overlap the floating electrode 6 is in contact with the i-AlGaN layer 2 to form a Schottky contact. The potential of the floating electrode 6 is determined by the capacitance between the gate electrode 5 and the floating electrode 6 and the capacitance between the floating electrode 6 and the drain electrode 4. Since the gate electrode 5 and the floating electrode 6 overlap with each other via the insulating film 7, the capacitance between the gate electrode 5 and the floating electrode 6 increases, and the clamp voltage can be easily controlled.

(Fourth embodiment)
FIG. 6 is an electrode pattern diagram and a cross-sectional view schematically showing the configuration of the nitride semiconductor HFET according to the fourth embodiment of the present invention. FIG. 6A is a schematic diagram showing an electrode pattern of an HFET, and FIGS. 6B and 6C are schematic diagrams showing an AA section and a BB section of the HFET, respectively.

  In the nitride semiconductor HFET according to the present embodiment, as shown in FIGS. 6B and 6C, the first electrode that covers the surface of the floating electrode 6 and the AlGaN layer 2 between the gate electrode 5 and the drain electrode 4 is provided. A field insulating film 8 is formed. A first field plate electrode 9 connected to the gate electrode 5 and arranged to extend toward the drain electrode 4 on the first field insulating film 8 is formed. As a result, the electric field concentration at the end of the gate electrode 5 facing the drain electrode 4 is alleviated, and an increase in on-resistance due to current collapse, a variation in gate threshold voltage, and an increase in leakage current can be suppressed. As described in the third embodiment, since the first field plate electrode 9 connected to the gate electrode 5 is formed so as to cover the floating electrode 6, the capacitance between the gate electrode 5 and the floating electrode 6 is increased. The effect of increasing the clamp voltage can be obtained.

(Fifth embodiment)
FIG. 7 is an electrode pattern diagram and a cross-sectional view schematically showing the configuration of a nitride semiconductor HFET according to the fifth embodiment of the present invention. FIG. 7A is a schematic diagram illustrating an electrode pattern of an HFET, and FIGS. 7B and 7C are schematic diagrams illustrating an AA cross section and a BB cross section of the HFET, respectively.

  In the nitride semiconductor HFET according to the present embodiment, as shown in FIG. 7B, the nitride semiconductor HFET is connected to the gate electrode 5 and arranged on the first field insulating film 8 so as to extend toward the drain electrode 4. One field plate electrode 9 is formed. Further, as shown in FIGS. 7A and 7C, a second field plate electrode 10 formed so as to be separated from the first field plate electrodes 9 and 9b and connected to the floating electrode 6 is disposed. Has been. The second field plate electrode 10 is arranged on the first field insulating film 8 so as to extend from the floating electrode 6 toward the drain electrode 4.

  Thereby, in addition to the effect of the first field plate electrode 9 described above, the effect of suppressing the electric field concentration of the floating electrode 6 at the end facing the drain electrode 4 is obtained. That is, by arranging the second field plate electrode 10, it is possible to suppress an increase in on-resistance, a gate threshold voltage variation, and an increase in leakage current due to current collapse. Then, as shown in FIG. 7A, the second field plate electrode 10 connected to the floating electrode 6 is brought closer to the drain electrode 4 than the first field plate electrode 9, so that the floating electrode 6 can be reliably connected. The potential barrier in the vicinity can be lowered, and the clamp voltage can be easily controlled.

  FIG. 8 is an electrode pattern diagram and a cross-sectional view schematically showing the configuration of a nitride semiconductor HFET according to a modification of the fifth embodiment. FIG. 8A is a schematic diagram showing an electrode pattern of an HFET, and FIGS. 8B and 8C are schematic diagrams showing an AA section and a BB section of the HFET, respectively.

  In the nitride semiconductor HFET according to the present embodiment, in addition to the configuration shown in FIG. 7, a second field insulating film 11 is provided and connected to the source electrode 3 as shown in FIGS. 8B and 8C. The third field plate electrode 12 is disposed on the second field insulating film 11. Thereby, the electric field concentration occurring at the end portions of the first and second field plate electrodes facing the drain electrode 4 can be suppressed, and further, the ON resistance increase due to current collapse, the gate threshold voltage fluctuation, and the leakage current Can be suppressed.

  The first to fifth embodiments of the present invention and the modifications thereof have been described above, but the present invention is not limited to these embodiments. That is, other than this, all modifications that can easily be considered by engineers in the field are included in the scope of the present invention.

  For example, a specific example in which the channel layer is a GaN layer and the barrier layer is an AlGaN layer has been illustrated. However, for example, an InGaN layer for the channel layer and a GaN layer for the barrier layer, or an AlGaN layer for the channel layer It is also possible to carry out using a combination of other nitride semiconductors such as those using an AlN layer as a layer or barrier layer, or a combination of nitride semiconductor layers in which the band gap is adjusted by changing the proportion of constituent elements. It is also possible to divert the structure of the gate electrode of the HFET shown in FIGS. 3 to 7 to the anode electrode of the HSBD shown in FIG.

  In general, the gate threshold voltage of the HFET is negative, and it becomes a normally-on type device. For this reason, the above-described embodiment is applied under a state where the gate voltage is applied to the negative side, and the voltage clamping is performed. That is, the present invention can be implemented with either a normally-off type element or a normally-on type element regardless of the gate threshold voltage. Further, although the description has been made using the single-stage source field plate structure for increasing the withstand voltage of the HFET, the present invention is not limited to this, and other high withstand voltage structures such as a drain field plate structure, a multi-stage field plate structure, and a RESURF structure are used. However, it can be implemented.

  Moreover, although the specific example mentioned above illustrated the case where it applied to SBD and HFET, the field effect using nitride semiconductors, such as MIS-HFET, MESFET, JFET etc. which were made into the gate insulated gate structure other than these, for example Any element can be implemented. In the case of the MIS gate structure, it is desirable that the floating electrode is also formed on the gate insulating film in order to reduce the leakage current through the floating electrode. Further, although the supporting substrate used for forming the GaN layer and the AlGaN layer is not shown, the present invention can be implemented with a GaN substrate, a SiC substrate, a sapphire substrate, a Si substrate, and the like, and is not limited by the supporting substrate material.

  In the present specification, “nitride semiconductor” means BxInyAlzGa (1-xyz) N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, 0 ≦ x + y + z ≦ 1. ) And a mixed crystal containing phosphorus (P), arsenic (As), etc. in addition to N (nitrogen).

DESCRIPTION OF SYMBOLS 1 GaN layer 2 AlGaN layer 3 Source electrode 4 Drain electrode 5 Gate electrode 6 Floating electrode 7 Insulating film 8 Field insulating film 9 Field plate electrode 10 Field plate electrode 13 Anode electrode 14 Cathode electrode 22 Short electrode part

Claims (2)

A first layer made of a first nitride semiconductor;
A second layer formed on the first layer and made of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor;
A first electrode electrically connected to the second layer and extending in a first direction;
A plurality of second electrodes provided on the second layer and spaced apart from the first electrode, the plurality of second electrodes being provided in the first direction;
A floating electrode provided between the second electrodes on the second layer and having a portion protruding from the second electrode toward the first electrode;
A third electrode provided on the second layer and spaced apart from the second electrode and the floating electrode;
A nitride semiconductor device comprising:   The thickness of the second layer located between the first layer and the second electrode and the floating electrode is such that the thickness of the second layer located between the first layer and the first electrode is The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device is thinner than the thickness of the second layer.

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