JP6280434B2 - Insulated gate field effect transistor using nitride semiconductor - Google Patents

Description

  In this specification, the gate electrode faces the nitride semiconductor through the gate insulating film, and the depletion layer that has spread in the nitride semiconductor contracts by applying a voltage higher than the threshold value to the gate electrode, so that the source and drain Disclosed is a field effect transistor with reduced resistance between them.

  A field effect transistor having a nitride semiconductor as a channel region is likely to be normally on due to a negative threshold voltage. Japanese Patent Application Laid-Open No. H10-228667 describes a technique for raising the threshold voltage to a positive voltage to make it normally off.

As shown in FIG. 11, the field effect transistor described in Patent Document 1 has a heterojunction structure of a GaN layer 12 and an AlGaN layer 10, and the gate electrode 2 is connected to the heterojunction interface via the gate insulating film 4. It has a structure opposite to.
In order to raise the threshold voltage to a positive voltage and make it normally off, in the technique of Patent Document 1, a recess reaching an intermediate depth from the top surface of the AlGaN layer 10 is provided, and fluorine ions are implanted from the bottom surface of the recess to fix the negative voltage. A region 14 into which charges are introduced is formed. In the negative fixed charge introduction region 14, it becomes difficult to invert to the n-type, and the threshold voltage is raised to a positive voltage. Reference numeral 6 is a source electrode, and 16 is a drain electrode.
In the technique of Patent Document 1, the threshold voltage is raised to a positive voltage by introducing a negative fixed charge into the channel region.

JP 2012-124442 A

The technique of Patent Document 1 is a useful technique for raising the threshold voltage of a field effect transistor using a nitride semiconductor to a positive voltage to make it normally off, but it increases the on-resistance. In the structure of FIG. 11, electrons move in the left-right direction in the negative fixed charge introduction region 14 and a current flows. When electrons move in the negative fixed charge introduction region 14, the electrons are scattered by ionized impurities. Electron mobility decreases and on-resistance increases.
The present specification discloses a technique for raising the threshold voltage toward the positive side while suppressing an increase in on-resistance. Here, “pulling up toward the plus side” is not limited to the case where the result is a plus voltage. It is required to raise the threshold voltage toward the positive side, and even if the result of the increase remains at a negative voltage, it may be advantageous to raise the threshold voltage toward the positive side. The technique described in this specification is also a useful technique in that case.

In this specification, an insulated gate field effect transistor in which a channel region is formed using a nitride semiconductor is disclosed. That is, the gate electrode is opposed to the channel region (formed of a nitride semiconductor) through the gate insulating film, and the depletion layer extending in the channel region is contracted by the potential applied to the gate electrode, so that the channel resistance is reduced. Disclosed is an insulated gate field effect transistor that utilizes the decreasing phenomenon.
In the insulated gate field effect transistor disclosed in this specification, when a channel region is observed along a direction in which a gate electrode extends (referred to as a longitudinal direction in this specification), a negative fixed charge is introduced. Regions (referred to as negative fixed charge introduction regions in this specification) and regions where negative fixed charges are not introduced (referred to as non-introduction regions in this specification) appear alternately.

When the channel region facing the gate electrode through the gate insulating film is observed along the longitudinal direction of the gate electrode, the negative fixed charge introduction region and the non-introduction region appear alternately, while suppressing an increase in on-resistance It becomes possible to raise the threshold voltage toward the positive side. The reason is considered as follows.
(1) In a state where a voltage higher than the threshold is not applied to the gate electrode (a state where the voltage of the gate electrode is lower than the threshold), a depletion layer spreads in the longitudinal direction from the negative fixed charge introduction region into the non-introduction region. When the voltage applied to the gate electrode is increased, the depletion layer contracts and the channel resistance decreases. When the negative fixed charge introduction region exists, in order to shrink the depletion layer extending from the negative fixed charge introduction region to the non-introduction region, it is necessary to raise the voltage applied to the gate electrode toward the positive side. When a structure in which negative fixed charge introduction regions and non-introduction regions appear alternately is adopted, the threshold voltage is raised toward the positive side.
(2) When a voltage equal to or higher than the threshold is applied to the gate electrode, the depletion layer that has spread to the non-introduced region contracts to form an electron movement path. A channel is formed in the non-introduced region. Electron mobility is high in the non-introduction region, and a low on-resistance can be obtained when a channel is formed in the non-introduction region. Although it is difficult to form a channel in the negative fixed charge introduction region and this may cause a reduction in the cross-sectional area of the electron movement path, an increase in on-resistance due to partial provision of the negative fixed charge introduction region is shown in FIG. When the increase in the on-resistance due to the structure (the structure in which the negative fixed charge introduction region 14 is formed without any break in the longitudinal direction) is compared, the increase in the former is less than the increase in the latter, and the increase in the on-resistance is suppressed within an allowable value. can do.

  As a field effect transistor using a nitride semiconductor, a HEMT (High Mobility Electron Transistor) using a heterojunction structure of a nitride semiconductor having a narrow band gap and a nitride semiconductor having a wide band gap is well known. The scope of technology is not limited to HEMT. The technique described in this specification can be applied to a field-effect transistor in which electrons travel through an n-type nitride semiconductor layer. An i-type or p-type nitride semiconductor layer is formed by providing an i-type or p-type nitride semiconductor layer in the middle of an n-type nitride semiconductor layer extending between the source contact region and the drain contact region. A field effect transistor serving as a channel region is obtained. When a channel region made of an i-type or p-type nitride semiconductor is observed in the longitudinal direction, if a structure in which negative fixed charge introduction regions and non-introduction regions appear alternately is employed, a threshold value is suppressed while suppressing an increase in on-resistance. The voltage can be pulled up toward the positive side.

When a heterojunction of a nitride semiconductor having a narrow band gap and a nitride semiconductor having a wide band gap exists, the former is an electron transit layer and the latter is an electron supply layer. The technique described in this specification can be applied to a HEMT transistor having a stacked structure of an electron transit layer and an electron supply layer.
In that case, it is desirable to form a recess extending from the upper surface of the electron supply layer toward the electron transit layer. The recess may remain at the intermediate depth of the electron supply layer, or may penetrate the electron supply layer and reach the intermediate depth of the electron transit layer. In the former case, the bottom surface of the recess is at an intermediate depth of the electron supply layer, and in the latter case, the bottom surface of the recess is at an intermediate depth of the electron transit layer. When applied to the HEMT, it is preferable to use a recess whose bottom surface is located between the intermediate depth of the electron supply layer and the intermediate depth of the electron transit layer. The wall surface of the recess is covered with a gate insulating film. Then, the gate electrode is filled in the recess whose wall surface is covered with the gate insulating film.
When the depth of the recess remains at an intermediate depth of the electron supply layer, a part of the electron transit layer faces the gate electrode through the gate insulating film and the electron supply layer. When the recess penetrates the electron supply layer, a part of the electron transit layer faces the gate electrode via the gate insulating film (without the electron supply layer). In this specification, the phrase “facing the gate electrode through the gate insulating film” includes both.
In this specification, an electron transit layer in a range facing the gate electrode through the gate insulating film is referred to as a channel region. When the negative fixed charge introduction region is not formed in the channel region, the entire electron transit layer in the range facing the gate electrode is depleted or not depleted depending on the potential of the gate electrode. In this case, the channel region is a region that is depleted or not depleted depending on the potential of the gate electrode. In the technique described in this specification, a negative fixed charge introduction region is formed in a part of the channel region. In the negative fixed charge introduction region, the phenomenon of depletion or not depletion depending on the potential of the gate electrode may not occur. However, in this specification, the electron transit layer in the range facing the gate electrode through the gate insulating film is depleted or not depleted depending on the potential of the gate electrode unless the negative fixed charge introduction region is formed. The entire range is called a channel region. The channel region referred to in this specification includes a negative fixed charge introduction region that may not be depleted or not depleted depending on the potential of the gate electrode. In this specification, a channel region in which the depletion layer has disappeared is referred to as a channel.
When a recess is provided in the electron supply layer and the recess is filled with the gate electrode, the distance from the gate electrode to the electron transit layer facing the gate electrode is shortened, and the threshold voltage is raised toward the positive side. When a technique for filling the recess with the gate electrode and a negative fixed charge introduction region appearing at a predetermined interval are used in combination, a normally-off HEMT transistor with low on-resistance can be realized.
An insulating film may be stacked on the upper surface of the electron supply layer. In this specification, it is called a spacer film. When the spacer film is provided, a recess reaching the electron supply layer from the upper surface of the spacer film can be formed.

When a high voltage is applied between the source electrode and the drain electrode without applying a voltage higher than the threshold voltage to the gate electrode (a state in which it is turned off), a channel region located near the drain electrode side boundary line on the bottom surface of the recess Electric field concentration tends to occur. If the electric field concentration can be reduced, the breakdown voltage of the field effect transistor can be improved. For this purpose, it is advantageous to reduce the distance between the negative fixed charge introduction region and the negative fixed charge introduction region adjacent thereto at a position along the drain electrode side boundary line on the bottom surface of the recess .
That is, when the channel region facing the gate electrode through the gate insulating film is observed along the boundary line extending on the source electrode side of the recess bottom surface and the boundary line extending on the drain electrode side of the recess bottom surface. The distance between the negative fixed charge introduction region and the negative fixed charge introduction region adjacent to the negative fixed charge introduction region is long when observed along the former boundary line (including the infinite case), and observed along the latter boundary line. With the short feature, the breakdown voltage is improved.
When the voltage between the source electrode and the drain electrode is increased, a current flows between the source electrode and the drain electrode even though a voltage higher than the threshold is not applied to the gate electrode. The withstand voltage in this specification refers to a source-drain voltage when current starts to flow between the source electrode and the drain electrode even though a voltage higher than a threshold is not applied to the gate electrode.

There are cases where measures against a weak current (leakage current) flowing between the source electrode and the drain electrode without applying a voltage higher than the threshold voltage to the gate electrode may be required.
In that case, a high resistance layer is stacked below the lower surface of the channel region, and the negative fixed charge introduction region extends from the upper surface of the channel region to the high resistance layer.
According to the above structure, the depletion layer spreads in the path through which the leak current flows, and the leak current is reduced.

According to the technique disclosed in this specification, the threshold voltage can be increased toward the positive side while suppressing an increase in on-resistance. Using this technique, it is possible to manufacture a normally-off field effect transistor having a low on-resistance. Further, by using the high resistance layer in combination, the leakage current can be reduced , and the withstand voltage can be increased by adjusting the shape of the negative fixed charge introduction region.

1 is an exploded perspective view of an insulated gate field effect transistor according to a first embodiment. The xz sectional view of FIG. 1 is shown. The x1-z sectional view of FIG. 1 is shown. The yz sectional view of FIG. 1 is shown. The top view of the insulated gate field effect transistor of 2nd Example is shown. The figure corresponding to FIG. 2 of the insulated gate field effect transistor of 2nd Example is shown. The top view of the insulated gate field effect transistor of 3rd Example is shown. The figure corresponding to FIG. 2 of the insulated gate field effect transistor of 4th Example is shown. The figure corresponding to FIG. 4 of the insulated gate field effect transistor of 4th Example is shown. The variation of the depth of a recess and a negative fixed charge introduction | transduction area | region is illustrated. 1 shows a conventional insulated gate field effect transistor.

The features of the technology disclosed in this specification will be summarized below. The items described below have technical usefulness independently.
(Feature 1) An electron transit layer that provides a channel region is formed of i-type GaN or n-type GaN, and one or more types of F, Cl, C, Mg, Zn, and Fe are introduced into the GaN. Thus, a negative fixed charge introduction region is formed.
(Feature 2) Recesses are formed at a plurality of longitudinal positions of the electron transit layer providing the channel region, and one or more kinds of F, Cl, C, Mg, Zn, Fe are introduced into the recesses. The single fixed crystal, polycrystal, or insulator is formed to form the negative fixed charge introduction region.

(First embodiment)
FIG. 1 is an exploded perspective view of an insulated gate field effect transistor 20 of the first embodiment. However, the illustration of the structure in front of the yz plane is omitted. 2 shows the xz cross section of FIG. 1 of the field effect transistor 20, FIG. 3 shows the x1-z cross section, and FIG. 4 shows the yz cross section. 2 to 3, a drain electrode 16 not shown in FIG. 1 is shown.
In FIG. 1, the y-axis shown in two places actually overlaps, and the y1 axis shown in two places actually overlaps. The x axis shown in the drawing passes through the negative fixed charge introduction region 14, and the x1 axis passes between a pair of adjacent negative fixed charge introduction regions 14.

1 to 4, reference numerals indicate the following.
2: Gate electrode: extends between the source electrode 6 and the drain electrode 16 in the y direction.
4: Gate insulating film: covers the lower and side surfaces of the gate electrode 2, insulates between the gate electrode 2 and the source electrode 6, insulates between the gate electrode 2 and the electron supply layer 10, and the gate electrode 2 and the electron transit layer 12 is insulated, and the gate electrode 2 and the drain electrode 16 are insulated.
6: Source electrode: in contact with the electron supply layer 10
8: Spacer film: formed of an insulating film, which insulates between the gate electrode 2 and the electron supply layer 10 and increases the separation distance between the gate electrode 2 and the electron supply layer 10.
10: Electron supply layer: formed of AlGaN. As will be described later, when the electron transit layer is made of GaN, Al _x In _y Ga _1-xy N can be generally used. 0 ≦ x <1, 0 ≦ y <1, and 0 ≦ 1-xy <1.
12: Electron travel layer: formed of GaN. The band gap of AlGaN> the band gap of GaN. In general, the electron supply layer 10 and the electron transit layer 12 can be formed by a combination of a nitride semiconductor having a large band gap and a nitride semiconductor having a small band gap. In this embodiment, the electron transit layer 12 is formed of i-type GaN. n-type GaN may be used instead of i-type GaN. A part 12a of the electron transit layer 12 faces the lower surface of the gate electrode 2 with the gate insulating film 4 interposed therebetween, and becomes a channel region.
14: Negative fixed charge introduction region: A negative fixed charge introduction region 14 is formed in a part of the electron transit layer 12 (= channel region 12a) in a range facing the gate electrode 2 through the gate insulating film 4. . When the channel region 12a is observed along the y-axis (in the longitudinal direction of the gate electrode 2), the negative fixed charge introduction region 14 appears at a predetermined distance L15.
15: Non-introduction region: between a pair of adjacent negative fixed charge introduction regions 14 and 14, and no negative fixed charge is introduced.
16: Drain electrode: in contact with the electron supply layer 10
17: A depletion layer formed without applying a voltage to the gate electrode 2.

1-4, a recess is formed from the upper surface of the spacer film 8 to the lower surface of the electron supply layer 10 (= the upper surface of the electron transit layer 12), and the wall surfaces (bottom surface and side surfaces) of the recess are gates. The gate electrode 2 is filled in a recess covered with the insulating film 4 and having a wall surface covered with the gate insulating film 4. The electron transit layer 12 is exposed on the bottom surface of the recess. The upper surface of the electron layer transit layer 12 is in direct contact with the gate insulating film 4.
A plurality of negative fixed charge introduction regions 14 are formed in a range exposed at the recess bottom surface of the electron transit layer 12. In the interval between a pair of adjacent negative fixed charge introduction regions 14, 14, no negative fixed charge is introduced into the i-type or n-type GaN forming the electron layer traveling layer 12, which becomes the non-introduction region 15. . The non-introduced region 15 faces the lower surface of the gate electrode 2 through the gate insulating film 4 and changes between a depleted state and a non-depleted state depending on the potential of the gate electrode 2. A channel is formed in the non-introduction region 15 of the electron transit layer 12.
The negative fixed charge introduction region 14 is formed by introducing one or more types of F, Cl, C, Mg, Zn, and Fe into a part of the channel region 12 a formed in a part of the electron transit layer 12. can do. Alternatively, the electron transit layer 12 is etched in the range where the negative fixed charge introduction region 14 is formed to provide a recess, and a p-type semiconductor (for example, p-type polycrystalline silicon or p-type GaN) is formed in the recess. May be. An insulator containing negative ions such as F may be formed in the recess.
When an n-type GaN layer is used for the electron transit layer 12 that provides the channel region 12a, the depletion layer spreads when no voltage higher than the threshold is applied to the gate electrode, and high electron movement occurs when a voltage higher than the threshold is applied to the gate electrode. In order to realize the degree, it is preferable that the impurity concentration is not too high. The impurity concentration of the electron transit layer 12 is preferably less than the impurity concentration of the negative fixed charge introduction region 14, and more preferably, the impurity concentration of the electron transit layer 12 <0.1 × the impurity concentration of the negative fixed charge introduction region 14. .

In a state where no voltage is applied to the gate electrode 2, a depletion layer extends in the y direction from the negative fixed charge introduction region 14 into the non-introduction region 15. In the first embodiment, as shown in FIG. 4, a pair of depletion layers 17 (a depletion layer extending in the + y direction and a −y direction) extending from the pair of adjacent negative fixed charge introduction regions 14, 14 between the adjacent pairs. Depletion layer) continues. That is, the distance L15 between the pair of negative fixed charge introduction regions 14 is set so that the depletion layer 17 continues.
Therefore, in this embodiment, the two-dimensional electron gas generated at the heterojunction interface between the electron supply layer 10 made of a nitride semiconductor having a large band gap and the electron transit layer 12 made of a nitride semiconductor having a small band gap is caused by the depletion layer 17. It is divided and no current flows between the source electrode 6 and the drain electrode 16.
When a voltage equal to or higher than the threshold voltage is applied to the gate electrode 2, the depletion layer 17 extending into the non-introduced region 15 contracts, an electron movement path (channel) opens in the non-introduced region 15, and electrons are supplied to the source electrode 6. And between the drain electrode 16. The non-introduction region 15 existing between the pair of negative fixed charge introduction regions 14 and 14 varies depending on the voltage of the gate electrode 2 between a state where carriers can move and a state where carriers cannot move. In the structure of FIGS. 1 to 4, a channel is formed in the non-introduced region 15 that is a part of the electron transit layer 12 made of a nitride semiconductor. Since the electron mobility is high in the non-introduced region 15, the on-resistance is low.
1-4 are intermittently disposed along the direction (y direction) in which the gate electrode 2 extends. When the channel region 12a facing the gate electrode 2 through the gate insulating film 4 is observed along the direction in which the gate electrode 2 extends, the region 14 into which the negative fixed charge is introduced and the negative fixed charge are introduced. The regions 15 not appearing alternately appear.

  In the transistor 20 of the first embodiment, the depletion layer 17 spreads in the non-introduction region 15 in a state where a voltage higher than the threshold is not applied to the gate electrode 2. By adjusting the length L15 of the non-introduction region 15 (= distance between a pair of adjacent negative fixed charge introduction regions 14 and 14), the depletion layer contracts and changes to a state in which carriers can move in the non-introduction region 15 The gate voltage (that is, the threshold voltage) can be adjusted. If the interval is narrowed, the threshold voltage is raised toward the positive side. In one specific example, the threshold voltage becomes a positive voltage when the distance L15 between a pair of adjacent negative fixed charge introduction regions 14 is 1 μm or less, and the normally-off characteristic can be adjusted.

In the transistor 20 of the first embodiment, when a voltage higher than the threshold is applied to the gate electrode 2, the depletion layer contracts and electrons can move through the non-introduction region 15. The non-introduced region 15 is made of i-type GaN and has high electron mobility. Low on-resistance.
In the transistor 20 of the first embodiment, the negative fixed charge introduction region 14 is partially provided. In the structure of FIG. 11, the negative fixed charge introduction region 14 is provided on the entire surface.
In the former case, electrons easily move in a region (non-introduction region 15) between a pair of adjacent negative fixed charge introduction regions 14. The increase in on-resistance due to partial provision of the negative fixed charge introduction region 14 is small.
In the latter case, an inversion layer is formed in the negative fixed charge introduction region 14, and a phenomenon in which electrons move through the inversion layer is used. The electrons passing through the negative fixed charge introduction region 14 are scattered by the ionic impurities introduced into the negative fixed charge introduction region 14, and the on-resistance is greatly increased.
The increase in on-resistance due to the structure of the first embodiment is much lower than the increase in on-resistance due to the structure in FIG.
When the negative fixed charge introduction region 14 is partially provided, it is not necessary to form an inversion layer in the negative fixed charge introduction region 14, and the concentration of the negative fixed charge introduced into the negative fixed charge introduction region 14 can be increased. . By adjusting the concentration of the negative fixed charge introduction region 14 and the length L15 of the non-introduction region 15, a high threshold voltage and a low on-resistance can be realized.

In the first embodiment, the recess reaches the lower surface of the electron supply layer 10 (= the upper surface of the electron transit layer 12). However, the technique described herein is not limited to the depth of the recess.
In FIG. 10A, the recess bottom surface coincides with the upper surface of the electron supply layer 10. In (B), the recess bottom surface reaches the intermediate depth of the electron supply layer 10. In the case of (A) and (B), the gate electrode 2 extends through the electron transit layer 12 (channel region referred to in this specification) in a range facing the gate electrode 2 through the gate insulating film 4 and the electron supply layer 10. The negative fixed charge introduction region 14 and the non-introduction region 15 appear alternately when observed along the direction in which the light is introduced. This is also included in the relationship in this specification where negative fixed charge introduction regions and non-introduction regions appear alternately in the channel region facing the gate electrode through the gate insulating film. In the structure of (A), the threshold voltage is raised toward the positive side by providing the negative fixed charge introduction region 14, but the relationship between the concentration of the two-dimensional electron gas formed at the heterojunction interface and the concentration of the negative fixed charge. In some cases, the threshold voltage cannot be shifted to a positive voltage. For normally-off, (C) and (D) described later are preferable.
In FIG. 10C, the bottom surface of the recess coincides with the lower surface of the electron supply layer 10. That is, it has been described in the first embodiment. In (D), the bottom surface of the recess reaches the intermediate depth of the electron transit layer 12. In the case of (C) and (D), the gate electrode 2 extends through the electron transit layer 12 (channel region) facing the gate electrode 2 via the gate insulating film 4 (without the electron supply layer 10). When observed along the direction, the negative fixed charge introduction region 14 and the non-introduction region 15 appear alternately. The negative fixed charge introduction region and the non-introduction region appear alternately in the channel region facing the gate electrode through the gate insulating film in this specification.
The recess reaches the upper surface of the electron transit layer 12 or is deeper than that, and the electron transit layer 12 providing the channel region does not go through the electron supply layer 10 but only through the gate insulating film 4. , The threshold voltage is easily shifted to a positive voltage and adjusted to normally off. According to the structure of (C) or (D), the specifications required for the transistor can often be satisfied.

(Second embodiment)
FIG. 5 shows a plan view of the transistor of the second embodiment. The same reference numerals are used for the same or similar members as those already described, and a duplicate description is omitted.
5 and 6, a line segment A indicates a boundary line on the source electrode 6 side of the bottom surface of the recess, and a line segment B indicates a boundary line on the drain electrode 16 side of the bottom surface of the recess. Actually, since the thickness of the gate insulating film 4 is thinner than that shown in FIG. 6, the line segment A is a boundary line on the side of the source electrode 6 on the lower surface of the gate electrode 2, and the line segment B is the gate. It can be said that this is the boundary line on the drain electrode 16 side of the lower surface of the electrode 2.
In the second embodiment shown in FIGS. 5 and 6, the negative fixed charge introduction region 14a has a triangular shape when viewed in plan. When the distance L15B between the pair of negative fixed charge introduction regions 14a adjacent to each other along the line segment B is measured, the distance L15B is short, and the distance increases as the line segment B approaches the line segment A. Since the negative fixed charge introduction region 14a does not reach the position along the line segment A, the distance between the pair of negative fixed charge introduction regions 14a adjacent along the line segment A is infinite. You can see that it is stretched.
In the case of the lateral transistor shown in FIG. 6, electric field concentration tends to occur in the electron transit layer 12 located in the vicinity of the line segment B. In the second embodiment, the negative fixed charge introduction regions 14a are densely arranged at positions where electric field concentration is likely to occur, and the electric field that tends to concentrate is effectively relaxed. In the second embodiment, the occurrence of electric field concentration can be suppressed and the breakdown voltage can be increased.
The plan view of FIG. 5 is divided into a large number of unit areas, and the amount of negative fixed charges (corresponding to the charge density) included in the unit areas is assumed. In that case, the average charge density measured along the line segment B becomes the maximum, and the average charge density decreases from the line segment B toward the A side. The negative fixed charge introduction region 14a is formed so that the average charge density increases as the boundary line A on the source electrode 6 side on the lower surface of the gate electrode 2 approaches the boundary line B on the drain electrode 16 side on the lower surface of the gate electrode. Thus, the withstand voltage of the transistor can be improved.

(Third embodiment)
In the embodiment shown in FIG. 7, the negative fixed charge introduction region 14 b is formed at a position away from the line segment A and close to the line segment B. That is, it is formed at a position biased toward the line segment B side. Also in this embodiment, the electric field concentration that is likely to occur in the electron transit layer 12 in the vicinity of the line segment B is effectively mitigated by the negative fixed charge introduction region 14b that is densely arranged in the vicinity of the line segment B. For this reason, the breakdown voltage can be increased.

(Fourth embodiment)
Even when a voltage higher than the threshold is not applied to the gate electrode, a weak current continues to flow between the source electrode and the drain electrode. In the present specification, this weak current is referred to as a leakage current. In the fourth embodiment, the leakage current can be reduced.
In the fourth embodiment, a high resistance layer 18 is provided below the lower surface of the electron transit layer 12, and the negative fixed charge introduction region 14 c reaches from the lower surface of the gate insulating film 4 to the upper surface of the high resistance layer 18. Then, a depletion layer spreads over almost the entire area of the electron transit layer 12, and leakage current is severely suppressed.
The high resistance layer 18 can be formed of a GaN layer to which C, Fe, or Zn is added. Alternatively, it can be formed of a nitride semiconductor having a larger band gap than the nitride semiconductor forming the electron transit layer 12. If the electron transit layer 12 is formed of GaN, for example, the AlGaN layer becomes the high resistance layer 18.
In the fourth embodiment, the negative fixed charge introduction region 14c reaches the high resistance layer 18, but the negative fixed charge introduction region 14c may not reach the high resistance layer 18 completely. Leakage current can also be suppressed in the relationship that the negative fixed charge introduction region 14 c is close to the high resistance layer 18.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

2: Gate electrode 4: Gate insulating film
6: Source electrode 8: Spacer film (insulating film)
10: Electron supply layer (AlGaN layer in the embodiment)
12: Electron transit layer providing a channel region (GaN layer in the embodiment)
12a: Channel region 14: Negative fixed charge introduction region 14a, 14b, 14c: Modification of negative fixed charge introduction region 15: Non-introduction region L15: Distance between a pair of adjacent negative fixed charge introduction regions 16: Drain electrode 17 : Depletion layer 18: High resistance layer 20: Field effect transistor

Claims (3)

The gate electrode is opposed to a channel region formed of a nitride semiconductor through a gate insulating film, and a high resistance layer is laminated under the lower surface of the channel region,
An insulated gate field effect transistor in which a depletion layer extending in the channel region is contracted by a potential applied to the gate electrode and a resistance between the source electrode and the drain electrode is reduced;
When the channel region is observed along the direction in which the gate electrode extends, regions where negative fixed charges are introduced and regions where negative fixed charges are not introduced alternately appear ,
The field effect transistor according to claim 1, wherein the negative fixed charge introduction region extends from an upper surface of the channel region to the high resistance layer . The high resistance layer, an electron transit layer laminated on the upper surface of the high resistance layer, and an electron supply layer laminated on the upper surface of the electron transit layer,
The electron transit layer is formed of a nitride semiconductor,
The electron supply layer is formed of a nitride semiconductor having a larger band gap than the nitride semiconductor forming the electron transit layer,
A recess extending from the upper surface of the electron supply layer toward the electron transit layer is formed,
A wall surface of the recess is covered with the gate insulating film;
The recess, whose wall surface is covered with the gate insulating film, is filled with the gate electrode,
A bottom surface of the recess is located between an intermediate depth of the electron supply layer and an intermediate depth of the electron transit layer;
The channel region includes the electron transit layer in a range opposed to the gate electrode through the gate insulating film and the electron supply layer, or the electron transit layer in a range opposed to the gate electrode through the gate insulating film. The field effect transistor according to claim 1, wherein When observing the channel region facing the gate electrode through the gate insulating film along the boundary line on the source electrode side of the recess bottom surface and the boundary line on the drain electrode side of the recess bottom surface The field effect according to claim 2, wherein a distance between a pair of adjacent negative fixed charge introduction regions is long when observed along the former boundary line and short when observed along the latter boundary line. Transistor.

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