JP6256741B2 - Package board for mounting semiconductor elements - Google Patents
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- JP6256741B2 JP6256741B2 JP2013192925A JP2013192925A JP6256741B2 JP 6256741 B2 JP6256741 B2 JP 6256741B2 JP 2013192925 A JP2013192925 A JP 2013192925A JP 2013192925 A JP2013192925 A JP 2013192925A JP 6256741 B2 JP6256741 B2 JP 6256741B2
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- 239000004065 semiconductor Substances 0.000 title claims description 39
- 239000000758 substrate Substances 0.000 claims description 203
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 137
- 229910052802 copper Inorganic materials 0.000 claims description 129
- 239000010949 copper Substances 0.000 claims description 129
- 239000000853 adhesive Substances 0.000 claims description 56
- 230000001070 adhesive effect Effects 0.000 claims description 56
- 239000004020 conductor Substances 0.000 claims description 38
- 229910000679 solder Inorganic materials 0.000 claims description 17
- 230000007423 decrease Effects 0.000 claims description 2
- 238000007747 plating Methods 0.000 description 43
- 239000010410 layer Substances 0.000 description 41
- 238000000034 method Methods 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 10
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- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 3
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- 239000004593 Epoxy Substances 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229920000459 Nitrile rubber Polymers 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
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- 239000004744 fabric Substances 0.000 description 2
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- -1 polyethylene terephthalate Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
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- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- IRLQAJPIHBZROB-UHFFFAOYSA-N buta-2,3-dienenitrile Chemical compound C=C=CC#N IRLQAJPIHBZROB-UHFFFAOYSA-N 0.000 description 1
- 125000003178 carboxy group Chemical group [H]OC(*)=O 0.000 description 1
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- 239000003795 chemical substances by application Substances 0.000 description 1
- 125000003700 epoxy group Chemical group 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
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- 229910052759 nickel Inorganic materials 0.000 description 1
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Description
本発明は、半導体素子搭載用パッケージ基板に関し、特にはキャビティ構造を有する半導体素子搭載用パッケージ基板に関する。 The present invention relates to a semiconductor device mounting package substrate, and more particularly to a semiconductor device mounting package substrate having a cavity structure.
電子部品の小型化や高密度化に伴い、システム化された半導体素子搭載用パッケージ基板（以下、「半導体素子搭載用パッケージ基板」を、「パッケージ基板」ということがある。）が求められている。ＳｉＰ（Ｓｙｓｔｅｍ ｉｎ Ｐａｃｋａｇｅ）に代表されるＰｏＰ（Ｐａｃｋａｇｅ ｏｎ Ｐａｃｋａｇｅ）では、近年、一つのパッケージ基板に半導体素子を複数積み重ねたパッケージが主流となってきている。これに伴い、汎用性や一般的なインフラ実装装置での適用が可能になり、キャビティ構造が求められている。 With downsizing and increasing the density of electronic components, there is a need for a systemized semiconductor device mounting package substrate (hereinafter, “semiconductor device mounting package substrate” may be referred to as “package substrate”). . In PoP (Package on Package) represented by SiP (System in Package), in recent years, a package in which a plurality of semiconductor elements are stacked on one package substrate has become the mainstream. Along with this, it becomes possible to apply to general-purpose and general infrastructure mounting apparatuses, and a cavity structure is required.
このようなキャビティ構造を有するパッケージ基板として、半導体素子搭載用の端子や外部との接続端子を備えたベース基板と、半導体素子を収納する開口を備えたキャビティ基板とを、接着剤を介して張り合わせ、且つ、キャビティ基板表面からベース基板に到る層間接続孔にめっきした後、導電ペーストを充填して、キャビティ基板表面の端子とベース基板とを電気的に接続したパッケージ基板が開示されている（特許文献１）。 As a package substrate having such a cavity structure, a base substrate having a semiconductor element mounting terminal and an external connection terminal and a cavity substrate having an opening for accommodating the semiconductor element are bonded together with an adhesive. In addition, there is disclosed a package substrate in which an interlayer connection hole extending from the cavity substrate surface to the base substrate is plated and then filled with a conductive paste to electrically connect the terminals on the cavity substrate surface and the base substrate ( Patent Document 1).
また、ベース基板にキャビティ形成用ストッパー層を形成し、キャビティ基板となる絶縁層を積層後に、レーザ加工を用いて、キャビティ形成用ストッパー層の上部の絶縁層を除去してキャビティを形成し、また、レーザ加工を用いて、キャビティ基板とベース基板とを貫通する層間接続孔を形成し、この層間接続孔にめっきを充填して、キャビティ基板表面の端子とベース基板とを電気的に接続したパッケージ基板が開示されている（特許文献２）。 In addition, after forming a cavity forming stopper layer on the base substrate and laminating the insulating layer to be the cavity substrate, laser processing is used to remove the insulating layer above the cavity forming stopper layer to form a cavity. A package in which an interlayer connection hole penetrating the cavity substrate and the base substrate is formed by using laser processing, and the interlayer connection hole is filled with plating to electrically connect the terminal on the surface of the cavity substrate and the base substrate. A substrate is disclosed (Patent Document 2).
しかしながら、特許文献１の方法では、キャビティ基板からベース基板に到る層間接続孔にめっきした後、導電ペーストを充填して、キャビティ基板表面の端子とベース基板とを電気的に接続するため、導電ペーストの充填性を考えると、アスペクト比をあまり大きくできない。このため、キャビティ基板表面に配置される外部との接続端子のピッチの高密度化が難しい。 However, in the method of Patent Document 1, the interlayer connection hole extending from the cavity substrate to the base substrate is plated and then filled with a conductive paste to electrically connect the terminal on the surface of the cavity substrate and the base substrate. Considering the filling properties of the paste, the aspect ratio cannot be increased too much. For this reason, it is difficult to increase the pitch of the connection terminals with the outside arranged on the surface of the cavity substrate.
また、特許文献２の方法では、キャビティ基板表面の端子とベース基板とを電気的に接続するために、キャビティ基板とベース基板とを貫通する層間接続孔を用いるため、非貫通孔を用いる場合に比べて、ある程度アスペクト比を大きくできるものの、層間接続のためにパッケージ基板の厚さ方向の全体が使われてしまうため、その分、配線のスペースがとられてしまい、高密度化の妨げになる問題がある。 Further, in the method of Patent Document 2, since an interlayer connection hole that penetrates the cavity substrate and the base substrate is used to electrically connect the terminal on the surface of the cavity substrate and the base substrate, the non-through hole is used. In comparison, although the aspect ratio can be increased to some extent, the entire thickness of the package substrate is used for the interlayer connection, so that the wiring space is taken correspondingly, which hinders high density. There's a problem.
本発明は上記問題点に鑑みなされたものであり、高密度実装を可能としつつ、キャビティ構造によって汎用性を実現可能な半導体素子搭載用パッケージ基板を提供する。 The present invention has been made in view of the above problems, and provides a package substrate for mounting a semiconductor element that can realize versatility with a cavity structure while enabling high-density mounting.
本発明は、以下のものに関する。
１． 絶縁層表面の導体回路上に凸状に配置されるカッパーポストを有するベース基板と、前記カッパーポストを収容する貫通孔及び前記ベース基板上にキャビティ部を形成する開口を有するキャビティ基板と、前記ベース基板とキャビティ基板との間に配置される接着剤と、を備え、前記カッパーポストとこれを収容する前記貫通孔の内壁との間に、前記接着剤が配置される半導体素子搭載用パッケージ基板であって、前記ベース基板とキャビティ基板とが、異なる寸法変化挙動を有するものであり、前記カッパーポストとこれを収容する前記貫通孔の内壁との間に間隙を有し、この間隙に前記接着剤が充填され、この接着剤の弾性率が５０℃で１００〜５００ＭＰａである半導体素子搭載用パッケージ基板。
２． 項１において、前記カッパーポストとこれを収容する前記貫通孔の内壁との間に配置される前記接着剤の熱膨張係数が、２０ｐｐｍ／℃以上である半導体素子搭載用パッケージ基板。
３． 項１又は２において、前記ベース基板の絶縁層表面の導体回路の底面及び側面が、前記絶縁層中に埋め込まれている半導体素子搭載用パッケージ基板。
４． 項１から３の何れかにおいて、前記ベース基板の絶縁層表面の導体回路上に、２種類以上の高さが配置されるカッパーポストの高さが２種類以上である半導体素子搭載用パッケージ基板。
５． 項１から４の何れかにおいて、前記ベース基板の絶縁層表面の導体回路上に配置されるカッパーポストの直径が、導体回路側から上方に向かって小さくなる半導体素子搭載用パッケージ基板。
６． 項１から５の何れかにおいて、前記ベース基板のカッパーポストの上端が、前記キャビティ基板の表面に露出する半導体素子搭載用パッケージ基板。
７． 項１から６の何れかにおいて、前記ベース基板のカッパーポストの上端が、前記キャビティ基板の表面に対して凹部を形成する半導体素子搭載用パッケージ基板。
８． 項１から７の何れかにおいて、前記カッパーポストの上端に、はんだが配置される半導体素子搭載用パッケージ基板。
９． 項８のパッケージ基板において、前記カッパーポストの上端に配置されるはんだの上端が、前記キャビティ基板の表面と面一である半導体素子搭載用パッケージ基板。
１０． 項１から６の何れか一のパッケージ基板において、前記カッパーポストの上端に、キャビティ基板の表面の導体回路が配置される半導体素子搭載用パッケージ基板。
The present invention relates to the following.
1. A base substrate having a copper post convexly disposed on a conductor circuit on the surface of the insulating layer; a cavity substrate having a through hole for accommodating the copper post; and an opening for forming a cavity portion on the base substrate; and the base and an adhesive disposed between the substrate and the cavity substrate, between the inner wall of the through hole to accommodate this and the copper post, in the semiconductor element mounting package substrate on which the adhesive is disposed The base substrate and the cavity substrate have different dimensional change behaviors, and have a gap between the copper post and the inner wall of the through hole that accommodates the copper post, and the adhesive in the gap A package substrate for mounting a semiconductor element in which the elastic modulus of the adhesive is 100 to 500 MPa at 50 ° C.
2 . Oite to claim 1, wherein the copper post and the thermal expansion coefficient of the adhesive disposed between the inner wall of the through hole, a semiconductor element mounting package substrate is 20 ppm / ° C. or higher to accommodate this.
3 . Item 3. The package substrate for mounting a semiconductor element according to Item 1 or 2 , wherein a bottom surface and a side surface of a conductor circuit on a surface of the insulating layer of the base substrate are embedded in the insulating layer.
4 . In any one of claim 1 3, wherein on the conductor circuit of the base substrate surface of the insulating layer, two or more semiconductor element mounting package substrate is copper height of the post height is arranged two or more.
5 . Item 5. The package board for mounting a semiconductor element according to any one of Items 1 to 4 , wherein the diameter of the copper post disposed on the conductor circuit on the insulating layer surface of the base substrate decreases from the conductor circuit side upward.
6 . Item 6. The package substrate for mounting a semiconductor element according to any one of Items 1 to 5 , wherein an upper end of a copper post of the base substrate is exposed on a surface of the cavity substrate.
7 . Item 7. The package substrate for mounting a semiconductor element according to any one of Items 1 to 6 , wherein an upper end of a copper post of the base substrate forms a recess with respect to a surface of the cavity substrate.
8 . Item 8. The package substrate for mounting a semiconductor element according to any one of Items 1 to 7 , wherein solder is disposed on an upper end of the copper post.
9 . Item 9. The package substrate for mounting a semiconductor element according to Item 8 , wherein the upper end of the solder disposed on the upper end of the copper post is flush with the surface of the cavity substrate.
10 . Item 7. The package substrate for mounting a semiconductor element according to any one of Items 1 to 6 , wherein a conductor circuit on a surface of the cavity substrate is disposed at an upper end of the copper post.
本発明によれば、高密度実装性や信頼性を確保しつつ、キャビティ構造によって汎用性を実現可能な半導体素子搭載用パッケージ基板を提供することができる。 ADVANTAGE OF THE INVENTION According to this invention, the package substrate for semiconductor element mounting which can implement | achieve versatility with a cavity structure can be provided, ensuring high density mounting property and reliability.
本発明の半導体素子搭載用パッケージ基板（以下、「半導体素子搭載用パッケージ基板」を、「パッケージ基板」ということがある。）の一実施形態について、図１を用いて以下に説明する。 One embodiment of a package substrate for mounting a semiconductor element of the present invention (hereinafter, “package substrate for mounting a semiconductor element” may be referred to as “package substrate”) will be described below with reference to FIG.
本発明のパッケージ基板の一実施形態は、図１に示すように、絶縁層１６表面の導体回路１７上に凸状に配置されるカッパーポスト７を有するベース基板３と、前記カッパーポスト７を収容する貫通孔９及び前記ベース基板３上にキャビティ部１２を形成する開口１０を有するキャビティ基板８と、前記ベース基板３とキャビティ基板８との間に配置される接着剤１１と、を備え、前記カッパーポスト７とこれを収容する前記貫通孔９の内壁との間に、前記接着剤１１が配置される半導体素子搭載用パッケージ基板１５である。 As shown in FIG. 1, an embodiment of the package substrate of the present invention accommodates a base substrate 3 having a copper post 7 that is convexly arranged on a conductor circuit 17 on the surface of an insulating layer 16 and the copper post 7. A cavity substrate 8 having a through-hole 9 and an opening 10 for forming a cavity portion 12 on the base substrate 3, and an adhesive 11 disposed between the base substrate 3 and the cavity substrate 8, A semiconductor element mounting package substrate 15 in which the adhesive 11 is disposed between the copper post 7 and the inner wall of the through hole 9 that accommodates the copper post 7.
本実施の形態におけるベース基板とは、半導体素子（図示しない。）を搭載する支持基板のことをいう。ベース基板は、例えば、一般的なビルドアップ製法により得ることができる。縁縁層表面の導体回路上に凸状に配置されるカッパーポストを有している。カッパーポストとは、主に銅で形成される凸形状の導体であり、ベース基板と異なるパッケージ基板等との接続用の端子（外部接続端子）や、ベース基板とキャビティ基板との接続用の端子（内部接続端子）を形成するために用いられる。カッパーポストの形成方法の一例としては、ベース基板の絶縁層表面の導体回路を含む全面に、給電層となる下地無電解めっきを形成した後、めっきレジストを形成し、電解銅めっきを行い、めっきレジストと不要な箇所の下地無電解めっきを除去することにより、所望の位置や範囲（大きさ、形状）に、所望の高さで形成することができる。本実施の形態では、カッパーポストは、ベース基板の絶縁層表面の導体回路上に凸状に形成され、キャビティ基板を貫通して、キャビティ基板の表面に達する高さに形成されている。 The base substrate in this embodiment refers to a support substrate on which a semiconductor element (not shown) is mounted. The base substrate can be obtained by, for example, a general buildup manufacturing method. It has a copper post arranged in a convex shape on the conductor circuit on the surface of the edge layer. A copper post is a convex conductor mainly made of copper, and is a terminal (external connection terminal) for connecting to a package board or the like different from the base board, or a terminal for connecting the base board to the cavity board. Used to form (internal connection terminal). As an example of the method of forming the copper post, after forming the base electroless plating serving as the power feeding layer on the entire surface including the conductor circuit on the surface of the insulating layer of the base substrate, forming a plating resist, performing electrolytic copper plating, By removing the resist and the underlying electroless plating at unnecessary portions, it can be formed at a desired height in a desired position and range (size, shape). In this embodiment, the copper post is formed in a convex shape on the conductor circuit on the surface of the insulating layer of the base substrate, and is formed so as to penetrate the cavity substrate and reach the surface of the cavity substrate.
本実施の形態におけるキャビティ基板とは、ベース基板上にキャビティを形成するためのものであり、キャビティとは半導体素子等を収納する空間を設けるものである。本実施の形態のキャビティ基板は、カッパーポストを収容する貫通孔と、ベース基板上にキャビティ部を形成する開口とを有している。このようなキャビティ基板の形成方法としては、例えば、銅張り積層板の銅箔を回路形成した後、ベース基板との張り合わせ面に接着剤を仮接着し、キャビティ用の開口と、カッパーポストを収容するための貫通孔とを設けることで形成できる。 The cavity substrate in the present embodiment is for forming a cavity on the base substrate, and the cavity is for providing a space for housing a semiconductor element or the like. The cavity substrate of the present embodiment has a through hole that accommodates the copper post, and an opening that forms a cavity portion on the base substrate. As a method of forming such a cavity substrate, for example, after forming a copper foil of a copper-clad laminate, an adhesive is temporarily bonded to the bonding surface with the base substrate, and an opening for the cavity and a copper post are accommodated. It can form by providing the through-hole for doing.
本実施における接着剤とは、ベース基板とキャビティ基板とを接着するものである。接着剤は、パッケージ基板の製造に用いられるエポキシやポリイミド系の多層化接着用の接着剤を用いることができ、熱プレスやラミネート等によりキャビティ基板に仮接着することができるのが望ましい。このような接着剤として、例えば、強化繊維に熱硬化性樹脂を含浸し、加熱・乾燥して、半硬化状にしたプリプレグや、ポリエチレンテレフタレートフィルム上に熱硬化性樹脂を塗布し、加熱・乾燥してドライフィルム状にした接着シートを使用することができる。熱硬化樹脂としては、エポキシ樹脂、フェノール樹脂、ポリイミド樹脂、ビスマレイミド樹脂等が使用でき、強化繊維としては、ガラス布、ガラス紙、アミド布、アミド紙が使用できる。 The adhesive in this embodiment is for bonding the base substrate and the cavity substrate. As the adhesive, an epoxy or polyimide multilayer adhesive used for manufacturing a package substrate can be used, and it is desirable that the adhesive can be temporarily bonded to the cavity substrate by hot pressing or lamination. As such an adhesive, for example, a curable fiber is impregnated with a thermosetting resin, heated and dried, and applied to a semi-cured prepreg or a polyethylene terephthalate film, and then heated and dried. Then, an adhesive sheet in the form of a dry film can be used. As the thermosetting resin, epoxy resin, phenol resin, polyimide resin, bismaleimide resin or the like can be used, and as the reinforcing fiber, glass cloth, glass paper, amide cloth or amide paper can be used.
また、接着剤は、エラストマー材であるのが好ましい。エラストマー材として使用する接着剤としては、十分な接着強度を有し、かつキャビティ基板とベース基板の寸法変化の挙動の差によって生じる、ベース基板のカッパーポストと、これを収容するキャビティ基板の貫通孔との位置関係の変動による歪みを吸収することができるものが好ましい。このような接着剤として、例えば、エポキシ樹脂及び硬化剤成分１００質量部に対し、ゴム変成のエポキシ樹脂２０質量部〜５０質量部、分子量が１万以上のエポキシ骨格の高分子成分１０質量部〜４０質量部、分子量５万以上のゴム成分５０質量部〜１５０質量部、硬化促進剤０．３質量部〜２．５質量部からなる接着剤組成物を、基材フィルムに塗布し、半硬化状態に熱処理してなる熱硬化性接着シートを、基材フィルムから剥がして、真空熱プレス等で加熱・加圧することで形成されるものが挙げられる。 The adhesive is preferably an elastomer material. As an adhesive used as an elastomer material, a base substrate copper post having sufficient adhesive strength and caused by a difference in dimensional change behavior between the cavity substrate and the base substrate, and a through hole of the cavity substrate for accommodating the same It is preferable to be able to absorb the distortion due to the fluctuation of the positional relationship between As such an adhesive, for example, 20 parts by mass to 50 parts by mass of a rubber-modified epoxy resin and 10 parts by mass of an epoxy skeleton polymer component having a molecular weight of 10,000 or more with respect to 100 parts by mass of the epoxy resin and the curing agent component An adhesive composition comprising 40 parts by mass, a rubber component having a molecular weight of 50,000 or more and 50 parts by mass to 150 parts by mass, and a curing accelerator 0.3 parts by mass to 2.5 parts by mass is applied to a base film and semi-cured. Examples include those formed by peeling a thermosetting adhesive sheet that is heat-treated into a state from a base film, and heating and pressing with a vacuum hot press or the like.
また、接着剤は、キャビティ基板にラミネータ等で仮接着可能なものが、作業性の点から望ましい。加熱・加圧後の接着剤の弾性率は、５０℃で１００ＭＰａ〜５００ＭＰａのものを使用でき、特には５００Ｍｐａ程度が望ましい。なお、弾性率は、株式会社ユービーエム製、Ｒｈｅｏｇｅｌ Ｅ−４０００型粘弾性測定装置を用い、ＤＶＥ法にて、引張モード、周波数１０Ｈｚ、昇温速度５℃／分の条件で測定した値である。樹脂フロー量（加熱・加圧後の端部からの樹脂流れ量）は、５０μｍ〜１５００μｍのものを使用でき、成形性と有底ビア内へのしみ出し量のバランスから１００μｍ〜５００μｍが望ましく、特には３００μｍ程度のものが望ましい。なお、樹脂フロー量は、加熱・加圧前のシート状態の接着剤を直径１０ｍｍの円形に打抜いたものをサンプルとして、これをＰＥＴ（ポリエチレンテレフタレート）フィルムで挟み込み、熱プレス（１００℃、３Ｍｐａ、５分）を行なった後、サンプルの直径を３箇所測定して平均し、熱プレス前の寸法との差を計算により求めることで測定した値である。 In addition, an adhesive that can be temporarily bonded to the cavity substrate with a laminator or the like is desirable from the viewpoint of workability. As the elastic modulus of the adhesive after heating and pressurization, an adhesive having a viscosity of 100 MPa to 500 MPa at 50 ° C. can be used, and about 500 MPa is particularly desirable. The elastic modulus is a value measured by the DVE method using a Rheogel E-4000 viscoelasticity measuring device manufactured by UBM Co., Ltd. under a tensile mode, a frequency of 10 Hz, and a heating rate of 5 ° C./min. . The resin flow amount (resin flow amount from the end after heating and pressurization) can be 50 μm to 1500 μm, and is preferably 100 μm to 500 μm from the balance between moldability and the amount of exudation into the bottomed via. In particular, about 300 μm is desirable. The resin flow amount was obtained by punching a sheet-form adhesive before heating / pressing into a circular shape with a diameter of 10 mm, and sandwiching it with a PET (polyethylene terephthalate) film, followed by hot pressing (100 ° C., 3 Mpa). 5 minutes), the diameter of the sample was measured at three locations, averaged, and the value measured by calculating the difference from the dimensions before hot pressing.
ゴム変成のエポキシ樹脂としては、ＣＴＢＮ（カルボキシ基末端ブタジエンニトリルゴム）変成品であり、かつ変成率が３０％〜６０％のものが挙げられる。ゴム成分としては、分子量５万以上のエポキシ基含有アクリルニトリルブタジエンゴムが挙げられる。半硬化状態は、基材フィルムに塗布した後の熱処理により、１０％〜６０％の硬化率とすることにより得ることができる。このようなエラストマーとしての作用を有する接着剤を使用することにより、エラストマー材としての接着剤が、キャビティ基板とベース基板の寸法変化の挙動の差によって生じる、ベース基板のカッパーポストと、これを収容するキャビティ基板の貫通孔との位置関係の変動による歪みを吸収するので、パッケージ基板の反りを抑制することができる。特に、キャビティ基板とベース基板に使用される材料や層構成が異なったり、キャビティ部用の開口を有するために開口率が異なる場合は、製造時や使用時のキャビティ基板とベース基板の寸法変化の挙動が異なるため、積層に用いる接着剤としてエラストマー材を使用するのが有効である。このような接着剤としては、例えば、ＡＳ２６００、ＡＳ３０００、ＧＦ３５００、ＧＦ３６００（何れも日立化成株式会社製 製品名）を挙げることができる。接着剤の厚みとしては、１０μｍ〜５０μｍを使用することができ、２０μｍ〜５０μｍが望ましく、特には、２５μｍ〜４０μｍが望ましい。これより薄い場合は、キャビティ基板の導体回路の厚みによる段差等を埋めることができず、またキャビティ基板とベース基板の寸法変化の挙動の違い等による歪みを吸収しにくくなる。これより厚い場合は、エラストマー材でもある接着剤の動きが大きくなり、接続信頼性が低下する可能性がある。 Examples of the rubber-modified epoxy resin include CTBN (carboxy group-terminated butadiene nitrile rubber) -modified products and those having a conversion rate of 30% to 60%. Examples of the rubber component include epoxy group-containing acrylonitrile butadiene rubber having a molecular weight of 50,000 or more. The semi-cured state can be obtained by setting the curing rate to 10% to 60% by heat treatment after being applied to the base film. By using such an adhesive having an action as an elastomer, the adhesive as an elastomer material accommodates the copper substrate post of the base substrate, which is caused by the difference in the dimensional change behavior of the cavity substrate and the base substrate. Since the distortion due to the fluctuation of the positional relationship with the through hole of the cavity substrate to be absorbed is absorbed, the warpage of the package substrate can be suppressed. In particular, if the material and layer configuration used for the cavity substrate and the base substrate are different, or if the aperture ratio is different due to having an opening for the cavity part, the dimensional change between the cavity substrate and the base substrate during manufacturing or use Since the behavior is different, it is effective to use an elastomer material as an adhesive used for lamination. Examples of such an adhesive include AS2600, AS3000, GF3500, and GF3600 (all are product names manufactured by Hitachi Chemical Co., Ltd.). The thickness of the adhesive may be 10 μm to 50 μm, preferably 20 μm to 50 μm, and particularly preferably 25 μm to 40 μm. If the thickness is smaller than this, a step due to the thickness of the conductor circuit of the cavity substrate cannot be filled, and it becomes difficult to absorb distortion due to a difference in behavior of dimensional change between the cavity substrate and the base substrate. If it is thicker than this, the movement of the adhesive, which is also an elastomer material, increases, and connection reliability may be reduced.
本実施の形態においては、カッパーポストとこれを収容する貫通孔の内壁との間に、ベース基板とキャビティ基板との間に配置される接着剤が配置される。つまり、ベース基板とキャビティ基板との間に配置される接着剤が、カッパーポストとこれを収容する貫通孔の内壁との間にも配置されている。これは、ベース基板とキャビティ基板とを接着剤を介して熱プレス等を用いて張り合わせる本接着の際に、接着剤が流動することで、カッパーポストとこれを収容する貫通孔の内壁との間にも接着剤が回りこむことで可能になる。このように、カッパーポストとこれを収容する貫通孔の内壁との間に、接着剤が配置されることで、接着剤が有するエラストマー性を利用して、ベース基板のカッパーポストと、これを収容するキャビティ基板の貫通孔との位置関係の変動による歪みを吸収することができる。このため、ベース基板とキャビティ基板を接着剤で張り合わせるという汎用プロセスを使うことで、キャビティ構造を有する高密度なパッケージ基板が形成できる。さらに、キャビティ構造によって、パッケージ形成における汎用性を実現できる。したがって、高密度実装性や信頼性を確保しつつ、キャビティ構造によって汎用性を実現可能なパッケージ基板を提供することができる。 In the present embodiment, an adhesive disposed between the base substrate and the cavity substrate is disposed between the copper post and the inner wall of the through hole that accommodates the copper post. That is, the adhesive disposed between the base substrate and the cavity substrate is also disposed between the copper post and the inner wall of the through hole that accommodates the copper post. This is because the adhesive flows when the base substrate and the cavity substrate are bonded to each other using a hot press or the like through the adhesive, so that the copper post and the inner wall of the through hole that accommodates the copper post This is possible because the adhesive is wrapped in between. As described above, the adhesive is disposed between the copper post and the inner wall of the through hole that accommodates the copper post, so that the copper substrate post and the base post are accommodated by utilizing the elastomeric property of the adhesive. It is possible to absorb distortion due to a change in the positional relationship with the through hole of the cavity substrate. Therefore, a high-density package substrate having a cavity structure can be formed by using a general-purpose process in which the base substrate and the cavity substrate are bonded together with an adhesive. Further, the cavity structure can realize versatility in package formation. Therefore, it is possible to provide a package substrate that can realize versatility with the cavity structure while ensuring high-density mounting and reliability.
カッパーポストとこれを収容する貫通孔の内壁との間に間隙を有しており、この間隙に接着剤が充填されるのが望ましい。これにより、カッパーポストと貫通孔の内壁との間の間隙が、いわゆる遊びの役割を果たし、緩衝作用を発揮することにより、キャビティ基板とベース基板の寸法変化の挙動の差によって、ベース基板のカッパーポストと、これを収容するキャビティ基板の貫通孔との位置関係に変動が生じても、カッパーポストと貫通孔の内壁とがすぐには接触し難いため、歪みを生じ難い。また、カッパーポストと貫通孔の内壁と間の間隙には、接着剤が充填されているため、隙間が生じないようにすることができ、また、接着剤が有するエラストマー性を利用して、ベース基板のカッパーポストと、これを収容するキャビティ基板の貫通孔との位置関係の変動による歪みを吸収することができる。カッパーポストとこれを収容する貫通孔の内壁との間に間隙を有するようにするには、例えば、ベース基板と張り合わせる前のキャビティ基板に予め形成する、カッパーポストを収容するための貫通孔の孔径を、カッパーポストの径に対して大きくしておく方法等をとることができる。カッパーポストとこれを収容する貫通孔の内壁との間の間隙に、接着剤を充填するには、ベース基板とキャビティ基板とを接着剤を介して熱プレス等を用いて張り合わせる本接着の際に、接着剤が十分流動するように熱プレス条件等を調整することで、カッパーポストとこれを収容する貫通孔の内壁との間の間隙に接着剤を充填することが可能になる。 It is desirable to have a gap between the copper post and the inner wall of the through hole that accommodates the copper post, and this gap is preferably filled with an adhesive. As a result, the gap between the copper post and the inner wall of the through-hole plays a role of so-called play and exhibits a buffering action, so that the difference in the dimensional change behavior between the cavity substrate and the base substrate causes a difference in the base substrate copper. Even if the positional relationship between the post and the through-hole of the cavity substrate that accommodates the post changes, the copper post and the inner wall of the through-hole do not readily come into contact with each other, so that distortion is hardly generated. In addition, since the gap between the copper post and the inner wall of the through hole is filled with an adhesive, it is possible to prevent the gap from being generated, and the base using the elastomeric property of the adhesive It is possible to absorb the distortion caused by the change in the positional relationship between the copper post of the substrate and the through hole of the cavity substrate that accommodates the copper post. In order to have a gap between the copper post and the inner wall of the through hole that accommodates the copper post, for example, a through hole for accommodating the copper post that is formed in advance on the cavity substrate before being bonded to the base substrate is used. A method of increasing the hole diameter with respect to the diameter of the copper post can be employed. In order to fill the gap between the copper post and the inner wall of the through hole that accommodates it with the adhesive, the base substrate and the cavity substrate are bonded to each other using a hot press or the like through the adhesive. In addition, by adjusting the hot press conditions or the like so that the adhesive flows sufficiently, the adhesive can be filled in the gap between the copper post and the inner wall of the through hole that accommodates the copper post.
カッパーポストとこれを収容する貫通孔の内壁との間に配置される接着剤の熱膨張係数が、２０ｐｐｍ／℃以上であることが望ましい。例えば、上述したエラストマー材となる高分子タイプの接着剤シートを用いることができる。 The thermal expansion coefficient of the adhesive disposed between the copper post and the inner wall of the through hole that accommodates the copper post is desirably 20 ppm / ° C. or higher. For example, a polymer type adhesive sheet to be the elastomer material described above can be used.
ベース基板の絶縁層表面の導体回路の底面及び側面が、絶縁層中に埋め込まれているのが望ましい。例えば、導体回路の底面及び側面が絶縁層中に埋め込まれている導体回路（埋め込み回路）を形成するには、例えば、銅箔表面にめっきレジストを形成し、次いで、電解銅めっきを行った後、めっきレジストを剥離し、熱プレスを用いて、銅箔表面の凸回路を絶縁層に転写する、いわゆる転写法を用いて形成することができる。このように、ベース基板の絶縁層表面の導体回路の底面及び側面が、絶縁層中に埋め込まれていることにより、絶縁層表面の導体回路は、その低面と側面が絶縁層と接着するので、導体回路の密着力が向上する。このため、ベース基板の絶縁層表面の導体回路上に凸状のカッパーポストが形成されることにより、カッパーポストの接触等による機械的な応力が加わり易くなっても、カッパーポストは剥離を生じ難くなり信頼性が向上する。 It is desirable that the bottom surface and the side surface of the conductor circuit on the surface of the insulating layer of the base substrate are embedded in the insulating layer. For example, to form a conductor circuit (embedded circuit) in which the bottom and side surfaces of the conductor circuit are embedded in an insulating layer, for example, after forming a plating resist on the copper foil surface and then performing electrolytic copper plating The plating resist can be peeled off, and a hot press can be used to transfer the convex circuit on the surface of the copper foil to the insulating layer. Thus, since the bottom surface and side surface of the conductor circuit on the surface of the insulating layer of the base substrate are embedded in the insulating layer, the lower surface and side surface of the conductor circuit on the surface of the insulating layer are bonded to the insulating layer. The adhesion of the conductor circuit is improved. For this reason, even if it becomes easy to apply mechanical stress due to contact of the copper post or the like by forming the convex copper post on the conductor circuit on the surface of the insulating layer of the base substrate, the copper post does not easily peel off. Reliability is improved.
ベース基板の絶縁層表面の導体回路上に配置されるカッパーポストの高さが２種類（２段階）以上であるのが望ましい。これにより、例えば、キャビティ内に立体回路を形成することができ、様々な端子構造が可能になるので、複数の半導体素子の搭載も可能になり、さらに高密度化を図ることができる。導体回路上に配置されるカッパーポストの高さを２種類（２段階）以上にする方法としては、例えば、ベース基板の絶縁層表面の導体回路を含む全面に、給電層となる下地無電解めっきと電解銅めっきを形成した後、１段目のカッパーポストに対応するめっきレジストを形成し、電解銅めっきを行い１段目のカッパーポストを形成する。その後、１段目のめっきレジストを剥離し、２段目のカッパーポストに対応するめっきレジストを形成する。このとき、めっきレジストの厚さを確保するため、複数層のめっきレジストを重ねて形成してもよい。次に、電解銅めっきを行い２段目のカッパーポストを形成する。その後、全てのめっきレジストと不要な箇所の給電層を除去することにより、所望の位置や範囲（大きさ、形状）に、所望の高さで、２種類（２段階）以上の高さを有するカッパーポストを形成することができる。 It is desirable that the height of the copper post disposed on the conductor circuit on the surface of the insulating layer of the base substrate is two kinds ( two stages ) or more. Thereby, for example, a three-dimensional circuit can be formed in the cavity, and various terminal structures are possible. Therefore, a plurality of semiconductor elements can be mounted, and the density can be further increased. As a method of making the height of the copper posts arranged on the conductor circuit more than two types ( two stages ) , for example, the base electroless plating that becomes the power supply layer on the entire surface including the conductor circuit on the surface of the insulating layer of the base substrate After forming the electrolytic copper plating, a plating resist corresponding to the first-stage copper post is formed, and electrolytic copper plating is performed to form the first-stage copper post. Thereafter, the first-stage plating resist is removed to form a plating resist corresponding to the second-stage copper post. At this time, in order to secure the thickness of the plating resist, a plurality of layers of plating resists may be stacked. Next, electrolytic copper plating is performed to form a second-stage copper post. After that, by removing all plating resists and unnecessary power feeding layers, the desired position and range (size, shape) have two or more types ( two steps ) at the desired height. Copper posts can be formed.
図７に示すように、ベース基板３のカッパーポスト７の上端が、キャビティ基板８の表面に露出するのが望ましい。これにより、カッパーポスト７の上端に、金めっきやはんだ、プリフラックス等を処理することで、そのまま外部接続端子として用いることが可能になる。カッパーポスト７の上端が、キャビティ基板８の表面に露出するようにするには、キャビティ基板８の表面側から、カッパーポスト７の上端が露出するまで研磨を行う方法を用いることができる。 As shown in FIG. 7, it is desirable that the upper end of the copper post 7 of the base substrate 3 is exposed on the surface of the cavity substrate 8. As a result, the upper end of the copper post 7 is treated with gold plating, solder, preflux or the like, so that it can be used as it is as an external connection terminal. In order to expose the upper end of the copper post 7 on the surface of the cavity substrate 8, a method of polishing from the surface side of the cavity substrate 8 until the upper end of the copper post 7 is exposed can be used.
ベース基板のカッパーポストの上端が、キャビティ基板の表面に対して凹部を形成するようにしてもよい。これにより、カッパーポストの上端を外部接続端子として使用する際に、接続する他のパッケージ基板のバンプ等との位置合せが容易になる。カッパーポストの上端が、キャビティ基板の表面に対して凹部を形成するようにするには、キャビティ基板の表面側から、カッパーポスト７の上端が露出するまでレーザ加工を行うか、又は、カッパーポストの上端が露出するまで研磨を行った後、カッパーポストの上端をエッチングする方法が挙げられる。 The upper end of the copper substrate post may form a recess with respect to the surface of the cavity substrate. Accordingly, when the upper end of the copper post is used as an external connection terminal, alignment with bumps of other package substrates to be connected becomes easy. In order for the upper end of the copper post to form a recess with respect to the surface of the cavity substrate, laser processing is performed from the surface side of the cavity substrate until the upper end of the copper post 7 is exposed, or There is a method in which the upper end of the copper post is etched after polishing until the upper end is exposed.
図８に示すように、カッパーポスト７の上端に、はんだ１４が配置されるようにしてもよい。これにより、カッパーポスト７の上端を、そのまま外部接続端子として用いることが可能になる。このように、カッパーポスト７の上端にはんだ１４を配置するには、キャビティ基板８の表面側から、カッパーポスト７の上端が露出するまでレーザ加工を行うか、カッパーポストの上端が露出するまで研磨を行った後、カッパーポスト７の上端に、はんだペーストやはんだボールを供給し、リフローする方法が挙げられる。さらに、カッパーポスト７の上端に配置されるはんだ１４の上端が、キャビティ基板８の表面と面一であるようにしてもよい。このように、はんだ１４の上端が、キャビティ基板８の表面と面一であるようにするには、キャビティ基板８の表面側から、研磨する方法が挙げられる。 As shown in FIG. 8, solder 14 may be disposed on the upper end of the copper post 7. Thereby, the upper end of the copper post 7 can be used as it is as an external connection terminal. As described above, in order to place the solder 14 on the upper end of the copper post 7, laser processing is performed from the surface side of the cavity substrate 8 until the upper end of the copper post 7 is exposed, or polishing is performed until the upper end of the copper post 7 is exposed. After performing the above, there is a method in which a solder paste or a solder ball is supplied to the upper end of the copper post 7 and reflowed. Further, the upper end of the solder 14 disposed at the upper end of the copper post 7 may be flush with the surface of the cavity substrate 8. Thus, in order to make the upper end of the solder 14 flush with the surface of the cavity substrate 8, a method of polishing from the surface side of the cavity substrate 8 can be mentioned.
図９に示すように、カッパーポスト７の上端に、キャビティ基板８の表面の導体回路１３が配置されるようにしてもよい。これにより、カッパーポスト７の上端にも導体回路１３を配置できるので、より高密度化を図ることができる。このように、カッパーポスト７の上端に、キャビティ基板８の表面の導体回路１３が配置されるようにするには、例えば、キャビティ基板８の表面側から、カッパーポスト７の上端が露出するまで研磨を行った後、無電解下地銅めっきを行い、めっきレジストを形成後に電解銅めっきを行い、めっきレジストを剥離し、不要な箇所の無電解下地銅めきを除去する方法が挙げられる。 As shown in FIG. 9, the conductor circuit 13 on the surface of the cavity substrate 8 may be disposed at the upper end of the copper post 7. Thereby, since the conductor circuit 13 can also be arrange | positioned also at the upper end of the copper post 7, it can achieve higher density. In this way, in order to arrange the conductor circuit 13 on the surface of the cavity substrate 8 at the upper end of the copper post 7, for example, polishing from the surface side of the cavity substrate 8 until the upper end of the copper post 7 is exposed. Then, electroless base copper plating is performed, and after forming a plating resist, electrolytic copper plating is performed, the plating resist is peeled off, and an electroless base copper plating at an unnecessary portion is removed.
以下に、本発明の実施例を説明するが、本発明は本実施例に限定されない。 Examples of the present invention will be described below, but the present invention is not limited to the examples.
（実施例１）
まず、図２に示すように、一般的なビルドアップ工法により、ベース基板３を形成した。なお、絶縁層１６表面の導体回路１７（図２の最も下側の導体回路１７）は、導体回路１７の底面及び側面が、絶縁層１６中に埋め込まれている。この埋め込み回路（導体回路１７）は、図示しないが、銅箔表面にめっきレジストを形成し、次いで、電解銅めっきを行った後、めっきレジストを剥離し、熱プレスを用いて、銅箔表面の凸回路を絶縁層１６に埋め込み、表面の銅箔をエッチング除去して、凸回路を絶縁層１６内に残す、いわゆる転写法を用いて形成した。
Example 1
First, as shown in FIG. 2, the base substrate 3 was formed by a general buildup method. The conductor circuit 17 on the surface of the insulating layer 16 (the lowermost conductor circuit 17 in FIG. 2) has the bottom surface and side surfaces of the conductor circuit 17 embedded in the insulating layer 16. Although not shown in the drawing, this embedded circuit (conductor circuit 17) forms a plating resist on the surface of the copper foil, and after performing electrolytic copper plating, the plating resist is peeled off and the surface of the copper foil is removed using a hot press. The convex circuit was embedded in the insulating layer 16, the copper foil on the surface was etched away, and the convex circuit was left in the insulating layer 16, and was formed using a so-called transfer method.
次いで、ベース基板３表面の両面にソルダーレジスト２を形成した後、このソルダーレジスト２を含む全面に、給電層１８を形成するため、下地無電解銅めっきと電解銅めっき（厚さ約２μｍ）を析出させた。次に、電解銅めっき表面に、１段目のカッパーポスト４に対応するめっきレジスト１を形成し、電解銅めっきを行い１段目のカッパーポスト４を形成した。次いで、１段目のカッパーポスト４に対応するめっきレジスト１の剥離を行った。 Next, after forming the solder resist 2 on both surfaces of the surface of the base substrate 3, in order to form the power supply layer 18 on the entire surface including the solder resist 2, a base electroless copper plating and an electrolytic copper plating (thickness of about 2 μm) are performed. Precipitated. Next, a plating resist 1 corresponding to the first-stage copper post 4 was formed on the electrolytic copper-plated surface, and electrolytic copper plating was performed to form the first-stage copper post 4. Next, the plating resist 1 corresponding to the first-stage copper post 4 was peeled off.
図３に示すように、図２で得た、１段目のカッパーポスト４を有するベース基板３上に、２段目のカッパーポストに対応するめっきレジストを形成した。このとき、めっきレジスト１の厚さを確保するため、３層のめっきレジスト１を重ねて形成した。次に、電解銅めっきを行い、２段目のカッパーポスト７を形成した。その後、全てのめっきレジスト１を除去することにより、２種類（２段階）以上の高さを有するカッパーポスト４，７を形成した。 As shown in FIG. 3, a plating resist corresponding to the second-stage copper post was formed on the base substrate 3 having the first-stage copper post 4 obtained in FIG. At this time, in order to ensure the thickness of the plating resist 1, three layers of the plating resist 1 were formed in an overlapping manner. Next, electrolytic copper plating was performed to form a second-stage copper post 7. Thereafter, all the plating resists 1 were removed to form copper posts 4 and 7 having two or more types ( two stages ) or more.
図４に示すように、図３で得た２種類（２段階）のカッパーポスト４，７を有するベース基板３の表面に、給電層１８として析出させた無電解銅めっきと電解銅めっきとを、硫酸過水系エッチング液を用いて、約３μｍ程度のエッチングを行って除去した。次いで、パラジウム除去液を用いて絶縁層１６表面に吸着したパラジウムの除去を行った。
As shown in FIG. 4, electroless copper plating and electrolytic copper plating deposited as a power feeding layer 18 on the surface of the base substrate 3 having the two types ( two stages ) of copper posts 4 and 7 obtained in FIG. Then, it was removed by etching with about 3 μm using a sulfuric acid / hydrogen peroxide etching solution. Next, palladium adsorbed on the surface of the insulating layer 16 was removed using a palladium removing solution.
図５に示すように、銅張り積層板の両面の銅箔を全面除去した後、銅箔を全面除去した絶縁層１９の表面に、余熱ラミネーターを用いて、接着剤を仮接着した。次に、ルーター加工機を用いて、キャビティ部１２を形成する開口１０及び２段目のカッパーポスト７を収容する貫通孔９を形成し、キャビティ基板８を準備した。 As shown in FIG. 5, after removing the copper foils on both sides of the copper-clad laminate, the adhesive was temporarily bonded to the surface of the insulating layer 19 from which the copper foils were completely removed using a residual heat laminator. Next, using the router processing machine, the opening 10 for forming the cavity portion 12 and the through hole 9 for accommodating the second-stage copper post 7 were formed, and the cavity substrate 8 was prepared.
図６に示すように、図４で得たベース基板３上に、図５で得たキャビティ基板８の接着剤１１を仮接着した面を向けて、真空熱プレス機を用いて本接着を行い、パッケージ基板１５を作製した。 As shown in FIG. 6, the surface temporarily bonded with the adhesive 11 of the cavity substrate 8 obtained in FIG. 5 is directed on the base substrate 3 obtained in FIG. 4, and the main bonding is performed using a vacuum hot press machine. A package substrate 15 was produced.
図７に示すように、図６で得たパッケージ基板１５のキャビティ基板８表面を、デバリング装置を用いて研磨し、カッパーポスト７の上端を露出させ、次いで、無電解ニッケル・金めっき（図示しない。）を施した。 As shown in FIG. 7, the surface of the cavity substrate 8 of the package substrate 15 obtained in FIG. 6 is polished using a deburring device to expose the upper end of the copper post 7, and then electroless nickel / gold plating (not shown) .) Was applied.
（実施例２）
図８に示すように、図６で得たパッケージ基板１５のカッパーポスト７の上部側からレーザー加工を施し、カッパーポスト７の上端を露出させ、ついで、プラズマ処理を用いて、有機物残渣を取り除き、次にはんだペーストを印刷法で形成した。
(Example 2)
As shown in FIG. 8, laser processing is performed from the upper side of the copper post 7 of the package substrate 15 obtained in FIG. 6 to expose the upper end of the copper post 7, and then organic processing residues are removed using plasma treatment, Next, a solder paste was formed by a printing method.
（実施例３）
図９に示すように、図７で得たパッケージ基板１５に、無電解銅めっきを施し、次いで、めっきレジスト（図示しない。）を、キャビティ部１２用の開口１０を覆うようにキャビティ基板８の表面に形成し、次いで、電解銅めっきをカッパーポスト７と接続するように形成し、次いで、エッチングレジスト（図示しない。）を、キャビティ部１２用の開口１０を覆うようにキャビティ基板８の表面に形成し、サブトラクト法で導体回路１３を形成した。次に、フィルムレジストを用いて、真空加圧ラミネーターで圧着を行い、次いで、フィルムレジスト形成工法を用いて、ソルダーレジスト２形成を行った。
(Example 3)
As shown in FIG. 9, the package substrate 15 obtained in FIG. 7 is subjected to electroless copper plating, and then a plating resist (not shown) is applied to the cavity substrate 8 so as to cover the opening 10 for the cavity portion 12. Then, an electrolytic copper plating is formed so as to connect with the copper post 7, and then an etching resist (not shown) is applied to the surface of the cavity substrate 8 so as to cover the opening 10 for the cavity portion 12. The conductor circuit 13 was formed by the subtract method. Next, the film resist was subjected to pressure bonding with a vacuum pressure laminator, and then the solder resist 2 was formed using a film resist forming method.
１：めっきレジスト
２：ソルダーレジスト
３：ベース基板
４：（１段目の）カッパーポスト
５：無電解銅めっき
６：電解銅めっき
７：（２段目の）カッパーポスト
８：キャビティ基板
９：貫通孔
１０：開口
１１：接着剤
１２：キャビティ部
１３：（キャビティ基板表面の）導体回路
１４：はんだ
１５：（半導体素子搭載用）パッケージ基板
１６：絶縁層
１７：（ベース基板表面の）導体回路
１８：給電層
１９：絶縁層
1: plating resist 2: solder resist 3: base substrate 4: (first stage) copper post 5: electroless copper plating 6: electrolytic copper plating 7: (second stage) copper post 8: cavity substrate 9: penetration Hole 10: Opening 11: Adhesive 12: Cavity part 13: Conductor circuit 14 (on the surface of the cavity substrate) 14: Solder 15: (for mounting a semiconductor element) Package substrate 16: Insulating layer 17: Conductor circuit 18 (on the surface of the base substrate) : Feed layer 19: Insulating layer
Claims (10)
前記ベース基板とキャビティ基板とが、異なる寸法変化挙動を有するものであり、
前記カッパーポストとこれを収容する前記貫通孔の内壁との間に間隙を有し、この間隙に前記接着剤が充填され、
この接着剤の弾性率が５０℃で１００〜５００ＭＰａである半導体素子搭載用パッケージ基板。 A base substrate having a copper post convexly disposed on a conductor circuit on the surface of the insulating layer; a cavity substrate having a through hole for accommodating the copper post; and an opening for forming a cavity portion on the base substrate; and the base and an adhesive disposed between the substrate and the cavity substrate, between the inner wall of the through hole to accommodate this and the copper post, in the semiconductor element mounting package substrate on which the adhesive is disposed There,
The base substrate and the cavity substrate have different dimensional change behavior,
There is a gap between the copper post and the inner wall of the through hole that accommodates the copper post, and the gap is filled with the adhesive,
A package substrate for mounting a semiconductor element, wherein the adhesive has an elastic modulus of 100 to 500 MPa at 50 ° C.
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