WO2012164719A1 - Substrate with built-in component, and method for producing said substrate - Google Patents

Substrate with built-in component, and method for producing said substrate Download PDF

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Publication number
WO2012164719A1
WO2012164719A1 PCT/JP2011/062693 JP2011062693W WO2012164719A1 WO 2012164719 A1 WO2012164719 A1 WO 2012164719A1 JP 2011062693 W JP2011062693 W JP 2011062693W WO 2012164719 A1 WO2012164719 A1 WO 2012164719A1
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WIPO (PCT)
Prior art keywords
component
layer
formed
adhesive layer
conductive
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Application number
PCT/JP2011/062693
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French (fr)
Japanese (ja)
Inventor
光昭 戸田
松本 徹
圭男 今村
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株式会社メイコー
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Priority to PCT/JP2011/062693 priority Critical patent/WO2012164719A1/en
Publication of WO2012164719A1 publication Critical patent/WO2012164719A1/en

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. IMC (insert mounted components)
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92142Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10636Leadless chip, e.g. chip capacitor or resistor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4602Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product
    • Y02P70/60Greenhouse gas [GHG] capture, heat recovery or other energy efficient measures relating to production or assembly of electric or electronic components or products, e.g. motor control
    • Y02P70/611Greenhouse gas [GHG] capture, heat recovery or other energy efficient measures relating to production or assembly of electric or electronic components or products, e.g. motor control the product being a printed circuit board [PCB]

Abstract

A substrate (1) with a built-in component, the substrate (1) being provided with an insulating layer (2), a conductive layer (6) formed on the surface of the insulating layer (2), an electric or electronic component (3) embedded in the insulating layer (2), a plurality of terminals (4) disposed on the component (3) and electrically connected to the conductive layer (6), and an adhesive layer (10) for adhering the terminals (4) to the conductive layer (6), wherein the adhesive layer (10) is formed only within a region that is approximately the same as the outer edge of the terminals (4), and a component main body (5) only comes into contact with the insulating layer (2), the component main body (5) being a section of the component (3) excluding the section on which the terminals (4) are disposed.

Description

Component built-in substrate and manufacturing method thereof

The present invention relates to a component-embedded substrate in which components are embedded and a method for manufacturing the same.

2. Description of the Related Art A component-embedded substrate in which components such as electronic components are embedded in an insulating layer is known (for example, see Patent Document 1). Generally, in such a component-embedded substrate, an adhesive is applied to an area corresponding to the component when the component is mounted. However, when the adhesive is applied to an area corresponding to a part, voids due to bubbles are locally generated in the adhesive. Such a state is called a void, and this void expands in the subsequent reflow process, or causes peeling or a short circuit.

Also, the adhesive is in contact with the circuit pattern that electrically connects the built-in components. For this reason, it is necessary that the adhesive is a material having an electrically good insulating property. Furthermore, the built-in component is electrically connected to the circuit pattern on the surface. For this reason, vias are also formed in the adhesive as a pretreatment. High connection reliability is required for a so-called conductive via in which conductivity is imparted to the via by plating or the like. Therefore, it is necessary to select an adhesive in consideration of laser processability for forming vias, plating coverage, and productivity.

Japanese translation of PCT publication No. 2008-522397

The present invention is a component-embedded substrate that can prevent generation of voids in an adhesive and has improved electrical insulation reliability, and a method for manufacturing the same.

In the present invention, an insulating layer, a conductive layer formed on the surface of the insulating layer, an electrical or electronic component embedded in the insulating layer, and provided in the component and electrically connected to the conductive layer In the component-embedded substrate having a plurality of terminals and an adhesive layer that adheres the terminals and the conductive layer, the adhesive layer is formed only within a range substantially equal to the outer edge of the terminal, A component main body which is a portion other than the terminal in the component is in contact with only the insulating layer.

Preferably, a plurality of the terminals are formed only on the peripheral edge of the component body, and the adhesive layer is formed on all of the terminals.

Preferably, a plurality of the terminals are formed over the entire one surface of the component main body, and the adhesive layer is formed on a part or all of the terminals.

Preferably, the adhesive layer is formed of an epoxy resin or a polyimide resin.
Preferably, the adhesive layer has a thickness of 10 μm to 120 μm.

Preferably, the adhesive layer is formed by stacking a plurality of adhesive portions of different materials or the same material.

Preferably, the adhesive layer has at least a first adhesive part in contact with the conductive layer and a second adhesive part in contact with the component as the adhesive part, and the glass transition temperature of the first adhesive part is 40. The glass transition temperature of the second adhesive portion is equal to or higher than the glass transition temperature of the first adhesive portion, and is in the range of 40 ° C. to 200 ° C. (TMA method).

Preferably, the thickness of the first adhesive portion is 5 μm to 60 μm, and the thickness of the second adhesive portion is 5 μm to 60 μm.

In the present invention, an adhesive layer forming step of forming the adhesive layer on the metal layer formed on the support plate, and bonding the terminal formed on the component to the adhesive layer, the adhesive layer A component-embedded board comprising: a component mounting step for mounting the component thereon; and a stacking step for stacking the insulating base material to be the insulating layer while pressing the component under vacuum. A manufacturing method for manufacturing is provided.

Preferably, the method further includes a conductive via forming step of forming a first conductive via by forming a via reaching the terminal from the outside of the metal layer after the laminating step and performing a conductive treatment on the via.

Preferably, the support plate used in the adhesive layer forming step is an aluminum plate, and the metal layer is a copper foil attached to the aluminum plate.
Preferably, the support plate used in the adhesive layer forming step is stainless steel, and the metal layer is a copper plating foil deposited on the stainless steel.

Preferably, a plurality of either or both of a semiconductor component having a plurality of electrodes and a passive component having a plurality of electrodes are mounted in the component mounting step.

Preferably, in the laminating step, a circuit board having either a conductive circuit, a conductive via, a conductive through hole, or a combination thereof in addition to the insulating layer is disposed on the side of the component, and the conductive via forming step Then, a second conductive via for electrically connecting the conductive layer and the circuit board is formed.

Preferably, in the conductive via formation step, the second conductive via is a filled via.
Preferably, the connection by the second conductive via has an any layer structure.

Preferably, in the adhesive layer forming step, the second adhesive portion is formed after the first adhesive portion is cured.

Preferably, in the conductive via forming step, the second conductive via has a diameter corresponding to a depth of the via to be formed, so that a depth: diameter ratio (aspect ratio of the hole) is 1 or less. And a diameter equal to or larger than that of the first conductive via.

Preferably, in the laminating step, the insulating base material having a thermal expansion coefficient close to that of the component is used.

According to the present invention, the adhesive layer is formed only in a range within approximately the same as the outer edge of the terminal. In other words, since the adhesive layer is formed to be approximately the same as, or within, or slightly larger than the outer edge of the surface facing the conductive layer of the terminal, the adhesive layer is the minimum necessary for mounting components. It will be formed in the size of. Therefore, voids can be prevented from occurring in the adhesive layer, and a highly reliable component-embedded substrate can be obtained. Moreover, the component main body which is parts other than the terminal in components contacts only the insulating layer. That is, this insulating layer is interposed between the adhesive layers. Therefore, high electrical insulation can be ensured between the terminals. As described above, by forming the adhesive layer corresponding to only the terminal portion, it is possible to form a stable adhesive layer even in a component having unevenness due to electronic circuits on the surface. As a result, it is possible to ensure the formation of stable conductive vias and high electrical connection reliability.

Moreover, if a component in which a plurality of terminals are formed only at the peripheral edge of the component main body is used as a built-in component, the interval between the terminals via the component main body is wide, and thus the interval between the adhesive layers can be widened. As a result, further electrical insulation can be ensured.

On the other hand, if the built-in component has a plurality of terminals formed over the entire surface of one side of the component body, and the adhesive layer is formed on a part of the terminal, the distance between the adhesive layers is increased. It can be provided and high electrical insulation can be secured. Even when a plurality of terminals are formed over the entire surface of one side of the component body, an adhesive layer may be formed for all the terminals if there is a sufficient space between the terminals. Even in this case, high electrical insulation can be ensured.

Further, according to the present invention, the adhesive layer is formed only in the same range as the outer edge of the terminal in the adhesive layer forming step, the adhesive layer and the terminal are bonded in the next component mounting step, and the next laminating step Press the insulating substrate. As a result, the insulating base material enters between the metal layer and the component main body, and the adhesive layers are adjacent to each other via the insulating base material. Therefore, high insulation between the terminals can be ensured when the terminals are conducted in the subsequent process. Moreover, since the lamination process is performed under vacuum, no voids are generated in the insulating base material.

Further, as the insulating base material, a material having a thermal expansion coefficient close to that of the component is preferably used. As a result, the behavior of the insulating substrate in a high-temperature environment can be brought close to that of the component, and it is possible to reduce the load caused by heat, such as internal stress, and to improve the connection reliability more effectively. Can do.

1 is a schematic cross-sectional view of a component built-in substrate according to the present invention. It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. It is a partial schematic diagram of another component built-in substrate according to the present invention. It is a partial schematic diagram of still another component-embedded substrate according to the present invention. It is AA sectional drawing of FIG. It is the schematic of another another component-embedded board which concerns on this invention.

As shown in FIG. 1, a component-embedded substrate 1 according to the present invention has a component 3 embedded in an insulating layer 2. The insulating layer 2 is formed by curing an insulating base material such as a prepreg. The component 3 is an electrical or electronic component, and is a chip component provided with terminals 4 serving as electrodes or a multi-pin component such as WL-CSP having a large number of terminals (FIG. 1 shows an example of a chip component). ing). That is, the component 3 is formed of a plurality of terminals 4 and other component bodies 5. A conductive layer 6 is formed on the surface of the insulating layer 2. In the figure, a double-sided substrate having conductive layers 6 formed on both sides is shown as an example. The conductive layer 6 is a metal conductor such as copper, and is patterned. The conductive layer 6 is electrically connected to the terminal 4 through the conductive via 7. For example, as shown in FIG. 1, the conductive layer 6 is partially exposed and covered with a solder resist 8. In the example of FIG. 1, a conductive through hole 18 that penetrates the substrate 1 and is subjected to a conductive process is formed. The conductive layers 6 on the front and back sides are electrically connected by the conductive through hole 18. The substrate 1 is a so-called double-sided substrate.

An adhesive layer 10 is disposed between the terminal 4 and the conductive layer 6. This adhesive layer 10 is formed only in a range substantially within the same range as the outer edge of the terminal 4 (FIG. 1 shows the adhesive layer 10 formed in a range equivalent to the outer edge of the terminal 4). Therefore, the component main body 5 which is a portion other than the terminal 4 in the component 3 is in contact with only the insulating layer 2. As described above, in the component-embedded substrate 1 of the present invention, the adhesive layer 10 is formed only in a range substantially within the outer edge of the terminal 4, and the adhesive layer 10 faces the conductive layer 6 of the terminal 4. Therefore, the adhesive layer 10 is formed in a minimum size necessary for mounting the component 3. Therefore, generation of voids in the adhesive layer 10 can be prevented, and the component-embedded substrate 1 with high reliability can be obtained. Even if voids are generated, since the adhesive layer 10 is formed in the minimum necessary size, only a limited size of voids can be generated, so that the influence on the reliability of the substrate 1 is small. Therefore, the component built-in substrate 1 with high reliability can be obtained. Further, since the component main body 5 is in contact only with the insulating layer 2, the insulating layer 2 is interposed between the adhesive layers 10. Therefore, electrical insulation between the terminals 4 can be ensured. Further, by forming the adhesive layer 10 corresponding to only the terminal 4 portion, the adhesive layer 10 can be stably formed even when the surface of the component 3 has irregularities due to electronic circuits. Thereby, it is possible to ensure the formation of the stable conductive via 7 and the reliability of the high electrical connection thereby.

Further, in the case of incorporating a component in which a plurality of terminals 4 are formed only at the peripheral portion of the component main body 5 (for example, a chip component having terminals only at both ends of the peripheral portion), the entire surface including the component main body 5 is included. Instead, the insulating layer 2 is formed between the terminals 4 by forming the adhesive layer 10 only for all of the terminals 4, so that high electrical insulation between the conductive vias 7 can be ensured.

The process for manufacturing such a component-embedded substrate 1 will be described below. In the following description, description will be made based on the drawings (FIGS. 2 to 8) showing only the part in the vicinity of the component 3 in the component-embedded substrate 1 shown in FIG.

First, an adhesive layer forming step is performed. In this step, first, as shown in FIG. 2, for example, a substrate in which a metal layer 12 is formed on a support plate 11 is prepared. The support plate 11 has a degree of rigidity required for process conditions. The support plate 11 is formed of a rigid SUS (stainless steel) plate or aluminum plate as a support base material. For example, when the support plate 11 is a SUS plate, the metal layer 12 is formed by depositing a copper plating foil having a predetermined thickness. Alternatively, the metal layer 12 is formed by attaching a copper foil if the support plate 11 is an aluminum plate. Then, as shown in FIG. 3, the adhesive layer 10 is applied on the metal layer 12 by, for example, a dispenser or printing. This adhesive layer 10 is formed of an epoxy-based or polyimide-based resin, and adheres the metal layer 12 and a terminal 4 described later. The adhesive layer 10 is formed to have the same size as the terminal 4 to be bonded, specifically, within the same range as the outer edge of the bonding surface of the terminal 4, and the thickness is not limited, but is about 10 μm to 120 μm. Are preferred.

After this, the component mounting process is performed. In this step, as shown in FIG. 4, for example, an electrical or electronic component 3 such as a chip component is mounted on the metal layer 12. Specifically, the terminal 4 provided in the component 3 is placed on the adhesive layer 10. As a result, the terminal and the adhesive layer 10 are bonded, and thus the metal layer 12 and the component 3 are connected via the adhesive layer 10. The adhesive layer 10 is cured by heating after the components are placed. A plurality of components 3 may be mounted. In this case, the adhesive layer 10 is formed corresponding to the number of parts 3. As the component 3 in this case, either or both of a semiconductor component having a plurality of electrodes and a passive component having a plurality of electrodes may be used.

After this, a lamination process is performed. This step is performed by laying up an insulating base material such as a prepreg on the side opposite to the side on which the metal layer 12 is disposed with respect to the component 3 and pressing it while heating under vacuum. This press is performed using, for example, a vacuum press machine. Since there is a sufficient gap between the component body 5 and the metal layer 12 due to the presence of the adhesive layer 10, the insulating substrate enters between the component body 5 and the metal layer 12 by this pressing. The insulating layer 2 is formed. Since the lamination process is performed under vacuum, no voids are generated in the insulating base material. Thereafter, the support plate 11 is removed. A metal layer 12 is laminated on one surface of the insulating layer 2, and another metal layer 13 is laminated on the other surface.

After this, a conductive via formation process is performed. In this step, first, as shown in FIG. 6, holes are formed using a laser or the like to form vias 14. Specifically, the via 14 is formed so as to reach the terminal 4 from the metal layer 12 through the adhesive layer 10. Further, depending on the structure, through conduction holes or conduction vias may be formed at this point in order to obtain electrical connection between the respective layers or front and back. After the via is formed, a desmear process is performed to remove the resin remaining during the via formation. Thereafter, as shown in FIG. 7, a plating process (conducting process) is performed, and plating is deposited in the via 14 to form the first conductive via 7. Then, a conductive layer forming step is performed. In this step, as shown in FIG. 8, a conductive pattern is formed on both surfaces of the insulating layer 2 using etching or the like, and the conductive layer 6 is formed. Then, a solder resist 8 is formed at a predetermined location (see FIG. 1).

In the laminating process described above, the circuit board 15 having either a conductive circuit, a conductive via, a conductive through-hole, or a combination thereof in addition to the insulating layer 2 is disposed on the side of the component 3, and in the conductive via forming process If the second conductive via 16 for electrically connecting the conductive layer 6 and the circuit board 15 is formed, a substrate 17 as shown in FIG. 12 can be formed. The substrate 17 is a so-called four-layer substrate. For example, the second conductive via 16 can be a filled via. Further, the connection by the second conductive via 16 may have an any layer structure.

As described above, according to the manufacturing method of the present invention, the adhesive layer 10 is formed only in the range substantially equal to the outer edge of the terminal 4 in the adhesive layer forming step, and the adhesive layer 10 and the terminal 4 are formed in the next component mounting step. And the insulating base material is pressed in the subsequent laminating step. Thereby, an insulating base material enters between the metal layer 12 and the component main body 5 which should finally become the conductive layer 6, and the adhesive layers 10 are adjacent to each other through the insulating base material. Therefore, insulation between the terminals 4 can be ensured when the terminals 4 are electrically connected to the conductive layer 6 in the subsequent steps (conductive via forming step, conductive layer forming step). As a result, the insulation between the conductive vias 7 can be ensured by the insulating layer 2. For this reason, as the selection of the adhesive to be used for the adhesive layer 10, the insulating performance can be excluded from the examination items, and the range of the adhesive selection can be widened.

Note that, as shown in FIG. 9, the adhesive layer 10 may be formed in two layers. In this case, in the above-described adhesive layer forming step, the first adhesive portion 10a is printed on the metal layer 12 by a known coating method (preferably a printing method) and then cured, and further on the second adhesive layer 10a. After the adhesive portion 10b is printed, the adhesive layer 10 and the terminal 4 are adhered and cured in a component mounting process. Thus, the adhesive layer 10 having a finally stable thickness can be obtained by forming the thin adhesive portion a plurality of times by one application. Although not limited, about 5 μm to 60 μm is preferable in one application. That is, the optimal thickness of the first and second adhesive portions is 5 μm to 60 μm. Thereby, each contact bonding layer 10 can be arrange | equalized to fixed height, and the position regarding the height direction of the components 3 becomes accurate. In addition, it is possible to secure a sufficient gap between the component 3 and the metal layer 12, and a good flow of the insulating base material can be realized. Moreover, the depth of the via 14 for connecting to a component can be adjusted by forming a plurality of adhesive portions and adjusting the thickness of the adhesive layer 10. Thereby, since the depth of the via 14 and the second conductive via 16 (see FIG. 12) formed in the inner layer can be made equal, the connection reliability when the plating is formed at the same time is improved. The adhesive layer 10 is not limited to two layers, and may be a plurality of layers.

Further, the bonding portion 10a and the bonding portion 10b are not limited to the same material, and each material can be selected according to necessary characteristics and characteristics (for example, the bonding layer 10a has a role as a buffer material for stress). For example, it may be possible to select a material having a relatively low elastic modulus or glass transition point compared to the insulating base material, or to select an adhesive having excellent component adhesion for the purpose of improving the component adhesion of the adhesive layer 10b. ).

For example, the glass transition temperature of the first adhesive portion 10a is 40 to 200 ° C. (TMA method), and the glass transition temperature of the second adhesive layer 10b is equal to or higher than the glass transition temperature of the first adhesive layer 10a. And it is in the range of 40 ° C. to 200 ° C. (TMA method).

In the above description, the chip component is described as an example of the component 3. However, in the case of a multi-pin component in which a plurality of terminals 4 are formed over one surface of the component body, an adhesive layer is formed on all the terminals 4 in the adhesive layer forming step. When 10 is formed, the insulating base material may not easily enter between the component main body 5 and the metal layer 12 in the lamination process. Therefore, in this case, as shown in FIGS. 10 and 11, the adhesive layer 10 is selectively formed on a part of the terminal 4 to ensure the fluidity of the insulating base material. Specifically, as shown in FIG. 11, when there are 25 terminals 4, if the adhesive layer 10 is formed corresponding to the terminals 4 at the four corners and the terminals 4 at the center, the insulating base material is A sufficient space can be secured. Furthermore, electrical insulation between the terminals 4 when finally becoming the substrate 1 can be ensured. In FIG. 11, the description of the insulating layer 2 shown in FIG. 10 is omitted. In particular, the selective formation of the adhesive layer 10 in this manner is effective even when the distance between the terminals 4 is small. Or it is effective also when the fluidity | liquidity of an insulating base material is low. The formation location of the adhesive layer 10 is appropriately selected according to the size of the component 3, the number of pins (number of terminals), the pin pitch (interval between terminals), and the material of the insulating base. In addition, by selectively forming the adhesive layer 10, it is possible to reduce stress applied to the component body 5 when the insulating base material is cured and contracted. Even when a plurality of terminals 4 are formed over the entire surface of one side of the component body 5, the adhesive layer 10 is attached to all the terminals 4 when there is a sufficient space between the terminals 4. It may be formed. Even in this case, high electrical insulation between the terminals 4 can be ensured.

Further, when a plurality of terminals 4 are formed over the entire surface of one side and the adhesive layer 10 is formed on a part of the terminal 4, the adhesive layer and the insulating base material are formed according to the diameter of the conductive via to be formed. It can be formed selectively.
For example, when a conductive via is formed with a small diameter via having a diameter of 50 μm or less, a material having good via formability can be selectively applied to the small diameter via portion in either the adhesive layer or the insulating substrate. It is possible to secure better via formation and reliability.

Hereinafter, although there are descriptions overlapping with the above, the effects of the present invention will be described.
A sufficient gap can be provided between the terminals 4 (between the conductive vias 7) by forming the adhesive layer 10 having the same size as the terminal 4, or a slightly smaller or somewhat larger shape, and the insulating layer 2 is formed in this gap. Can be formed. Thereby, the insulation between the terminals 4 can be improved regardless of the insulation of the adhesive layer 10.

Since the insulating layer 2 is molded under vacuum using a vacuum pressure press, it is possible to suppress the generation of voids between the terminals 4 and to obtain high reliability.

By forming the insulating layer 2 between the terminals 4 as described above, it is possible to form a circuit having a different potential between the terminals 4 because insulation is ensured regardless of the material selection of the adhesive layer 10.

Since all the surfaces of the component main body 5 are covered with the insulating layer 2, the behavior of the substrate when heat-treated, such as during laminating press or surface mounting reflow, can be mitigated.

DESCRIPTION OF SYMBOLS 1 Component built-in board | substrate 2 Insulating layer 3 Component 4 Terminal 5 Component main body 6 Conductive layer 7 1st conduction | electrical_connection via 8 Solder resist 10 Adhesion layer 11 Supporting plate 12 Metal layer 13 Metal layer 14 Via 15 Circuit board 16 2nd conduction | electrical_connection via 17 Substrate 18 conduction through hole

Claims (19)

  1. An insulating layer;
    A conductive layer formed on the surface of the insulating layer;
    Electrical or electronic components embedded in the insulating layer;
    A plurality of terminals provided on the component and electrically connected to the conductive layer;
    In the component-embedded substrate provided with an adhesive layer for bonding the terminal and the conductive layer,
    The adhesive layer is formed only within a range substantially equal to the outer edge of the terminal,
    A component built-in substrate, wherein a component main body, which is a portion other than the terminal in the component, is in contact only with the insulating layer.
  2. A plurality of the terminals are formed only at the peripheral edge of the component body,
    The component built-in board according to claim 1, wherein the adhesive layer is formed on all of the terminals.
  3. A plurality of the terminals are formed over the entire one surface of the component body,
    The component built-in substrate according to claim 1, wherein the adhesive layer is formed on a part or all of the terminals.
  4. 2. The component built-in substrate according to claim 1, wherein the adhesive layer is formed of an epoxy resin or a polyimide resin.
  5. 2. The component built-in substrate according to claim 1, wherein the adhesive layer has a thickness of 10 μm to 120 μm.
  6. 2. The component built-in board according to claim 1, wherein the adhesive layer is formed by stacking a plurality of adhesive portions of different materials or the same material.
  7. The adhesive layer has at least a first adhesive portion in contact with the conductive layer and a second adhesive portion in contact with the component as the adhesive portion,
    The glass transition temperature of the first adhesive portion is 40 ° C. to 200 ° C. (TMA method),
    The component according to claim 6, wherein the glass transition temperature of the second adhesive portion is not less than the glass transition temperature of the first adhesive portion and is in the range of 40 ° C to 200 ° C (TMA method). Built-in board.
  8. The component-embedded substrate according to claim 6, wherein the thickness of the first adhesive portion is 5 to 60 µm, and the thickness of the second adhesive portion is 5 to 60 µm.
  9. An adhesive layer forming step of forming the adhesive layer on the metal layer formed on the support plate;
    A component mounting step of bonding the terminal formed on the component to the adhesive layer, and mounting the component on the adhesive layer;
    A manufacturing method for manufacturing a component-embedded substrate according to claim 1, further comprising a stacking step of stacking the insulating base material to be the insulating layer while pressing the component under vacuum. .
  10. A conductive via forming step of forming a first conductive via by forming a via reaching the terminal from the outside of the metal layer after the laminating step and conducting the conductive treatment to the via; The manufacturing method according to claim 9.
  11. The manufacturing method according to claim 9, wherein the support plate used in the bonding layer forming step is an aluminum plate, and the metal layer is a copper foil attached to the aluminum plate.
  12. 10. The manufacturing method according to claim 9, wherein the support plate used in the adhesive layer forming step is stainless steel, and the metal layer is a copper plating foil deposited on the stainless steel.
  13. 10. The manufacturing method according to claim 9, wherein, in the component mounting step, a semiconductor component having a plurality of electrodes or a passive component having a plurality of electrodes is mounted in a plurality.
  14. In the laminating step, in addition to the insulating layer, a circuit board having either a conductive circuit or a conductive via or a conductive through hole or a combination thereof is disposed on the side of the component,
    The manufacturing method according to claim 10, wherein a second conductive via for electrically connecting the conductive layer and the circuit board is formed in the conductive via forming step.
  15. 15. The manufacturing method for manufacturing a component built-in board according to claim 14, wherein, in the conductive via formation step, the second conductive via is a filled via.
  16. The manufacturing method according to claim 14, wherein the connection by the second conductive via has an any layer structure.
  17. The manufacturing method according to claim 9, wherein, in the adhesive layer forming step, the second adhesive portion is formed after the first adhesive portion is cured.
  18. 11. The manufacturing method according to claim 10, wherein, in the conductive via forming step, the second conductive via is formed to have a diameter equal to or larger than that of the first conductive via.
  19. 2. The conductive via forming step, wherein the conductive via formed in the adhesive layer and the conductive via formed in the insulating base are formed to have different diameters among the first conductive vias. 10. The production method according to 10.
PCT/JP2011/062693 2011-06-02 2011-06-02 Substrate with built-in component, and method for producing said substrate WO2012164719A1 (en)

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