JP2004128481A - Wiring board and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board which is equipped with a build-up layer only on the surface of a core board and never warped or hard to be warped and to provide a method of manufacturing the same. <P>SOLUTION: The wiring board 1 includes the core board 2 with a front surface 4 and a rear surface 5, a surface wiring layer 8 and a rear wiring layer 9 which are separately formed on the front surface 4 and rear surface 5 of the core board 2 respectively, the build-up layer BU which is formed on the surface 4 of the core board 2 and composed of insulating layers 10 and 16 and wiring layers 14 and 20 which are located between the insulating layers 10 and 16, and a back insulating layer 11 formed on the rear surface 5 of the core board 2. Furthermore, the back insulating layer 11 has, at least, one of physical properties, such as a Young's modulus of 4 Gpa or above (1), a thermal expansion coefficient (RT to Tg) of 20 ppm or above (2), an elongation of 4% or below (3), and a cure shrinkage of 1,000 ppm or above. <P>COPYRIGHT: (C)2004,JPO

Description

【００２４】
表１によれば、裏面絶縁層の各特性が前記特性（１）〜（４）に含まれる実施例１，２のコア基板は、その裏面絶縁層１１側が凹む反りの反り量が６．５ｎｍ以上と高くなった。これに対し、前記特性（１）〜（４）の何れかを欠く比較例１〜４のコア基板における反り量は、２．００〜約４．５ｎｍに留まった。
以上のような実施例１，２の結果によって、前記特性（１）〜（４）を併有する裏面絶縁層１１をコア板２の裏面５に形成することにより、コア基板２の表面４上方に形成するビルドアップ層ＢＵの反り変形を解消または抑制できることが裏付けられた。
【００２５】
次に、以上のような配線基板１の製造方法を図２〜図３により説明する。
図２（Ａ）は、厚みが約８００μｍのコア基板２の断面を示し、その表面４と裏面５とには、厚みが約１８μｍの銅箔４ａ，５ａが全面に貼り付けてある。かかるコア基板２における所定の位置に対し、その厚み方向に沿ってドリルの挿入またはレーザ（炭酸ガスレーザなど）の照射を行う。
その結果、図２（Ｂ）に示すように、コア基板２において、その表面４と裏面５との間を貫通する直径約２００μｍのスルーホール３が複数穿孔される。
次に、各スルーホール３の内壁に予めＰｄなどを含むメッキ触媒を付着した後、図２（Ｃ）に示すように、コア基板２の全面に対し無電解銅メッキおよび電解銅メッキを施す。
【００２６】
その結果、図２（Ｃ）に示すように、各スルーホール３の内壁に沿ってスルーホール導体６が形成され、コア基板２の表面４と裏面５には、前記銅箔４ａ，５ａを含む銅メッキ膜４ｂ，５ｂが形成される。尚、図２（Ｃ）では、かかる銅メッキ膜４ｂ，５ｂの厚みは、前記銅箔４ａ，５ａと便宜上同じ厚みとして図示した。次いで、図２（Ｄ）に示すように、各スルーホール導体６の内側に、シリカフィラなどの無機フィラを含むエポキシ樹脂からなる充填樹脂７を形成した後、かかる充填樹脂７を蓋メッキするため、コア基板２の表面４および裏面５の全面に図示しない銅メッキ層を形成する。この状態で、かかる銅メッキ層の上に所定のパターンを有する図示しないエッチングレジストを形成した後、かかるレジストの隙間から露出する上記銅メッキ層４ｂ，５ｂをエッチングして除去する公知のサブトラクティブ法を施す。その結果、図２（Ｄ）に示すように、コア基板２の表面４および裏面５には、上記レジストのパターンに倣った所定パターンの表面配線層８と裏面配線層９とが個別に形成される。
【００２７】
図３（Ａ）に示すように、スルーホール導体６、表面配線層８、および裏面配線層９を有する一対のコア基板２，２を、それらの裏面５，５を対向させ、両者の間に裏面絶縁層１１およびクッション性を有する離型シート２７を挟持して積層し且つ拘束する。かかる状態で、一対のコア基板２、一対の裏面絶縁層１１、および離型剤２７を図３（Ａ）中の矢印で示すように、ホットプレスにより加熱しつつ加圧する。
その結果、図３（Ｂ）に示すように、上記一対のコア基板２，２の裏面５および裏面配線層９の上方に、前記樹脂シートにガラス繊維を含有する裏面絶縁層１１が個別に形成される。これにより、各裏面絶縁層１１は、各コア基板２の裏面５に密着すると共に、これら裏面絶縁層１１自体が生じる反りを互いに抑制しつつ、各コア基板２の裏面５にかかる裏面絶縁層１１を平坦に形成できる。
【００２８】
次いで、図３（Ｂ）において、一対のコア基板２の外側に露出する表面４の上方にビルドアップ層ＢＵを形成する。この工程は、前記ビルドアップ層ＢＵを形成する前記ビルドアップ絶縁層１０，１６、絶縁層２２、ビルドアップ配線層１４，２０、およびフィルドビア導体１２，１８を、公知のビルトアップ技術（セミアディティブ法、フルアディティブ法、サブトラクティブ法、フィルム状樹脂材料のラミネートによる絶縁層の形成、フォトリソグラフィ技術）により形成する。更に、前記ハンダバンプ（ＩＣ接続端子）２６を第１主面２４側に形成する。
最後に、一対のコア基板２を分離した後、それぞれの裏面側絶縁層１１にレーザ加工などによって開口部１５を形成した後、その底部に露出する前記配線１７の表面にＮｉメッキおよびＡｕメッキを施す。
この結果、前記図１に示した配線基板１を得ることができる。
尚、以上のような製造工程は、複数のコア基板２（製品単位）を平面方向に併有する多数個取りの基板（パネル）にて行っても良い。
【００２９】
図４は、配線基板１の応用形態の配線基板１ａにおける主要部の断面を示す。配線基板１ａは、図４に示すように、多層基板のコア基板２と、コア基板２の表面４と裏面５との間を貫通する複数のスルーホール導体６と、コア基板２の表面４や裏面５に形成した表面配線層８および裏面配線層９と、を備えている。
また、図４に示すように、コア基板２の表面４上方には、前記同様の複数の絶縁層１０，１６，２２と複数の配線層１４，２０とを、交互に積層したビルドアップ層ＢＵが形成される。前記同様に、表面配線層８、ビルドアップ配線層１４，２０間を導通するフィルドビア導体１２，１８や、最上層の上記配線層２０にはハンダバンプ２６が形成されている。
更に、コア基板２の裏面５上（図面下側）には、前記（１）ヤング率が４Ｇｐａ以上、（２）熱膨張率（ＲＴ〜Ｔｇ）が２０ｐｐｍ以下、（３）伸び率が４％以下、および（４）硬化収縮が１０００ｐｐｍ以上の特性を、併有する裏面絶縁層１１が形成されると共に、その開口部１５の底部には前記同様の配線１７が位置している。
【００３０】
コア基板２は、エポキシ系樹脂にガラス繊維などを含有させた厚みが約４００μｍで熱膨張率が３０ｐｐｍ／℃以下の絶縁層２ａと、同じ素材からなり厚みが約２００μｍで熱膨張率が３０ｐｐｍ／℃以下の絶縁層２ｂ，２ｃと、これらの間に位置する銅メッキからなる厚み約１５μｍの配線層２５，２７とからなる。かかる多層基板のコア基板２の表面４と裏面５との間を貫通する直径約２００μｍで複数のスルーホール３が複数貫通し、各スルーホール３の内壁に沿って厚み数１０μｍで銅メッキ製のスルーホール導体６が形成される。各スルーホール導体６の内側には、シリカフィラなどの無機フィラを含む充填樹脂７が形成されている。また、各スルーホール導体６は、その中間で配線層２５，２７と接続されている。
【００３１】
以上のような配線基板１ａによれば、裏面絶縁層１１によりビルドアップ層ＢＵ側が凹形となる反りが防げると共に、コア基板２中の配線層２５，２７も、スルーホール導体６を介してコア配線層８，９やビルドアップ配線層１４，２０と確実に導通する。このため、多くの配線層を高密度で有し且つ互いに安定した導通を得ることが可能となる。
尚、コア基板２は、中央の絶縁層２ａにおける表面２１と裏面２３とに予め配線層２５，２７を前述したサブトラクティブ法などにより形成し、これらの上に絶縁層２ｂ，２ｃを形成した後、厚み方向に前記同様してスルーホール３、スルーホール導体６、および充填樹脂７を形成を形成することにより得られる。これ以降は、前記図３（Ａ），（Ｂ）の各工程を経ることにより、図４に示すような配線基板１ａを得ることができる。
【００３２】
本発明は、以上において説明した各形態に限定されるものではない。
前記裏面絶縁層の素材は、前記（１）〜（４）の特性を有するものであれば、前記の形態に限るものではない。
また、前記コア基板２などの材質は、前記ガラス繊維または炭素繊維を含むものであれば、エポキシ系樹脂の他、ビスマレイミド・トリアジン（ＢＴ）樹脂、エポキシ樹脂、ポリイミド樹脂などを用いても良い。あるいは、連続気孔を有するＰＴＦＥなど３次元網目構造のフッ素系樹脂にガラス繊維などを含有させた複合材料などを用いることも可能である。
【００３３】
あるいは、前記コア基板２や多層基板のコア基板２における絶縁層２ａ〜２ｃの材質をセラミックとしても良い。かかるセラミックには、アルミナ、珪酸、ガラスセラミック、窒化アルミニウムなどが含まれ、更には約１０００℃以下の比較的低温で焼成が可能な低温焼成基板を用いることもできる。
かかるセラミックからなるコア基板２は、以下のようにして形成される。
未焼成のアルミナなどからなるセラミックグリーンシートにレーザ加工または金型加工などにて、スルーホール３を形成する。次に、かかるスルーホール３にＷなどの金属粉末を含む導電性ペーストを印刷して充填する。尚、この導電性ペーストは、追ってセラミックグリーンシートの焼成時に同時に燒結されて、前記スルーホール導体６となる。次いで、上記セラミックグリーンシート表面上の所定位置にも、導電性ペーストを所定パターンで印刷する。尚、この表面に印刷された導電性ペーストは、追ってセラミックグリーンシートの焼成時に同時に燒結されて、前記配線層２５，２７、表面配線層８、裏面配線層９などとなる。
更に、導電性ペーストが印刷された単層または複数の未焼成セラミックセラミックグリーンシート２ａ，２ｂ，２ｃをラミネートし熱圧着することで一体化し、未焼成のコア基板２とする。そして、かかる未焼成のコア基板２を約１３００℃にて焼成することで、焼成後のセラミックからなる単層または多層基板のコア基板２が得られる。尚、セラミックからなるコア基板２の場合、スルーホール３の内側には、前記充填樹脂７は形成せず、省略される。加えて、かかるコア基板２の表面４上には、樹脂フィルムからなる絶縁層１０などがラミネートされると共に、前述したビルドアップ工程によりビルドアップ層ＢＵが形成される。
【００３４】
尚、上記導電性ペーストは、Ｍｏ、Ｃｕ、Ａｇ、Ａｕ、Ａｇ−Ｐｔ、Ａｇ−Ｐｄなどの素材としても良い。
前記スルーホール導体６、表面配線層８、配線層１４，２０などの材質は、前記Ｃｕ（銅）の他、Ａｇ、Ｎｉ、Ｎｉ−Ａｕ系などにしても良く、あるいは金属のメッキ層を用いず、導電性樹脂を塗布するなどの方法により形成しても良い。
【００３５】
更に、前記ビルドアップ層の絶縁層１０，１６などの材質は、前記エポキシ樹脂を主成分とするもののほか、同様の耐熱性、パターン成形性などを有するポリイミド樹脂、ＢＴ樹脂、ＰＰＥ樹脂、あるいは、連続気孔を有するＰＴＦＥなど３次元網目構造のフッ素系樹脂にエポキシ樹脂などの樹脂を含浸させた樹脂−樹脂系の複合材料などを用いることもできる。尚、絶縁層の形成には、絶縁性の樹脂フィルムを熱圧着する方法のほか、液状の樹脂をロールコータにより塗布する方法を用いることもできる。尚また、絶縁層に混入するガラス繊維またはガラスフィラの組成は、Ｅガラス、Ｄガラス、Ｑガラス、Ｓガラスの何れか、またはこれらのうちの２種類以上を併用したものとしても良い。
また、ビア導体は、前記フィルドビア導体１２などでなく、内部が完全に導体で埋まってない逆円錐形状のコンフォーマルビア導体とすることもできる。あるいは、各ビア導体の軸心をずらしつつ積み重ねるスタッガードの形態でも良いし、途中で平面方向に延びる配線層が介在する形態としても良い。
【００３６】
【発明の効果】
以上に説明した本発明の配線基板（請求項１）によれば、裏面絶縁層は、前記特性（１）乃至（４）を有するので、一定以上の弾性および熱膨張率を有し、且つ伸び率が低く、硬化収縮が高くなっているため、コア基板を挟んで、その表面上方に形成されるビルドアップ層の硬化収縮などのバランスが保ち易くなる。
従って、ビルドアップ層側の中央部が凹む厚み方向に反りを生じないか、極く僅かな反りに抑制可能とした配線基板とすることができると共に、表面配線層、裏面配線層、ビルドアップ配線層、およびスルーホール導体の相互間における導通を確実に取ることが可能となる。しかも、ビルドアップ配線層から第１主面よりも高く突出するハンダバンプに、かかる第１主面に実装するＩＣチップなどの電子部品を確実に接続することができる。
【００３７】
また、請求項２の配線基板によれば、裏面絶縁層に求められる前記各特性を確実に得られるため、配線基板全体の反りを一層防止することが可能となる。
更に、請求項３の配線基板によれば、コア基板にセラミックを用いることでコア基板自体が反りにくい材質となるため、前記ビルドアップ層などが一層反りにくくなり、且つ接続性に優れた配線基板とすることが可能となる。
一方、本発明の配線基板の製造方法（請求項４）によれば、一対のコア基板をそれらの裏面を対向させ、一対の裏面絶縁層および離型シートを介して積層して加圧するため、上記一対のコア基板の各裏面に裏面絶縁層自体が生じる反りを互いに抑制しつつ形成できる。しかも、各コア基板の表面において、前記ビルドアップ層をそれぞれ平坦にして形成することもできる。
【図面の簡単な説明】
【図１】本発明の配線基板の１形態における主要部を示す断面図。
【図２】（Ａ）〜（Ｄ）は上記配線基板を得るための主な製造工程を示す概略図。
【図３】（Ａ），（Ｂ）は図２（Ｄ）に続く主な製造工程を示す概略図。
【図４】図１の配線基板の応用形態の配線基板における主要部を示す断面図。
【図５】（Ａ），（Ｂ）は従来の配線基板における主要部を示す断面図。
【符号の説明】
１，１ａ……配線基板、　　　　　　２……………コア基板、
４……………表面、　　　　　　　　５……………裏面、
８……………表面配線層、　　　　　９……………裏面配線層、
１０，１６…絶縁層、　　　　　　　１１…………裏面絶縁層、
１４，２０…配線層、　　　　　　　２７…………離型シート、
ＢＵ…………ビルドアップ層[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a wiring board having a build-up layer only above a surface of a core substrate, and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, in order to meet the demand for cost reduction, as shown in FIG. 5A, a plurality of insulating layers 35, 39, 41 and a plurality of wiring layers 34, 37 are provided only above one surface (front surface) 32 of the core substrate 31. , 40 is proposed (for example, see Patent Document 1). The core substrate 31 is an insulating plate having a thickness of about 800 μm, and has insulating layers 35, 39, 41 having a thickness of about 30 μm and wiring layers 34, 37, 40 having a thickness of about 15 μm alternately stacked on a surface 32 thereof. I have.
In addition, as shown in FIG. 5A, via conductors 36 and 38 are formed in the insulating layers 35 and 39 for conduction between the wiring layers 34, 37 and 40. Further, a plurality of solder bumps 42 penetrating the insulating layer (solder resist layer) 41 and projecting higher than the first main surface 43 are formed at predetermined positions on the uppermost wiring layer 40. It is individually connected to terminals of electronic components such as an IC chip (not shown) mounted thereon.
[0003]
[Patent Document 1]
JP-A-2002-290031 (FIG. 1 etc.)
[0004]
In the wiring board 30 as described above, the build-up layer BU including the insulating layers 35, 39, 41 and the wiring layers 34, 37, 40 is formed on the surface 32 side of the core substrate 31. Nothing is formed on the back surface 33 side of the core substrate 31.
Therefore, due to the difference in the coefficient of thermal expansion between the core substrate 31 and the insulating layers 35, 39, and 41, the entire wiring substrate 30 is moved in the thickness direction of the wiring substrate 30 as shown by a dashed line in FIG. And a warp deformed by about 4 to 5 mm in the thickness direction with respect to the length of 330 mm in the vertical direction. Due to such a warp, for example, the connection between the wiring layers 34, 37, 40, the via conductors 36, 38, and the solder bumps 42 becomes insufficient, so that there is a problem that conduction cannot be established therebetween.
In addition, when connecting an electronic component such as an IC chip to the solder bump 42, there is a problem that the connection becomes insufficient due to the warpage.
[0005]
In order to solve the above problems, a wiring board 50 as shown in FIG. That is, the wiring substrate 50 includes a core substrate 51 which is an insulating plate having a thickness of about 800 μm, insulating layers 60, 66, 72 having a thickness of about 30 μm above the surface 52 thereof, and wiring layers 58, 64, 70 having a thickness of about 15 μm. It includes a build-up layer BU and the like alternately stacked, a wiring layer 59 having a thickness of about 15 μm and an insulating layer (solder resist layer) 61 having a thickness of about 40 μm formed on the back surface 53 of the core substrate 51.
A plurality of through holes 54 penetrating between the front surface 52 and the back surface 53 are formed in the core substrate 51, and a through hole conductor 56 and a filling resin 57 are formed along the inner walls thereof. Each through-hole conductor 56 is connected to the wiring layers 58 and 59 at the upper end and the lower end.
[0006]
As shown in FIG. 5B, via conductors 62 and 68 are formed in the insulating layers 60 and 66 to conduct between the wiring layers 58, 64 and 70. A plurality of solder bumps 76 penetrating the insulating layer (solder resist layer) 72 and projecting higher than the first main surface 74 are formed at predetermined positions on the uppermost wiring layer 72. It is individually connected to terminals of electronic components such as an IC chip (not shown) to be mounted.
On the other hand, as shown in FIG. 5B, a wiring 67 extending from the wiring layer 59 formed on the back surface 53 of the core substrate 51 and exposed from the opening 65 of the insulating layer 61 toward the second main surface 63 is not shown. Used as a connection terminal to a printed circuit board such as a motherboard. In the wiring substrate 50 described above, the build-up layer BU and the like and the thick insulating layer (solder resist layer) 61 are arranged with the core substrate 51 interposed therebetween. For this reason, the warpage due to the difference in the coefficient of thermal expansion between the core substrate 51 and the insulating layers 60, 66, and 72 is caused by a certain degree of deformation near the second main surface 63, as indicated by a dashed line in FIG. Is suppressed.
[0007]
[Problems to be solved by the invention]
However, due to the warpage shown in FIG. 5B, the interconnection between the wiring layers 58, 64, 70, the via conductors 62, 68, the solder bumps 76, the through-hole conductors 56, and the wiring layer 59 becomes insufficient. Therefore, there is a problem that conduction cannot be established between them. Further, when connecting an electronic component such as an IC chip to the solder bumps 76, there is also a problem that the connection becomes insufficient due to the warpage. The present invention solves the problems in the prior art described above, and provides a wiring board having a build-up layer only on the surface of a core substrate and causing no warping or hardly warping, and a method for manufacturing the same. That is the task.
[0008]
[Means for Solving the Problems]
The present invention has been conceived to solve or suppress the shrinkage deformation caused by the build-up layer formed above the surface of the core substrate by the characteristics of the back surface insulating layer formed on the back surface of the core substrate. It was made.
[0009]
That is, the wiring board of the present invention (claim 1) comprises: a core substrate having a front surface and a back surface; a front wiring layer and a back wiring layer separately formed on the front and back surfaces of the core substrate; And a back-up insulating layer formed above a back surface of the core substrate, the build-up layer including a plurality of insulating layers and a plurality of wiring layers positioned therebetween, and a back surface insulating layer formed above the back surface of the core substrate. The insulating layer has at least one of the following characteristics (1) to (4).
(1) Young's modulus is 4 Gpa or more, (2) Thermal expansion coefficient (RT to Tg) is 20 ppm or more, (3) Elongation is 4% or less (excluding 0), (4) Curing shrinkage is 1000 ppm or more. 0010
According to this, since the back surface insulating layer formed on the back surface of the core substrate has the above-described characteristics (1) to (4), the back surface insulating layer has elasticity and thermal expansion coefficient of a certain level or more, In addition, the elongation is low and the curing shrinkage is high. For this reason, even if the build-up layer is formed above the surface of the core substrate, the build-up layer and the core substrate formed by a plurality of insulating layers and a plurality of wiring layers which form the build-up layer are depressed upward. Warpage deformation can be eliminated or suppressed very slightly. That is, the back surface insulating layer also has a function of correcting such warpage in the wiring board. Therefore, a wiring board having a flat build-up layer on the surface can be obtained. In addition, an electronic component such as an IC chip mounted on the first main surface can be reliably connected to the solder bump projecting higher than the first main surface from the build-up wiring layer.
It is preferable to satisfy all of the above characteristics (1) to (4) from the viewpoint of the effect of preventing warpage. The coefficient of thermal expansion (RT to Tg) indicates a coefficient of thermal expansion in a plane direction along the back surface of the core substrate.
[0011]
In addition, the wiring board of the present invention includes a core substrate having a front surface and a back surface, a front surface wiring layer and a back surface wiring layer individually formed on the front surface and the back surface of the core substrate, and a front surface and a back surface of the core substrate. A through-hole conductor penetrating therethrough and connecting between the front surface wiring layer and the back surface wiring layer; a plurality of insulating layers formed above the surface of the core substrate and a plurality of wiring layers positioned therebetween; A back-up insulating layer formed above the back surface of the core substrate, wherein the back-side insulating layer has at least one of the characteristics (1) to (4). Is also possible.
[0012]
The present invention also includes a wiring board (claim 2) in which the back surface insulating layer is obtained by curing a semi-curable resin sheet containing inorganic fibers or organic fibers.
According to this, since the characteristics (1) to (4) required for the back surface insulating layer can be reliably provided, the wiring substrate having the flat build-up layer on the surface with no warping or suppressed as described above is provided. It is even more certain.
The inorganic fibers include, for example, glass fibers, and nonwoven fabrics and glass fillers of glass fibers having a random orientation are particularly recommended. When such an inorganic fiber is blended in the core substrate or the back surface insulating layer at a ratio of 40 to 60 wt%, a low coefficient of thermal expansion described later can be realized. Further, the glass fiber includes any one of E glass, D glass, Q glass, and S glass, or a combination of two or more of them. On the other hand, the organic fibers include epoxy fibers and the like.
Further, the semi-curable resin sheet is a prepreg made of, for example, an epoxy resin impregnated with fibers of an inorganic or organic material or a non-woven fabric fiber, a bismaleimide triazine (BT) resin, a polyimide resin, and the like. Refers to processing such as UV (ultraviolet) irradiation, heat curing, and thermocompression on the sheet.
[0013]
In addition, the present invention includes a wiring substrate (claim 3), wherein the core substrate is made of ceramic. According to this, by using ceramic for the core substrate, the core substrate itself is made of a material that is unlikely to warp, so that each part of the substrate is more unlikely to warp, and a wiring board with excellent connectivity can be obtained. .
[0014]
On the other hand, a method for manufacturing a wiring board according to the present invention (claim 4) is a method for manufacturing a wiring board, comprising: a pair of core substrates having a front surface and a back surface and having at least a back wiring layer formed on the back surface; Forming a back surface insulating layer on each of the back surface and the back surface wiring layer, laminating via a release sheet, and pressing the plurality of insulating layers on each surface of the pair of core substrates; And forming a build-up layer including a plurality of wiring layers located at the same position.
According to this, the pair of core substrates are pressed with the pair of core substrates in a state in which the pair of core substrates are laminated with a back surface insulating layer on each back surface with their back surfaces facing each other via a release sheet. Warpage can be suppressed, and the build-up layer can be formed flat on the surface of each core substrate.
The release sheet preferably has both cushioning properties. Further, each of the above steps can be performed by a pair of multi-cavity panels each having a plurality of core substrates as product units.
In other words, the present invention can include a method of manufacturing a wiring board, wherein the core substrate is made of ceramic. In this case, by using ceramic for the core substrate, since the core substrate itself is a material that is less likely to warp, it is possible to provide a wiring substrate that is less likely to warp and that has excellent connectivity.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a preferred embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a sectional view showing a main part of a wiring board 1 of the present invention.
As shown in FIG. 1, the wiring board 1 includes a core substrate 2 having a front surface 4 and a back surface 5, a plurality of through-hole conductors 6 penetrating between the front surface 4 and the back surface 5 of the core substrate 2, A front wiring layer 8 and a rear wiring layer 9 which are individually formed on the front surface 4 and the rear surface 5 of the substrate 2.
As shown in FIG. 1, a plurality of build-up insulating layers 10 and 16, an insulating layer (solder resist) layer 22 and a plurality of build-up wiring layers 14 and 20 are provided above the surface 4 of the core substrate 2. The build-up layers BU alternately stacked are formed, and the back surface insulating layer 11 is formed above the back surface 5 of the core substrate 2 (the lower side in the drawing).
[0016]
The core substrate 2 has a substantially square shape in a plan view, and has a thickness of 400 to 1000 μm (800 μm in the present embodiment) in which an epoxy resin contains glass fibers or carbon fibers (glass fibers in the present embodiment). An insulating plate having an expansion coefficient of 30 ppm / ° C. or less. A plurality of through holes 3 having a diameter of about 200 μm penetrate between the front surface 4 and the back surface 5 of the core substrate 2, and a through-hole conductor 6 made of copper plating and having a thickness of several tens μm is formed along the inner wall of each through hole 3. Have been. Filled resin 7 containing an inorganic filler such as a silica filler is formed inside each through-hole conductor 6.
Further, as shown in FIG. 1, a front surface wiring layer 8 and a rear surface wiring layer 9 each having a predetermined pattern made of copper plating having a thickness of about 15 μm are separately formed on the front surface 4 and the rear surface 5 of the core substrate 2. Is connected to the upper or lower end of each through-hole conductor 6.
[0017]
Further, as shown in FIG. 1, above the surface 4 of the core substrate 2, an epoxy resin containing an inorganic filler such as a silica filler is used. Build-up wiring layers 14 and 20 made of copper plating formed between the layer (solder resist layer) 22 and the build-up insulating layers 10 and 16 and between the build-up insulating layer 16 and the insulating layer 22. Is located. Filled via conductors 12 and 18 made of copper plating are formed on the build-up insulating layers 10 and 16 to conduct between the surface wiring layer 8 and the build-up wiring layers 14 and 20. The build-up insulating layers 10, 16 and the build-up wiring layers 14, 20 form a build-up layer BU. Incidentally, the thermal expansion coefficients of the build-up insulating layers 10 and 16 and the insulating layer 22 are about 40 to 70 ppm / ° C.
[0018]
At predetermined positions on the uppermost wiring layer 20, a plurality of solder bumps 26 penetrating the insulating layer (solder resist layer) 22 and projecting higher than the first main surface 24 are formed. The bumps 26 are made of, for example, a low melting point alloy such as Sn-Ag, and are individually connected to terminals (not shown) of an IC chip (electronic component) 28 mounted on the first main surface 24 as shown in FIG. You. The terminals and the solder bumps 26 are buried and protected by an underfill material (not shown).
[0019]
As shown in FIG. 1, a back surface insulating layer 11 having a thickness of 20 to 150 μm (40 μm in the present embodiment) is provided above the back surface 5 of the core substrate 2 (under the drawing) and above the back wiring layer 9. Is formed. The back surface insulating layer 11 is obtained by, for example, curing a semi-curable resin sheet obtained by impregnating an inorganic resin (glass fiber in the present embodiment) with an epoxy resin or the like, by performing a vacuum hot press treatment. The back surface insulating layer 11 has (1) a Young's modulus of 4 Gpa or more, (2) a thermal expansion coefficient (RT to Tg) of 20 ppm or more, (3) an elongation of 4% or less, and (4) a curing shrinkage of 1000 ppm or more. , Has the characteristic of. The thermal expansion coefficient (RT to Tg) is a thermal expansion coefficient along a plane parallel to the back surface 5 of the core substrate 2. The elongation does not include 0.
[0020]
A plurality of openings 15 are formed at predetermined positions of the back surface insulating layer 11 so as to open toward the second main surface 13 which is the surface thereof, and at the bottom thereof, the second main surface 13 extends from the core wiring layer 9. The wiring 17 exposed on the side is located. The surface of the wiring 17 is coated with Ni plating and Au plating, and serves as a connection terminal to a printed board such as a mother board (not shown) on which the wiring board 1 is mounted.
The opening 15 is formed so that the opening ratio of the entire insulating layer 11 is not more than 15% in order to maintain the above-mentioned characteristics of the back surface insulating layer 11. Further, a pin made of a copper-based or iron-based alloy may be connected to the wiring 17 via solder.
[0021]
In the wiring board 1 as described above, since the back surface insulating layer 11 has the above-mentioned properties (1) to (4) together, it has elasticity and thermal expansion coefficient of a certain level or more, and low elongation rate. Curing shrinkage is high. For this reason, the balance between the cure shrinkage of the build-up layer BU including the build-up insulation layers 10 and 16 alternately stacked above the front surface 4 with the core substrate 2 interposed therebetween and the cure shrinkage of the back surface insulation layer 11 and the like. Is easy to keep.
As a result, according to the wiring board 1, it is possible to prevent the warp in the thickness direction or to suppress the warp to a very slight warp.
Therefore, in the wiring board 1, conduction between the core wiring layers 8, 9, the build-up wiring layers 14, 20, the via conductors 12, 18, and the through-hole conductor 6 can be reliably and stably conducted. Become. In addition, the back surface insulating layer 11 may be an adhesive resin containing the inorganic fiber. Further, as the glass fiber, a glass nonwoven fabric containing a glass thread having a wire diameter of about 8 μm and having a relatively short length that is irregularly laminated may be used.
[0022]
【Example】
Here, the characteristics (1) to (4) of the back surface insulating layer 11 used for the wiring board 1 of the present invention will be verified. Six core substrates 2 each having a thickness of 800 μm, containing glass fibers in an epoxy resin, and affixing copper foils each having a thickness of 18 μm on the front surface 4 and the back surface 5 were prepared. After forming a back surface insulating layer containing the resin and the fiber shown in Table 1 with a thickness of 60 μm on the back surface 5 of these core substrates 2, heating and pressurizing at 200 ° C. for 100 minutes (about 2.94 × 10 ⁶ N / m ² ).
As shown in Table 1, the six core substrates 2 were used as Examples 1 and 2 and Comparative Examples 1 to 4 according to the type of the material of the back surface insulating layer. Table 1 shows the characteristics such as the Young's modulus of the back surface insulating layer of each example.
Further, after the hot pressing, the core substrate 2 with the back surface insulating layer of each example was placed on a surface plate with the back surface insulating layer facing upward, and the amount of warpage at the most warped position among the four corners (Single veneer warpage) was measured with a caliper, and the results are also shown in Table 1.
[0023]
[Table 1]

[0024]
According to Table 1, in the core substrates of Examples 1 and 2 in which the respective characteristics of the back surface insulating layer are included in the characteristics (1) to (4), the amount of warpage of the warp in which the back surface insulating layer 11 side is depressed is 6.5 nm. It was higher than above. On the other hand, the amount of warpage in the core substrates of Comparative Examples 1 to 4 lacking any of the characteristics (1) to (4) remained at 2.00 to about 4.5 nm.
According to the results of Examples 1 and 2 as described above, by forming the back surface insulating layer 11 having the above characteristics (1) to (4) on the back surface 5 of the core plate 2, It has been proved that the warp deformation of the build-up layer BU to be formed can be eliminated or suppressed.
[0025]
Next, a method for manufacturing the wiring substrate 1 as described above will be described with reference to FIGS.
FIG. 2A shows a cross section of the core substrate 2 having a thickness of about 800 μm, and copper foils 4 a and 5 a having a thickness of about 18 μm are attached to the front surface 4 and the back surface 5 of the entire surface. A predetermined position on the core substrate 2 is subjected to insertion of a drill or irradiation of a laser (a carbon dioxide laser or the like) along the thickness direction thereof.
As a result, as shown in FIG. 2B, in the core substrate 2, a plurality of through holes 3 having a diameter of about 200 μm penetrating between the front surface 4 and the back surface 5 are formed.
Next, after a plating catalyst containing Pd or the like is attached to the inner wall of each through hole 3 in advance, as shown in FIG. 2C, the entire surface of the core substrate 2 is subjected to electroless copper plating and electrolytic copper plating.
[0026]
As a result, as shown in FIG. 2C, a through-hole conductor 6 is formed along the inner wall of each through-hole 3, and the front surface 4 and the back surface 5 of the core substrate 2 include the copper foils 4a, 5a. Copper plating films 4b and 5b are formed. In FIG. 2C, the thicknesses of the copper plating films 4b and 5b are illustrated as the same thickness as the copper foils 4a and 5a for convenience. Next, as shown in FIG. 2D, a filling resin 7 made of an epoxy resin containing an inorganic filler such as a silica filler is formed inside each through-hole conductor 6, and then the filling resin 7 is plated with a lid. Then, a copper plating layer (not shown) is formed on the entire front surface 4 and the rear surface 5 of the core substrate 2. In this state, a known subtractive method of forming an etching resist (not shown) having a predetermined pattern on the copper plating layer and etching and removing the copper plating layers 4b and 5b exposed from gaps in the resist is used. Is applied. As a result, as shown in FIG. 2D, on the front surface 4 and the back surface 5 of the core substrate 2, a front wiring layer 8 and a back wiring layer 9 having a predetermined pattern following the resist pattern are individually formed. You.
[0027]
As shown in FIG. 3A, a pair of core substrates 2 and 2 having a through-hole conductor 6, a front surface wiring layer 8, and a back surface wiring layer 9 are placed with their back surfaces 5 and 5 facing each other. The back insulating layer 11 and the release sheet 27 having a cushioning property are sandwiched, laminated and restrained. In this state, the pair of core substrates 2, the pair of back surface insulating layers 11, and the release agent 27 are pressurized while being heated by a hot press, as indicated by arrows in FIG.
As a result, as shown in FIG. 3 (B), a back surface insulating layer 11 containing glass fiber in the resin sheet is individually formed above the back surface 5 and the back surface wiring layer 9 of the pair of core substrates 2 and 2. Is done. Thereby, each back surface insulating layer 11 adheres closely to the back surface 5 of each core substrate 2, and also suppresses the warpage generated by the back surface insulating layers 11 themselves, and also forms the back surface insulating layer 11 on the back surface 5 of each core substrate 2. Can be formed flat.
[0028]
Next, in FIG. 3B, a build-up layer BU is formed above the surfaces 4 exposed outside the pair of core substrates 2. In this step, the build-up insulating layers 10 and 16 forming the build-up layer BU, the insulating layer 22, the build-up wiring layers 14 and 20, and the filled via conductors 12 and 18 are combined with a known build-up technique (semi-additive method). , A full additive method, a subtractive method, an insulating layer formed by laminating a film-like resin material, and a photolithography technique). Further, the solder bumps (IC connection terminals) 26 are formed on the first main surface 24 side.
Finally, after separating the pair of core substrates 2, an opening 15 is formed in each of the backside insulating layers 11 by laser processing or the like, and the surface of the wiring 17 exposed at the bottom thereof is plated with Ni and Au. Apply.
As a result, the wiring board 1 shown in FIG. 1 can be obtained.
The above manufacturing process may be performed on a multi-cavity substrate (panel) having a plurality of core substrates 2 (product units) in the plane direction.
[0029]
FIG. 4 shows a cross section of a main part of a wiring board 1 a in an application form of the wiring board 1. As shown in FIG. 4, the wiring substrate 1a includes a core substrate 2 of a multilayer substrate, a plurality of through-hole conductors 6 penetrating between the front surface 4 and the rear surface 5 of the core substrate 2, a front surface 4 of the core substrate 2, And a front surface wiring layer 8 and a back surface wiring layer 9 formed on the back surface 5.
Further, as shown in FIG. 4, above the surface 4 of the core substrate 2, a build-up layer BU in which a plurality of insulating layers 10, 16, 22 and a plurality of wiring layers 14, 20 as described above are alternately stacked. Is formed. Similarly to the above, the solder vias 26 are formed on the surface wiring layer 8, the filled via conductors 12 and 18 that conduct between the build-up wiring layers 14 and 20, and the uppermost wiring layer 20.
Further, on the back surface 5 (lower side in the drawing) of the core substrate 2, (1) the Young's modulus is 4 Gpa or more, (2) the thermal expansion coefficient (RT to Tg) is 20 ppm or less, and (3) the elongation rate is 4%. Hereinafter, and (4) the back surface insulating layer 11 having the property of curing shrinkage of 1000 ppm or more is formed, and the wiring 17 similar to the above is located at the bottom of the opening 15.
[0030]
The core substrate 2 is made of the same material as the insulating layer 2a having a thickness of about 400 μm and a thermal expansion coefficient of 30 ppm / ° C. or less in which an epoxy resin contains glass fiber or the like, and a thickness of about 200 μm and a thermal expansion coefficient of 30 ppm / It is composed of insulating layers 2b and 2c at a temperature of not more than 0.degree. C. and wiring layers 25 and 27 of copper plating and having a thickness of about 15 .mu.m located therebetween. A plurality of through holes 3 having a diameter of about 200 μm penetrate between the front surface 4 and the back surface 5 of the core substrate 2 of such a multilayer substrate, and a number of 10 μm thick copper plated along the inner wall of each through hole 3. A through-hole conductor 6 is formed. Filled resin 7 containing an inorganic filler such as a silica filler is formed inside each through-hole conductor 6. Each through-hole conductor 6 is connected to the wiring layers 25 and 27 in the middle.
[0031]
According to the wiring board 1a as described above, the back surface insulating layer 11 can prevent the build-up layer BU from being warped such that the build-up layer BU side is concave, and the wiring layers 25 and 27 in the core substrate 2 are also connected to the core via the through-hole conductor 6. Conduction with the wiring layers 8 and 9 and the build-up wiring layers 14 and 20 is ensured. For this reason, it is possible to have many wiring layers at high density and obtain stable conduction with each other.
In the core substrate 2, wiring layers 25 and 27 are previously formed on the front surface 21 and the back surface 23 of the central insulating layer 2a by the above-described subtractive method or the like, and the insulating layers 2b and 2c are formed thereon. The through-hole 3, the through-hole conductor 6, and the filling resin 7 are formed in the thickness direction in the same manner as described above. Thereafter, the wiring board 1a as shown in FIG. 4 can be obtained through the steps shown in FIGS. 3A and 3B.
[0032]
The present invention is not limited to the embodiments described above.
The material of the back surface insulating layer is not limited to the above-described embodiment as long as it has the characteristics (1) to (4).
In addition, as long as the material of the core substrate 2 or the like includes the glass fiber or the carbon fiber, a bismaleimide triazine (BT) resin, an epoxy resin, a polyimide resin, or the like may be used in addition to the epoxy resin. . Alternatively, it is also possible to use a composite material or the like in which glass fiber or the like is contained in a fluororesin having a three-dimensional network structure such as PTFE having continuous pores.
[0033]
Alternatively, the material of the insulating layers 2a to 2c in the core substrate 2 or the multilayer core substrate 2 may be ceramic. Such ceramics include alumina, silicic acid, glass ceramics, aluminum nitride, and the like, and a low-temperature fired substrate that can be fired at a relatively low temperature of about 1000 ° C. or less can also be used.
The core substrate 2 made of such a ceramic is formed as follows.
A through hole 3 is formed in a ceramic green sheet made of unfired alumina or the like by laser processing or die processing. Next, a conductive paste containing a metal powder such as W is printed and filled in the through holes 3. The conductive paste is simultaneously sintered at the time of firing the ceramic green sheet to form the through-hole conductor 6. Next, a conductive paste is also printed at a predetermined position on the surface of the ceramic green sheet in a predetermined pattern. The conductive paste printed on the surface is simultaneously sintered when the ceramic green sheet is fired, and becomes the wiring layers 25 and 27, the surface wiring layer 8, the back wiring layer 9, and the like.
Further, a single layer or a plurality of unfired ceramic ceramic green sheets 2 a, 2 b, 2 c on which the conductive paste is printed are laminated and thermocompression bonded to form an unfired core substrate 2. Then, by firing the unfired core substrate 2 at about 1300 ° C., the fired ceramic single-layer or multilayer core substrate 2 is obtained. In the case of the core substrate 2 made of ceramic, the filling resin 7 is not formed inside the through hole 3 and is omitted. In addition, on the surface 4 of the core substrate 2, the insulating layer 10 made of a resin film and the like are laminated, and the build-up layer BU is formed by the above-described build-up process.
[0034]
The conductive paste may be a material such as Mo, Cu, Ag, Au, Ag-Pt, or Ag-Pd.
The material of the through-hole conductor 6, the surface wiring layer 8, the wiring layers 14 and 20, etc. may be Ag, Ni, Ni-Au or the like in addition to Cu (copper), or use a metal plating layer. Instead, it may be formed by a method such as applying a conductive resin.
[0035]
Further, the material of the insulating layers 10 and 16 of the build-up layer includes, in addition to the epoxy resin as a main component, a polyimide resin, a BT resin, a PPE resin, or the like having similar heat resistance and pattern moldability. A resin-resin composite material in which a resin such as an epoxy resin is impregnated with a fluorine-based resin having a three-dimensional network structure such as PTFE having continuous pores can also be used. The insulating layer may be formed by a method of applying a liquid resin by a roll coater in addition to a method of thermocompression bonding an insulating resin film. The composition of the glass fiber or glass filler mixed into the insulating layer may be any one of E glass, D glass, Q glass, and S glass, or a combination of two or more of them.
Further, the via conductor may be a conformal via conductor having an inverted conical shape in which the inside is not completely filled with the conductor, instead of the filled via conductor 12 or the like. Alternatively, a staggered configuration in which the via conductors are stacked while shifting their axes may be used, or a configuration in which a wiring layer extending in the plane direction is interposed in the middle.
[0036]
【The invention's effect】
According to the wiring board of the present invention described above (claim 1), since the back surface insulating layer has the above-mentioned properties (1) to (4), it has elasticity and thermal expansion coefficient of a certain level or more, and Since the ratio is low and the curing shrinkage is high, it is easy to maintain the balance such as the curing shrinkage of the build-up layer formed above the surface of the core substrate with the core substrate interposed therebetween.
Therefore, it is possible to provide a wiring board in which the warp does not occur in the thickness direction in which the central portion on the buildup layer side is depressed or can be suppressed to a very small warp, and the front surface wiring layer, the back surface wiring layer, the buildup wiring It is possible to ensure conduction between the layer and the through-hole conductor. In addition, an electronic component such as an IC chip mounted on the first main surface can be reliably connected to the solder bump projecting higher than the first main surface from the build-up wiring layer.
[0037]
Further, according to the wiring board of the second aspect, since each of the above-mentioned characteristics required for the back surface insulating layer can be reliably obtained, it is possible to further prevent the entire wiring board from being warped.
Furthermore, according to the wiring substrate of claim 3, since the core substrate itself is made of a material that is less likely to be warped by using ceramics for the core substrate, the build-up layer and the like are less likely to be warped, and the wiring substrate is excellent in connectivity. It becomes possible.
On the other hand, according to the method for manufacturing a wiring board of the present invention (claim 4), a pair of core substrates are laminated with a pair of back surface insulating layers and a release sheet interposed therebetween, and pressurized. The pair of core substrates can be formed while suppressing the warpage caused by the back surface insulating layer itself on each back surface of the pair of core substrates. In addition, the build-up layers can be formed flat on the surface of each core substrate.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a main part in one embodiment of a wiring board of the present invention.
FIGS. 2A to 2D are schematic diagrams showing main manufacturing steps for obtaining the wiring board.
FIGS. 3A and 3B are schematic diagrams showing main manufacturing steps following FIG. 2D.
FIG. 4 is a sectional view showing a main part of a wiring board according to an application of the wiring board of FIG. 1;
FIGS. 5A and 5B are cross-sectional views showing main parts of a conventional wiring board.
[Explanation of symbols]
1, 1a ... wiring board, 2 ... core board,
4 ... front side, 5 ... back side,
8 front surface wiring layer, 9 back surface wiring layer,
10, 16 ... insulating layer, 11 ... back surface insulating layer,
14, 20: wiring layer, 27: release sheet,
BU ………… Build-up layer

Claims (4)

A core substrate having a front surface and a back surface,
A front surface wiring layer and a back surface wiring layer formed separately on the front surface and the back surface of the core substrate,
A build-up layer formed above the surface of the core substrate and including a plurality of insulating layers and a plurality of wiring layers located therebetween;
A back surface insulating layer formed above the back surface of the core substrate,
The back surface insulating layer has at least one of the following characteristics (1) to (4).
A wiring board characterized by the above-mentioned.
(1) Young's modulus is 4 Gpa or more (2) Thermal expansion coefficient (RT to Tg) is 20 ppm or more (3) Elongation is 4% or less (4) Curing shrinkage is 1000 ppm or more The wiring board according to claim 1, wherein the back surface insulating layer is obtained by curing a semi-curable resin sheet containing inorganic fibers or organic fibers. The core substrate is made of ceramic,
The wiring board according to claim 1, wherein: It is a manufacturing method of the wiring board in any one of Claims 1 thru | or 3, Comprising:
A pair of core substrates having a front surface and a back surface and having at least a back surface wiring layer formed on the back surface are formed by forming a back surface insulating layer on each of the back surface and the back surface wiring layer and laminating via a release sheet. Pressurizing,
Forming a build-up layer including a plurality of insulating layers and a plurality of wiring layers located therebetween on each surface of the pair of core substrates,
A method for manufacturing a wiring board, comprising:

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