JP6245380B2 - Light emitting device and method for manufacturing light emitting device - Google Patents
Light emitting device and method for manufacturing light emitting device Download PDFInfo
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- -1 InGaP Inorganic materials 0.000 claims description 4
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Led Devices (AREA)
Description
本発明は、発光素子、及び発光素子の製造方法に関し、特に基板上にエピタキシャル成長によって第一半導体層、活性層、第二半導体層、窓層兼支持基板を形成し、基板を除去した後に電極を形成した発光素子基板へ粗面処理を施す際の構造及び製造方法に関する。 The present invention relates to a light-emitting element and a method for manufacturing the light-emitting element, and in particular, a first semiconductor layer, an active layer, a second semiconductor layer, and a window layer / support substrate are formed on a substrate by epitaxial growth. The present invention relates to a structure and a manufacturing method for performing a rough surface treatment on a formed light emitting element substrate.
近年、発光ダイオード（ＬＥＤ）の高効率化が進み、照明器具への適用が進んでいる。従来の照明器具はＩｎＧａＮ系の青色ＬＥＤと蛍光剤を組み合わせた器具がほとんどであった。しかし、蛍光剤を使用した際には原理的にストークスロスの発生が避けられず、蛍光剤が受光した全ての光を別の波長に変換はできない問題があった。特に青色より相対的に長波長の黄色や赤色といった領域でこの問題が顕著である。 In recent years, the efficiency of light emitting diodes (LEDs) has increased, and the application to lighting fixtures has progressed. Most conventional lighting fixtures are a combination of an InGaN blue LED and a fluorescent agent. However, when a fluorescent agent is used, the occurrence of Stokes loss is unavoidable in principle, and there is a problem that it is impossible to convert all the light received by the fluorescent agent into another wavelength. In particular, this problem is remarkable in a region such as yellow or red having a longer wavelength than blue.
この問題を解決するために、黄色や赤色ＬＥＤと青色ＬＥＤを組み合わせる技術が近年採用されている。その際、ＣＯＢ（ｃｈｉｐ ｏｎ ｂｏａｒｄ）型のように一方の面に光を取り出すのではなく、ボードの上にＬＥＤを並べてフィラメント型で発光させる電球タイプの照明器具が普及しつつある。このタイプの器具に適用するＬＥＤ素子は、フィラメント全面にわたって光を取り出す必要があるため、素子の一方に光を取り出すタイプは適しておらず、チップ全球に光を取り出す配光を有する素子が理想的である。 In order to solve this problem, a technique of combining a yellow or red LED and a blue LED has recently been adopted. At that time, instead of taking out light on one surface as in the case of COB (chip on board) type, a light bulb type luminaire in which LEDs are arranged on a board to emit light in a filament type is becoming widespread. Since the LED element applied to this type of device needs to extract light over the entire surface of the filament, the type that extracts light to one of the elements is not suitable, and an element having a light distribution that extracts light to the entire chip is ideal. It is.
青色ＬＥＤであるＩｎＧａＮ系ＬＥＤはサファイア基板を用いるのが一般的であり、サファイア基板は発光波長に対して透明であるため、前述の照明器具に対しては理想的な形態になっている。しかし、黄色や赤色のＬＥＤにおいては、発光波長に対して光吸収基板となるＧａＡｓやＧｅを出発基板にしており、前記の用途には適さない。 The InGaN-based LED, which is a blue LED, generally uses a sapphire substrate, and the sapphire substrate is transparent to the emission wavelength, and thus is an ideal form for the above-described lighting fixture. However, in yellow and red LEDs, GaAs or Ge serving as a light-absorbing substrate with respect to the emission wavelength is used as a starting substrate, which is not suitable for the above-described use.
この問題を解決するために、特許文献１に示すように発光部に透明基板を接合する方法や、特許文献２に示すように支持基板に用いられるような厚さまで窓層を成長し、光吸収基板である出発基板を除去してＬＥＤにする技術が開示されている。 In order to solve this problem, a window layer is grown to a thickness that can be used for a support substrate as shown in Patent Document 1 or a method of bonding a transparent substrate to a light emitting portion as shown in Patent Document 2, and absorbs light. A technique for removing a starting substrate, which is a substrate, to make an LED is disclosed.
特許文献１で開示される方法では、必要な厚さ以上の透明基板を接合する必要があり、接合後に基板を所定の厚さまで削る必要があるため、コストアップの要因となる。また、通常、接合に用いられる基板は２００μｍ以上の厚さがある。ＬＥＤ素子に要求される膜厚は、配光特性及び他の素子とのアセンブリ性を考慮すると、せいぜい１００μｍ前後であるため、この程度の厚さまで薄膜化加工する必要がある。薄膜化加工にあたり、加工を行うことによる工数の増加、及び、ウェーハが割れるリスクも増大し、コストアップ及び歩留まり低下要因となる。 In the method disclosed in Patent Document 1, it is necessary to join a transparent substrate having a thickness greater than a necessary thickness, and it is necessary to cut the substrate to a predetermined thickness after joining. This causes an increase in cost. In general, the substrate used for bonding has a thickness of 200 μm or more. The film thickness required for the LED element is at most about 100 μm in consideration of the light distribution characteristic and the assemblability with other elements. Therefore, it is necessary to thin the film to such a thickness. In thinning processing, the number of man-hours due to processing and the risk of wafer breakage also increase, leading to increased costs and reduced yield.
一方、特許文献２に開示される支持基板に用いることができる厚さまで結晶成長により成長した窓層を支持基板として利用する方法では、所望の厚さまで窓層を成長すればよく、薄膜化加工や基板接合・接着の工程が不要のため、低コストでの形成が可能であり、優れた方法である。 On the other hand, in the method of using a window layer grown by crystal growth to a thickness that can be used for the support substrate disclosed in Patent Document 2 as the support substrate, the window layer may be grown to a desired thickness. Since the step of bonding and bonding the substrates is not necessary, it can be formed at a low cost and is an excellent method.
また、前述のような透明支持基板を有する発光素子においては、発光素子内部での多重反射を防止し、光吸収を抑制することで発光効率を上げる手法が取られるのが一般的である。特許文献３では、厚い窓層兼電流拡散層と厚い窓層兼支持基板が発光部を挟む構造において、窓層兼電流拡散層及び窓層兼支持基板に粗面をかけ、発光部には粗面をかけない方法が提案されている。ただ、この方法は窓層兼電流拡散層部を貫通する深いトレンチを形成する必要があり、コストがかかるだけでなく、上部と下部の電極の高低差が大きすぎるため、ワイヤーボンディングを行うことが難しい。フリップチップ型に適用するに際しても、厚い絶縁膜と非常に長い金属ビアを形成する必要があり、コストアップ要因となる。従って、上部電極部である窓層兼電流拡散層部が薄いことが望まれる。 In addition, in a light emitting device having a transparent support substrate as described above, it is common to take a method of increasing luminous efficiency by preventing multiple reflections inside the light emitting device and suppressing light absorption. In Patent Document 3, in a structure in which a thick window layer / current diffusion layer and a thick window layer / support substrate sandwich a light emitting portion, the window layer / current diffusion layer and the window layer / support substrate are roughened, and the light emitting portion is rough. A method that does not face the surface has been proposed. However, this method requires the formation of a deep trench that penetrates the window / current diffusion layer portion, which is not only costly, but the height difference between the upper and lower electrodes is too large, so that wire bonding can be performed. difficult. Even when applied to the flip chip type, it is necessary to form a thick insulating film and a very long metal via, which causes an increase in cost. Therefore, it is desirable that the window layer / current diffusion layer portion which is the upper electrode portion is thin.
窓層兼電流拡散層の厚さが薄く、上部電極部と下部電極部の高低差が少なく、かつ、光取り出し部もしくは光反射部に粗面を有する開示技術として、特許文献４及び５が挙げられる。特許文献４では、光取り出し面側と反対側のｎ型半導体層表面に粗面を形成しているが、フリップチップ型への技術開示であり、電極側から窓層側への効率的な光反射を目的としている。また、窓層兼支持基板と発光部両者へ粗面をかけることの難しさが開示されている。 Patent Documents 4 and 5 are disclosed as disclosure techniques in which the window layer / current diffusion layer is thin, the height difference between the upper electrode part and the lower electrode part is small, and the light extraction part or the light reflection part has a rough surface. It is done. In Patent Document 4, a rough surface is formed on the surface of the n-type semiconductor layer on the side opposite to the light extraction surface side, but this is a technical disclosure of a flip-chip type, and efficient light from the electrode side to the window layer side. The purpose is reflection. Further, it is disclosed that it is difficult to apply a rough surface to both the window layer / support substrate and the light emitting portion.
特許文献５では、発光部表面に粗面が施されており、発光部側面に異なる角度のメサ形状あるいは単純なメサ形状を有する技術が開示されている。この場合、基板には粗面を必要としない反射型の構造が採用されている。また、発光部表面はフォトリソグラフィーにより２μｍ周期等の凹凸を形成する技術が開示されている。 Patent Document 5 discloses a technique in which a light emitting portion surface has a rough surface and the light emitting portion side surface has a mesa shape with a different angle or a simple mesa shape. In this case, the substrate has a reflective structure that does not require a rough surface. Further, a technique is disclosed in which the surface of the light emitting part is formed with irregularities having a period of 2 μm by photolithography.
一方、窓層兼支持基板をエピタキシャル成長で形成した場合、格子不整に起因して基板は大きく反っており、たとえ密着露光法を採用したとしてもフォトリソグラフィー法では発光部表面に２μｍ以下のピッチの均一パターンを形成することが極めて困難である。従って、窓層兼支持基板をエピタキシャル成長で形成した場合、発光部表面の粗面化は、粗面液を利用して行うことになる。 On the other hand, when the window layer / support substrate is formed by epitaxial growth, the substrate is greatly warped due to lattice irregularity, and even if the contact exposure method is adopted, the photolithography method has a uniform pitch of 2 μm or less on the light emitting portion surface. It is very difficult to form a pattern. Therefore, when the window layer / supporting substrate is formed by epitaxial growth, the surface of the light emitting portion is roughened by using a rough surface liquid.
しかしながら、発光部表面の粗面化を粗面液で行った後、素子分離を実施した場合、素子分離した発光部の側面の形状は、粗面化を行った発光部表面の凹凸を反映した形状になる。これは、素子分離において、凹部は薄いため発光部のエッチングが早く終了して窓層兼支持基板部に達するのに対し、凸部は厚いため窓層兼支持基板部に遅く達する。そのため、凸部をエッチングする間に、凹部で発光部をオーバーエッチングし、発光部の側面にエッチング方向の投影視において凹凸を形成するためである。このように、発光部の表面を粗面液によって粗面化した後に、素子分離を行う場合、素子分離した発光部の側面の形状における凸部に電界が集中しやすく、リーク不良やＥＳＤ（静電気放電）不良を発生する問題があった。 However, when the element separation is performed after roughening the surface of the light emitting portion with a rough surface liquid, the shape of the side surface of the light emitting portion after the element separation reflects the unevenness of the surface of the light emitting portion that has been roughened. Become a shape. In the element isolation, the recesses are thin, so that the etching of the light emitting portion is completed early and reaches the window layer / support substrate portion, whereas the protrusions are thick, so that they reach the window layer / support substrate portion later. Therefore, during etching of the convex portion, the light emitting portion is over-etched with the concave portion, and unevenness is formed on the side surface of the light emitting portion in a projection view in the etching direction. Thus, when element isolation is performed after the surface of the light emitting portion is roughened with a rough surface liquid, the electric field tends to concentrate on the convex portions in the shape of the side surface of the light emitting portion that has been element-isolated, leading to leakage defects and ESD (electrostatic discharge). There was a problem of generating a discharge.
本発明は上記問題に鑑みてなされたものであって、窓層兼支持基板と発光部を有し、発光部を粗面液で粗面化した後、素子分離を行う発光素子において、リーク不良やＥＳＤ不良の発生が抑えられた発光素子及び発光素子の製造方法を提供することを目的とする。 The present invention has been made in view of the above problems, and has a window layer / supporting substrate and a light emitting part, and after the light emitting part is roughened with a rough surface liquid, the light emitting element is subjected to element separation and has a leakage defect. Another object of the present invention is to provide a light-emitting element in which the occurrence of ESD defects and the production of the light-emitting element are suppressed.
上記目的を達成するために、本発明によれば、窓層兼支持基板と、前記窓層兼支持基板上に設けられ、第二導電型の第二半導体層と、活性層と、第一導電型の第一半導体層とをこの順に含む発光部とを有する発光素子において、
前記発光素子は、前記発光部が除去された除去部と、前記除去部以外の非除去部と、該非除去部の前記第一半導体層上に設けられた第一オーミック電極と、前記除去部の前記窓層兼支持基板上に設けられた第二オーミック電極とを有し、
前記第一半導体層表面及び前記発光部の側面の少なくとも一部は絶縁保護膜で被覆され、前記第一半導体層の外周部を除く表面及び前記窓層兼支持基板の表面が粗面化され、且つ、前記発光部側面のＲｚが２μｍ未満であることを特徴とする発光素子を提供する。To achieve the above object, according to the present invention, a window layer / support substrate, a second conductivity type second semiconductor layer, an active layer, and a first conductivity layer provided on the window layer / support substrate. In a light emitting device having a light emitting part including a first semiconductor layer of the type in this order,
The light emitting element includes: a removed portion from which the light emitting portion has been removed; a non-removed portion other than the removed portion; a first ohmic electrode provided on the first semiconductor layer of the non-removed portion; A second ohmic electrode provided on the window layer and supporting substrate;
At least a part of the surface of the first semiconductor layer and the side surface of the light emitting portion is covered with an insulating protective film, the surface excluding the outer peripheral portion of the first semiconductor layer and the surface of the window layer and supporting substrate are roughened, And the Rz of the side surface of the said light emission part is less than 2 micrometers, The light emitting element characterized by the above-mentioned is provided.
このような発光素子であれば、粗面化により発光効率を向上させるとともに、発光部側面の凹凸形状に依存するリーク不良及びＥＳＤ不良の発生が抑えられた発光素子となる。 With such a light emitting device, the light emitting efficiency is improved by roughening the surface, and the light emitting device in which the occurrence of leakage failure and ESD failure depending on the uneven shape on the side surface of the light emitting portion is suppressed.
このとき、前記窓層兼支持基板はＧａＰ、ＧａＡｓＰ、ＡｌＧａＡｓ、サファイア（Ａｌ２Ｏ３）、石英（ＳｉＯ２）、ＳｉＣのいずれかからなり、前記第一半導体層、前記活性層、前記第二半導体層がＡｌＧａＩｎＰまたはＡｌＧａＡｓからなるものであることが好ましい。
このように、窓層兼支持基板、第一半導体層、活性層、第二半導体層として、上記のような材料を好適に用いることができる。At this time, the window layer / support substrate is made of any one of GaP, GaAsP, AlGaAs, sapphire (Al 2 O 3 ), quartz (SiO 2 ), and SiC, and includes the first semiconductor layer, the active layer, and the second layer. The semiconductor layer is preferably made of AlGaInP or AlGaAs.
Thus, the above materials can be suitably used as the window layer / support substrate, the first semiconductor layer, the active layer, and the second semiconductor layer.
また、本発明によれば、基板上に、該基板と格子整合系の材料で第一半導体層、活性層、第二半導体層を順次エピタキシャル成長により成長させて発光部を形成する工程と、該発光部の上に前記基板に対して非格子整合系の材料で窓層兼支持基板をエピタキシャル成長により形成する工程と、前記基板を除去する工程と、前記第一半導体層の表面に第一オーミック電極を形成する工程と、前記第一半導体層の表面に粗面処理を行う第一粗面処理工程と、前記発光部の一部を除去する除去部と、それ以外の非除去部を形成する素子分離工程と、前記発光部が除去された窓層兼支持基板上に第二オーミック電極を形成する工程と、前記第一半導体層表面及び前記発光部の側面の少なくとも一部を絶縁保護膜で被覆する工程、前記窓層兼支持基板の表面及び側面を粗面化する第二粗面処理工程からなり、
前記第一粗面処理工程において、第一オーミック電極周辺及び、その後の前記素子分離工程で前記非除去部の前記第一半導体層表面の外周部となる領域については粗面化しないことを特徴とする発光素子の製造方法を提供する。In addition, according to the present invention, a step of forming a light emitting portion by sequentially growing a first semiconductor layer, an active layer, and a second semiconductor layer on a substrate with a lattice-matching material with the substrate, and the light emission Forming a window layer / support substrate by epitaxial growth on the substrate with a non-lattice-matched material, removing the substrate, and providing a first ohmic electrode on the surface of the first semiconductor layer. A step of forming, a first rough surface treatment step of performing a rough surface treatment on the surface of the first semiconductor layer, a removal portion for removing a part of the light emitting portion, and an element separation for forming other non-removal portions A step of forming a second ohmic electrode on the window layer / support substrate from which the light emitting portion has been removed, and covering at least a part of the surface of the first semiconductor layer and the side surface of the light emitting portion with an insulating protective film. Process of the window layer and supporting substrate Made from the second surface roughening step of roughening the surface and side surfaces,
In the first rough surface treatment step, the first ohmic electrode periphery and the region that becomes the outer peripheral portion of the surface of the first semiconductor layer of the non-removed portion in the subsequent element isolation step are not roughened. A method for manufacturing a light emitting device is provided.
このような製造方法であれば、粗面化により発光効率を向上させるとともに、発光部側面の凹凸形状に依存するリーク不良及びＥＳＤ不良の発生が抑えられた発光素子を製造することができる。 With such a manufacturing method, it is possible to manufacture a light emitting element in which the light emission efficiency is improved by roughening, and the occurrence of leakage failure and ESD failure depending on the uneven shape on the side surface of the light emitting portion is suppressed.
このとき、前記基板をＧａＡｓまたはＧｅとし、前記窓層兼支持基板をＧａＰ、ＧａＡｓＰ、ＡｌＧａＡｓ、サファイア（Ａｌ ２ Ｏ ３ ）、石英（ＳｉＯ ２ ）、ＳｉＣのいずれかとし、前記第一半導体層、前記活性層、前記第二半導体層をＡｌＧａＩｎＰまたはＡｌＧａＡｓとすることが好ましい。
このように、基板、窓層兼支持基板、第一半導体層、活性層、第二半導体層として、上記のような材料を好適に用いることができる。
At this time, the substrate is GaAs or Ge , and the window layer / support substrate is any one of GaP , GaAsP , AlGaAs, sapphire (Al 2 O 3 ), quartz (SiO 2 ), SiC , the first semiconductor layer, The active layer and the second semiconductor layer are preferably made of AlGaInP or AlGaAs.
Thus, the above materials can be suitably used for the substrate, the window / support substrate, the first semiconductor layer, the active layer, and the second semiconductor layer.
このとき、前記第一粗面処理工程は、
有機酸と無機酸の混合液が用いられ、前記有機酸は、クエン酸・マロン酸・蟻酸・酢酸・酒石酸のいずれか一種類以上含有し、前記無機酸は塩酸・硫酸・硝酸・弗酸のいずれか一種類以上を含有する溶液を用いて行い、
前記第二粗面処理工程は、
クエン酸・マロン酸・蟻酸・酢酸・酒石酸の有機酸からいずれか１種類以上を含み、かつ、塩酸、硫酸、硝酸、弗酸の無機酸のいずれか１種類以上を含み、かつ、沃素を含む溶液を用いて行うことが好ましい。At this time, the first rough surface treatment step,
A mixed solution of an organic acid and an inorganic acid is used, and the organic acid contains at least one of citric acid, malonic acid, formic acid, acetic acid, and tartaric acid, and the inorganic acid includes hydrochloric acid, sulfuric acid, nitric acid, and hydrofluoric acid. Using a solution containing any one or more of them,
The second rough surface treatment step includes
Contains at least one organic acid such as citric acid, malonic acid, formic acid, acetic acid, and tartaric acid, and contains one or more inorganic acids such as hydrochloric acid, sulfuric acid, nitric acid, and hydrofluoric acid, and contains iodine. It is preferable to use a solution.
このようにすれば、確実に表面を粗面化することができる。 In this way, the surface can be reliably roughened.
このとき、前記素子分離工程は、
塩酸を含有するウェットエッチング液によるウェットエッチング法により行い、前記第一粗面処理工程において粗面化させない領域に非Ａｌ含有層を残留させ、エッチングマスクとして使用することができる。
このようにすれば、素子分離を行った発光部の側面に明瞭なメサ形状を得ることができる。At this time, the element isolation step includes:
It can be performed by a wet etching method using a wet etching solution containing hydrochloric acid, and a non-Al-containing layer can be left in a region that is not roughened in the first roughening treatment step, and can be used as an etching mask.
In this way, it is possible to obtain a clear mesa shape on the side surface of the light emitting portion where element isolation has been performed.
このとき、前記非Ａｌ含有層は、ＧａＡｓ、ＩｎＧａＰ、ＩｎＧａＡｓ、Ｇｅのいずれか１層以上含み、前記ウェットエッチング後に前記非Ａｌ含有層を除去する工程を行うことが好ましい。
このようにすれば、素子分離を行った発光部の側面に明瞭なメサ形状をより確実に得ることができる。At this time, it is preferable that the non-Al-containing layer includes at least one of GaAs, InGaP, InGaAs, and Ge, and a step of removing the non-Al-containing layer after the wet etching is performed.
In this way, a clear mesa shape can be more reliably obtained on the side surface of the light emitting part that has been subjected to element isolation.
また、前記素子分離工程は、
塩化水素を含有するガスによるドライエッチング法により行うことができる。
このようにすれば、素子分離を行った発光部の側面にくびれのない形状を得ることができる。The element isolation step includes
It can be performed by a dry etching method using a gas containing hydrogen chloride.
In this way, it is possible to obtain a shape with no constriction on the side surface of the light emitting portion from which element isolation has been performed.
本発明の発光素子、及び発光素子の製造方法は、粗面化により発光効率を向上させるとともに、発光部側面の凹凸形状に依存するリーク不良及びＥＳＤ不良の発生が抑えられた発光素子を得ることができる。 The light-emitting element and the method for manufacturing the light-emitting element of the present invention provide a light-emitting element in which light emission efficiency is improved by roughening and the occurrence of leakage failure and ESD failure depending on the uneven shape on the side surface of the light-emitting portion is suppressed. Can do.
以下、本発明について実施の形態を説明するが、本発明はこれに限定されるものではない。
前述のように、発光部の表面を粗面液によって一様に粗面化した後に、素子分離を行う場合、リーク不良やＥＳＤ不良が発生する問題があった。Hereinafter, although an embodiment is described about the present invention, the present invention is not limited to this.
As described above, when element separation is performed after the surface of the light-emitting portion is uniformly roughened with a rough surface liquid, there is a problem in that leakage failure and ESD failure occur.
そこで、本発明者らはこのような問題を解決すべく鋭意検討を重ねた。その結果、発光部表面を粗面化する際に、その後の素子分離で第一半導体層表面の外周部となる領域については粗面化をしないことで、発光部側面のＲｚを２μｍ未満とすることができ、これによって、リーク不良及びＥＳＤ不良を抑えることができることに想到した。そして、これらを実施するための最良の形態について精査し、本発明を完成させた。Therefore, the present inventors have intensively studied to solve such problems. As a result, when the surface of the light emitting portion is roughened, the region that becomes the outer peripheral portion of the surface of the first semiconductor layer in the subsequent element separation is not roughened, so that the R z on the side surface of the light emitting portion is less than 2 μm. Thus, the inventors have conceived that leakage defects and ESD defects can be suppressed. And the best form for implementing these was scrutinized and the present invention was completed.
まず、本発明の発光素子について図１を参照して説明する。
図１に示すように、本発明の発光素子１は、窓層兼支持基板１０７と、窓層兼支持基板１０７上に設けられ、第二導電型の第二半導体層１０５と、活性層１０４と、第一導電型の第一半導体層１０３とをこの順に含む発光部１０８とを有している。First, the light-emitting element of the present invention will be described with reference to FIG.
As shown in FIG. 1, the light emitting device 1 of the present invention is provided on a window layer / support substrate 107, a window layer / support substrate 107, a second conductivity type second semiconductor layer 105, an active layer 104, The light emitting unit 108 includes the first conductivity type first semiconductor layer 103 in this order.
窓層兼支持基板１０７はＧａＰ、ＧａＡｓＰ、ＡｌＧａＡｓ、サファイア（Ａｌ２Ｏ３）、石英（ＳｉＯ２）、ＳｉＣ等からなり、第一半導体層１０３、活性層１０４、第二半導体層１０５がＡｌＧａＩｎＰまたはＡｌＧａＡｓからなるものとすることができる。The window layer / support substrate 107 is made of GaP, GaAsP, AlGaAs, sapphire (Al 2 O 3 ), quartz (SiO 2 ), SiC, etc., and the first semiconductor layer 103, the active layer 104, and the second semiconductor layer 105 are made of AlGaInP or It can consist of AlGaAs.
発光素子１は、発光部１０８の少なくとも第一半導体層１０３と活性層１０４が除去された除去部１７０と、除去部１７０以外の非除去部１８０と、該非除去部１８０の第一半導体層１０３上に設けられた第一オーミック電極１２１と、除去部１７０の窓層兼支持基板１０７上に設けられた第二オーミック電極１２２とを有している。 The light emitting element 1 includes a removal unit 170 from which at least the first semiconductor layer 103 and the active layer 104 of the light emitting unit 108 are removed, a non-removal unit 180 other than the removal unit 170, and the first semiconductor layer 103 of the non-removal unit 180. And a second ohmic electrode 122 provided on the window layer / supporting substrate 107 of the removing portion 170.
第一半導体層１０３表面及び発光部１０８の側面の少なくとも一部は絶縁保護膜１５０で被覆され、第一半導体層１０３の外周部（第二領域１３１）を除く表面及び窓層兼支持基板１０７の表面が粗面化され、且つ、発光部１０８側面のＲｚが２μｍ未満である。
なお、本願におけるＲｚは表面の十点平均粗さ（ＪＩＳ Ｂ０６０１−１９９４）を示すものとする。At least a part of the surface of the first semiconductor layer 103 and the side surface of the light emitting unit 108 is covered with an insulating protective film 150, and the surface of the first semiconductor layer 103 excluding the outer peripheral part (second region 131) and the window layer / supporting substrate 107. The surface is roughened, and the R z on the side surface of the light emitting unit 108 is less than 2 μm.
In addition, Rz in this application shall show the 10-point average roughness (JIS B0601-1994) of the surface.
このような本発明の発光素子１であれば、粗面化により発光効率を向上させるとともに、発光部１０８側面のＲｚが２μｍ未満であるので、凹凸形状に依存するリーク不良及びＥＳＤ不良の発生が抑えられた発光素子となる。With such a light emitting device 1 of the present invention, the light emission efficiency is improved by roughening the surface, and the Rz on the side surface of the light emitting unit 108 is less than 2 μm. Thus, the light emitting element is suppressed.
次に、本発明の発光素子の製造方法について図２―図８を参照して説明する。
まず、図３に示すように出発基板として、基板１０１を用意する（図２のＳＰ１）。Next, a method for manufacturing a light emitting device of the present invention will be described with reference to FIGS.
First, as shown in FIG. 3, a substrate 101 is prepared as a starting substrate (SP1 in FIG. 2).
基板１０１としては、ＧａＡｓまたはＧｅを好適に用いることができる。
このようにすれば、後述する活性層１０４の材料を格子整合系でエピタキシャル成長を行うことができるため、活性層１０４の品質を向上させやすく、輝度上昇や寿命特性の向上が得られる。As the substrate 101, GaAs or Ge can be preferably used.
In this way, since the material of the active layer 104 to be described later can be epitaxially grown in a lattice matching system, the quality of the active layer 104 can be easily improved, and the luminance can be increased and the life characteristics can be improved.
次に、基板１０１上に、基板１０１と格子定数が異なる第一導電型の第一半導体層１０３、活性層１０４、第二導電型の第二半導体層１０５を順次エピタキシャル成長により成長させて発光部１０８を形成する（図２のＳＰ２）。
なお、図示しないが、基板１０１と第一半導体層１０３の間には、後述する基板１０１を除去する工程のために、基板除去選択エッチング層が挿入されることが好ましい。Next, a first conductive type first semiconductor layer 103 having a lattice constant different from that of the substrate 101, an active layer 104, and a second conductive type second semiconductor layer 105 are sequentially grown on the substrate 101 by epitaxial growth, so that the light emitting unit 108 is obtained. (SP2 in FIG. 2).
Although not shown, it is preferable that a substrate removal selective etching layer is inserted between the substrate 101 and the first semiconductor layer 103 for the step of removing the substrate 101 described later.
次に、発光部１０８の上に基板１０１に対して非格子整合系の材料で窓層兼支持基板１０７をエピタキシャル成長により形成して、エピタキシャル基板１０９を作製する（図２のＳＰ３）。 Next, the window layer / support substrate 107 is formed by epitaxial growth on the light emitting portion 108 with a material of a non-lattice matching system with respect to the substrate 101 to produce the epitaxial substrate 109 (SP3 in FIG. 2).
上記ＳＰ２、３において、具体的には、図３に示すように、基板１０１上に例えばＭＯＶＰＥ法（有機金属気相成長法）やＭＢＥ（分子線エピタキシー法）、ＣＢＥ（化学線エピタキシー法）により第一導電型の第一半導体層１０３、活性層１０４、第二導電型の第二半導体層１０５からなる発光部１０８上に、緩衝層１０６、窓層兼支持基板１０７をこの順にエピタキシャル成長したエピタキシャル基板１０９を作製することができる。
なお、窓層兼支持基板１０７は、ＨＶＰＥ法（ハイドライド気相成長法）により形成してもよい。In SP2 and SP3, specifically, as shown in FIG. 3, on the substrate 101, for example, by MOVPE (metal organic chemical vapor deposition), MBE (molecular beam epitaxy), or CBE (chemical beam epitaxy). An epitaxial substrate in which a buffer layer 106 and a window layer / support substrate 107 are epitaxially grown in this order on a light emitting portion 108 including a first semiconductor layer 103 of the first conductivity type, an active layer 104, and a second semiconductor layer 105 of the second conductivity type. 109 can be produced.
Note that the window layer / support substrate 107 may be formed by HVPE (hydride vapor phase epitaxy).
活性層１０４は発光波長に応じて（ＡｌｘＧａ１−ｘ）ｙＩｎ１−ｙＰ（０≦ｘ≦１、０．４≦ｙ≦０．６）またはＡｌｚＧａ１―ｚＡｓ（０≦ｚ≦０．４５）で形成される。可視光照明に適用する場合、ＡｌＧａＩｎＰを選択するのが好適であり、赤外照明に適用する場合、ＡｌＧａＡｓを選択するのが好適である。ただし、活性層１０４の設計に関しては、超格子等の利用により波長は材料組成に起因する波長以外に調整可能であるため、上記の材料に限られない。The active layer 104 has (Al x Ga 1-x ) y In 1-y P (0 ≦ x ≦ 1, 0.4 ≦ y ≦ 0.6) or Al z Ga 1-z As (0 ≦ z ≦ 0.45). When applying to visible light illumination, it is preferable to select AlGaInP, and when applying to infrared illumination, it is preferable to select AlGaAs. However, the design of the active layer 104 is not limited to the above materials because the wavelength can be adjusted by using a superlattice or the like other than the wavelength resulting from the material composition.
第一半導体層１０３、第二半導体層１０５はＡｌＧａＩｎＰもしくはＡｌＧａＡｓが選択され、その選択は活性層１０４と必ずしも同一の材料でなくともよい。 AlGaInP or AlGaAs is selected for the first semiconductor layer 103 and the second semiconductor layer 105, and the selection may not necessarily be made of the same material as that of the active layer 104.
本実施形態においては、最も単純な構造である第一半導体層１０３、活性層１０４、第二半導体層１０５が同一材料であるＡｌＧａＩｎＰの場合を例示するが、第一半導体層１０３あるいは第二半導体層１０５は特性向上のため、各層内には複数層が含まれるのが一般的であり、第一半導体層１０３あるいは第二半導体層１０５が単一層であることに限定されない。 In the present embodiment, the first semiconductor layer 103, the active layer 104, and the second semiconductor layer 105 having the simplest structure are exemplified by AlGaInP, which is the same material, but the first semiconductor layer 103 or the second semiconductor layer is exemplified. 105 generally includes a plurality of layers in order to improve characteristics, and the first semiconductor layer 103 or the second semiconductor layer 105 is not limited to a single layer.
窓層兼支持基板１０７としては、ＧａＰ、ＧａＡｓＰ、ＡｌＧａＡｓ、サファイア（Ａｌ２Ｏ３）、石英（ＳｉＯ２）、ＳｉＣ等を好適に用いることができる。窓層兼支持基板１０７をＧａＡｓＰまたはＧａＰで形成した場合、緩衝層１０６はＩｎＧａＰで形成するのが最も好適である。
また、窓層兼支持基板１０７は格子整合系の材料であるＡｌＧａＡｓで形成することも可能である。また、窓層兼支持基板１０７として、ＧａＡｓＰを選択すると、耐候性が良好である。
しかし、ＧａＡｓＰと、ＡｌＧａＩｎＰ系材料またはＡｌＧａＡｓ系材料との間には大きな格子不整が存在するため、ＧａＡｓＰには高密度のひずみや貫通転位が入る。その結果、エピタキシャル基板１０９は大きな反りを有する。As the window layer / supporting substrate 107, GaP, GaAsP, AlGaAs, sapphire (Al 2 O 3 ), quartz (SiO 2 ), SiC, or the like can be suitably used. When the window layer / support substrate 107 is formed of GaAsP or GaP, the buffer layer 106 is most preferably formed of InGaP.
The window layer / support substrate 107 can also be formed of AlGaAs, which is a lattice matching material. Further, when GaAsP is selected as the window layer / supporting substrate 107, the weather resistance is good.
However, since there is a large lattice mismatch between GaAsP and an AlGaInP-based material or AlGaAs-based material, high-density strain and threading dislocations enter GaAsP. As a result, the epitaxial substrate 109 has a large warp.
ここで、自然超格子の形成による波長シフトを防止するため、発光部１０８は、成長面に対して結晶学的に１２度以上傾斜して成長が行われることが好ましい。この傾斜方向は、どの方向に選択することも可能だが、スクライブ・ブレーキング工程で素子を分離する工程を採用する場合、スクライブ線の一方には結晶軸が傾斜せず直交する方向を選択し、スクライブ線の他方には結晶軸が傾斜する方向を選択すれば、素子側面が素子表面及び裏面に対して傾斜する面を少なくできる。従って、通常はスクライブ線の一方は傾斜しない方向が選択されるが、２０度程度の素子側面の傾斜は、アセンブリ上は大きな問題にならない。従って、上記直交方向は、厳密に一致する必要はなく、直交方向より±２０度程度の角度範囲は直交方向に概念的に含まれる。 Here, in order to prevent a wavelength shift due to the formation of the natural superlattice, the light emitting portion 108 is preferably grown with a crystallographic inclination of 12 degrees or more with respect to the growth surface. This tilt direction can be selected in any direction, but when adopting the process of separating the elements in the scribe and braking process, select the direction in which the crystal axis does not tilt and is orthogonal to one of the scribe lines, If the direction in which the crystal axis is inclined is selected for the other of the scribe lines, it is possible to reduce the number of elements whose side surfaces are inclined with respect to the element surface and the back surface. Therefore, a direction in which one of the scribe lines is not inclined is usually selected, but the inclination of the element side surface of about 20 degrees is not a big problem on the assembly. Therefore, the orthogonal directions do not have to coincide exactly, and an angular range of about ± 20 degrees from the orthogonal directions is conceptually included in the orthogonal directions.
次に、エピタキシャル基板１０９から基板１０１を除去して、図４に示すように発光素子基板１１０を作製する（図２のＳＰ４）。
具体的には、エピタキシャル基板１０９から基板１０１をウェットエッチング法により除去し、発光素子基板１１０とすることができる。Next, the substrate 101 is removed from the epitaxial substrate 109, and the light emitting element substrate 110 is manufactured as shown in FIG. 4 (SP4 in FIG. 2).
Specifically, the light emitting element substrate 110 can be obtained by removing the substrate 101 from the epitaxial substrate 109 by wet etching.
次に、図５に示すように、発光素子基板１１０の第一半導体層１０３の基板除去面１２０上に、発光素子へ電位を供給するための第一オーミック電極１２１を形成する（図２のＳＰ５）。 Next, as shown in FIG. 5, a first ohmic electrode 121 for supplying a potential to the light emitting element is formed on the substrate removal surface 120 of the first semiconductor layer 103 of the light emitting element substrate 110 (SP5 in FIG. 2). ).
次に、図６に示すように第一半導体層１０３の表面に粗面処理を行う第一粗面処理工程を行う（図２のＳＰ６）。第一粗面処理工程では、第一オーミック電極１２１周辺の第三領域１３０及び、第一半導体層１０３の表面の一部の第二領域１３１については粗面化を行わないようにする。 Next, as shown in FIG. 6, a first rough surface treatment step is performed to roughen the surface of the first semiconductor layer 103 (SP6 in FIG. 2). In the first rough surface treatment step, the third region 130 around the first ohmic electrode 121 and the second region 131 on the surface of the first semiconductor layer 103 are not roughened.
第一粗面処理工程は、有機酸と無機酸の混合液が用いられ、前記有機酸としてカルボン酸、特には、クエン酸・マロン酸・蟻酸・酢酸・酒石酸のいずれか一種類以上含有し、前記無機酸は塩酸・硫酸・硝酸・弗酸のいずれか一種類以上を含有する溶液を用いて行うことができる。
このようにすれば、確実に表面を粗面化することができる。In the first rough surface treatment step, a mixed solution of an organic acid and an inorganic acid is used, and the organic acid contains carboxylic acid, in particular, any one or more of citric acid, malonic acid, formic acid, acetic acid, tartaric acid, The inorganic acid can be used using a solution containing one or more of hydrochloric acid, sulfuric acid, nitric acid, and hydrofluoric acid.
In this way, the surface can be reliably roughened.
第三領域１３０は第一粗面処理工程でのオーバーエッチングを抑止し、第一オーミック電極１２１の電極剥離の抑制の効果がある。一方、第三領域１３０の幅は粗面化の効果による反射防止効果が少なくならないように、広すぎない適切な幅に設定する必要がある。反射防止効果の減少が少なく、電極剥離の抑制に効果が得られる幅として、第一粗面処理により粗面化される深さの０．５〜１５倍程度の幅を有することが好適である。粗面の凹凸高さは発光波長の１／２の整数倍であることが好ましい。 The third region 130 has an effect of suppressing over-etching in the first rough surface treatment step and suppressing electrode peeling of the first ohmic electrode 121. On the other hand, the width of the third region 130 needs to be set to an appropriate width that is not too wide so that the antireflection effect due to the roughening effect is not reduced. It is preferable to have a width of about 0.5 to 15 times the depth roughened by the first roughening treatment as a width that has a small decrease in the antireflection effect and is effective in suppressing electrode peeling. . The uneven height of the rough surface is preferably an integral multiple of 1/2 of the emission wavelength.
第二領域１３１の幅は、第一粗面処理により粗面化される深さの０．５〜１５倍程度の幅を有することが好適である。
ここで、前述の基板除去選択エッチング層を第一半導体層１０３の上に設けた場合に、該基板除去選択エッチング層と第一半導体層１０３との間に第一粗面処理選択エッチング層（不図示）を設けることが好ましく、これにより基板除去後に第一粗面処理選択エッチング層を第二領域１３１に残留させて、第一粗面処理を行うと良い。このようにすれば、第一粗面処理工程におけるフォトレジストパターン下へのオーバーエッチングを低減することができる。The width of the second region 131 is preferably about 0.5 to 15 times the depth roughened by the first roughening process.
Here, when the above-described substrate removal selective etching layer is provided on the first semiconductor layer 103, a first rough surface treatment selective etching layer (non-etching layer) is provided between the substrate removal selective etching layer and the first semiconductor layer 103. It is preferable to provide the first rough surface treatment by leaving the first rough surface treatment selective etching layer in the second region 131 after removing the substrate. In this way, over-etching under the photoresist pattern in the first rough surface treatment step can be reduced.
第一粗面液は非Ａｌ含有材料から成る層に対して選択エッチング性を有するため、第一粗面処理選択エッチング層をＧａＡｓ、ＩｎＧａＰ、ＩｎＧａＡｓ、Ｇｅで構成することが好ましい。このようにすれば、第一粗面処理選択エッチング層端部を起点としてファセットが形成され、パターン下へのオーバーエッチングを抑止することができる。ただし、第一粗面処理選択エッチング層を用いた場合、非Ａｌ含有材料は発光波長に対して光を吸収するため、第一粗面処理後、ＳＰＭ等の過酸化水素水含有液で第一粗面処理選択エッチング層を選択的に除去する工程を加えることが好ましい。 Since the first rough surface liquid has a selective etching property with respect to the layer made of the non-Al-containing material, the first rough surface treatment selective etching layer is preferably composed of GaAs, InGaP, InGaAs, or Ge. In this way, facets are formed starting from the edge portion of the first rough surface treatment selective etching layer, and over-etching under the pattern can be suppressed. However, when the first rough surface treatment selective etching layer is used, the non-Al-containing material absorbs light with respect to the emission wavelength. Therefore, after the first rough surface treatment, the first surface is treated with a hydrogen peroxide solution containing SPM or the like. It is preferable to add a step of selectively removing the rough surface treatment selective etching layer.
第二領域１３１の幅は第一粗面処理により粗面化される深さだけでなく、フォトリソグラフィーのアライメント精度によっても制約がある。アライメント精度が高いアライナーもしくはステッパーを使用すればアライメント精度を見越した付加幅は少なくてすみ、一方、アライメント精度が低いアライナーを用いる場合は、精度を見越して付加幅を多くすることが好ましい。 The width of the second region 131 is limited not only by the depth roughened by the first roughening process but also by the alignment accuracy of photolithography. If an aligner or stepper with high alignment accuracy is used, the additional width in anticipation of alignment accuracy can be reduced. On the other hand, when an aligner with low alignment accuracy is used, it is preferable to increase the additional width in anticipation of accuracy.
以上の工程を行うことにより、第一半導体層１０３表面に、粗面化していない平坦な第二領域１３１を得ることができる。これにより、後述する素子分離工程において素子分離した発光部１０８の側面の凹凸発生を抑えることができる。 By performing the above steps, a flat second region 131 that is not roughened can be obtained on the surface of the first semiconductor layer 103. As a result, it is possible to suppress the occurrence of unevenness on the side surface of the light emitting unit 108 that has been subjected to element isolation in the element isolation step described later.
次に、図７に示すように、発光部１０８の一部を除去する除去部１７０と、それ以外の非除去部１８０を形成する素子分離工程を行う（図２のＳＰ７）。 Next, as shown in FIG. 7, an element isolation process is performed to form a removal unit 170 that removes a part of the light emitting unit 108 and a non-removal unit 180 other than that (SP7 in FIG. 2).
素子分離工程は、例えば、フォトリソグラフィー法により、レジストで第一半導体層１０３上の所定の領域（図６における第二オーミック電極形成領域１４０、スクライブ領域１４１）を開口させたパターンを形成し、このレジストをエッチングマスクとして用いてエッチングすることによって行うことができる。
上記エッチングは、塩酸を含有するウェットエッチング液によるウェットエッチング法により、第二半導体層１０５、緩衝層１０６もしくは窓層兼支持基板１０７を露出させた除去部１７０と、除去部１７０以外の非除去部１８０を形成することができる。In the element isolation step, for example, a pattern in which predetermined regions (second ohmic electrode formation region 140 and scribe region 141 in FIG. 6) are opened with a resist by a photolithography method is formed. This can be performed by etching using a resist as an etching mask.
The etching is performed by a wet etching method using a wet etching solution containing hydrochloric acid to remove the second semiconductor layer 105, the buffer layer 106, or the window layer / support substrate 107, and a non-removed portion other than the removed portion 170. 180 can be formed.
このとき、上記の第一粗面処理工程において粗面化させない第二領域１３１に非Ａｌ含有層（不図示）を残留させ、エッチングマスクとして使用することができる。
非Ａｌ含有層は、ＧａＡｓ、ＩｎＧａＰ、ＩｎＧａＡｓ、Ｇｅのいずれか１層以上含むものとすることができる。非Ａｌ含有層は、塩酸を含有したエッチング液ではエッチングされないため、非Ａｌ含有層端部を起点としてファセットが形成されるので、素子分離を行った発光部１０８の側面に明瞭なメサ形状を得ることができる。ただし、非Ａｌ含有層を用いた場合、素子分離工程後、非Ａｌ含有層を硫酸過水等の過酸化水素水含有液で選択的に非Ａｌ含有層を除去する工程を行うことが好ましい。At this time, a non-Al-containing layer (not shown) can remain in the second region 131 that is not roughened in the first rough surface treatment step, and can be used as an etching mask.
The non-Al-containing layer may include one or more of GaAs, InGaP, InGaAs, and Ge. Since the non-Al-containing layer is not etched with an etching solution containing hydrochloric acid, facets are formed starting from the end of the non-Al-containing layer, so that a clear mesa shape is obtained on the side surface of the light-emitting portion 108 where element isolation has been performed. be able to. However, when the non-Al-containing layer is used, it is preferable to perform a step of selectively removing the non-Al-containing layer with a hydrogen peroxide solution-containing liquid such as sulfuric acid / hydrogen peroxide after the element isolation step.
また、素子分離工程は、上記のウェットエッチング法の他、ハロゲンガス、好ましくは塩化水素を含有するガスを用いる方法により、ドライエッチング法にて行うこともできる。
このようにすれば、素子分離を行った発光部の側面にくびれ（オーバーエッチング）のない形状を得ることができる。In addition to the wet etching method described above, the element isolation step can also be performed by a dry etching method by a method using a halogen gas, preferably a gas containing hydrogen chloride.
By doing so, it is possible to obtain a shape without constriction (over-etching) on the side surface of the light-emitting portion from which element isolation has been performed.
次に、図８に示すように、発光部１０８が除去された窓層兼支持基板１０７上の除去部１７０上に第二オーミック電極１２２を形成する（図２のＳＰ８）。 Next, as shown in FIG. 8, the second ohmic electrode 122 is formed on the removal portion 170 on the window layer / support substrate 107 from which the light emitting portion 108 has been removed (SP8 in FIG. 2).
次に、図８に示すように、第一半導体層１０３表面及び発光部１０８の側面の少なくとも一部を絶縁保護膜１５０で被覆する（図２のＳＰ９）。
絶縁保護膜１５０は透明で絶縁性を有する材料であれば、どのような材料でも可能である。絶縁保護膜１５０としては、例えばＳｉＯ２もしくはＳｉＮｘを用いることが好適である。このようなものであれば、フォトリソグラフィー法と弗酸を含有したエッチング液によって、第一オーミック電極１２１及び第二オーミック電極１２２の上部を開口する加工を容易に行うことができる。Next, as shown in FIG. 8, at least a part of the surface of the first semiconductor layer 103 and the side surface of the light emitting unit 108 is covered with an insulating protective film 150 (SP9 in FIG. 2).
The insulating protective film 150 can be any material as long as it is transparent and has insulating properties. As the insulating protective film 150, for example, SiO 2 or SiN x is preferably used. If it is such, the process which opens the upper part of the 1st ohmic electrode 121 and the 2nd ohmic electrode 122 with the photolithographic method and the etching liquid containing a hydrofluoric acid can be performed easily.
次に、図１に示すように、窓層兼支持基板１０７の表面及び側面を粗面化する第二粗面処理工程を行う（図２のＳＰ１０）。 Next, as shown in FIG. 1, a second rough surface treatment step is performed to roughen the surface and side surfaces of the window layer / support substrate 107 (SP10 in FIG. 2).
第二粗面処理を行う前に、まず、除去部１７０に沿ってスクライブ線をけがき、ブレーキングを行うことで発光素子を分離して、発光素子ダイスを形成することが好ましい。発光素子ダイス形成後、窓層兼支持基板１０７が上面になるように発光素子ダイスを保持テープに転写してから、下記の第二粗面処理を行うことが好ましい。 Before performing the second rough surface treatment, it is preferable to first scribe lines along the removal portion 170 and perform braking to separate the light emitting elements to form a light emitting element die. After forming the light emitting element die, it is preferable to transfer the light emitting element die to the holding tape so that the window layer / supporting substrate 107 is on the upper surface, and then perform the following second roughening treatment.
第二粗面処理工程は、クエン酸・マロン酸・蟻酸・酢酸・酒石酸の有機酸からいずれか１種類以上を含み、かつ、塩酸、硫酸、硝酸、弗酸の無機酸のいずれか１種類以上を含み、かつ、沃素を含む溶液を用いて行うことができる。 The second rough surface treatment step includes one or more organic acids such as citric acid, malonic acid, formic acid, acetic acid, and tartaric acid, and one or more inorganic acids such as hydrochloric acid, sulfuric acid, nitric acid, and hydrofluoric acid. And a solution containing iodine.
上述した第一粗面処理工程で用いた第一半導体層１０３に施す第一粗面液と、第二粗面処理工程で窓層兼支持基板１０７に施す第二粗面液とは液組成が異なる。そのため、エッチング特性が異なるため、必然的に第一半導体層１０３と窓層兼支持基板１０７が有する粗面の形状及びＲａ（算術平均粗さ）は異なったものとなる。The first rough surface liquid applied to the first semiconductor layer 103 used in the first rough surface treatment step described above and the second rough surface liquid applied to the window layer / support substrate 107 in the second rough surface treatment step have liquid compositions. Different. Therefore, since the etching characteristics are different, the shape of the rough surface and R a (arithmetic average roughness) of the first semiconductor layer 103 and the window layer / support substrate 107 inevitably differ.
上記で説明した本発明の発光素子の製造方法であれば、第一半導体層１０３表面に粗面化しない第二領域１３１を設けることで、素子分離工程において、発光部１０８にオーバーエッチングが生じることが抑制されるため、素子分離した発光部１０８の側面の形状は第二領域１３１の形状に略一致する。そのため、素子分離した発光部１０８の側面のＲｚを２μｍ未満とすることができるので、素子分離した発光部１０８の側面の形状における凸部に電界集中が発生することを抑止することができる。これにより、粗面化により発光効率を向上させるとともに、発光部側面の凹凸形状に依存するリーク不良及びＥＳＤ不良の発生が抑えられた発光素子を製造することができる。In the method for manufacturing a light emitting device of the present invention described above, overetching occurs in the light emitting portion 108 in the device isolation process by providing the second region 131 that is not roughened on the surface of the first semiconductor layer 103. Therefore, the shape of the side surface of the light emitting unit 108 separated from the element substantially matches the shape of the second region 131. Therefore, Rz on the side surface of the light-emitting portion 108 separated from the element can be less than 2 μm, and thus it is possible to prevent electric field concentration from occurring in the convex portion in the shape of the side surface of the light-emitting portion 108 separated from the element. As a result, it is possible to manufacture a light emitting device in which the luminous efficiency is improved by roughening and the occurrence of leakage defects and ESD defects depending on the uneven shape on the side surface of the light emitting part is suppressed.
以下、本発明の実施例及び比較例を示して本発明をより具体的に説明するが、本発明はこれらに限定されるものではない。 EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples and comparative examples of the present invention, but the present invention is not limited to these.
（実施例１）
結晶軸が［００１］方向より［１１０］方向に１５°傾斜した厚さ２８０μｍのｎ型ＧａＡｓ基板１０１上にｎ型ＧａＡｓバッファ層（不図示）を０．５μｍ、ｎ型ＡｌＩｎＰ基板除去選択エッチング層（不図示）を１μｍ成長させた後、ＭＯＶＰＥ法でＡｌＧａＩｎＰから成るｎ型クラッド層（第一半導体層１０３）、活性層１０４、ｐ型クラッド層（第二半導体層１０５）で構成される発光部１０８を６．５μｍ形成し、更にｐ型ＩｎＧａＰからなる緩衝層１０６を０．３μｍ形成し、ＧａＰ窓層兼支持基板１０７の一部としてｐ型ＧａＰからなる層を１μｍ形成した。次に、ＨＶＰＥ炉に移してｐ型ＧａＰからなる窓層兼支持基板１０７を１２０μｍ成長させ、エピタキシャル基板１０９を得た（図３参照）。Example 1
An n-type AlInP substrate removal selective etching layer is formed on an n-type GaAs buffer layer (not shown) of 0.5 μm on a 280 μm thick n-type GaAs substrate 101 whose crystal axis is inclined by 15 ° in the [110] direction from the [001] direction. After growing 1 μm (not shown), a light-emitting unit composed of an n-type cladding layer (first semiconductor layer 103), an active layer 104, and a p-type cladding layer (second semiconductor layer 105) made of AlGaInP by the MOVPE method. 108 μm was formed, a buffer layer 106 made of p-type InGaP was formed 0.3 μm, and a p-type GaP layer 1 μm was formed as a part of the GaP window layer / support substrate 107. Next, the substrate was transferred to an HVPE furnace, and a window layer / support substrate 107 made of p-type GaP was grown by 120 μm to obtain an epitaxial substrate 109 (see FIG. 3).
次に、ＧａＡｓ基板１０１、ＧａＡｓバッファ層およびｎ型ＡｌＩｎＰ基板除去選択エッチング層を除去して発光素子基板１１０を作製した（図４参照）。 Next, the GaAs substrate 101, the GaAs buffer layer, and the n-type AlInP substrate removal selective etching layer were removed to produce a light emitting element substrate 110 (see FIG. 4).
次に、発光素子基板１１０の第一半導体層１０３の基板除去面１２０上へ第一オーミック電極１２１を形成し（図５参照）、フォトリソグラフィー法により第三領域１３０及び第二領域１３１をレジストで被覆するパターンを形成した。図９に示すように、第三領域１３０は第一オーミック電極に沿って、第二領域１３１は素子分離予定線１６０に沿って設けた。第三領域１３０の幅はエッチング深さの４倍の２μｍとした。また、第二領域１３１の幅は６μｍとした。 Next, a first ohmic electrode 121 is formed on the substrate removal surface 120 of the first semiconductor layer 103 of the light emitting element substrate 110 (see FIG. 5), and the third region 130 and the second region 131 are formed of a resist by photolithography. A pattern to be coated was formed. As shown in FIG. 9, the third region 130 is provided along the first ohmic electrode, and the second region 131 is provided along the element isolation planned line 160. The width of the third region 130 was 2 μm, which is four times the etching depth. The width of the second region 131 was 6 μm.
次に第一半導体層１０３表面に第一粗面処理工程を施した（図６参照）。第一粗面液は酢酸と塩酸の混合液を作製し、常温で１分エッチングすることで粗面処理を実現した。 Next, a first rough surface treatment step was performed on the surface of the first semiconductor layer 103 (see FIG. 6). As the first rough surface liquid, a mixed liquid of acetic acid and hydrochloric acid was prepared, and the rough surface treatment was realized by etching at room temperature for 1 minute.
次に、フォトリソグラフィー法により、第二オーミック電極形成領域１４０及びスクライブ領域１４１（図６参照）以外をレジストで被覆し、塩酸を含有するウェットエッチング液によるウェットエッチング法で素子分離工程を実施し、発光部１０８を除去して窓層兼支持基板１０７が露出した除去部１７０と、それ以外の非除去部１８０を形成した（図７参照）。 Next, by a photolithography method, a region other than the second ohmic electrode formation region 140 and the scribe region 141 (see FIG. 6) is covered with a resist, and an element isolation step is performed by a wet etching method using a wet etching solution containing hydrochloric acid. The light emitting portion 108 was removed to form a removal portion 170 where the window layer / support substrate 107 was exposed, and other non-removal portions 180 (see FIG. 7).
以上の工程を行った結果、素子分離を行った発光部の側面のＲｚはフォトレジストパターン精度に応じた０．５μｍ程度を示した。As a result of performing the above steps, the R z on the side surface of the light emitting portion from which the element was isolated showed about 0.5 μm corresponding to the photoresist pattern accuracy.
次に、除去部１７０に第二オーミック電極１２２を形成した（図８参照）。次に、ＳｉＯ２からなる絶縁保護膜１５０を積層し、第一半導体層１０３表面及び発光部１０８の側面を絶縁保護膜１５０で被覆した。そして、第一オーミック電極１２１及び第二オーミック電極１２２部分をフォトリソグラフィー法と弗酸エッチングにより、絶縁保護膜１５０に開口部を形成した。Next, the 2nd ohmic electrode 122 was formed in the removal part 170 (refer FIG. 8). Next, an insulating protective film 150 made of SiO 2 was laminated, and the surface of the first semiconductor layer 103 and the side surfaces of the light emitting unit 108 were covered with the insulating protective film 150. Then, openings were formed in the insulating protective film 150 at the first ohmic electrode 121 and the second ohmic electrode 122 by photolithography and hydrofluoric acid etching.
次に、露出させた除去部１７０に沿ってスクライブ線をけがき、スクライブ線に沿ってクラック線を伸ばし、その後、ブレーキングを行うことで素子を分離し、発光素子ダイスを形成した。 Next, the scribe line was scribed along the exposed removal part 170, the crack line was extended along the scribe line, and then the elements were separated by braking to form a light emitting element die.
発光素子ダイス形成後、第一オーミック電極が設けられている面がテープ面側になるように保持テープに発光素子ダイスを転写し、その後、第二粗面処理工程を実施した。第二粗面処理工程で窓層兼支持基板の粗面化を行う際に用いる粗面液は、酢酸と弗酸、沃素の混合液を作製した。そして、常温で１分エッチングすることで第二粗面処理を行った。 After the light emitting element die was formed, the light emitting element die was transferred to the holding tape so that the surface on which the first ohmic electrode was provided was on the tape surface side, and then the second rough surface treatment step was performed. As a rough surface solution used for roughening the window layer / supporting substrate in the second rough surface treatment step, a mixed solution of acetic acid, hydrofluoric acid and iodine was prepared. And the 2nd roughening process was performed by etching for 1 minute at normal temperature.
以上のようにして図９に示すような発光素子を製造した。 A light emitting device as shown in FIG. 9 was manufactured as described above.
図１１には実施例１における素子分離部の端部の写真を示した。図１１では、第二領域１３１の端部を直線で形成した状態を示していることがわかる。 FIG. 11 shows a photograph of the end of the element isolation portion in Example 1. FIG. 11 shows that the end portion of the second region 131 is formed in a straight line.
上記のようにして作製した発光素子でランプを作製し、測定及び評価を行った。 A lamp was manufactured with the light emitting element manufactured as described above, and measurement and evaluation were performed.
実施例１で製造した発光素子で作製したランプの逆方向印加電流値１０μＡ時における逆方向電圧（ＶＲ）の結果を図１３に示す。なお、図１３には後述する実施例２及び比較例の結果も併せて示した。
その結果、図１３に示すように、実施例１及び後述する実施例２で作製したランプは、逆方向印加電流値が１０μＡの場合、ＶＲは３０Ｖ以上必要で、ＶＲ値３０Ｖ未満を示すランプは発生しなかった。一方、後述する比較例で作製したランプの約半数のＶＲ値が３０Ｖ未満を示した。このように、本発明の発光素子は、第二領域の存在によって逆方向電圧の特性が優れたものとなることが分かった。FIG. 13 shows the results of reverse voltage (VR) when the reverse direction applied current value of the lamp manufactured by the light emitting element manufactured in Example 1 is 10 μA. FIG. 13 also shows the results of Example 2 and Comparative Example described later.
As a result, as shown in FIG. 13, in the lamps manufactured in Example 1 and Example 2 described later, when the reverse direction applied current value is 10 μA, VR is required to be 30V or more, and the lamp showing VR value of less than 30V is Did not occur. On the other hand, the VR value of about half of the lamps produced in the comparative examples described later was less than 30V. Thus, it was found that the light emitting device of the present invention has excellent reverse voltage characteristics due to the presence of the second region.
次に、実施例１で製造した発光素子で作製したランプを用いて、ＥＳＤ試験を行った結果を図１４に示す。ＥＳＤ実施条件はＨＢＭ（ＨｕｍａｎＢｏｄｙ Ｍｏｄｅｌ）で行った。なお、図１４には後述する実施例２及び比較例の結果も併せて示した。
その結果、図１４に示すように、実施例１及び後述する実施例２で作製したランプでは、２０００ＶまでのＥＳＤ試験において、ＥＳＤ破壊が発生しなかった。一方後述する比較例においては１００Ｖ程度のＥＳＤ電圧でＥＳＤ破壊が発生し、６００Ｖまでには試験投入した全ての素子がＥＳＤ破壊された。Next, FIG. 14 shows the results of an ESD test using a lamp manufactured using the light-emitting element manufactured in Example 1. The ESD execution conditions were HBM (Human Body Model). FIG. 14 also shows the results of Example 2 and Comparative Example described later.
As a result, as shown in FIG. 14, in the lamps manufactured in Example 1 and Example 2 described later, ESD breakdown did not occur in the ESD test up to 2000V. On the other hand, in a comparative example to be described later, an ESD breakdown occurred at an ESD voltage of about 100V, and by 600V, all the elements that were put into the test were destroyed.
（実施例２）
まず、実施例１と同様にして、第一粗面処理工程まで行った。(Example 2)
First, it carried out similarly to Example 1 to the 1st roughening process process.
次に、ドライエッチング法を行うために、第一半導体層、第一オーミック電極を被覆するようにＳｉＯ２膜を３００ｎｍ被覆し、フォトリソグラフィー法により、素子分離予定形状のレジストパターンを形成した。次に、弗酸によりパターン開口部をエッチングした。
そして、開口パターンを有するＳｉＯ２膜をエッチングマスクとして、ドライエッチング法を実施した。ドライエッチングに際しては塩素含有ガスを導入したＲＩＥ法もしくはＩＣＰ法によって素子分離を実施し、発光部を除去して、窓層兼支持基板を露出させた除去部を形成した。Next, in order to perform the dry etching method, a SiO 2 film was coated with a thickness of 300 nm so as to cover the first semiconductor layer and the first ohmic electrode, and a resist pattern having an element isolation shape was formed by a photolithography method. Next, the pattern opening was etched with hydrofluoric acid.
Then, a dry etching method was performed using an SiO 2 film having an opening pattern as an etching mask. In dry etching, element isolation was performed by the RIE method or ICP method in which a chlorine-containing gas was introduced, and the light emitting portion was removed to form a removed portion exposing the window layer / support substrate.
以上の工程を行った結果、素子分離を行った発光部の側面のＲｚはＳｉＯ２マスクのパターン精度に応じた０．５μｍ程度を示した。As a result of performing the above steps, the R z on the side surface of the light emitting portion from which element isolation was performed showed about 0.5 μm corresponding to the pattern accuracy of the SiO 2 mask.
その後、実施例１と同様にして、第二オーミック電極の形成から第二粗面処理工程までを行い、図１０に示すような発光素子を製造した。 Then, it carried out similarly to Example 1, and formed from the formation of the 2nd ohmic electrode to the 2nd roughening process process, and manufactured the light emitting element as shown in FIG.
上記のようにして作製した発光素子でランプを作製し、測定及び評価を行った。 A lamp was manufactured with the light emitting element manufactured as described above, and measurement and evaluation were performed.
実施例２で製造した発光素子で作製したランプの逆方向印加電流値１０μＡ時における逆方向電圧（ＶＲ）の結果を図１３に示した。
その結果、図１３に示すように、実施例２で作製したランプは、逆方向印加電流値が１０μＡの場合、ＶＲは３０Ｖ以上必要で、ＶＲ値３０Ｖ未満を示すランプは発生しなかった。本発明の発光素子は、第二領域の存在によって逆方向電圧の特性が優れたものとなることが分かった。FIG. 13 shows the results of reverse voltage (VR) when the reverse direction applied current value of the lamp manufactured by the light emitting device manufactured in Example 2 is 10 μA.
As a result, as shown in FIG. 13, in the lamp manufactured in Example 2, when the reverse direction applied current value was 10 μA, VR was required to be 30 V or more, and a lamp showing a VR value of less than 30 V was not generated. It has been found that the light emitting device of the present invention has excellent reverse voltage characteristics due to the presence of the second region.
次に、実施例２で製造した発光素子で作製したランプを用いて、ＥＳＤ試験を行った結果を図１４に示した。ＥＳＤ実施条件はＨＢＭ（ＨｕｍａｎＢｏｄｙ Ｍｏｄｅｌ）で行った。
その結果、図１４に示すように、実施例２で作製したランプでは、２０００ＶまでのＥＳＤ試験において、ＥＳＤ破壊が発生しなかった。Next, FIG. 14 shows a result of an ESD test using a lamp manufactured using the light-emitting element manufactured in Example 2. The ESD execution conditions were HBM (Human Body Model).
As a result, as shown in FIG. 14, in the lamp manufactured in Example 2, ESD breakdown did not occur in the ESD test up to 2000V.
（比較例）
第一粗面処理工程において、第二領域を設けなかったこと以外は、実施例１同様にして発光素子の製造を行った。
その結果、比較例では第一粗面処理によって生じた凹凸（第一半導体層表面のＲｚ＝０．６μｍ前後）が素子分離工程によって増大し、素子分離を行った発光部の側面のＲｚは３〜４μｍに達した。
図１２に比較例における素子分離部端部の写真を示した。(Comparative example)
In the first rough surface treatment step, a light emitting device was manufactured in the same manner as in Example 1 except that the second region was not provided.
As a result, in the comparative example, the unevenness (R z = 0.6 μm on the surface of the first semiconductor layer) generated by the first rough surface treatment is increased by the element isolation process, and the R z on the side surface of the light emitting part that has performed element isolation is increased. Reached 3-4 μm.
FIG. 12 shows a photograph of the end portion of the element isolation portion in the comparative example.
上記のようにして作製した発光素子でランプを作製し、測定及び評価を行った。 A lamp was manufactured with the light emitting element manufactured as described above, and measurement and evaluation were performed.
比較例で製造した発光素子で作製したランプの逆方向印加電流値１０μＡ時における逆方向電圧（ＶＲ）の結果を図１３に示した。
その結果、図１３に示すように、比較例で作製したランプの約半数のＶＲ値が３０Ｖ未満を示した。FIG. 13 shows the results of reverse voltage (VR) when the reverse direction applied current value of the lamp manufactured with the light emitting device manufactured in the comparative example is 10 μA.
As a result, as shown in FIG. 13, the VR value of about half of the lamps produced in the comparative example was less than 30V.
次に、比較例で製造した発光素子で作製したランプを用いて、ＥＳＤ試験を行った結果を図１４に示す。ＥＳＤ実施条件はＨＢＭ（ＨｕｍａｎＢｏｄｙ Ｍｏｄｅｌ）で行った。
その結果、図１４に示すように、比較例で作製したランプでは、１００Ｖ程度のＥＳＤ電圧でＥＳＤ破壊が発生し、６００Ｖまでには試験投入した全ての素子がＥＳＤ破壊された。Next, FIG. 14 shows the results of an ESD test using a lamp manufactured using the light-emitting element manufactured in the comparative example. The ESD execution conditions were HBM (Human Body Model).
As a result, as shown in FIG. 14, in the lamp manufactured in the comparative example, ESD breakdown occurred at an ESD voltage of about 100V, and all the devices that were put into the test were ESD destroyed by 600V.
（実験）
素子分離工程形成時のマスクパターンを変化させ、発光部の側面のＲｚを変化させたこと以外は、実施例１の方法で製造した発光素子でランプ複数を製作した（実験１）。
素子分離工程形成時のマスクパターンを変化させ、発光部の側面のＲｚを変化させたこと以外は、実施例２の方法で製造した発光素子でランプ複数を製作した（実験２）。(Experiment)
A plurality of lamps were manufactured using the light-emitting element manufactured by the method of Example 1 except that the mask pattern at the time of forming the element separation process was changed and the Rz on the side surface of the light-emitting portion was changed (Experiment 1).
A plurality of lamps were manufactured using the light emitting device manufactured by the method of Example 2 except that the mask pattern at the time of forming the device isolation process was changed and the Rz on the side surface of the light emitting portion was changed (Experiment 2).
そして、上記の実験１、２のランプの逆方向印加電流値１０μＡ時におけるＶＲ不良率の測定を行った結果を図１５に示した。なお、逆方向印加電流１０μＡ時のＶＲ値が３０Ｖ未満のものをＶＲ不良として測定を行った。 FIG. 15 shows the result of measurement of the VR defect rate when the reverse applied current value of the lamps in Experiments 1 and 2 was 10 μA. In addition, the VR value at the time of reverse direction applied current of 10 μA was measured as VR failure when it was less than 30V.
その結果、図１５に示したように、実験１、２共にＲｚが２μｍ未満までにおいて、ＶＲ不良はほとんど発生しないが、Ｒｚが２μｍ以上の場合には、実験１、２共にＶＲ不良が増加し始めることが分かる。As a result, as shown in FIG. 15, VR failure hardly occurs when Rz is less than 2 μm in both experiments 1 and 2, but when Rz is 2 μm or more, VR failure is found in both experiments 1 and 2. You can see that it starts to increase.
素子分離を行った発光部側面の形状は、素子分離工程における第一半導体層の外周部の形状をほぼ踏襲するため、素子分離工程時の第一半導体層の外周部の凹凸が大きい程、ＶＲ不良が発生しやすいことを図１５は示している。
従って、発光部側面のＲｚは２μｍ未満であることが必要である。図１５ではＶＲ不良についてのみ示したが、逆バイアスを印加した際のリーク電流値を示すＩＲ特性に関しても同様の傾向であった。Since the shape of the side surface of the light emitting portion after the element isolation substantially follows the shape of the outer periphery of the first semiconductor layer in the element isolation process, the larger the irregularity of the outer periphery of the first semiconductor layer during the element isolation process, the greater the VR. FIG. 15 shows that defects are likely to occur.
Therefore, the Rz on the side surface of the light emitting unit needs to be less than 2 μm. In FIG. 15, only the VR failure is shown, but the same tendency was observed with respect to the IR characteristic indicating the leakage current value when the reverse bias was applied.
また、発光部側面の凹凸が発光部側面上で均一ではなく、発光素子側面の一部の凹凸量を半分にしたパターンを準備し、測定を行ったが、ＶＲ不良発生の傾向は、同一の凹凸量で構成されたパターンの場合と同様であった。従って、発光部側面の凹凸とＶＲ不良率発生の関係は、発光部側面のＲｚが２μｍ以上であればＶＲ不良率が増加することを示していることが分かる。従って、リーク不良あるいはＥＳＤ不良を抑止するためには、発光部側面のＲｚが２μｍ未満であることが必要である。Further, the unevenness on the side surface of the light emitting unit was not uniform on the side surface of the light emitting unit, and a pattern was prepared by halving the amount of unevenness on the side surface of the light emitting element, and the measurement was performed. It was the same as the case of the pattern comprised by the unevenness | corrugation amount. Therefore, it can be seen that the relationship between the unevenness on the side surface of the light emitting part and the occurrence of the VR defect rate indicates that the VR defect rate increases when Rz on the side surface of the light emitting part is 2 μm or more. Therefore, in order to suppress leakage failure or ESD failure, it is necessary that Rz on the side surface of the light emitting portion is less than 2 μm.
なお、本発明は、上記実施形態に限定されるものではない。上記実施形態は例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に包含される。 The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.
Claims (8)
前記発光素子は、前記発光部が除去された除去部と、前記除去部以外の非除去部と、該非除去部の前記第一半導体層上に設けられた第一オーミック電極と、前記除去部の前記窓層兼支持基板上に設けられた第二オーミック電極とを有し、
前記第一半導体層表面及び前記発光部の側面の少なくとも一部は絶縁保護膜で被覆され、前記第一半導体層の外周部を除く表面及び前記窓層兼支持基板の表面が粗面化され、且つ、前記発光部側面のＲｚが２μｍ未満であることを特徴とする発光素子。A window layer / supporting substrate; a light emitting unit provided on the window layer / supporting substrate, including a second conductive type second semiconductor layer, an active layer, and a first conductive type first semiconductor layer in this order; In a light emitting device having
The light emitting element includes: a removed portion from which the light emitting portion has been removed; a non-removed portion other than the removed portion; a first ohmic electrode provided on the first semiconductor layer of the non-removed portion; A second ohmic electrode provided on the window layer and supporting substrate;
At least a part of the surface of the first semiconductor layer and the side surface of the light emitting portion is covered with an insulating protective film, the surface excluding the outer peripheral portion of the first semiconductor layer and the surface of the window layer and supporting substrate are roughened, In addition, the light-emitting element, wherein R z on the side surface of the light-emitting portion is less than 2 μm.
前記第一粗面処理工程において、第一オーミック電極周辺及び、その後の前記素子分離工程で前記非除去部の前記第一半導体層表面の外周部となる領域については粗面化しないことを特徴とする発光素子の製造方法。Forming a light emitting portion on the substrate by sequentially growing a first semiconductor layer, an active layer, and a second semiconductor layer using a lattice-matching material with the substrate by epitaxial growth; and Forming a window layer and supporting substrate by epitaxial growth using a non-lattice matching material, removing the substrate, forming a first ohmic electrode on the surface of the first semiconductor layer, and the first A first rough surface treatment step for performing a rough surface treatment on the surface of the semiconductor layer; a removal portion for removing a part of the light emitting portion; an element separation step for forming other non-removed portions; and the light emitting portion removed. A step of forming a second ohmic electrode on the window / cumulative substrate thus formed; a step of covering at least part of the surface of the first semiconductor layer and the side surface of the light emitting portion with an insulating protective film; Roughen the surface and side of Made from the second surface roughening step,
In the first rough surface treatment step, the first ohmic electrode periphery and the region that becomes the outer peripheral portion of the surface of the first semiconductor layer of the non-removed portion in the subsequent element isolation step are not roughened. A method for manufacturing a light emitting device.
有機酸と無機酸の混合液が用いられ、前記有機酸は、クエン酸・マロン酸・蟻酸・酢酸・酒石酸のいずれか一種類以上含有し、前記無機酸は塩酸・硫酸・硝酸・弗酸のいずれか一種類以上を含有する溶液を用いて行い、
前記第二粗面処理工程は、
クエン酸・マロン酸・蟻酸・酢酸・酒石酸の有機酸からいずれか１種類以上を含み、かつ、塩酸、硫酸、硝酸、弗酸の無機酸のいずれか１種類以上を含み、かつ、沃素を含む溶液を用いて行うことを特徴とする請求項４に記載の発光素子の製造方法。The first rough surface treatment step includes
A mixed solution of an organic acid and an inorganic acid is used, and the organic acid contains at least one of citric acid, malonic acid, formic acid, acetic acid, and tartaric acid, and the inorganic acid includes hydrochloric acid, sulfuric acid, nitric acid, and hydrofluoric acid. Using a solution containing any one or more of them,
The second rough surface treatment step includes
Contains at least one organic acid such as citric acid, malonic acid, formic acid, acetic acid, and tartaric acid, and contains one or more inorganic acids such as hydrochloric acid, sulfuric acid, nitric acid, and hydrofluoric acid, and contains iodine. The method for producing a light-emitting element according to claim 4, wherein the method is performed using a solution.
塩酸を含有するウェットエッチング液によるウェットエッチング法により行い、前記第一粗面処理工程において粗面化させない領域に非Ａｌ含有層を残留させ、エッチングマスクとして使用することを特徴とする請求項３から請求項５のいずれか一項に記載の発光素子の製造方法。The element isolation step includes
The wet etching method using a wet etching solution containing hydrochloric acid is used, and a non-Al-containing layer is left in a region that is not roughened in the first roughening treatment step, and is used as an etching mask. The manufacturing method of the light emitting element as described in any one of Claims 5.
塩化水素を含有するガスによるドライエッチング法により行うことを特徴とする請求項３から請求項５のいずれか一項に記載の発光素子の製造方法。The element isolation step includes
The method for manufacturing a light-emitting element according to claim 3, wherein the method is performed by a dry etching method using a gas containing hydrogen chloride.
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