JP6216668B2 - 表示装置の製造方法 - Google Patents
表示装置の製造方法 Download PDFInfo
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- JP6216668B2 JP6216668B2 JP2014053604A JP2014053604A JP6216668B2 JP 6216668 B2 JP6216668 B2 JP 6216668B2 JP 2014053604 A JP2014053604 A JP 2014053604A JP 2014053604 A JP2014053604 A JP 2014053604A JP 6216668 B2 JP6216668 B2 JP 6216668B2
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Description
酸化物半導体層4は,ゲート絶縁膜3が形成されたガラス基板1上に、スパッタリング法により、In-Ga-Zn-O系In-Al-Zn-O系、In-Sn-Zn-O系、In-Zn-O系、In-Sn-O系、Zn-O系、Sn-O系などの酸化物半導体を成膜する。続いて、酸化物半導体上に感光性樹脂膜を塗布した後に、現像しパターニングすることでレジストパターンを形成する。その後、レジストパターンから露出する酸化物半導体をウエットエッチングにより除去した後レジストパターンを剥離し、酸化物半導体層4を形成する。また酸化物半導体層4に酸素(O2)や一酸化二窒素(N2O)を用いてプラズマ処理を施すことで、酸素欠陥の少ない酸化物半導体層4を形成することができる。(工程c)
チャネル保護層5は、酸化物半導体層4が成膜されたガラス基板1に、プラズマCVD法等によりシリコン酸化膜を成膜し、チャネル保護層5上に感光性樹脂膜を塗布した後に、現像しパターニングすることでレジストパターンを形成する。その後、レジストパターンから露出するチャネル保護層5をドライエッチングにより除去した後、レジストパターンを剥離する。(工程d,工程e)
また図には示していないが、ソース・ドレイン電極を形成する前に、ゲート電極へのコンタクトホールを形成しておいても良い。
続いて、ソース・ドレイン電極C8上に感光性樹脂膜を塗布した後に、現像しパターニングすることでレジストパターン12を形成する。その後、レジストパターンから露出するソース・ドレイン電極C8、ソース・ドレイン電極B7をウエットエッチングまたはドライエッチングにより除去し、ソース・ドレイン電極A6はエッチングせずに残しておく。ここで、ガラス基板1面内のエッチングバラつきやプロセスバラつきを考慮して、ソース・ドレイン電極B7は完全にエッチングされずに残っていても良いし、ソース・ドレイン電極A6が少しエッチングされていても良い。(工程g,工程h)
次に、ガラス基板1の表面に酸化処理すなわちレジストパターン12から露出した部分のソース・ドレイン電極A6を酸素プラズマ処理などで酸化処理することで金属酸化層9を形成する。ソース・ドレイン電極B7が残留している場合には、ソース・ドレイン電極A6およびソース・ドレイン電極B7の両方を酸化処理し金属酸化層9を形成する。(工程i)
チタンの酸化は酸素プラズマ処理以外に、一酸化二窒素(N2O)でのプラズマ処理、酸化雰囲気での熱処理によって形成しても良い。金属酸化層9の形成後にレジストパターン12を剥離する。(工程j)このように、金属酸化層9を形成することで、酸化物半導体層4への光の入射を抑え、閾値電圧のシフトを抑えることが出来る。つまり、金属酸化層9は、酸化物半導体層4への外部からの光の入射を遮蔽する遮光層として機能する。金属酸化層9の膜厚は、50nm以上200nm以下とすることで、酸化されずにソース・ドレイン電極A6となる領域の電気特性と酸化され金属酸化層9となる領域の遮光特性をより好適に得ることができる。
Claims (10)
- 以下の工程を含む表示装置の製造方法;
(a)基板上に第一の金属膜を成膜し、パターニングによりゲート電極を形成する工程、
(b)前記基板および前記ゲート電極を覆うように、前記基板および前記ゲート電極上にゲート絶縁膜を形成する工程、
(c)前記ゲート絶縁膜上に半導体酸化膜を成膜し、パターニングにより酸化物半導体層を形成する工程、
(d)前記ゲート絶縁膜および前記酸化物半導体層上にシリコン酸化膜を成膜し、パターニングにより前記酸化物半導体層上にチャネル保護層を形成する工程、
(e)前記ゲート絶縁膜、前記酸化物半導体層、前記チャネル保護層を覆うようにソース・ドレイン電極となる第二の金属膜、第三の金属膜、第四の金属膜を下層から順に成膜し、パターニングにより前記チャネル保護層上の前記第三の金属膜および前記第四の金属膜を除去し、前記第二の金属膜を露出する工程、
(f)前記基板の表面に酸化処理を施し、前記第二の金属膜が露出した領域に金属酸化層を形成する工程。 - 前記(d)工程において、前記シリコン酸化膜のパターニングにより前記酸化物半導体層上にチャネル保護層を形成する際、同時に前記酸化物半導体層上に前記シリコン酸化膜を貫通する複数のコンタクトホールを形成することを特徴とする請求項1に記載の表示装置の製造方法。
- 前記第一の金属膜は、チタン、モリブデン、アルミニウム、クロム、銅、タングステン、ジルコニウム、タンタル、銀、マンガンのいずれか、或いはこれらの組み合わせによる合金であることを特徴とする請求項1または2に記載の表示装置の製造方法。
- 前記第二の金属膜、前記第三の金属膜、前記第四の金属膜は、チタン、モリブデン、アルミニウム、クロム、銅、タングステン、ジルコニウム、タンタル、銀、マンガンのいずれか、或いはこれらの組み合わせによる合金であることを特徴とする請求項1から3のいずれかに記載の表示装置の製造方法。
- 前記酸化物半導体層は、In−Ga−Zn−O、In―Al−Zn−O、In−Sn−Zn−O、In−Zn−O、In−Sn−O、Zn−O、Sn−Oのいずれかを主成分とすることを特徴とする請求項1から4のいずれかに記載の表示装置の製造方法。
- 前記金属酸化層の膜厚は、50nm以上200nm以下であることを特徴とする請求項1から5のいずれかに記載の表示装置の製造方法。
- 前記基板はガラス基板であり、前記基板と前記ゲート電極が直接接しないよう、前記基板および前記ゲート電極間にシリコン窒化膜が形成されていることを特徴とする請求項1から6のいずれかに記載の表示装置の製造方法。
- 前記金属酸化層は、前記酸化物半導体層への外部からの光の入射を遮蔽する遮光層であることを特徴とする請求項1から7のいずれかに記載の表示装置の製造方法。
- 前記表示装置は、フリンジ電界を利用して液晶分子を駆動させるFFS(フリンジ・フィールド・スイッチング)方式の液晶表示装置であることを特徴とする請求項1から8のいずれかに記載の表示装置の製造方法。
- 前記表示装置は、発光素子に有機発光ダイオードを用いた有機EL表示装置であることを特徴とする請求項1から8のいずれかに記載の表示装置の製造方法。
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