JP6196305B2 - マルチコアプロセッサ用の調整可能なマルチティアｓｔｔ−ｍｒａｍキャッシュ - Google Patents

マルチコアプロセッサ用の調整可能なマルチティアｓｔｔ−ｍｒａｍキャッシュ Download PDF

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JP6196305B2
JP6196305B2 JP2015526678A JP2015526678A JP6196305B2 JP 6196305 B2 JP6196305 B2 JP 6196305B2 JP 2015526678 A JP2015526678 A JP 2015526678A JP 2015526678 A JP2015526678 A JP 2015526678A JP 6196305 B2 JP6196305 B2 JP 6196305B2
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cache
stt
mram
core
core processor
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JP2015528601A5 (enExample
JP2015528601A (ja
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スン・エイチ・カン
シャオチュン・ジュウ
シャオシア・ウ
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クアルコム，インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/22—Employing cache memory using specific memory technology
    • G06F2212/222—Non-volatile memory

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Mram Or Spin Memory Techniques (AREA)
JP2015526678A 2012-08-10 2013-08-07 マルチコアプロセッサ用の調整可能なマルチティアｓｔｔ−ｍｒａｍキャッシュ Expired - Fee Related JP6196305B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/571,426 2012-08-10
US13/571,426 US9244853B2 (en) 2012-08-10 2012-08-10 Tunable multi-tiered STT-MRAM cache for multi-core processors
PCT/US2013/054004 WO2014025920A1 (en) 2012-08-10 2013-08-07 Tunable multi-tiered stt-mram cache for multi-core processors

Publications (3)

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JP2015528601A JP2015528601A (ja) 2015-09-28
JP2015528601A5 JP2015528601A5 (enExample) 2016-09-08
JP6196305B2 true JP6196305B2 (ja) 2017-09-13

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JP2015526678A Expired - Fee Related JP6196305B2 (ja) 2012-08-10 2013-08-07 マルチコアプロセッサ用の調整可能なマルチティアｓｔｔ−ｍｒａｍキャッシュ

Country Status (7)

Country Link
US (1) US9244853B2 (enExample)
EP (1) EP2883151B1 (enExample)
JP (1) JP6196305B2 (enExample)
KR (1) KR20150041092A (enExample)
CN (1) CN104520838B (enExample)
IN (1) IN2015MN00076A (enExample)
WO (1) WO2014025920A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9858111B2 (en) * 2014-06-18 2018-01-02 Empire Technologies Development Llc Heterogeneous magnetic memory architecture
CN105740164B (zh) 2014-12-10 2020-03-17 阿里巴巴集团控股有限公司 支持缓存一致性的多核处理器、读写方法、装置及设备
JP2016170729A (ja) * 2015-03-13 2016-09-23 株式会社東芝 メモリシステム
JP6039772B1 (ja) 2015-09-16 2016-12-07 株式会社東芝 メモリシステム
JP5992592B1 (ja) * 2015-09-16 2016-09-14 株式会社東芝 キャッシュメモリシステム
KR102007068B1 (ko) * 2016-01-15 2019-08-05 한양대학교 산학협력단 Stt-mram을 포함하는 메모리 시스템 및 그 구축 방법
US11138125B2 (en) * 2017-07-21 2021-10-05 Taiwan Semiconductor Manufacturing Company Limited Hybrid cache memory and method for reducing latency in the same
CN108932206B (zh) * 2018-05-21 2023-07-21 南京航空航天大学 一种三维多核处理器混合缓存架构及方法
US11216387B2 (en) * 2019-09-16 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid cache memory and method for controlling the same
US12308072B2 (en) 2021-03-10 2025-05-20 Invention And Collaboration Laboratory Pte. Ltd. Integrated scaling and stretching platform for optimizing monolithic integration and/or heterogeneous integration in a single semiconductor die
US12400949B2 (en) 2021-03-10 2025-08-26 Invention And Collaboration Laboratory Pte. Ltd. Interconnection structure and manufacture method thereof
CN119493532B (zh) * 2025-01-17 2025-04-29 山东浪潮科学研究院有限公司 一种混合缓存架构及缓存数据管理方法、系统

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4341355B2 (ja) * 2003-09-24 2009-10-07 ソニー株式会社 磁気記憶装置、磁気記憶装置の書き込み方法および磁気記憶装置の製造方法
US20050071564A1 (en) * 2003-09-25 2005-03-31 International Business Machines Corporation Reduction of cache miss rates using shared private caches
TWI285893B (en) 2004-11-12 2007-08-21 Ind Tech Res Inst Hybrid MRAM memory array architecture
JP5243746B2 (ja) * 2007-08-07 2013-07-24 ルネサスエレクトロニクス株式会社 磁気記憶装置の製造方法および磁気記憶装置
JP5488833B2 (ja) * 2008-03-07 2014-05-14 日本電気株式会社 Ｍｒａｍ混載システム
US9159910B2 (en) * 2008-04-21 2015-10-13 Qualcomm Incorporated One-mask MTJ integration for STT MRAM
US8564079B2 (en) * 2008-04-21 2013-10-22 Qualcomm Incorporated STT MRAM magnetic tunnel junction architecture and integration
KR100979351B1 (ko) * 2008-07-25 2010-08-31 주식회사 하이닉스반도체 멀티 스택 ｓｔｔ－ｍｒａｍ 장치 및 그 제조 방법
US8719610B2 (en) * 2008-09-23 2014-05-06 Qualcomm Incorporated Low power electronic system architecture using non-volatile magnetic memory
US8966181B2 (en) 2008-12-11 2015-02-24 Seagate Technology Llc Memory hierarchy with non-volatile filter and victim caches
US8914568B2 (en) 2009-12-23 2014-12-16 Intel Corporation Hybrid memory architectures
US8315081B2 (en) * 2010-03-22 2012-11-20 Qualcomm Incorporated Memory cell that includes multiple non-volatile memories
JP2012014787A (ja) * 2010-06-30 2012-01-19 Sony Corp 記憶装置
US8456883B1 (en) * 2012-05-29 2013-06-04 Headway Technologies, Inc. Method of spin torque MRAM process integration

Also Published As

Publication number Publication date
KR20150041092A (ko) 2015-04-15
US20140047184A1 (en) 2014-02-13
WO2014025920A1 (en) 2014-02-13
EP2883151A1 (en) 2015-06-17
EP2883151B1 (en) 2022-06-22
JP2015528601A (ja) 2015-09-28
CN104520838B (zh) 2018-01-16
IN2015MN00076A (enExample) 2015-10-16
CN104520838A (zh) 2015-04-15
US9244853B2 (en) 2016-01-26

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