JP6175838B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  As a method of bonding semiconductor substrates, there is a method of directly bonding semiconductor substrates without providing a bonding film made of metal or resin. According to this bonding method, the structures provided on the respective semiconductor substrates can be optically, electrically, or thermally coupled. Therefore, a method for bonding semiconductor substrates is attracting attention as a method for manufacturing optical devices and electronic devices. A device manufactured using this bonding method can exhibit new functions and performances that are not found in conventional devices as described in Non-Patent Document 1.

  As a method of bonding semiconductor substrates, for example, Patent Document 1 describes a method of bonding activated substrate surfaces. In this bonding method, the surface of the semiconductor substrate is activated by irradiating the surface of the semiconductor substrate disposed in the vacuum chamber with an argon beam. Then, the semiconductor substrates are bonded together by pressing the surfaces of the activated semiconductor substrates together.

  As another method, Patent Document 2 describes a method using a hydrophilic treatment. In this bonding method, a hydrophilized oxide film is formed using an ECR sputtering method in which the target is silicon and the plasma gases are oxygen and argon. Then, the semiconductor substrates are joined by pressing the hydrophilized oxide films together.

JP-A-10-92702 JP 2010-232568 A

ECOC 2009,20-24September, 2009, Viena, Austria, Paper 1.7.1

  Patent Documents 1 and 2 and Non-Patent Document 1 disclose a technique for bonding semiconductor substrates, but do not disclose a technique related to an alignment mark used in a manufacturing process after bonding.

  When another semiconductor substrate is bonded to the surface of the semiconductor substrate on which the alignment mark is formed, the alignment mark is covered with another semiconductor substrate. In order to use this alignment mark in a manufacturing process after bonding, another semiconductor substrate is etched to form an opening for exposing the alignment mark. However, in forming the opening, it is difficult to stop etching at the interface between the semiconductor substrate on which the alignment mark is formed and the semiconductor substrate covering the alignment mark. Therefore, since the alignment mark is etched when the alignment mark is exposed, the alignment mark may not be used in the subsequent manufacturing process.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a method for manufacturing a semiconductor device having an alignment mark applicable to a manufacturing process after bonding.

  The method for manufacturing a semiconductor device according to the present invention includes a first element partition region for forming an element structure of an optical device, a first region provided around the first element partition region, and the first element partition region. A second region provided in the periphery of the substrate, a step of preparing a first substrate containing silicon, a step of forming a first alignment mark in the first region, and forming a wafer alignment mark in the second region And a second element partition region for growing an epitaxial layer of a group III-V compound semiconductor on a wafer containing a group III-V compound semiconductor to form an element structure of an optical device, the second element partition Forming a second substrate having a third region provided in the periphery of the region and a fourth region provided in the periphery of the second element partition region; and a second alignment layer on the epitaxial layer in the third region. Forming a third mark, etching the fourth region of the second substrate to form a third substrate, and positioning the second element partition region on the first element partition region. Using the first alignment mark and the second alignment mark, the third region is located on one region and the fourth region is located on the second region. Positioning the third substrate thereon, positioning the third substrate on the first substrate, and then bonding the third substrate to the first substrate to form a fourth substrate; And removing the fourth region from the fourth substrate to form a fifth substrate.

  In this manufacturing method, the first and second alignment marks are used to position the third substrate on the first substrate. According to the use of the first and second alignment marks, the second element partition region is positioned on the first element partition region, the third region is positioned on the first region, and the second region is positioned on the second region. The third substrate can be positioned on the first substrate so that the four regions are located. After positioning the third substrate on the first substrate, the third substrate is bonded to the first substrate to form a fourth substrate. In the fourth substrate, since the fourth region is recessed by the etching that has already been performed, a step is formed between the third region and the fourth region. Due to this step, a gap is provided between the second region and the fourth region, so that the second region is not bonded to the fourth region. After forming the fourth substrate, the fourth region is removed from the fourth substrate to expose the wafer alignment mark. According to these steps, the wafer alignment mark is not damaged when the fifth substrate with the wafer alignment mark exposed is formed. Therefore, a semiconductor device having a wafer alignment mark that can be used in a subsequent manufacturing process can be manufactured.

  In the step of forming the third substrate of the manufacturing method according to the present invention, a recess for exposing the wafer is formed in the fourth region by etching the epitaxial layer in the fourth region, and the fifth region is formed. In the step of forming a substrate, the wafer is etched to remove the wafer from the fourth substrate. A recess for exposing the wafer is already formed in the fourth region of the second substrate by etching the epitaxial layer. Accordingly, since the epitaxial layer does not exist in the fourth region and only the wafer remains, the second region covered with the wafer is exposed by removing the wafer from the fourth substrate. As a result, the wafer alignment mark in the second region can be exposed.

  Further, in the step of forming the second substrate of the manufacturing method according to the present invention, a first silicon oxide layer is formed on the epitaxial layer, and in the step of forming the third substrate, the step in the fourth region is performed. In the step of etching the first silicon oxide layer to form a second silicon oxide layer having an opening in the fourth region and forming the fifth substrate, the fourth region is formed after the wafer is removed by etching. The epitaxial layer is removed. According to these steps, the second silicon oxide layer is disposed between the first element partition region and the second element partition region in the fifth substrate. Accordingly, since the second element partition region is not directly bonded to the first element partition region, it is possible to protect the first element partition region and the second element partition region from damage caused during the bonding.

  In the step of preparing the first substrate of the manufacturing method according to the present invention, the first element partition region is etched to form a first mesa structure for the first optical waveguide. According to this process, it is possible to manufacture a semiconductor device having a structure in which an epitaxial layer is bonded to a first substrate having a first mesa structure.

  Further, the manufacturing method according to the present invention includes a step of forming the first mesa structure for the first optical waveguide by etching the first region after the step of forming the wafer alignment mark. The step of forming the first mesa structure includes a step of positioning a first photomask with respect to the first substrate with reference to the wafer alignment mark, and a first step for forming the first mesa structure. Forming a mask on the first region using the first photomask; and etching the first region using the first mask to form the first mesa structure; ,including. A semiconductor device in which an epitaxial layer is bonded to the first substrate on which the first mesa structure is formed can be manufactured.

  Further, the second mesa structure of the manufacturing method according to the present invention includes a portion formed on the first mesa structure so as to extend in the extending direction of the first mesa structure. According to this configuration, a semiconductor device including an optical waveguide including a first mesa structure having a refractive index of silicon and a second mesa structure having a refractive index of a III-V compound semiconductor can be manufactured.

  Further, the step of forming the second mesa structure of the manufacturing method according to the present invention includes a step of positioning a photomask with respect to the fifth substrate with reference to the wafer alignment mark, and forming the second mesa structure. Forming a mask for forming the second mesa structure on the epitaxial layer using the photomask, etching the epitaxial layer in the second element partition region using the mask, including. According to this step, the photomask is positioned with respect to the fourth substrate using the wafer alignment mark. According to the positioning using the wafer alignment mark, the photomask is accurately positioned on the first mesa structure, so that the second mesa structure can be formed on the first mesa structure.

  The first substrate of the manufacturing method according to the present invention is an SOI substrate. According to this configuration, a semiconductor device having a structure in which an epitaxial layer of a III-V group compound semiconductor is disposed on an SOI substrate can be manufactured.

  According to the present invention, a method for manufacturing a semiconductor device having an alignment mark applicable to a subsequent manufacturing process is provided.

FIG. 1 is a diagram showing main steps of the manufacturing method according to the first embodiment. 2A is a plan view of the SOI substrate, and FIG. 2B is a diagram showing a cross section taken along line II-II of the SOI substrate. 3 (a) is a view showing a cross section of the SOI substrate, FIG. 3 (b) is a plan view of the SOI substrate, and FIG. 3 (c) is IV-IV of the portion (b). It is a figure which shows the cross section of the SOI substrate along a line. FIGS. 4A to 4D are cross-sectional views taken along line III-III in FIG. 2A. 5 (a) is a view showing a cross section of the SOI substrate, FIG. 5 (b) is a plan view of the SOI substrate, and FIG. 5 (c) is IV-IV of the (b) portion. It is a figure which shows the cross section of the SOI substrate along a line. 6A is a plan view of the second substrate, and FIG. 6B is a cross-sectional view of the second substrate along the line V-V in FIG. 6A. 7 (a) is a diagram showing a cross section of the second substrate, FIG. 7 (b) is a plan view of the second substrate, and FIG. 7 (c) is VI of (b). It is a figure which shows the cross section of the 2nd board | substrate along the -VI line. 8 (a) is a diagram showing a cross section of the third substrate, FIG. 8 (b) is a plan view of the third substrate, and FIG. 8 (c) is a VII of FIG. 8 (b). It is a figure which shows the cross section of the 3rd board | substrate along the -VII line. 9 (a) and 9 (b) are diagrams showing one process of the method for manufacturing a semiconductor device. FIGS. 10A and 10B are cross-sectional views of the SOI substrate and the third substrate, and FIG. 10C is a cross-sectional view of the substrate product. 11A is a view showing a cross section of the fourth substrate from which the wafer is removed, FIG. 11B is a plan view of the fifth substrate, and FIG. It is a figure which shows the cross section of the 5th board | substrate along the XX line of the () part. 12A is a view showing a cross section of the fifth substrate, and FIGS. 12B and 12C are views showing a part of the cross section of the fifth substrate. Parts (a) to (c) of FIG. 13 are cross-sectional views of one element formed on the fifth substrate. 14 (a) is a plan view of one element formed on the fifth substrate. FIGS. 14 (b) and 14 (c) are XIII-XIII lines in FIG. 14 (a). It is a figure which shows the cross section along line. FIGS. 15A and 15B are cross-sectional views of one element formed on the fifth substrate. FIG. 16A is a plan view of one element formed on the fifth substrate, and FIG. 16B is a cross-sectional view taken along line XV-XV in FIG. FIG. 17 (a) to 17 (c) are cross-sectional views of one element formed on the fifth substrate. 18A is a plan view of one element formed on the fifth substrate, and FIG. 18B is a sectional view taken along line XVII-XVII of FIG. 18A. FIG. 18C is a diagram showing a cross section of one element formed on the fifth substrate. FIG. 19 is a diagram showing main steps of the manufacturing method of the second embodiment. 20A is a diagram showing a cross section of the third substrate, FIG. 20B is a plan view showing the third substrate, and FIG. 20C is a diagram (b) of FIG. It is a figure which shows the cross section along the XIX-XIX line | wire in a () part. 21 (a) and 21 (b) are cross-sectional views of the SOI substrate and the third substrate, and FIG. 21 (c) is a cross-sectional view of the substrate product from which the wafer is removed. 22A is a plan view of the fifth substrate, and FIG. 22B is a diagram showing a cross section taken along line XXI-XXI of FIG. 22A.

  Hereinafter, an embodiment of a method for manufacturing a semiconductor device will be described in detail with reference to FIGS. In the description of the drawings, the same elements are denoted by the same reference numerals. The semiconductor device is a substrate in which an epitaxial layer of a III-V compound semiconductor is bonded to an SOI substrate. Further, in this semiconductor device, a waveguide constituting the phase control unit of the Mach-Zehnder modulator is formed. The phase control unit controls the phase of light propagating through the waveguide by changing the refractive index of the waveguide.

(First embodiment)
A method for manufacturing a semiconductor device according to the first embodiment will be described. FIG. 1 is a diagram illustrating main steps of the manufacturing method according to the first embodiment. Part (a) of FIG. 2 is a plan view of the SOI substrate. Part (b) of FIG. 2 is a view showing a cross section taken along line II-II of the SOI substrate.

  Step S1 for preparing an SOI (Silicon On Insulator) substrate 1 as a first substrate is performed (see FIG. 1). As shown in FIG. 2A, the SOI substrate 1 is a disc-shaped substrate, and an orientation flat (OF) 7 is provided on a part of the edge E1. The SOI substrate 1 has a first element partition region C1, a first region A1, and a second region A2.

  The first element partition region C1 is a region including a partition 5 in which element structures of a plurality of optical devices arranged one-dimensionally or two-dimensionally are formed. The element structure formed in the first element partition region C1 includes, for example, a Mach-Zehnder modulator waveguide structure. As shown in FIG. 2A, the first element partition region C1 has a rectangular outer shape in plan view, but is not limited to this shape. In the first element partition region C1, the second element partition region of the third substrate is attached to the whole or a part of the first element partition region C1.

  The first area A1 is an area where the first alignment mark is formed. The second region A2 is a region where a wafer alignment mark is formed. The first region A1 and the second region A2 are provided in a region surrounding the first element partition region C1. The first region A1 and the second region A2 may include the edge E1 of the SOI substrate 1.

  The first region A1 and the second region A2 are provided around the first element partition region C1. More specifically, the first region A1 and the second region A2 can be provided between the first element partition region C1 and the edge E1 of the SOI substrate 1. The first region A1 is provided on both sides of the first element partition region C1 so as to sandwich the first element partition region C1. The second region A2 is provided on both sides of the first element partition region C1 so as to sandwich the first element partition region C1. The first region A1 and the second region A2 are alternately arranged along one side C1a of the first element partition region C1 facing the first region A1 and the second region A2.

As shown in part (b) of FIG. 2, the SOI substrate 1 has a structure in which a silicon substrate 2, a box layer 3, and a device layer 4 are laminated. The box layer 3 is an insulating layer made of silicon oxide (SiO ₂ ) disposed between the silicon substrate 2 and the device layer 4. The thickness of the box layer 3 is, for example, 2.0 μm. The device layer 4 is made of single crystal silicon (Si). The thickness of the device layer 4 is 0.7 μm, for example.

  In the flowchart of FIG. 1, the steps S1, S2, and S3 are separate steps, but the steps S1 to S3 are performed at the same time or after the wafer alignment mark MW is manufactured, The 1-mesa structure 8 and the first alignment mark M1 may be formed.

  Step S1a for forming a wafer alignment mark on the device layer 4 in the second region A2 is performed. 3 (a) is a view showing a cross section of the SOI substrate, FIG. 3 (b) is a plan view of the SOI substrate, and FIG. 3 (c) is IV-IV of the portion (b). It is a figure which shows the cross section of the SOI substrate along a line. The wafer alignment mark MW is for positioning the photomask with respect to the SOI substrate 1 in a later manufacturing process.

  An insulating layer is formed in the device layer. The insulating layer is made of silicon nitride (SiN) and is formed by a chemical vapor deposition method (CVD method). A resist mask patterned into a predetermined shape is formed on the insulating layer. The resist mask is made of a resist material and is formed by a spin coating method and a photolithography method. A pattern is formed on the resist mask by photolithography. The resist mask is for forming a wafer alignment mark.

The insulating layer is etched using a resist mask. The insulating layer is etched by a reactive ion etching method (RIE method) using CF ₄ gas as an etching gas. By this etching, the pattern of the resist mask is transferred to the insulating layer (see part (a) of FIG. 3). After the insulating layer is etched, the resist mask is removed. The resist mask is removed by an ashing process using O ₂ gas, a dissolution process using an organic solvent, or the like (see part (b) of FIG. 3 and part (c) of FIG. 3).

  The device layer 4 is etched using the patterned insulating layer. The device layer 4 is etched by a dry etching method such as an RIE method. After the etching is completed, the insulating layer is removed with buffered hydrofluoric acid. Through the above-described step S1a, the wafer alignment mark MW is formed on the device layer.

  Step S2 of forming the first mesa structure for the first optical waveguide by etching the first element partition region C1 is performed (see FIG. 1). FIGS. 4A to 4D are cross-sectional views taken along line III-III in FIG. 2A.

  As shown in part (a) of FIG. 4, an insulating layer 11 is formed on the device layer 4. The insulating layer 11 is made of silicon nitride (SiN) and is formed by a chemical vapor deposition method (CVD method). A resist mask 12 patterned into a predetermined shape is formed on the insulating layer 11. The resist mask 12 is made of a resist material and is formed by a spin coating method and a photolithography method. The position of the waveguide is determined with reference to the wafer alignment mark MW. A pattern 13 is formed on the resist mask 12 by photolithography. The resist mask 12 is for forming a first mesa structure.

As shown in part (b) of FIG. 4, the insulating layer 11 is etched using the resist mask 12. The insulating layer 11 is etched by a reactive ion etching method (RIE method) using CF ₄ gas as an etching gas. By this etching, the pattern 13 of the resist mask 12 is transferred to the insulating layer 11. After the insulating layer 11 is etched, the resist mask 12 is removed. The resist mask 12 is removed by ashing processing using O ₂ gas, dissolution processing using an organic solvent, or the like.

  As shown in part (c) of FIG. 4, the device layer 4 is etched using the patterned insulating layer 11. The device layer 4 is etched by a dry etching method such as an RIE method.

  As shown in FIG. 4D, after the etching is completed, the insulating layer 11 is removed with buffered hydrofluoric acid. Through the above step S2, the first mesa structure 8 and the groove 9 are formed in the device layer 4. The section 5 (see the part (a) in FIG. 2) where the first mesa structure 8 is formed has a terrace 10.

  Step S3 of forming a first alignment mark on the device layer 4 in the first region A1 is performed. (See FIG. 1). The first alignment mark M1 is for positioning the third substrate on the SOI substrate 1.

  5 (a) is a view showing a cross section of the SOI substrate, FIG. 5 (b) is a plan view of the SOI substrate, and FIG. 5 (c) is IV-IV of the (b) portion. It is a figure which shows the cross section of the SOI substrate along a line. After an insulating layer is formed on the device layer 4 using the CVD method, a resist mask having a predetermined pattern is formed on the insulating layer. The position of the first alignment mark M1 is positioned with reference to the wafer alignment mark MW. Next, the insulating layer is etched using the RIE method. By this etching, the insulating layer mask 14 to which the resist mask pattern is transferred is formed. The pattern transferred to the insulating layer mask 14 is for forming the first alignment mark M1. The pattern has an opening 14a for the first alignment mark M1 in the first region A1. After the insulating layer mask 14 is formed, the resist mask is removed (see part (a) of FIG. 5).

  The device layer 4 is etched using the patterned insulating layer 14. The device layer 14 is etched by a dry etching method such as an RIE method. After the etching is completed, the insulating layer 14 is removed with buffered hydrofluoric acid. Through the above step S3, the wafer alignment mark MW is formed on the device layer.

  In addition, when the etching depth of process S1a, S2, and S3 may be the same, you may produce all simultaneously. Steps S2 and S3 are positioned and produced with reference to the wafer alignment mark MW produced in step S1a. The order of steps S2 and S3 may be reversed.

  Step S4 for forming the second substrate is performed (see FIG. 1). 6A is a plan view of the second substrate, and FIG. 6B is a cross-sectional view of the second substrate along the line V-V in FIG. 6A. First, step S <b> 4 a for growing the epitaxial layer 23 on the wafer 22 is performed. The wafer 22 is made of a III-V group compound semiconductor such as InP. The epitaxial layer 23 includes a plurality of semiconductor layers made of III-V compound semiconductors. The epitaxial layer 23 is grown using metal organic chemical vapor deposition (MOCVD).

  The epitaxial layer 23 will be described in detail. The epitaxial layer 23 has a structure in which a buffer layer 23a grown on the wafer 22, an etch stop layer 23b, a lower cladding layer 23c, a quantum well layer 23d, and an upper cladding layer 23e are stacked in this order. Yes. The buffer layer 23a is a layer made of InP and having a thickness of 500 nm. The etch stop layer 23b is a layer made of InGaAs and having a thickness of 250 nm. The etch stop layer 23b functions as an etch stop layer when removing the wafer 22 in step S8 described later. The lower cladding layer 23c is a layer made of InP and having a thickness of 1250 nm. The quantum well layer 23d is a layer in which 25 layers of a first layer made of AlGaInAs and a second layer made of AlInAs and 5 nm in thickness are stacked. The upper cladding layer 23e is a layer made of InP and having a thickness of 360 nm.

  The second substrate 20 has a second element partition region C2, a third region A3, and a fourth region A4. The second element partition region C2 is a region where a plurality of element structures of the optical device are formed. The third region A3 is a region where the second alignment mark is formed. The fourth region A4 is a region where a recess is formed. The fourth region A4 includes a portion to be removed in a later step in order to expose the wafer alignment mark MW provided in the second region A2 of the SOI substrate 1.

  The third region A3 and the fourth region A4 are provided in a region surrounding the second element partition region C2. The third region A3 and the fourth region A4 may include the edge E2 of the second substrate 20. The third region A3 and the fourth region A4 are provided around the second element partition region C2. More specifically, the third region A3 and the fourth region A4 are provided between the second element partition region C2 and the edge E2 of the second substrate 20. The third region A3 can be provided on both sides of the second element partition region C2 so as to sandwich the second element partition region C2. The fourth region A4 is provided on both sides of the second element partition region C2 so as to sandwich the second element partition region C2. The third region A3 and the fourth region A4 are alternately arranged along one side C2a of the second element partition region C2 facing the third region A3 and the fourth region A4.

  Next, step S5 of forming a second alignment mark on the epitaxial layer 23 in the third region A3 is performed (see FIG. 1). The second alignment mark is for positioning the third substrate on the SOI substrate 1. (A) part of FIG. 7 is a figure which shows the cross section of a 2nd board | substrate. Moreover, the (b) part of FIG. 7 is a top view of a 2nd board | substrate, and the (c) part of FIG. 7 is a figure which shows the cross section of the 2nd board | substrate along the VI-VI line of the (b) part. is there.

As shown in FIG. 7A, an insulating layer made of SiN is formed on the epitaxial layer 23 by the CVD method. Next, a resist mask having a predetermined pattern is formed on the insulating layer by spin coating and photolithography. Subsequently, the insulating layer mask 24 having a predetermined pattern is formed by etching the insulating layer by RIE using CF ₄ gas. After the insulating layer mask 24 is formed, the resist mask is removed by ashing using O ₂ gas or dissolution treatment using an organic solvent. The insulating layer mask 24 is for forming the second alignment mark M2. The insulating layer mask 24 has an opening 24a for the second alignment mark M2 on the third region A3.

  The epitaxial layer 23 is etched by, for example, about 200 nm using the insulating layer mask 24, thereby forming the second alignment mark M2 in the third region A3. As shown in FIGS. 7B and 7C, after the etching is completed, the insulating layer mask 24 is removed using buffered hydrofluoric acid.

  Step S6 for forming the third substrate is performed (see FIG. 1). Step S6 includes a step S6a for etching the fourth region A4 and a step S6b for forming the silicon oxide layer 33 after the step S6a. FIG. 8A shows a cross section of the third substrate. Part (b) of FIG. 8 is a plan view of the third substrate. (C) part of FIG. 8 is a figure which shows the cross section of the 3rd board | substrate along the VII-VII line of the (b) part.

Step S6a for etching the fourth region A4 to form a recess is performed. As shown in FIG. 8A, an insulating layer made of SiN is formed on the epitaxial layer 23 by the CVD method. Next, a resist mask having a predetermined pattern is formed on the insulating layer by spin coating and photolithography. Subsequently, the insulating layer mask 31 having a predetermined pattern is formed by etching the insulating layer by RIE using CF ₄ gas. After the insulating layer mask 31 is formed, the resist mask is removed by ashing using O ₂ gas or dissolution treatment using an organic solvent. The insulating layer mask 31 is for forming the recess 32 in the fourth region A4.

  Then, by etching the epitaxial layer 23 using the insulating layer mask 31, the recess 32 is formed in the fourth region A4. Due to the recess 32, a step is formed between the third region A3 and the fourth region A4. In this etching, the epitaxial layer 23 is etched until the wafer 22 is exposed from the recess 32 in the fourth region A4. For this reason, the recess 32 is etched up to the wafer substrate. Therefore, the depth of the concave portion 32 only needs to be deeper than the thickness of the epitaxial layer 23, and is, for example, 2.8 μm to 5.0 μm.

  The fourth region A4 to be removed in a later step is etched in advance to form the recess 32 in the fourth region A4, whereby the fourth region A4 can be easily removed in the later step. According to the recess 32, the epitaxial layer 23 in the fourth region A4 is removed in advance, so that only the wafer 22 and the silicon oxide layer 33a (see part (a) in FIG. 11) on the fourth region A4 are removed. Thus, the wafer alignment mark MW can be easily exposed.

  Then, after the etching is completed, the insulating layer mask 31 is removed using buffered hydrofluoric acid.

Step S6b for forming the silicon oxide layer 33 is performed. The silicon oxide layer 33 is formed by ECR sputtering. The silicon oxide layer 33 is formed on the surface 23p of the epitaxial layer 23, the bottom surface 32a and the side surface 32b of the recess 32. Note that the bottom surface 32 a of the recess 32 is included in the surface 22 a of the wafer 22. Here, the following parameters were used for forming the silicon oxide layer 33.
The thickness of the silicon oxide layer 33: 100 nm.
Ar flow rate: 20 sccm.
O ₂ flow rate: 8 sccm.
Microwave power: 500W.
RF power: 500W.

  After the silicon oxide layer 33 is formed, the third substrate 30 is annealed. The annealing conditions are a processing temperature of 350 ° C. and a processing time of 1 hour. By this annealing treatment, the gas contained in the silicon oxide layer 33 is released.

  Through the above steps S5 and S6, the third substrate 30 having the second alignment mark M2 and the recess 32 is formed.

  Here, in order to bond the substrates, it is desirable that the microroughness (Ra) of the surfaces of the substrates to be bonded is about 1 nm or less. This is because when the microroughness is increased, the effective contact area between the substrates is reduced, and the bonding strength cannot be maintained. Examples of a method for forming the silicon oxide layer 33 on the substrate include a CVD method and a sputtering method. However, depending on the film formation method, the microroughness of the surface of the silicon oxide layer 33 after film formation is large and may not be suitable for direct bonding.

  As a result of intensive studies by the inventors, the surface of the silicon oxide layer 33 formed by thermal CVD at normal pressure has a large microroughness. Therefore, it was found that the method is not suitable for the method of forming the silicon oxide layer 33 used for direct bonding. On the other hand, the surface of the silicon oxide layer 33 formed by ECR sputtering has a small microroughness. Therefore, it has been found that the ECR sputtering method is suitable for the method of forming the silicon oxide layer 33 used for direct bonding.

  When the substrate on which the silicon oxide layer 33 is formed is silicon, the silicon oxide layer 33 may be formed using a surface thermal oxidation method. When the substrate on which the silicon oxide layer 33 is to be formed is made of GaAs or InP, the silicon oxide layer 33 may be formed by sputtering or the like.

  Step S7 for hydrophilizing the surface of the SOI substrate 1 and the surface of the third substrate 30 is performed (see FIG. 1). Step S7 includes a step of activating the surface of the SOI substrate 1 and the surface of the third substrate 30, and a step of hydrophilizing the surface of the SOI substrate 1 and the surface of the third substrate 30. Part (a) of FIG. 9 is a diagram illustrating a process of activating the surface of the SOI substrate and the surface of the third substrate. Part (b) of FIG. 9 is a diagram showing a process of hydrophilizing the surface of the SOI substrate and the surface of the third substrate.

As shown in part (a) of FIG. 9, the SOI substrate 1 and the third substrate 30 are disposed in the plasma chamber 34. After disposing the SOI substrate 1 and the third substrate 30, the inside of the plasma chamber 34 is decompressed, and at least one of N ₂ , O _2, or Ar gas is introduced into the plasma chamber 34. Then, the gas is turned into plasma by applying a predetermined high-frequency power from the electrode 34a to the gas. By exposing to the plasma, the surface of the SOI substrate 1 and the surface of the third substrate 30 are activated. The following parameters were used for activation of the surface of the SOI substrate 1 and the surface of the third substrate 30.
Upper electrode high frequency power 200W.
Lower electrode high frequency power 100W.
Gas species N _2.
Gas flow rate 20 sccm.
Gas pressure 0.3 mbar.
Time 30 seconds.

  As shown in part (b) of FIG. 9, the activated SOI substrate 1 and the third substrate 30 are converted into a liquid 36a containing moisture (for example, pure water) or a gas 36b (for example, air having a humidity of about the room atmosphere). Expose to. By this treatment, OH groups are adsorbed on the surface of the SOI substrate 1 and the surface of the third substrate 30, and the respective surfaces become hydrophilic.

  Step S8 for positioning the third substrate 30 on the SOI substrate 1 is performed (see FIG. 1). FIG. 10A shows a cross section of the SOI substrate and the third substrate in step S8.

  As shown in FIG. 10A, positioning is performed using the first alignment mark M1 of the SOI substrate 1 and the second alignment mark M2 of the third substrate 30. At this time, the third substrate 30 is disposed on the SOI substrate 1 so that the second alignment mark M2 intersects the virtual line K1. The imaginary line K1 is a line that passes through the first alignment mark M1 and extends in a direction orthogonal to the surface 1a of the SOI substrate 1. By step S8, the second element partition region C2 is positioned on the first element partition region C1, the third region A3 is positioned on the first region A1, and the fourth region A4 is positioned on the second region A2. The third substrate 30 is positioned with respect to the SOI substrate 1 so as to be positioned. According to step S8, the fourth region A4 is positioned on the second region A2 where the wafer alignment mark MW is formed, and the fourth region A4 is prevented from being bonded to the second region A2. Therefore, the wafer alignment mark MW can be easily exposed in a later process.

  Step S9 for forming the fourth substrate 40 is performed (see FIG. 1). Step S9 includes a step S9a for bringing the third substrate 30 into contact with the SOI substrate 1, a step S9b for pressing at least one of the SOI substrate 1 and the third substrate 30, and a step S9c for annealing the substrate product. Yes. (B) part of Drawing 10 is a figure showing the section of the SOI substrate and the 3rd substrate in process S9a and S9b. (C) part of Drawing 10 is a figure showing the section of the substrate product in process S9c.

  Step S9a is performed. As shown in part (b) of FIG. 10, the third substrate 30 is brought into contact with the SOI substrate 1. At this time, the device layer 4 comes into contact with the silicon oxide layer 33 of the third substrate 30. More specifically, the first region A1 of the SOI substrate 1 is in contact with the third region A3 of the third substrate 30. On the other hand, the epitaxial layer 23 in the fourth region A4 of the third substrate 30 has already been etched, and a recess 32 is formed in the fourth region A4 of the third substrate 30. For this reason, since a gap is formed between the second region A2 of the SOI substrate 1 and the fourth region A4 of the third substrate 30, the device layer 4 in the second region A2 is oxidized in the fourth region A4. It does not contact the silicon layer 33.

  Step S9b for pressing at least one of the SOI substrate 1 and the third substrate 30 is performed (see FIG. 1). First, the SOI substrate 1 is placed on the support base 38. The third substrate 30 is pressed against the SOI substrate 1 using the pressing tool 39. For the pressing tool 39, for example, tweezers can be used. When pressing the third substrate 30, the back surface 22 b of the wafer 22 of the third substrate 30 is pressed. The load to press is 20-500g, and is about 100g as an example. By this pressing, the first region A1 of the SOI substrate 1 and the third region A3 of the third substrate 30 are joined (spontaneous joining) by van der Waals force. In addition to the region where the first region A1 of the SOI substrate 1 and the third region A3 of the third substrate 30 are joined, all of the contact between the device layer 4 of the SOI substrate 1 and the silicon oxide layer 33 of the third substrate 30 are made. A junction is formed in this region. By this step S9b, a substrate product 37 in which the third substrate 30 is temporarily bonded to the SOI substrate 1 is formed.

  Here, in the substrate product 37, the silicon oxide layer 33 in the second element partition region C2 is bonded to the terrace 10 in the first element partition region C1. Further, in the substrate product 37, the silicon oxide layer 33 in the second element partition region C2 is bonded to the first mesa structure 8 in the first element partition region C1. In the first element partition region C1, the groove 9 is not in contact with the silicon oxide layer 33 in the second element partition region C2, and therefore is not joined to the silicon oxide layer 33 (see the part (b) in FIG. 12).

  According to step S9b, the third substrate 30 can be bonded to the SOI substrate 1 without performing the pressure treatment on the entire region where the SOI substrate 1 and the third substrate 30 are bonded. Therefore, damage to the SOI substrate 1 and the third substrate 30 due to pressing can be suppressed. Moreover, damage to the first mesa structure 8 of the SOI substrate 1 due to pressing can be suppressed.

  Step S9c is performed (see FIG. 1). This annealing process is performed to increase the bonding strength of the silicon oxide layer 33 to the device layer 4.

As shown in part (c) of FIG. 10, the substrate product 37 is placed in a heating furnace 41, and the substrate product 37 is heated at a temperature of about 200 ° C. to 500 ° C. for about 2 hours. By this heating, H ₂ O is desorbed from the junction interface J between the device layer 4 and the silicon oxide layer 33. By desorption of H ₂ O, the bonding state of the bonding interface J changes from bonding by van der Waals force due to OH groups to cross-linking bonding by “—O—”, thereby increasing bonding strength. By this step S9c, the fourth substrate 40 in which the third substrate 30 is bonded to the SOI substrate 1 is formed.

  The bonding interface J includes a bonding interface between the device layer 4 in the first region A and the silicon oxide layer 33 in the third region A3. Further, the bonding interface J includes a bonding interface between the terrace 10 in the first element partition region C1 and the silicon oxide layer 33 in the second element partition region C2. Further, the junction interface J includes a junction interface between the first mesa structure 8 in the first element partition region C1 and the silicon oxide layer 33 in the second element partition region C2.

By the way, in the method of bonding the substrate by hydrophilizing the substrate surface, H ₂ O is generated from the bonding interface J during the annealing process. This H ₂ O may generate voids at the bonding interface J. In order to suppress the generation of voids, it is necessary to previously provide a substrate with grooves and holes for discharging the generated H ₂ O. On the other hand, when the silicon oxide layer 33 is formed on the epitaxial layer 23 of the third substrate 30, H ₂ O generated by the annealing process is absorbed by the silicon oxide layer 33. Therefore, the generation of voids due to H ₂ O can be suppressed without devising the generation of voids such as grooves and holes.

  In the case where the silicon oxide layer 33 is formed on the epitaxial layer 23 of the third substrate 30, the epitaxial layer 23 can be protected from damage that occurs during bonding.

  Step S10 for forming the fifth substrate (semiconductor device) by removing the fourth region A4 from the fourth substrate 40 is performed (see FIG. 1). Step S10 includes a step S10a for removing the wafer 22 from the fourth substrate 40 and a step S10b for removing the silicon oxide layer 33 in the fourth region A4 from the fourth substrate 40. Part (a) of FIG. 11 is a view showing a cross section obtained by removing the wafer from the fourth substrate. Part (b) of FIG. 11 is a plan view of the fifth substrate. (C) part of FIG. 11 is a figure which shows the cross section of the 5th board | substrate along the XX line of the (b) part.

  As shown in part (a) of FIG. 11, step S10a is performed. The wafer 22 made of InP is removed by immersing the fourth substrate 40 in a hydrochloric acid solution. At this time, the etching is stopped by the etch stop layer 23b on the buffer layer 23a (see the part (b) in FIG. 5). Through the above step S10a, the fourth substrate 40 from which the wafer 22 has been removed is formed.

  Step S10b is performed as shown in part (b) and part (c) of FIG. The silicon oxide layer 33a in the fourth region A4 is removed by immersing the fourth substrate 40 from which the wafer 22 has been removed in BHF. From the epitaxial layer 23, the wafer alignment mark MW formed in the second region A2 is exposed. Since this wafer alignment mark MW is not collapsed, it can be used in a subsequent manufacturing process. Therefore, according to the manufacturing method of the first embodiment, the unjoined region in the fourth region A4 of the epitaxial layer 23 can be removed in a self-aligning manner, so that the manufacturing process of the semiconductor device can be simplified. Here, the unjoined region is a region where the recess 32 is formed. The fifth substrate (semiconductor device) 50 is formed by the above steps S10a and S10b.

  The trench 9 in the first element partition region C1 is not joined to the epitaxial layer 23 of the third substrate 30, but the region of the epitaxial layer 23 that is not joined to the trench 9 is not removed (FIG. 12B). Section).

  Step S11 for forming the second mesa structure is performed (see FIG. 1). Step S11 includes a step S11a for positioning the photomask, a step S11b for forming the insulating layer mask, and a step S11c for forming the second mesa structure. (A) part of Drawing 12 is a figure showing the section of the 5th substrate in process S11a. (B) part of Drawing 12 is a figure showing the section of the 5th substrate in which the insulating layer mask was formed. (C) part of Drawing 12 is a figure showing a section of a part of the 5th substrate in process S11c.

  As shown in part (a) of FIG. 12, an insulating layer is formed on the epitaxial layer 23. The insulating layer is a layer made of SiN and having a thickness of 500 nm formed by a CVD method. A resist layer is formed on this insulating layer. The resist layer is applied to the entire surface of the insulating layer by, for example, a spin coating method.

  Step S11a of placing the photomask 61 on the fifth substrate 50 on which the insulating layer and the resist layer are formed is performed. The photomask 61 has an opening pattern for forming the second mesa structure 62 (see the part (c) in FIG. 12). The photomask 61 is positioned with respect to the fifth substrate 50 with reference to the wafer alignment mark MW. By positioning the photomask 61 based on the wafer alignment mark MW, the opening pattern of the photomask 61 can be accurately arranged on the first mesa structure 8 of the SOI substrate 1.

Step S11b of forming the insulating layer mask 63 using the photomask 61 is performed. After positioning the photomask 61, an exposure process of irradiating the resist layer with light through the photomask 61 is performed. After the exposure process is completed, the photomask 61 is removed from above the fifth substrate 50. Then, the exposed resist layer is immersed in a developing solution to remove a part of the resist layer. As a result, a resist mask having an opening pattern for forming the second mesa structure 62 is formed. Subsequently, the insulating layer is etched using a resist mask. The insulating layer is etched by the RIE method using CF ₄ gas as an etching gas. After the insulating layer is etched, the resist mask is removed by an ashing process using O ₂ gas or a dissolution process using an organic solvent. Through the above-described step S11b, the insulating layer mask 63 is formed in the epitaxial layer 23 as shown in FIG.

  A second mesa structure 62 for the second optical waveguide is formed (step S11c). As shown in part (c) of FIG. 12, the epitaxial layer 23 is etched using the insulating layer mask 63. For this etching, a dry etching method such as an RIE method is used. The etching depth D is 1.76 to 2.1 μm, and is 2 μm as an example. Then, the insulating layer mask 63 is removed with buffered hydrofluoric acid. Through the above step S <b> 11, the second mesa structure 62 is formed in the epitaxial layer 23.

  Since the epitaxial layer 23 is bonded onto the SOI substrate 1, the second mesa structure 62 of the epitaxial layer 23 is disposed above the first mesa structure 8 of the SOI substrate 1. Further, the second mesa structure 62 includes a portion formed so as to extend in the extending direction of the first mesa structure 8. That is, when the first mesa structure 8 and the second mesa structure 62 are viewed in plan, the first mesa structure 8 and the second mesa structure 62 are optically bonded so as to overlap. According to such a waveguide structure, since the mesa structure 8 and the mesa structure 36 are adjacently joined to each other, light can be transited with a short coupling length.

  Step S12 for forming electrodes is performed (see FIG. 1). (A) part-(c) part of Drawing 13 is a figure showing the section of one element formed in the 5th substrate in process S12.

As shown in part (a) of FIG. 13, a protective layer 64 is formed. The protective layer 64 covers the surface 23p of the epitaxial layer 23, the upper surface 62a and the side surface 62b of the second mesa structure 62. The protective layer 64 is made of an insulating material such as SiO ₂ formed by the CVD method. Further, the thickness of the protective layer 64 is, for example, 200 nm to 400 nm.

  As shown in part (b) of FIG. 13, a resin layer 66 is formed on the protective layer 64. The resin layer 66 is made of benzocyclobutene (hereinafter referred to as BCB) and is formed by a spin coating method. The height H1 from the surface 64a of the protective layer 64 to the surface 66a of the resin layer 66 is formed to be higher than the height H2 from the surface 64a of the protective layer 64 to the upper surface 62a of the second mesa structure 62. . The thickness H3 of the resin layer 66 on the second mesa structure 62 is, for example, 1.5 μm to 3.0 μm.

  As shown in part (c) of FIG. 13, a resist mask 67 is formed on the resin layer 66. The resist mask 67 is for providing an opening 66 b in the resin layer 66 on the second mesa structure 62. The opening 66 b is for exposing the upper surface 62 a of the second mesa structure 62.

  The opening pattern of the resist mask 67 extends along the direction in which the second mesa structure 62 extends. The resist mask 67 is formed by forming a resist layer on the resin layer 66 and patterning the resist layer by photolithography. Note that a photomask for forming the resist mask 67 is positioned with reference to the wafer alignment mark MW.

The resin layer 66 is etched using the resist mask 67. In this step, the resin layer 66 is etched until the protective layer 64 on the second mesa structure 62 is exposed. In this step, an RIE method using CF ₄ gas and O ₂ gas as etching gas is used. After the etching, the resist mask 67 is removed by dissolution treatment with an organic solvent or the like to expose the surface 66a of the resin layer 66.

  Part (a) of FIG. 14 is a plan view of one element formed on the fifth substrate in step S12. 14B and 14C are cross-sectional views taken along line XIII-XIII in FIG. 14A. As shown in FIGS. 14A and 14B, a resist mask 68 is formed on the resin layer 66. The resist mask 68 is formed by forming a resist layer on the resin layer 66 and patterning the resist layer by photolithography. The resist mask 68 has an opening pattern 68 a formed on the surface 64 p of the protective layer 64. Note that a photomask for forming the resist mask 68 is positioned with reference to the wafer alignment mark MW.

The resin layer 66 is etched using the resist mask 68. In this step, the resin layer 66 is etched until the protective layer 64 is exposed. In this step, an RIE method using CF ₄ gas and O ₂ gas as etching gas is used. After the etching, the resist mask 68 is removed by dissolution treatment with an organic solvent or the like to expose the surface 66a of the resin layer 66.

  Through the above steps, as shown in part (c) of FIG. 14, an opening 66 b and an opening 66 c are formed in the resin layer 66 from the surface 66 a of the resin layer 66 to the protective layer 64.

  FIGS. 15A and 15B are cross-sectional views of one element formed on the fifth substrate in step S12. As shown in FIG. 15A, the protective layer 64 is etched using the resin layer 66 having openings 66b and 66c as a mask. By this etching, as shown in FIG. 15B, the upper surface 62a of the second mesa structure 62 is exposed from the opening 66b. Further, the surface 23p of the epitaxial layer 23 is exposed from the opening 66c.

  Part (a) of FIG. 16 is a plan view of one element formed on the fifth substrate in step S12. 16B is a diagram showing a cross section taken along line XV-XV in FIG. As shown in FIGS. 16A and 16B, a p-electrode Ep and an n-electrode En are formed. The p-electrode Ep reaches the surface 66a of the resin layer 66 from the upper surface 62a of the second mesa structure 62 through the opening 66b. The upper surface 62a of the second mesa structure 62 and the p-electrode Ep are in ohmic contact. The n-electrode En reaches the surface 66a of the resin layer 66 from the surface 23p of the epitaxial layer 23 through the opening 66c. The surface 23p of the epitaxial layer 23 and the n-electrode En are in ohmic contact.

  The p electrode Ep and the n electrode En are formed by, for example, a vacuum deposition method. The p electrode Ep and the n electrode En are made of a conductive material such as metal. Through the above step S12, the p electrode Ep and the n electrode En are formed.

  A step S13 for isolating each element formed in the epitaxial layer 23 is performed. Parts (a) to (c) of FIG. 17 are views showing a cross section of one element formed on the fifth substrate in step S13. As shown in FIG. 17A, a protective layer 69 is formed on the surface 66a of the resin layer 66, the p-electrode Ep, and the n-electrode En. The protective layer 69 is made of SiN. A resist mask 71 is formed on the protective layer 69 by spin coating and photolithography. Note that a photomask for forming the resist mask 71 is positioned using the wafer alignment mark MW as a reference.

As shown in FIG. 17B, the protective layer 69, the resin layer 66, and the protective layer 64 are etched using the resist mask 71 until the epitaxial layer 23 is exposed. For the etching of the protective layers 64 and 69, for example, an RIE method using CF ₄ gas as an etching gas can be used. For the etching of the resin layer 66, for example, an RIE method using CF ₄ gas and O ₂ gas as etching gases can be used. Thereafter, the resist mask is removed by an ashing process using O ₂ gas or a dissolution process using an organic solvent.

  As shown in FIG. 17C, the epitaxial layer 23 is dry etched. The etching depth at this time is such that the epitaxial layer 23 remains slightly. Thereafter, etching is performed with a hydrochloric acid-based etchant until the silicon oxide layer 33 is exposed. Through the above step S13, the respective elements formed in the epitaxial layer 23 are electrically isolated from each other.

  Part (a) of FIG. 18 is a plan view of one element formed on the fifth substrate. (B) part of FIG. 18 is a figure which shows the cross section along the XVII-XVII line of the (a) part of FIG. FIG. 18C is a diagram showing a cross section of one element formed on the fifth substrate.

As shown in FIGS. 18A and 18B, openings 69a and 69b are formed in the protective layer 69 on the p-electrode Ep and the n-electrode En. First, after forming a resist layer on the entire surface of the protective layer 69, a resist mask is formed by photolithography. Note that a photomask for forming a resist mask is positioned with reference to the wafer alignment mark MW. Then, for example, the protective layer 69 is etched using the resist mask by the RIE method using CF ₄ gas as an etching gas until the p electrode Ep and the n electrode En are exposed. Thereafter, the resist mask is removed by an ashing process using O ₂ gas or a dissolution process using an organic solvent.

  As shown in part (c) of FIG. 18, step S <b> 14 of polishing the back surface 2 a of the silicon substrate 2 of the SOI substrate 1 is performed. After the step S14, when the SOI substrate 1 is separated for each element, the Mach-Zehnder modulator 100 attached on the SOI substrate 1 is completed. Such a Mach-Zehnder modulator 100 is a Mach-Zehnder modulator having both a high-performance InP-based Mach-Zehnder modulator and a small waveguide having a small bending radius.

  Here, the manufacturing method of the semiconductor substrate which is a comparative example is demonstrated. In a conventional process, an SOI substrate having a wafer alignment mark and an epitaxial layer are formed without providing a step between a first element partition area for forming an element structure and a second area for forming a wafer alignment mark. Is attached to a third substrate. According to such a process, the epitaxial layer is bonded to the second region. Therefore, it is necessary to remove the epitaxial layer on the wafer alignment mark in order to expose the wafer alignment mark. In this removal process, it is required to remove the epitaxial layer so that the wafer alignment mark can be seen and to prevent the wafer alignment mark from being damaged by being etched. Therefore, it is required to stop etching at the junction interface between the epitaxial layer and the second region.

  However, it is difficult to accurately control the timing for stopping etching. Accordingly, there is a possibility that the second region where the wafer alignment mark is formed is etched and the wafer alignment mark is damaged and cannot be used in a subsequent manufacturing process. Furthermore, since the number of processes increases, it is not suitable for manufacturing an element.

  On the other hand, according to the semiconductor element manufacturing method of the first embodiment, the first and second alignment marks M 1 and M 2 are used to position the third substrate 30 on the SOI substrate 1. According to the use of the first and second alignment marks M1 and M2, the second element partition region C2 is positioned on the first element partition region C1, and the third region A3 is positioned on the first region A1, The third substrate 30 can be positioned on the SOI substrate 1 such that the fourth region A4 is positioned on the second region A2. After positioning the third substrate 30 on the SOI substrate 1, the fourth substrate 40 is formed by bonding the third substrate 30 to the SOI substrate 1. In the fourth substrate 40, since the fourth region A4 is made concave by the etching that has already been performed, a step is formed between the third region A3 and the fourth region A4. Due to this step, a gap is provided between the second region A2 and the fourth region A4 in the fourth substrate 40, and therefore the second region A2 is not bonded to the fourth region A4. Thereafter, the fourth region A4 is removed from the fourth substrate 40 to expose the wafer alignment mark MW. According to these steps 1 to S10, the wafer alignment mark MW is not damaged when the fifth substrate 50 with the wafer alignment mark MW exposed is formed. Accordingly, the fifth substrate (semiconductor device) 50 having the wafer alignment mark MW that can be used in the subsequent manufacturing processes S11 to S14 can be manufactured.

(Second Embodiment)
A method for manufacturing a semiconductor device according to the second embodiment will be described. FIG. 19 is a diagram illustrating main steps of the manufacturing method according to the second embodiment. As shown in FIG. 19, in the manufacturing method of the second embodiment, the step S6 of forming the third substrate is replaced with the step S6c of forming a silicon oxide layer instead of the steps S6a and S6b, and the silicon oxide layer. It differs from the manufacturing method of 1st Embodiment by the point including process S6d to etch. The manufacturing method of the second embodiment is different from the manufacturing method of the first embodiment in that the step S10 for forming the fifth substrate includes a step S10c for removing the epitaxial layer instead of the step S10b. To do. Hereinafter, step S6c, step S6d, step S10c, and the like will be described in detail.

  In the flowchart of FIG. 19, Step S1, Step S2, and Step S3 are separate steps, but Steps S1 to S3 are performed simultaneously or after the wafer alignment mark MW is fabricated, The 1 mesa structure 8 and the first alignment mark may be formed as M1.

Step S6c for forming a silicon oxide layer is performed. (A) part of Drawing 20 is a figure showing the section of the 3rd substrate in process S6c. As shown in part (a) of FIG. 20, in step S <b> 6 c, a first silicon oxide layer 82 is formed on the epitaxial layer 23. The first silicon oxide layer 82 is formed by ECR sputtering. The following parameters were used for forming the first silicon oxide layer 82.
The thickness of the silicon oxide layer 82: 100 nm.
Ar flow rate: 20 sccm.
O ₂ flow rate: 8 sccm.
Microwave power: 500W.
RF power: 500W.

  After forming the first silicon oxide layer 82, the third substrate 81 is annealed. The annealing conditions are a processing temperature of 350 ° C. and a processing time of 1 hour. By this annealing treatment, the gas contained in the first silicon oxide layer 82 is released.

  Step S6d for etching the first silicon oxide layer 82 is performed. 20B is a plan view showing the third substrate in step S6d, and FIG. 20C is a cross-sectional view taken along line XIX-XIX in FIG. 20B. It is.

A resist mask having a predetermined opening pattern is formed on the first silicon oxide layer 82. This resist mask is for etching the fourth region A4. Therefore, at least the fourth region A4 is exposed from the opening pattern. After forming the resist mask, the first silicon oxide layer 82 is etched using BHF until the epitaxial layer 23 is exposed. After the etching, the resist mask is removed by ashing using O ₂ gas or dissolution treatment using an organic solvent. Through the steps S6c and S6d described above, the second silicon oxide layer 83 having a predetermined shape is formed as shown in FIGS. 20B and 20C.

  Here, the second silicon oxide layer 83 will be further described. The second silicon oxide layer 83 includes a base portion 83a formed in the second element partition region C2 and a protruding portion 83b formed in the third region A3. The base 83a has a rectangular shape in plan view, and covers the entire surface of the second element partition region C2. The protrusion 83b extends from the edge of the base 83a toward the edge E3 of the third substrate 81 on the third region A3. The protrusion 83b is formed so as to cover the second alignment mark M2. The second silicon oxide layer 83 is preferably not formed so as to surround the fourth region A4. According to such a second silicon oxide layer 83, the epitaxial layer 23 can be easily removed.

  As shown in part (c) of FIG. 20, the second silicon oxide layer 83 is not formed on the fourth region A4, and the surface 23p of the epitaxial layer 23 is exposed. Therefore, in the third substrate 81, the surface 23p of the epitaxial layer 23 in the fourth region A4 is recessed by the thickness of the protrusion 83b with respect to the surface of the protrusion 83b in the third region A3. According to the second silicon oxide layer 83, since the step is provided between the third region A3 and the fourth region A4, the fourth region A4 is not joined to the second region A2 of the SOI substrate 1. This step has the same thickness as the silicon oxide layer and is 10 nm to 500 nm. For example, 100 nm. Further, the second silicon oxide layer 83 is not bonded onto the wafer alignment mark MW formed in the second region A2 of the SOI substrate 1.

  Next, as shown in part (a) of FIG. 21, when the third substrate 81 is positioned on the SOI substrate 1 in step S8, the first alignment mark M1 and the second alignment mark M2 are used. By using the first alignment mark M1 and the second alignment mark M2, the protruding portion 83b formed in the third region A3 can be disposed on the first region A1. Accordingly, it is possible to prevent the second silicon oxide layer 83 from being bonded to the second region A2 where the wafer alignment mark MW is formed.

  As shown in part (b) of FIG. 21, after performing the positioning step S8, the third region A3 of the third substrate 81 is brought into contact with the first region A1 of the SOI substrate 1, and the back surface 81b of the third substrate 81 is contacted. Is pressed by the pressing tool 39 (see part (b) of FIG. 10). By this pressing, a substrate product in which the third substrate 81 is temporarily bonded to the SOI substrate 1 is formed. Then, the fourth substrate 84 is formed by annealing the substrate product. The annealing conditions are a heating temperature of 200 ° C. to 500 ° C. and a heating time of 2 hours.

  The bonding interface J in the fourth substrate 84 includes an interface in which the device layer 4 in the first region A1 is bonded to the protrusion 83b in the third region A3. Further, the bonding interface J includes an interface in which the base portion 82a of the second element partition region C2 is bonded to the device layer 4 of the first element partition region C1. More specifically, it includes an interface in which the base portion 82a is bonded to the terrace 10 of the first element partition region C1, and an interface in which the base portion 83a is bonded to the first mesa structure 8.

  Step S10a for etching the wafer 22 is performed. (C) part of FIG. 21 is a figure which shows the cross section of the substrate product which removed the wafer. The wafer 22 made of InP is removed by immersing the fourth substrate 84 in a hydrochloric acid solution. As shown in part (c) of FIG. 21, when the wafer 22 is removed from the fourth substrate 84, the second silicon oxide layer 83 and the epitaxial layer 23 remain on the SOI substrate 1.

  Step S10c for removing the epitaxial layer 23 is performed. Part (a) of FIG. 22 is a plan view of the substrate product obtained by removing the epitaxial layer that is not bonded to the SOI substrate from the fourth substrate. (B) part of Drawing 22 is a figure showing the section which followed the XXI-XXI line of the (a) part of Drawing 22.

  In the substrate product 85, since the second silicon oxide layer 83 is not formed in the outer peripheral region including the edge E3 (see the part (c) in FIG. 21), the epitaxial layer 23 is not bonded to the device layer 4. That is, the region of the epitaxial layer 23 not bonded to the device layer 4 has a hook shape protruding from the region bonded to the device layer 4 with the second silicon oxide layer 83 interposed therebetween. Accordingly, the unbonded epitaxial layer 23 cannot be ensured with sufficient strength and is easily removed. As shown in part (b) of FIG. 22, when the substrate product 85 is placed in the ultrasonic wave application device 87 and ultrasonic waves are applied, the unbonded region is removed from the substrate product 85 and the fifth substrate (semiconductor device) ) 86 is formed.

  In addition to removing the unbonded area, in addition to the method of applying ultrasonic waves, for example, the unbonded area can be removed by applying a force with a clean stick, or the unbonded area can be removed after being attached to the adhesive sheet. It may be removed.

  In the fifth substrate 86, the wafer alignment mark MW formed in the second region A2 is exposed. Since this wafer alignment mark MW is not collapsed, it can be used in subsequent manufacturing processes S11 to S14. Therefore, according to the manufacturing method of the second embodiment, the unjoined region of the epitaxial layer 23 including the fourth region A4 can be removed in a self-aligning manner, so that the manufacturing process of the semiconductor device can be simplified.

  According to the method for manufacturing a semiconductor device of the second embodiment, the wafer alignment mark MW is not damaged when the fifth substrate 50 with the wafer alignment mark MW exposed is formed, as in the first embodiment. . Accordingly, the fifth substrate (semiconductor device) 50 having the wafer alignment mark MW that can be used in the subsequent manufacturing processes S11 to S14 can be manufactured.

  The present invention is not limited to the specific configuration disclosed in the present embodiment.

  In the manufacturing method of the semiconductor device according to the first and second embodiments, a bonding method using a hydrophilic treatment is used for bonding the SOI substrate 1 and the third substrate 30, but the bonding method is not limited to this. As a bonding method, a surface activated bonding method may be used. In the surface activation bonding method, the SOI substrate 1 and the third substrate 30 are placed in a vacuum chamber, and each surface is irradiated with an Ar beam to be activated. And it joins by making the activated surfaces contact. According to this bonding method, when the third substrate 30 is bonded to the SOI substrate 1, it is not necessary to heat-treat the SOI substrate 1 and the third substrate 30. Therefore, the Mach-Zehnder modulator 100 and the first substrate that are not exposed to the heat treatment are used. Five substrates 50 and 86 can be manufactured. In the surface activated bonding method, the surfaces of the activated SOI substrate 1 and the third substrate 30 are not hydrophilized, so that the silicon oxide layer 33 does not need to be formed on the third substrate 30. In this case, the epitaxial layer 23 of the third substrate 30 is directly bonded to the device layer 4 of the SOI substrate 1.

  Further, an indirect bonding method may be used as the bonding method. In the indirect bonding method, metal, resin, or the like is disposed and bonded to the bonding interface J between the SOI substrate 1 and the third substrate 30.

  Before the third substrate 30 is hydrophilized, the surface of the silicon oxide layers 33 and 83 may be further polished. Since the microroughness of the surface is reduced by polishing, the silicon oxide layers 33 and 83 and the SOI substrate 1 can be reliably bonded.

  Since the first optical waveguide and the second optical waveguide must be manufactured based on the wafer alignment mark MW, after the wafer alignment mark MW is manufactured, the first optical waveguide and the second optical waveguide are aligned with the wafer alignment mark MW. An optical waveguide is manufactured, or the first optical waveguide is manufactured simultaneously with the wafer alignment mark MW.

  In addition, if the second alignment mark M2 is formed in the third region A3 after etching the fourth region A4 of the second substrate 20, there is a possibility that misalignment may occur. Therefore, the fourth region A4 and the second alignment mark M2 It is desirable to produce both simultaneously. When the fourth region A4 and the second alignment mark M2 are separately manufactured, the wafer alignment mark MW is also formed on the second substrate 20, and the fourth region A4 and the second alignment mark are based on the alignment mark MW. It is necessary to produce the mark M2.

  In 1st and 2nd embodiment, process S1a which forms the 1st mesa structure 8 should just be implemented as needed, and process S1a does not need to be implemented.

  In the first and second embodiments, the step S1a for forming the first mesa structure 8 may be performed after the step S2 for forming the first alignment mark M1 and the step S3 for forming the wafer alignment mark MW.

  If the wafer alignment mark MW is formed first, the first mesa structure 8 and the first alignment mark M1 may be formed on the basis thereof. If the wafer alignment mark MW is formed first, then either the first mesa structure 8 or the first alignment mark M1 may be formed first.

  In the first and second embodiments, in step S9b, the back surface 2a of the silicon substrate 2 of the SOI substrate 1 may be pressed, and the back surface 22b of the third substrate 30 and the back surface 2a of the SOI substrate 1 are sandwiched from both sides. You may press.

  In the second embodiment, in step S6, after etching the first silicon oxide layer 82 (step S6d), a step of etching the epitaxial layer 23 until the wafer 22 is exposed may be further performed. According to this step, the wafer alignment mark MW in the second region A2 can be exposed by performing the step S10a of etching the wafer 22 in the step S10 of forming the fifth substrate 86.

DESCRIPTION OF SYMBOLS 1 ... SOI substrate (1st substrate), 20 ... 2nd substrate, 22 ... Wafer, 23 ... Epitaxial layer, 30 ... 3rd substrate, 40 ... 4th substrate, 50 ... 5th substrate (semiconductor device), 100 ... Mach Zender modulator, A1 ... first region, A2 ... second region, A3 ... third region, A4 ... fourth region, C1 ... first element partition region, C2 ... second element partition region, M1 ... first alignment mark , M2 ... second alignment mark, MW ... wafer alignment mark.

Claims (7)

A first element partition region for forming an element structure of an optical device; a first region provided around the first element partition region; and a second region provided around the first element partition region. And preparing a first substrate containing silicon;
Forming a wafer alignment mark in the second region;
Forming a first alignment mark in the first region;
A second element partition region for forming an element structure of an optical device by growing an epitaxial layer of a group III-V compound semiconductor on a wafer containing a group III-V compound semiconductor, around the second element partition region Forming a second substrate having a third region provided and a fourth region provided around the second element partition region;
Forming a second alignment mark on the epitaxial layer in the third region;
Etching the epitaxial layer of the fourth region of the second substrate to the wafer is exposed, and forming a third substrate,
The second element partition region is positioned on the first element partition region, the third region is positioned on the first region, and the fourth region is positioned on the second region. Positioning the third substrate on the first substrate using the first alignment mark and the second alignment mark;
After positioning the third substrate on the first substrate, bonding the third substrate to the first substrate to form a fourth substrate;
And a step of removing the wafer from the fourth substrate and forming a fifth substrate. A first element partition region for forming an element structure of an optical device; a first region provided around the first element partition region; and a second region provided around the first element partition region. And preparing a first substrate containing silicon;
Forming a wafer alignment mark in the second region;
Forming a first alignment mark in the first region;
An epitaxial layer of a III-V compound semiconductor is grown on a wafer containing a III-V compound semiconductor, and a first silicon oxide layer is formed on the epitaxial layer to form an element structure of an optical device. Forming a second substrate having a second element partition region, a third region provided around the second element partition region, and a fourth region provided around the second element partition region;
Forming a second alignment mark on the epitaxial layer in the third region;
Etching the first silicon oxide layer in the fourth region of the second substrate to form a third substrate including a second silicon oxide layer having an opening in the fourth region ;
The second element partition region is positioned on the first element partition region, the third region is positioned on the first region, and the fourth region is positioned on the second region. Positioning the third substrate on the first substrate using the first alignment mark and the second alignment mark;
After positioning the third substrate on the first substrate, bonding the third substrate to the first substrate to form a fourth substrate;
Wherein by removing the epitaxial layer of the fourth region from the fourth substrate after removing the wafer while removing the wafer has a step of forming a fifth substrate, and wherein the A method for manufacturing a semiconductor device. After the step of forming the wafer alignment mark, the step of etching the first region to form a first mesa structure for a first optical waveguide;
Forming the first mesa structure comprises:
Positioning a first photomask with respect to the first substrate with respect to the wafer alignment mark;
Forming a first mask for forming the first mesa structure on the first region using the first photomask;
Etching the first region using the first mask to form the first mesa structure;
The manufacturing method of the semiconductor device of Claim 1 or Claim 2 containing this. 4. The semiconductor device according to claim 3 , further comprising: forming a second mesa structure for a second optical waveguide by etching the epitaxial layer in the second element partition region after forming the fifth substrate. 5. Production method. 5. The method of manufacturing a semiconductor device according to claim 4 , wherein the second mesa structure includes a portion formed on the first mesa structure so as to extend in an extending direction of the first mesa structure. The step of forming the second mesa structure includes:
Positioning a photomask with respect to the fifth substrate with respect to the wafer alignment mark;
Forming a mask for forming the second mesa structure on the epitaxial layer using the photomask;
And forming an etching to the second mesa structure the epitaxial layer of the second element dividing area by using the mask, a method of manufacturing a semiconductor device according to claim 4 or claim 5. The method for manufacturing a semiconductor device according to claim 1 , wherein the first substrate is an SOI substrate.

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