CN109003935A - Semiconductor devices and its manufacturing method - Google Patents
Semiconductor devices and its manufacturing method Download PDFInfo
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- CN109003935A CN109003935A CN201710423669.5A CN201710423669A CN109003935A CN 109003935 A CN109003935 A CN 109003935A CN 201710423669 A CN201710423669 A CN 201710423669A CN 109003935 A CN109003935 A CN 109003935A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 219
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 152
- 238000000034 method Methods 0.000 claims description 33
- 150000002500 ions Chemical class 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 8
- 239000007769 metal material Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 abstract description 23
- 230000005540 biological transmission Effects 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 6
- 230000002411 adverse Effects 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 30
- 229910052710 silicon Inorganic materials 0.000 description 30
- 239000010703 silicon Substances 0.000 description 30
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 239000012212 insulator Substances 0.000 description 8
- 230000003287 optical effect Effects 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 5
- 238000009413 insulation Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
The present invention provides a kind of semiconductor devices and its manufacturing methods, groove is formed in the first semiconductor substrate, it covers on groove and the first semiconductor substrate and is again bonded the first semiconductor substrate with the second semiconductor substrate for being covered with second insulating layer after the first insulating layer, then the second semiconductor substrate is thinned backwards to the surface of second insulating layer, and remaining second semiconductor substrate is performed etching to form ducting layer, the ducting layer is formed with above its further groove, the thickness of the ducting layer underlying insulating layer is greater than the thickness of insulating layer at remaining position, the loss of waveguide transmission can not only be reduced, and it can be avoided advanced line unit conjunction in the prior art and carry out adverse effect caused by recess etch again, improve the performance of semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of semiconductor devices and its manufacturing method.
Background technique
Silicon-on-insulator (Silicon-On-Insulator, SOI), the also referred to as silicon in insulating substrate, in top layer silicon and back
One layer of buries oxide layer (BOX) is introduced between substrate, is a kind of novel silicon with unique " silicon/insulation layer/silicon " three-decker
Base semiconductor material.It realizes the Fully dielectric isolation of device and substrate by buries oxide layer.
The silicon line layer with one fixed width is formed by performing etching to the top layer silicon in silicon-on-insulator, on silicon line layer top
Portion and surrounding cover silicon dioxide insulating layer, form semiconductor devices.Since silicon has different refractive index, silicon from silica
Refractive index (about 3.5) be greater than silica (about 1.45) refractive index, the semiconductor when silicon line layer is surrounded by silica
Device forms waveguide, can be used in transmitting light or optical signal.
When the semiconductor devices is coupled with external circuit, light or optical signal are transmitted to waveguide from external circuit and will cause one
Fixed loss, and in order to reduce the loss in the transmission process, it needs to form groove in the backing bottom close to external circuit, have
Body, a groove is formed in the backing bottom below silicon line layer and buries oxide layer, i.e., below the buries oxide layer with silicon line layer
Form a cavity.The general method combined by dry etching with wet etching forms groove in the prior art, but can not
The meeting avoided is there are some problems, such as silicon residual, the problems such as mechanical strength is insecure, finally formed partly leads to influence
The performance of body device.
Therefore it provides a kind of loss that can either reduce waveguide transmission, and will not be to the semiconductor device that performance impacts
The technical issues of manufacturing method of part is those skilled in the art's urgent need to resolve.
Summary of the invention
The purpose of the present invention is to provide a kind of semiconductor devices and its manufacturing methods, before semiconductor substrate bonding first
It forms groove and fills insulating layer, the performance of semiconductor devices is improved on the basis of reducing waveguide transmission loss.
To achieve the above object, the present invention provides a kind of manufacturing method of semiconductor devices, comprising the following steps:
One first semiconductor substrate is provided, forms a groove in first semiconductor substrate；
The first insulating layer is formed on the groove and first semiconductor substrate；
One second semiconductor substrate is provided, forms second insulating layer in second semiconductor substrate；
The one side and second semiconductor substrate of first insulating layer will be formed in first semiconductor substrate
On be formed with being bonded on one side for the second insulating layer；
Second semiconductor substrate is thinned backwards to the surface of the second insulating layer；
Remaining second semiconductor substrate is etched to form multiple ducting layers, wherein being formed with above the groove described
Ducting layer.
Optionally, it is formed after ducting layer, the manufacturing method of the semiconductor devices further include: in the second insulating layer
And third insulating layer is formed on the ducting layer.
Optionally, it is formed after third insulating layer, the manufacturing method of the semiconductor devices further include: exhausted in the third
A contact hole is formed in edge layer, the contact holes exposing goes out the ducting layer, and fills metal material in the contact hole.
Optionally, it is formed after the second insulating layer, the manufacturing method of the semiconductor devices further include: to described
Two semiconductor substrates carry out ion implanting, form ion implanted layer inside second semiconductor substrate.
Optionally, it is formed after the ion implanted layer, the manufacturing method of the semiconductor devices further include: to described
Two insulating layers carry out planarization process.
Optionally, in the step of second semiconductor substrate is backwards to the surface of the second insulating layer is thinned, removal
Second semiconductor substrate of the ion implanted layer and the ion implanted layer backwards to the second insulating layer side.
Optionally, second semiconductor substrate is thinned after the surface of the second insulating layer, the semiconductor
The manufacturing method of device further include: planarization process is carried out to remaining second semiconductor substrate.
Optionally, first insulating layer, second insulating layer are identical as the material of third insulating layer.
Optionally, first insulating layer, second insulating layer and third insulating layer are silicon oxide layer.
Correspondingly, the present invention also provides a kind of semiconductor devices, comprising:
Semiconductor substrate；
Groove in the semiconductor substrate；
Cover the insulating layer of the semiconductor substrate and the groove；
Multiple ducting layers in the insulating layer, wherein the top of the groove has the ducting layer.
Optionally, the insulating layer includes the first insulating layer for covering the semiconductor substrate and the groove, is located at institute
State the second insulating layer on the first insulating layer and the third insulating layer in the second insulating layer；Wherein, the waveguide
Layer is located on the second insulating layer, and the third insulating layer covers the second insulating layer and the ducting layer.
Optionally, first insulating layer, second insulating layer are identical as the material of third insulating layer.
Optionally, first insulating layer, second insulating layer and third insulating layer are silicon oxide layer
Optionally, the semiconductor devices further include: the contact hole in the third insulating layer, the contact hole prolong
The ducting layer is extended to, is filled with metal material in the contact hole.
Compared with prior art, semiconductor devices provided by the invention and its manufacturing method have the advantages that
The present invention forms groove in the first semiconductor substrate first, covers first on groove and the first semiconductor substrate
The first semiconductor substrate is bonded with the second semiconductor substrate for being covered with second insulating layer again after insulating layer, then thinned the
Two semiconductor substrates perform etching to form ducting layer backwards to the surface of second insulating layer, and to remaining second semiconductor substrate,
The ducting layer is formed with above the groove, the thickness of the ducting layer underlying insulating layer is greater than insulating layer at remaining position
Thickness, the loss of waveguide transmission can not only be reduced, and can be avoided advanced line unit conjunction in the prior art carry out again it is recessed
Adverse effect caused by groove etched, improves the performance of semiconductor devices.
Detailed description of the invention
Fig. 1~2 are each step sectional view of the preparation method of semiconductor device.
Fig. 3 is the top view of semiconductor device.
Fig. 4 is the flow chart of the manufacturing method of semiconductor devices provided by one embodiment of the invention.
Fig. 5~Figure 12 is each step sectional view of the manufacturing method of semiconductor devices provided by one embodiment of the invention.
Specific embodiment
Fig. 1~2 are each step sectional view of the preparation method of semiconductor device, and Fig. 3 is the vertical view of semiconductor device
Figure.Please refer to shown in FIG. 1 to FIG. 3, under normal circumstances, the preparation method of the semiconductor devices the following steps are included:
First step: providing a silicon-on-insulator, including semiconductor substrate 1 (being equivalent to bottom silicon layer), is formed in described
The first insulating layer 2 (being equivalent to buries oxide layer) in semiconductor substrate 1, and the top layer being formed on first insulating layer 2
Silicon layer.The top silicon layer is performed etching, multiple ducting layers 3 are formed on first insulating layer 2, then described first
Second insulating layer 4 is formed on insulating layer 2 and ducting layer 3, forms semiconductor devices as shown in Figure 1.
First insulating layer 2 is identical as the material of second insulating layer 4, preferably silica.The ducting layer 3 is by institute
The first insulating layer 2 is stated to be surrounded with the second insulating layer 4, and the refractive index of the ducting layer 3 is greater than first insulating layer 2
With the refractive index of second insulating layer 4, when being passed through optical signal in the ducting layer 3, the semiconductor devices forms waveguiding structure.
Silicon-on-insulator can be formed using the method for wafer bonding, such as surface is formed with the two and half of insulating layer and is led
Body substrate is bonded, and silicon-on-insulator is consequently formed.It is of course also possible to directly provide semi-conductive substrate 1, partly led described
The first insulating layer 2 is formed in body substrate 1, forms top silicon layer on first insulating layer 2, then according to above-mentioned identical step
Suddenly semiconductor devices as shown in Figure 1 is formed.
When the semiconductor devices is coupled with external circuit, light or optical signal are transmitted to waveguide from external circuit and will cause one
Fixed loss, and in order to reduce the loss in the transmission process, it needs to be formed in the semiconductor devices close to external circuit
One groove forms groove in the semiconductor substrate 1 with ducting layer 3 above.Therefore, further include the steps that etched recesses.
Second step: the second insulating layer 4, the first insulating layer 2 and part semiconductor substrate 1 are performed etching, shape
At groove 5, the groove 5 extends to the inside of the semiconductor substrate 1, and is connected in the semiconductor substrate 1.Specifically
, the second insulating layer 4 and the first insulating layer 2 of 3 two sides of ducting layer are performed etching, groove is formed, is exposed described
Semiconductor substrate 1 can preferably carve the second insulating layer 4 and the first insulating layer 2 using the method for dry etching
Erosion；Then the semiconductor substrate 1 exposed is performed etching using wet etching, and etches the first of 3 bottom of ducting layer simultaneously
Semiconductor substrate 1 under insulating layer 2 forms groove 5, as shown in Figure 2.Fig. 3 is the top view of the semiconductor devices.
As shown in Figure 2 and Figure 3, inevitably existed using the method that dry etching forms groove 5 with wet etching
Some problems, such as: it can be remained there are silicon below ducting layer 3 and buries oxide layer (the silicon residual 1 ' in such as Fig. 2), and nothing
Whether there is below method on-line checking buries oxide layer has silicon residual；The rough surface of buries oxide layer after etching；And due to
The remaining presence of silicon, needs over etching that can completely remove, but excessive etching, will cause the mistake of support column between groove
It etches (support column 6 in such as Fig. 3 will cause over etching), causes the mechanical strength of finally formed semiconductor devices insecure；
And before packaging, groove 5 is constantly exposed in air, and the property that will cause some materials in semiconductor devices becomes
Change, the final performance for influencing semiconductor devices.
Damage of the optical signal in transmission process can be reduced by forming groove below the buries oxide layer with ducting layer above
It loses, and when the thickness of the buries oxide layer below ducting layer is larger, it is identical as having reeded effect at preferably greater than 5 μm, together
Sample can reduce loss of the optical signal in transmission process.
Inventor is in view of the above problems, propose a kind of preparation method of semiconductor devices.
To keep the contents of the present invention more clear and easy to understand, below in conjunction with Figure of description, the contents of the present invention are done into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, and general replacement well known to those skilled in the art is also contained
Lid is within the scope of the present invention.
Secondly, the present invention has carried out detailed statement using schematic diagram, in detail that example of the present invention, for the ease of saying
Bright, schematic diagram is not partially enlarged in proportion to the general scale, should not be to this as restriction of the invention.
The present invention provides a kind of manufacturing method of semiconductor devices, comprising the following steps: one first semiconductor substrate is provided,
A groove is formed in first semiconductor substrate；The first insulation is formed on the groove and first semiconductor substrate
Layer；One second semiconductor substrate is provided, forms second insulating layer in second semiconductor substrate；By first semiconductor
It is formed on substrate in the one side and second semiconductor substrate of first insulating layer and is formed with the second insulating layer
It is bonded on one side；Second semiconductor substrate is thinned backwards to the surface of the second insulating layer；Etch remaining the second half
Conductor substrate is to form multiple ducting layers, wherein being formed with the ducting layer above the groove.
The present invention forms groove in the first semiconductor substrate first, covers first on groove and the first semiconductor substrate
The first semiconductor substrate is bonded with the second semiconductor substrate for being covered with second insulating layer again after insulating layer, then thinned the
Two semiconductor substrates perform etching to form ducting layer backwards to the surface of second insulating layer, and to remaining second semiconductor substrate,
The ducting layer is formed with above the groove, the thickness of the ducting layer underlying insulating layer is greater than insulating layer at remaining position
Thickness, the loss of waveguide transmission can not only be reduced, and can be avoided advanced line unit conjunction in the prior art carry out again it is recessed
Adverse effect caused by groove etched, improves the performance of semiconductor devices.
Referring to FIG. 4, its flow chart for the manufacturing method of semiconductor devices provided by one embodiment of the invention.Such as figure
Shown in 4, the present invention provides a kind of manufacturing method of semiconductor devices, comprising the following steps:
Step S01: one first semiconductor substrate is provided, forms a groove in first semiconductor substrate；
Step S02: the first insulating layer is formed on the groove and first semiconductor substrate；
Step S03: one second semiconductor substrate is provided, forms second insulating layer in second semiconductor substrate；
Step S04: the one side of first insulating layer and described the second half will be formed in first semiconductor substrate
Being bonded on one side for the second insulating layer is formed on conductor substrate；
Step S05: second semiconductor substrate is thinned backwards to the surface of the second insulating layer；
Step S06: remaining second semiconductor substrate of etching is to form multiple ducting layers, wherein the groove is upper rectangular
At there is the ducting layer.
Fig. 5~Figure 12 is the structural representation of each step of manufacturing method of semiconductor devices provided by one embodiment of the invention
Figure, please refers to shown in Fig. 4, and combines Fig. 5~Figure 12, the manufacturing method for the semiconductor devices that the present invention will be described in detail proposes:
As shown in figure 5, one first semiconductor substrate 10 is provided in step S01, in first semiconductor substrate 10
Form a groove 11.In the present embodiment, shallow trench isolation can be equipped in first semiconductor substrate 10 (not show in figure
Out), the material of first semiconductor substrate 10 can be monocrystalline silicon, polysilicon, unformed silicon, silicon Germanium compound or insulator
Upper silicon (SOI) etc. or other materials well known by persons skilled in the art, can be with shape in first semiconductor substrate 10
At doped region or other semiconductor structures etc., which is not limited by the present invention.
A groove 11 is formed in first semiconductor substrate 10, specifically includes the following steps:
Step S011 forms a photoresist layer (being not shown in Fig. 5) in first semiconductor substrate 10.Preferably,
Photoresist layer can be formed in first semiconductor substrate 10 by spin coating mode.
Step S012 forms patterned photoresist layer (being not shown in Fig. 5) with development to photoresist layer exposure.Tool
Body, one mask plate is set in the top of the photoresist layer, exposes photoresist layer corresponding to groove predetermined position, then
It is exposed, photoresist layer of the development removal later through overexposure exposes first semiconductor substrate 10.The present embodiment
In, it is illustrated so that photoresist layer is positive photoresist as an example.
Step S013 performs etching first semiconductor substrate 10 using patterned photoresist layer as exposure mask, is formed
Groove 11.Preferably, the depth of the groove 11 is 0.1 μm~5 μm.In the present embodiment, as shown in figure 5, the groove 11
Section is rectangle, and in other embodiments, the section of the groove 11 can be square, inverted trapezoidal, arc-shaped etc. various
Shape well known by persons skilled in the art or the shape of the groove 11 can be determined by actual process conditions, of the invention
It does not limit this.
In step S02, the first insulating layer 12 is formed on the groove 11 and first semiconductor substrate 10, is formed
Structure as shown in FIG. 6.Preferably, first insulating layer 12 is oxide layer, such as silicon oxide layer.It can be using deposition work
Skill, deposits the first insulating layer 12 in first semiconductor substrate 10, and first insulating layer 12 fills the groove 11 simultaneously
Cover first semiconductor substrate 10.In other embodiments, oxidation technology or those skilled in the art can also have been used
Other techniques known form first insulating layer 12.
Then, planarization process is carried out to first insulating layer 12.Preferably, using the method pair of chemical mechanical grinding
First insulating layer 12 carries out planarization process, and first insulating layer 12 is made to have smooth surface, to guarantee subsequent half
The bonding precision of conductor substrate.In other embodiments, planarization process can also be carried out using other methods, such as: it uses
The methods of electrobrightening or etching carry out planarization process, and purpose is to have smooth surface, and the present invention is to specific flat
Change mode is without limitation.
In step S03, one second semiconductor substrate 20 is provided, forms second in second semiconductor substrate 20 absolutely
Edge layer 21, as shown in Figure 7.
The material of second semiconductor substrate 20 can be monocrystalline silicon, polysilicon, unformed silicon, silicon Germanium compound or exhausted
Silicon (SOI) etc. or other materials well known by persons skilled in the art on edge body.Preferably, the second insulating layer 21 is oxygen
Change layer, such as silicon oxide layer.In the present embodiment, by carrying out thermal oxide to second semiconductor substrate 20, described the
The surface of two semiconductor substrates 20 forms silicon oxide layer.In other embodiments, depositing operation or this field skill can also be used
Other techniques known to art personnel form the silicon oxide layer.
Then, ion implanting is carried out to second semiconductor substrate 20, in the 20 inside shape of the second semiconductor substrate
At ion implanted layer 22, in the present embodiment, the ion of injection is hydrogen ion.Preferably, second semiconductor can be served as a contrast
The one side that bottom 20 is formed with second insulating layer 21 carries out ion implanting, the ion implanted layer 22 to second semiconductor substrate
20 are formed with the distance of 21 one side of second insulating layer, i.e., the depth of the described ion implanting is determined by each parameter of the ion implanting
It is fixed, such as energy, injection length of injection etc..It is of course also possible to before forming second insulating layer 21, led to described the second half
Body substrate 20 carries out ion implanting.Which is not limited by the present invention.
Then, planarization process is carried out to the second insulating layer 21.Preferably, using the method pair of chemical mechanical grinding
The second insulating layer 21 carries out planarization process, and the second insulating layer 21 is made to have smooth surface, to guarantee subsequent half
The bonding precision of conductor substrate.In other embodiments, planarization process can also be carried out using other methods, such as: it uses
The methods of electrobrightening or etching carry out planarization process, and purpose is to have smooth surface, and the present invention is to specific flat
Change mode is without limitation.
In step S04, one side and the institute of first insulating layer 12 will be formed in first semiconductor substrate 10
It states and is formed with being bonded on one side for the second insulating layer 21 in the second semiconductor substrate 20, form structure as shown in Figure 8.
The second semiconductor substrate 20 for being formed with second insulating layer 21 is inverted, and is formed with the first of the first insulating layer 12
Semiconductor substrate 10 is bonded, and first insulating layer 12 is used as bonded layer with second insulating layer 21, can be improved two and half
The efficiency of conductor substrate bonding.
In step S05, second semiconductor substrate 20 is thinned backwards to the surface of the second insulating layer 21, is formed such as
Structure shown in Fig. 9.
In the present embodiment, second semiconductor substrate 20 is thinned backwards to the second insulating layer 21 by the method for removing
Surface, thinned second semiconductor substrate 20 with a thickness of the ion implanted layer 22 and the ion implanted layer 22
Second semiconductor substrate 20 backwards to 21 side of second insulating layer removes the ion note using the method for removing
Enter layer 22 and the ion implanted layer 22 deviates from second semiconductor substrate 20 of 21 side of second insulating layer.From described
Ion implanted layer 22 is removed, and will be far from second semiconductor substrate 20 removing of 21 side of second insulating layer, shape
At semiconductor devices include: remaining a part of second semiconductor substrate 20, second insulating layer 21, the first insulating layer
12 and first semiconductor substrate 10, second semiconductor substrate 20 be top silicon layer, first semiconductor substrate 10 is
Bottom silicon layer, first insulating layer 12 constitute buries oxide layer 30 with second insulating layer 21.
Carrying out annealing process makes the hydrogen ion injected in the ion implanted layer 22 form bubble, so that far from described second
A part of second semiconductor substrate 20 of insulating layer 21 is removed.The temperature of the annealing process is less than 400 DEG C, such as 390
DEG C, 370 DEG C or 350 DEG C.Then planarization process is carried out to the surface that remaining second semiconductor substrate 20 exposes.
Finally further include high annealing, increases the bonding force between first insulating layer 12 and the second insulating layer 21
Degree forms semiconductor devices, and the surface that can also be exposed to second semiconductor substrate 20 is ground, described in adjustment
The thickness of the second semiconductor substrate 20 in buries oxide layer 30.
In step S06, remaining second semiconductor substrate 20 is etched to form multiple ducting layers 40, wherein the groove
Top be formed with the ducting layer 40, form structure as shown in Figure 10.
Specifically, forming patterned photoresist layer (being not shown in Figure 10) in second semiconductor substrate 20, cruelly
Expose predetermined the second semiconductor substrate 20 for forming ducting layer, using the patterned photoresist layer as exposure mask, etches described the
Two semiconductor substrates 20 form multiple ducting layers 40, wherein the ducting layer 40, i.e. ducting layer are formed with above the groove
The thickness of the buries oxide layer of 40 lower sections is greater than the thickness of the buries oxide layer in remaining place, and the waveguide being consequently formed can reduce this partly
When conductor device is coupled with external circuit, when light or optical signal are transmitted to waveguide from external circuit caused by loss.
In the prior art, it carries out after bonding together to form silicon-on-insulator, etching forms ducting layer, then again to ducting layer
The semiconductor substrate of lower section performs etching to form groove.In the present invention, groove 11 is first formed in the first semiconductor substrate 10,
Groove 11 is filled later and is bonded again with the second semiconductor substrate 20, ducting layer 40 is eventually formed and makes the waveguide
The thickness of the buries oxide layer 30 of 40 lower section of layer is greater than the thickness of remaining buries oxide layer 30, plays former reeded work in the prior art
With.Problem caused by etched recesses in the prior art is avoided simultaneously, such as: it will not be deposited below ducting layer, buries oxide layer
There is silicon residual；There is no over etchings, will not impact to the mechanical strength of semiconductor devices；Directly served as a contrast in the first semiconductor
It etching groove and is filled on bottom, compared with the method for etching groove in the prior art, simple process, thus, it is possible to avoid burying oxygen
Change the rough surface of layer；Most of all, not fluted be exposed in air.Therefore, using semiconductor of the present invention
The production method of device can not only reduce the loss during waveguide transmission, and can be avoided advanced in the prior art
Line unit conjunction carries out adverse effect caused by recess etch again, improves the performance of semiconductor devices.
It is formed after ducting layer 40 further include: third insulation is formed in the second insulating layer 21 and the ducting layer 40
Layer 50, as shown in figure 11.Third insulating layer 50 is deposited in the second insulating layer 21, the third insulating layer 50 covers described
Second insulating layer 21 and the ducting layer 40.Preferably, the third insulating layer 50, second insulating layer 21 and the first insulating layer
12 material is all the same, and the third insulating layer 50 is oxide layer, such as silicon oxide layer.
Then, a contact hole 60 is formed in the third insulating layer 50, the contact hole 60 exposes the ducting layer
40, and metal material 61 is filled in the contact hole 60, form structure as shown in figure 12.
Specifically, a patterned photoresist layer (being not shown in Figure 12) is formed on the third insulating layer 50, exposure
The predetermined forming region of the contact hole out, then using the patterned photoresist layer as exposure mask, to the third insulating layer 50
It performs etching, forms the contact hole 60, the contact hole 60 exposes the waveguide 40.Then it is filled out in the contact hole 60
Metal material 61 is filled, the contact for the waveguide 40 with remaining part, the metal material 61 is preferably tungsten.It needs to illustrate
It is in attached drawing 12, to illustrate only two ducting layers 40, be formed with contact hole 60 on a ducting layer 40, another ducting layer
Formed fluted under 40, which only schematically illustrates, when any one ducting layer 40 needs are in contact with remaining part,
To be formed on contact hole, contact material is filled, and 10 fluted a, ducting layer 10 in lower section of ducting layer in Figure 12
Lower section does not have groove, again is just for illustrating ducting layer tool there are two types of situation, pre- standing wave before bonding when needing to be arranged groove
Groove is formed in the first semiconductor substrate below conducting shell, does not need to not necessarily form groove when setting groove.
Correspondingly, the present invention also provides a kind of semiconductor devices, using the manufacturing method of semiconductor devices as described above
It is fabricated, comprising:
Semiconductor substrate；
Groove in the semiconductor substrate；
Cover the insulating layer of the semiconductor substrate and the groove；
Multiple ducting layers in the insulating layer, wherein the top of the groove has the ducting layer.
Specifically, please referring to shown in Figure 12, the semiconductor devices includes: the first semiconductor substrate 10；It is formed in described
Groove in first semiconductor substrate 10；The first insulating layer 12 of the semiconductor substrate 10 and groove is covered, is located at described the
Second insulating layer 21 on one insulating layer 12；Multiple ducting layers 40 in second insulating layer 21；Cover second insulation
The third insulating layer 50 of layer 21 and ducting layer 40, wherein the top of the groove has the ducting layer 40.Described the first half
Conductor substrate 10 is used as bottom silicon layer, and first insulating layer 12 constitutes buries oxide layer 30, ducting layer 40 with second insulating layer 21
It is covered positioned at the top of buries oxide layer 30, and by third insulating layer 50, forms waveguiding structure.
Preferably, the material of first insulating layer 12, second insulating layer 21 and third insulating layer 50 is all the same, described
The material of first insulating layer 12, second insulating layer 21 and third insulating layer 50 is oxide layer, such as silicon oxide layer.Certainly,
In other embodiments, the material of first insulating layer 12, second insulating layer 21 and third insulating layer 50 can also be different,
Which is not limited by the present invention.
The semiconductor devices further include: the contact hole 60 being formed in the third insulating layer 50, the contact hole 60
Extend to the ducting layer 40, be filled with metal material 61 in the contact hole 60, preferably tungsten, for the ducting layer 40 with
The contact of remaining part.
In conclusion semiconductor devices provided by the invention and its manufacturing method, the shape first in the first semiconductor substrate
At groove, is covered on groove and the first semiconductor substrate after the first insulating layer and by the first semiconductor substrate and to be covered with the again
Second semiconductor substrate of two insulating layers is bonded, and the second semiconductor substrate is then thinned backwards to the surface of second insulating layer, and right
Remaining second semiconductor substrate performs etching to form ducting layer, and the ducting layer is formed with above the groove, the wave
The thickness of conducting shell underlying insulating layer is greater than the thickness of insulating layer at remaining position, can not only reduce the loss of waveguide transmission, and
And can be avoided advanced line unit conjunction in the prior art and carry out adverse effect caused by recess etch again, improve semiconductor device
The performance of part.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (14)
1. a kind of manufacturing method of semiconductor devices, which comprises the following steps:
One first semiconductor substrate is provided, forms a groove in first semiconductor substrate；
The first insulating layer is formed on the groove and first semiconductor substrate；
One second semiconductor substrate is provided, forms second insulating layer in second semiconductor substrate；
By the one side for being formed with first insulating layer in first semiconductor substrate and shape in second semiconductor substrate
At there is being bonded on one side for the second insulating layer；
Second semiconductor substrate is thinned backwards to the surface of the second insulating layer；
Remaining second semiconductor substrate is etched to form multiple ducting layers, wherein being formed with the waveguide above the groove
Layer.
2. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that formed after ducting layer, described half
The manufacturing method of conductor device further include: third insulating layer is formed in the second insulating layer and the ducting layer.
3. the manufacturing method of semiconductor devices as claimed in claim 2, which is characterized in that formed after third insulating layer, institute
State the manufacturing method of semiconductor devices further include: a contact hole is formed in the third insulating layer, the contact holes exposing goes out
The ducting layer, and metal material is filled in the contact hole.
4. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that formed the second insulating layer it
Afterwards, the manufacturing method of the semiconductor devices further include: ion implanting is carried out to second semiconductor substrate, described second
Ion implanted layer is formed inside semiconductor substrate.
5. the manufacturing method of semiconductor devices as claimed in claim 4, which is characterized in that formed the ion implanted layer it
Afterwards, the manufacturing method of the semiconductor devices further include: planarization process is carried out to the second insulating layer.
6. the manufacturing method of semiconductor devices as claimed in claim 5, which is characterized in that the second semiconductor lining is being thinned
In the step of bottom is backwards to the surface of the second insulating layer, the ion implanted layer and the ion implanted layer are removed backwards to institute
State second semiconductor substrate of second insulating layer side.
7. the manufacturing method of semiconductor devices as claimed in claim 6, which is characterized in that second semiconductor substrate is thinned
After the surface of the second insulating layer, the manufacturing method of the semiconductor devices further include: led to remaining the second half
Body substrate carries out planarization process.
8. the manufacturing method of the semiconductor devices as described in any one of claim 2~7, which is characterized in that described first absolutely
Edge layer, second insulating layer are identical as the material of third insulating layer.
9. the manufacturing method of semiconductor devices as claimed in claim 8, which is characterized in that first insulating layer, second are absolutely
Edge layer and third insulating layer are silicon oxide layer.
10. a kind of semiconductor devices characterized by comprising
Semiconductor substrate；
Groove in the semiconductor substrate；
Cover the insulating layer of the semiconductor substrate and the groove；
Multiple ducting layers in the insulating layer, wherein the top of the groove has the ducting layer.
11. semiconductor devices as claimed in claim 10, which is characterized in that the insulating layer includes covering the semiconductor lining
First insulating layer of bottom and the groove, the second insulating layer on first insulating layer and be located at described second absolutely
Third insulating layer in edge layer；Wherein, the ducting layer is located on the second insulating layer, and the third insulating layer covers institute
State second insulating layer and the ducting layer.
12. semiconductor devices as claimed in claim 11, which is characterized in that first insulating layer, second insulating layer and the
The material of three insulating layers is identical.
13. semiconductor devices as claimed in claim 12, which is characterized in that first insulating layer, second insulating layer and the
Three insulating layers are silicon oxide layer.
14. semiconductor devices as claimed in claim 11, which is characterized in that the semiconductor devices further include: be located at described
Contact hole in third insulating layer, the contact hole extend to the ducting layer, are filled with metal material in the contact hole.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102033332A (en) * | 2009-09-25 | 2011-04-27 | 英特尔公司 | Optical modulator utilizing wafer bonding technology |
| CN102148183A (en) * | 2011-03-10 | 2011-08-10 | 上海宏力半导体制造有限公司 | Method for forming SOI (Silicon On Insulator) with stepped buried oxide layer |
| CN103794542A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor substrate |
| CN104956482A (en) * | 2012-12-26 | 2015-09-30 | 美光科技公司 | Semiconductor substrate for photonic and electronic structures and method of manufacture |
| US20150277041A1 (en) * | 2014-03-27 | 2015-10-01 | International Business Machines Corporation | Optical device and manufacturing method therefor |
-
2017
- 2017-06-07 CN CN201710423669.5A patent/CN109003935A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102033332A (en) * | 2009-09-25 | 2011-04-27 | 英特尔公司 | Optical modulator utilizing wafer bonding technology |
| CN102148183A (en) * | 2011-03-10 | 2011-08-10 | 上海宏力半导体制造有限公司 | Method for forming SOI (Silicon On Insulator) with stepped buried oxide layer |
| CN103794542A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor substrate |
| CN104956482A (en) * | 2012-12-26 | 2015-09-30 | 美光科技公司 | Semiconductor substrate for photonic and electronic structures and method of manufacture |
| US20150277041A1 (en) * | 2014-03-27 | 2015-10-01 | International Business Machines Corporation | Optical device and manufacturing method therefor |
Non-Patent Citations (1)
| Title |
|---|
| P. SIFFERT, E. KRIMMEL: "《硅技术的发展和未来》", 28 February 2009 * |
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| CN113311536B (en) * | 2020-02-27 | 2023-10-13 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for manufacturing the same |
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