JP6244380B2 - Structure and manufacturing method of photonic device - Google Patents

Description

[US Government Rights]
This invention was made with government support under Contract No. HR0011-11-9-0009, which was awarded by DARPA. The US government has certain rights to the invention.

[Technical field]
Embodiments of the structures and methods described herein form a photonic device on an integrated circuit substrate with sufficient optical isolation between the photonic device and the substrate material, and an evanescent between the two. It relates to suppressing binding.

  Today, there is a trend to integrate photonic devices and electronic devices on the same semiconductor substrate. As a support substrate for such integration, a silicon-on-insulator (SOI) substrate can be used. When forming a photonic device such as an optical waveguide, a cladding for confining a light wave propagating along the waveguide is provided around the core of the waveguide. The core material has a refractive index greater than that of the cladding. When silicon (having a refractive index of about 3.47) is used as the waveguide core material, the waveguide cladding can be formed of a lower refractive index material. For example, silicon dioxide (having a refractive index of about 1.54) is often used as the waveguide cladding.

  When using a silicon-on-insulator substrate as a support substrate, the cladding material under the waveguide core is the buried oxide (BOX) insulator (also typically silicon dioxide) of the SOI substrate. And the waveguide core can be formed from silicon on a BOX insulator. The BOX cladding functions to prevent leakage of an optical signal due to evanescent coupling from the silicon waveguide core to the SOI structure supporting silicon substrate. However, to prevent such evanescent coupling, the BOX cladding material under the waveguide core needs to be relatively thick. For example, this thickness is thicker than 1.0 μm, and in many cases, 2.0 to 3.0 μm. As the BOX cladding material becomes thicker, the cladding material impedes heat flow to the underlying silicon. Therefore, the effect of the silicon substrate as a radiator is reduced particularly for CMOS circuits that can be formed on the same substrate. In addition, in the case of a certain electronic device (such as a high-speed logic circuit integrated on the same SOI substrate as the photonic device), it is necessary to make the BOX of the SOI substrate relatively thin, usually 100 to 200 nm. The thickness is in the range. Such thin BOX insulator SOI provides a good substrate for electronic devices, but is insufficient to prevent the evanescent coupling of the silicon waveguide core to the supporting silicon underlying the SOI substrate. Unnecessary optical signal loss occurs. Furthermore, SOI substrates are relatively expensive and sometimes have limited availability.

  Therefore, non-SOI substrates have also been used to integrate electronic devices and photonic devices on the same substrate. One technique that can be used to prevent evanescent coupling between an optical device and an underlying non-SOI substrate is disclosed in US Pat. No. 7,920,770. In this patent, a deep isolation trench is etched in the substrate under the manufactured optical device. By the described etching, a substantially curved trench is provided under the optical device. As already mentioned, the underlying cladding material for a photonic device (such as a waveguide core) needs to be at least 1 μm thick, preferably 2.0-3.0 μm thick. Further, the cladding material should be stretched at least 1 μm laterally past each side edge of the photonic device at the depth described above. However, to meet this cladding depth criterion, it is necessary to extend the curved trench laterally beyond 1 μm past the side edge of the photonic device. If the curved trench extends more laterally beyond the side edge of the photonic device, the substrate area to be used for the formation of the photonic device becomes larger. The 7,920,770 patent also discloses providing another optical device manufacturing material on top of the substrate on which the optical device is formed.

  What is needed is a non-SOI substrate that provides a substantially rectangular lower cladding suitable for forming both CMOS and photonic devices, as well as a simplified method of forming photonic devices and underlying cladding. It is. A substrate structure that does not require the presence of another optical device manufacturing material on top of the non-SOI substrate is also desired.

It is a figure which shows one Embodiment of the photonic device manufactured on the upper part of the board | substrate in a cross section. It is a figure which shows another embodiment of the photonic device manufactured on the upper part of the board | substrate in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 1 in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 1 in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 1 in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 1 in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 1 in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 1 in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 1 in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 1 in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 1 in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 1 in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 1 in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 1 in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 1 in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 1 in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 1 in a cross section. It is a figure which shows the cross sectional view and planar view about a part of embodiment of FIG. It is a figure which shows the cross sectional view and planar view about a part of embodiment of FIG. It is a figure which shows the cross-sectional view and planar view about other one part of embodiment of FIG. It is a figure which shows the cross-sectional view and planar view about other one part of embodiment of FIG. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 2 in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 2 in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 2 in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 2 in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 2 in a cross section. It is a figure which shows the process sequence which can be utilized for formation of embodiment of FIG. 2 in a cross section. It is a figure which shows the cross section of the board | substrate which concerns on embodiment of FIG. 1, Comprising: The electronic device and the photonic device were manufactured together on the upper part. FIG. 3 is a diagram illustrating a cross section of the substrate according to the embodiment of FIG. 2, on which both an electronic device and a photonic device are manufactured.

  The embodiments described herein provide a photonic device. The photonic device is, for example, a waveguide formed of a core formed from a semiconductor substrate material and a lower cladding material associated therewith, which is provided in the cavity of the substrate material. This cavity is located below the photonic device. Embodiments of a photonic device and a method for forming a base cladding are also described.

  Embodiments described herein also provide a photonic device (eg, a waveguide) on top of a semiconductor substrate having a generally rectangular lower cladding formed therein.

  Various embodiments described herein provide a non-SOI substrate suitable for integration of CMOS and photonic devices.

  FIG. 1 is a diagram structurally showing an embodiment of the present invention. In this embodiment, an oxide (for example, silicon dioxide) filled cavity 125 that functions as a lower cladding of the photonic device is provided in a part of the semiconductor substrate 101. The photonic device shown in FIG. 1 is a waveguide including a waveguide core 129 as a constituent element. The oxide filled cavity 125 has a substantially rectangular cross section. The photonic device further comprises an upper cladding in the form of an oxide 135 (eg, silicon dioxide formed on both sides and on top of the waveguide core 129). The oxide 135 formed on the upper portion of the waveguide core 129 is an interlayer dielectric (ILD) formed as a part of a metal wiring interconnecting the CMOS circuit and the photonic circuit, as will be described in detail below. ) May be part of the structure.

  The waveguide core 129 is formed from the edge 131 (FIG. 3K) of the substrate 101. This edge is created during the etching of the substrate 101 to make the oxide filled cavity 125 substantially rectangular. Since the waveguide core 129 is formed of the same semiconductor material in which the oxide-filled cavity 125 is formed, it is necessary to add another processing step to form another photonic device manufacturing layer on the substrate 101. There is no.

  FIG. 2 is a diagram showing another embodiment. Also in this embodiment, the substrate 201 is manufactured to produce a substantially rectangular oxide-filled cavity 225. The oxide filled cavity 225 functions as the lower cladding of the waveguide. This waveguide comprises a waveguide core 229 provided on top of the oxide material 203. This oxide material is, for example, silicon dioxide, and functions as a protective layer for the substrate 201. The oxide 235 (for example, silicon dioxide) formed on the upper portion of the waveguide core 229 becomes an upper clad provided on both sides and the upper portion of the waveguide core 229. The oxide may be part of an interlayer dielectric (ILD) structure formed as part of a metal interconnect that interconnects the CMOS circuit and the photonic circuit. Unlike the embodiment of FIG. 1, the embodiment of FIG. 2 includes a waveguide core 229 formed from a photonic device fabrication layer, which includes an oxide layer 225 and an oxide spacer. Provided on top of layer 203.

  3A to 3O are diagrams showing a processing sequence starting from the semiconductor substrate 101 to form the structure of FIG. The substrate material may be a single crystal silicon semiconductor material. However, this processing sequence may be used for other substrate materials suitable for the manufacture of CMOS and photonic devices. Examples of such a substrate material include polycrystalline silicon, silicon carbide, and silicon germanium. The processing sequence shown in FIGS. 3A to 3O can be performed before, after, or during processing performed on the substrate 101 to form a CMOS device on another part of the same substrate 101.

FIG. 3A is a diagram showing a part of the semiconductor substrate 101 having the upper surface 104 that is the starting point of the process. As shown in FIG. 3B, a layer of the protective material 103 is formed on the upper surface of the substrate 101. This protective material may be, for example, an oxide such as silicon dioxide (SiO ₂ ), and is grown or laminated on the upper surface of the substrate 101 to protect the substrate 101 from subsequent processing steps. The hard mask material 105 is, for example, silicon nitride (Si ₃ N ₄ ) and is then deposited on the protective material 103.

  Next, as shown in FIG. 3C, a patterned photoresist material 107 is formed on the hard mask material 105. This pattern defines openings 109 in the photoresist material 107.

  As shown in FIG. 3D, the opening 109 is used for etching reaching the substrate 101 through the hard mask material 105 and the protective material 103 to form a substrate trench 111 in the upper surface 104 of the substrate 101. The etching for performing etching through the protective layer 103 and the hard mask 105 for forming the trench 111 can be anisotropic dry etching. Next, the photoresist material 107 is removed.

FIG. 3E is a view showing a state in which a protective liner 113 is formed on the side surface of the trench 111 and the side surfaces of the protective material 103 and the hard mask material 105 in the opening 109. The protective liner 113 can be, for example, an oxide such as SiO ₂ and can be deposited by deposition. Since the region to be protected during subsequent processing is at the side wall of the substrate trench 111, a protective liner 113 may be grown on the side wall and bottom of the trench 111 instead of being deposited by deposition. In any case, as shown in FIG. 3F, the bottom of the protective liner 113 in the trench 111 is removed by anisotropic wet etching or anisotropic dry etching so that the protective liner 113 is left on the side surface of the trench 111. To do. When the protective liner 113 is attached by deposition, the protective liner 113 is also left on the side surface of the opening 109 provided in the protective material 103 and the hard mask material 105. The depth l of the substrate trench 111 also determines the length l (FIG. 3F) of the protective liner 113 along the side of the trench 111, but this depth is the target of the edge 131 (FIG. 3J) of the substrate 101 that is subsequently generated. Selected based on thickness. This edge is used to form a photonic device element as described below. For example, when the target thickness of the photonic device element (such as the waveguide core 129) is a value in the range of about 30 nm to about 1 μm, the depth of the trench 111 and the length of the protective liner 103 along the side surface of the trench 111 Similarly, l (which is inevitably determined by the depth of the trench 111) is the same value corresponding to a range of about 30 nm to about 1 μm.

  After the formation of the protective liner 113, isotropic wet etching of the substrate 101 is started through the opening 109 and the trench 111 as shown in FIG. 3G, thereby starting to form a cavity 117 in the substrate 101. The etchant etches the silicon substrate 101, not the protective liner 113 or the protective material 103. To facilitate minimizing the area of the substrate 101 occupied by the photonic device and the associated underlying cladding, a substantially rectangular etching cavity is desired. Methods capable of performing substantially rectangular cavity etching in silicon substrates and suitable etchants therefor are disclosed in US Pat. No. 7,628,932 and US Pat. No. 8,159,050, which are hereby incorporated by reference. These entire applications are incorporated by reference as part of the specification.

Prior to wet etching, silicon etching is first performed in trench 111 to expose the desired silicon surface of substrate 101. The wet etchant may be selected based on the desired cavity shape, the desired shape of the edge 131 (FIG. 3J) of the substrate 101 and the crystal orientation of the substrate. When silicon of <100> plane is used, the wet etching solution can be a hydroxide. Examples of such hydroxides include NH ₄ OH or tetramethylammonium hydroxide (TMAH), and NH ₄ OH forms a shape cavity faster than TMAH. The etching rate of the substrate 101 varies depending on the direction of the silicon surface. FIG. 3G shows the start of etching, where a substantially hexagonal cavity has begun to be formed. By further etching, a substantially diamond-shaped cavity 119 is generated as shown in FIG. 3H. Further etching is performed to generate a substantially hexagonal cavity 121 extending in the lateral direction in FIG. 3I. In order to form a substantially rectangular shape from the cavity of FIG. 3I, corners perpendicular to the cavity 121 may be made using different etchants. Therefore, using a buffered fluoride etch solution with a volume ratio of NH ₄ F: QEII: H ₂ O ₂ of about 4: 2: 3, the cavity 121 of FIG. The corners may be formed into cavities, and these corners generate a substantially rectangular cavity 123 shown in FIG. 3J. QEII is a commercially available etching solution available from “Olin Microelectronics Materials” (Norwalk, Conn.). A substantially rectangular cavity 123 creates an edge 131 of the substrate material above the cavity 123.

  Following wet etching to define the cavity 123 having a substantially rectangular cross-sectional shape shown in FIG. 3J, the protective material 103 and the hard mask material 105 are removed by dry etching or chemical mechanical polishing to expose the upper surface 104 of the substrate 101. . Next, by cleaning the substrate 101, as shown in FIG. 3K, the substrate 101 having a substantially rectangular cavity 123, an edge 131, and a part of the protective liner 113 remains.

  Next, as shown in FIG. 3L, the cavity 123 is filled with an oxide material 125 (eg, silicon dioxide). The oxide material 125 functions as the lower cladding of subsequently formed photonic devices and may be formed by deposition, spin coating or thermal growth.

  FIG. 3M is a diagram illustrating a state in which the patterned photoresist material 127 is formed on the edge 131 of the substrate 101. The photoresist material functions as a mask when anisotropic etching is performed on the substrate 101 and the edge portion 131. As shown in FIG. 3N, this etching stops at the top surface of the oxide 125 to produce a photonic device element in the form of a waveguide core 129. The waveguide core 129 is supported on the upper surface of the oxide material 125, and this oxide material becomes the lower cladding of the waveguide core 129. Next, as shown in FIG. 3O, an upper cladding material in the form of an oxide 135 (eg, silicon dioxide) is formed on both sides and the upper portion of the silicon waveguide core 129 in the completed state shown in FIG. A waveguide is formed.

  The oxide material 125 is described in connection with FIG. 3L, where the oxide material is formed in a generally rectangular cavity 123 before the waveguide core device 129 is formed. did. However, the oxide material 125 can also be formed in the cavity 123 after the waveguide core 129 is formed.

  4A and 4A-1 are respectively a plan view and a cross-sectional view (along lines A-1 to A-1) of a part of the structure of FIG. The plan view of FIG. 4A shows the structure under the oxide 135 with a dotted line. 4A-1 is a cross-sectional view taken out across the position of the trench 111 provided in the substrate 101. Etching for forming a substantially rectangular cavity 123 is performed through this trench. Oxides 125 and 135 are shown together in the cross section of FIG. 4A-1. The oxide 125 is also indicated by a dotted line in the plan view of FIG. 4A. As shown in FIG. 4A, a plurality of trenches 111 are formed, and these trenches are arranged in a linear direction along the substrate 101. Thus, a linearly extending underlying cladding oxide 125 is provided for the linearly extending waveguide core 129.

  4B and 4B-1 are respectively a plan view and a cross-sectional view (along line B-1 to B-1) of another part of the structure of FIG. The plan view of FIG. 4B shows the structure under the oxide 135 with a dotted line. This cross-sectional view is taken out across the waveguide core 129 extending linearly, and shows a state in which the waveguide core 129 is surrounded by the clad oxides 125 and 135 in the cross section of FIG. 4B-1. Show. The linearly extending oxide 125 and the waveguide core 129 are indicated by dotted lines in the plan view of FIG. 4B. The upper cladding oxide 135 is part of an interlayer dielectric (ILD) structure used to support the metal wiring pattern for connecting the CMOS and photonic devices in the manner described below in connection with FIG. It can be.

  The embodiment of FIG. 1 provides an optical device in the form of a waveguide with a core 129 formed of a substrate material. When viewed in cross-section, this waveguide has a lower cladding formed in a substantially rectangular cavity of the substrate, and suppresses the size of the area of the substrate 101 necessary for forming an optical device, compared to a curved cavity. However, it has a structure that is easy to manufacture.

  5A-5E are cross-sectional views illustrating a processing sequence that can be used to form the embodiment of FIG.

  FIG. 5A is a diagram illustrating a semiconductor substrate 201 that can be formed of the same material as the substrate 101 (for example, single crystal silicon).

FIG. 5B is a diagram showing a state in which a protective oxide material 203 (for example, silicon dioxide) is formed on the substrate 201. The oxide material 203 can be grown or formed by deposition or spin coating. The photonic device manufacturing material 213 is formed on the oxide material 203 by, for example, deposition. The photonic device manufacturing material 213 can be single crystal silicon, polycrystalline silicon, amorphous silicon, or other material suitable for forming a photonic device. Such other materials include Si ₃ N ₄ , Si _x N _y , SiO _x N _y , SiC, Si _x Ge _y , GaAs, AlGaAs, InGaAs or InP, where x and y are positive It is an integer (for example, 1, 2, etc.). The material 213 is selected to have a higher refractive index than the surrounding cladding material that will be formed later. FIG. 5B also shows a patterned photoresist 227 provided on top of the photonic device manufacturing material 213.

  FIG. 5C is a diagram showing the structure of FIG. 5B. This figure shows a state after the photonic device manufacturing material 213 is etched using anisotropic wet etching or anisotropic dry etching using the photoresist 227 as a mask, and then the photoresist 227 is removed. ing. A photonic device element (for example, the waveguide core 229) formed of the photonic device manufacturing material 203 remains on the oxide material 203.

  Next, as shown in FIG. 5D, the opening 209 is etched into the oxide material 203 using a patterned photoresist (not shown). The opening 209 partially extends to the substrate 201 to form a trench 211 in the substrate 201. Following this, the substrate 201 is further etched using the techniques and etching materials described above with respect to FIGS. 3G-3K to form a generally rectangular cavity 223 in the substrate. This cavity extends laterally past the side edge of the waveguide core 229. The etchant etches the silicon substrate 201 instead of the protective material 203. The cavity 223 and opening 209 are then filled with an oxide 225 (eg, silicon dioxide) formed by growth, deposition, or spin coating, as shown in FIG. 5E. As shown in FIG. 5F, an oxide 235 (eg, silicon dioxide) is formed on top of the waveguide core 229 so that the oxide lower cladding 225 and the oxide upper cladding 235 completely surround the waveguide core 229. To do. This oxide 235 can be formed separately by the method described below in connection with FIG. 7, or the interlayer used to support the metal wiring pattern for connecting the CMOS and photonic devices. It can be part of insulation (ILD).

  FIG. 6 is a view showing a state in which the embodiment of FIG. 1 is formed on the substrate 101. The substrate 101 has a CMOS circuit formed in a part thereof, and a photonic device (for example, a waveguide) formed in the other part thereof. FIG. 6 also shows that the upper cladding oxide 135 can be formed as part of an interlayer dielectric (ILD) structure that supports one or more metal wiring layers 141. This CMOS circuit is exemplified by a MOSFET transistor 151. The transistor is formed on top of a gate oxide 155 and includes a source region 157 and a drain region 159 with a gate 153 having sidewall spacers 163. This CMOS circuit is isolated by a shallow trench isolation structure 161. This CMOS device (eg, transistor 151) can be formed in the substrate 101 before, after, or during the formation of the waveguide core 129 and its associated oxide-filled cavity 125.

  FIG. 7 is a view showing a state in which the embodiment of FIG. 2 is formed on the substrate 201. The substrate 201 has a CMOS circuit formed in a part thereof, and a photonic device (for example, a waveguide) formed in the other part thereof. FIG. 7 also shows that an upper cladding oxide 135 can be formed as part of an interlayer dielectric (ILD) structure that supports one or more metal wiring layers 141. This CMOS circuit is exemplified by a MOSFET transistor 151. The transistor is formed on top of a gate oxide 155 and includes a source region 157 and a drain region 159 with a gate 153 having sidewall spacers 163. This CMOS circuit is isolated by a shallow trench isolation structure 161. The CMOS device (eg, transistor 151) can be formed in the substrate 201 before, after, or during the formation of the waveguide core 229 and its associated oxide-filled cavity 225.

  As can be understood from FIGS. 6 and 7, the embodiment shown in FIGS. 1 and 2 may be part of a common substrate 101 (201) on which a CMOS circuit and a photonic device and a photonic circuit are formed. it can.

  While exemplary methods and apparatus embodiments of the present invention have been described above, the present invention is not limited to the specific details of these embodiments, and modifications may be made without departing from the concept or scope of the present invention. It is possible. For example, a waveguide with an associated core 129 (229) and surrounding upper and lower oxide claddings have been described and illustrated, but using silicon from the substrate 101 (FIG. 1), or Other photonic devices can also be constructed from the photonic device manufacturing material (FIG. 2). Such photonic devices include light modulators, filters, diffraction gratings, splitters, photodetectors, light emitters, and other photonic devices. The transistor 151 is just an example of various electronic devices and electronic circuits that can be formed in the CMOS region of the substrate 101 (201). Although the silicon substrate has been described in connection with the embodiment of FIG. 1, the substrate 101 can also be formed of other materials suitable for the formation of photonic device elements. Similarly, the silicon substrate 201 described in connection with FIG. 2 may be formed of other materials suitable for supporting photonic devices.

  Accordingly, the invention is not limited by the foregoing description, but is only limited by the scope of the appended claims.

Claims (28)

A method of forming a photonic structure,
Etching a semiconductor substrate to form a cavity having a substantially rectangular cross-sectional shape in the semiconductor substrate, and producing an edge including a part of the semiconductor substrate between the upper surface of the semiconductor substrate and the cavity. And forming a photonic device element from the edge of the semiconductor substrate,
Forming a hard mask on the semiconductor substrate;
Forming a patterned photoresist on top of the hard mask to define trench locations;
Etching the semiconductor substrate through the hard mask to form the trench; and forming an oxide material between the hard mask and the semiconductor substrate;
A method further comprising:   The method of claim 1, wherein the photonic device element comprises a waveguide core.   The method of claim 1, further comprising filling the cavity with a cladding material.   The method of claim 3, wherein the cladding material comprises an oxide.   The method according to claim 4, wherein the semiconductor substrate comprises a silicon substrate.   The method of claim 5, wherein the oxide comprises silicon dioxide. The method of claim 1, further comprising: forming a trench in the surface of the semiconductor substrate using a mask and an initial etch; and forming the cavity using a first isotropic etch through the trench. the method of.   The method of claim 7, further comprising forming an etch protection liner on a sidewall of the trench prior to performing the first isotropic etch.   The method of claim 8, wherein the etch protection liner is comprised of an oxide.   The method according to claim 9, wherein the oxide comprises silicon dioxide.   The method of claim 7, wherein the first isotropic etch comprises a hydroxide etch.   The method of claim 11, wherein the hydroxide etching includes using NH 4 OH or TMAH as an etchant. A method of forming a photonic structure,
Etching the semiconductor substrate to form a cavity having a substantially rectangular cross-sectional shape in the semiconductor substrate, and producing an edge including a part of the semiconductor substrate between the upper surface of the semiconductor substrate and the cavity ; And forming a photonic device element from the edge of the semiconductor substrate,
Forming a trench in the surface of the semiconductor substrate using a mask and an initial etch, and forming the cavity using a first isotropic etch through the trench;
The isotropic etching is composed of hydroxide etching,
Performing a second isotropic etch following the first isotropic etch to etch the cavity. The second isotropic etching includes using buffered fluoride as an etchant.
The method of claim 13.   15. The method of claim 14, wherein the buffered fluoride etch solution is comprised of NH4F, QEII, and H2O2.   The method of claim 13, wherein forming the photonic device element is performed after the second isotropic etching.   The method of claim 2, further comprising forming a cladding material around the top and sides of the photonic device element. The method of claim 17 , wherein the cladding material around the top and side surfaces of the photonic device element comprises an oxide. The method of claim 18 , wherein the oxide comprises silicon dioxide. Selectively forming a hard mask on the semiconductor substrate;
A portion of the semiconductor substrate is formed by etching the semiconductor substrate using the hard mask as a mask to form a trench and expanding the trench to form a cavity having a substantially rectangular cross-sectional shape in the semiconductor substrate. Forming an edge located on the cavity, the edge consisting of
Filling the cavity with an insulator to support the edge; and selectively removing the edge supported by the insulator to form a photonic device element;
Including methods. Forming a cavity having a substantially rectangular cross-sectional shape in the substrate, the cavity being formed so as to leave an edge including a part of the substrate between the upper surface of the substrate and the cavity;
Filling the cavity with an insulating material to support the edge, and filling the cavity with the insulating material to support the edge, and then forming a photonic device element from a portion of the edge;
Including methods. The method of claim 21 , wherein the insulating material is a first cladding material. Forming the cavity in the substrate includes forming a trench extending into the substrate from the top surface of the substrate, and etching the substrate through the trench;
The method of claim 21 , comprising: The method of claim 21, wherein the substrate comprises single crystal silicon. The method of claim 21 , wherein the photonic device element comprises a waveguide core. 26. The method of claim 25 , wherein the waveguide core comprises single crystal silicon. The method of claim 22, wherein the first cladding material comprises an oxide material. 23. The method of claim 22 , further comprising covering the first cladding material and the photonic device element with a second cladding material.

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