CN111562687B

CN111562687B - Method for manufacturing semiconductor device, semiconductor device and semiconductor integrated circuit

Info

Publication number: CN111562687B
Application number: CN202010440338.4A
Authority: CN
Inventors: 朱继光; 何来胜
Original assignee: United Microelectronics Center Co Ltd
Current assignee: United Microelectronics Center Co Ltd
Priority date: 2020-05-22
Filing date: 2020-05-22
Publication date: 2023-06-13
Anticipated expiration: 2040-05-22
Also published as: CN111562687A

Abstract

A method of manufacturing a semiconductor device, and a semiconductor integrated circuit are disclosed. The method comprises the following steps: providing a semiconductor-on-insulator substrate, wherein the semiconductor-on-insulator substrate comprises a first substrate, a first insulating layer and a semiconductor layer; patterning the semiconductor layer to form an optical waveguide; forming at least one functional layer stacked on one another on a side of the semiconductor layer facing away from the first insulating layer, comprising: forming a second insulating layer on one side of the semiconductor layer, which is away from the first insulating layer; bonding the at least one functional layer to a carrier substrate; completely removing the first substrate; and forming a first heat regulating resistor on one side of the first insulating layer, which is far away from the second insulating layer, wherein the orthogonal projection of the first heat regulating resistor on the first insulating layer is at least partially overlapped with the orthogonal projection of the optical waveguide on the first insulating layer.

Description

Method for manufacturing semiconductor device, semiconductor device and semiconductor integrated circuit

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a method of manufacturing a semiconductor device, and a semiconductor integrated circuit.

Background

Silicon photonics utilizes optical signals instead of electrical signals to transmit data. It offers advantages of high integration, high transmission rate, low power consumption, etc., and is thus considered a promising technology. The development of silicon-oriented photo-chip processes based on complementary metal-compound semiconductor (CMOS) processes is the dominant research direction in the industry.

However, CMOS process compatible silicon photofabrication is facing some challenges. For example, to provide an optical transmission channel to a photonic device, a windowing process is required to etch through multiple layers of dielectric material in a silicon photonics chip, resulting in difficulty in large-scale application of the silicon photonics process. In addition, to achieve improved electrical performance (e.g., microwave loss), it may be desirable to sacrifice performance (e.g., structural stability) of other aspects of the silicon photonics chip.

Disclosure of Invention

It would be advantageous to provide a mechanism that alleviates, mitigates or even eliminates one or more of the above problems.

According to some embodiments of the present disclosure, there is provided a method of fabricating a semiconductor device, comprising: providing a semiconductor-on-insulator substrate, wherein the semiconductor-on-insulator substrate comprises a first substrate, a first insulating layer on the first substrate and a semiconductor layer on the first insulating layer; patterning the semiconductor layer to form an optical waveguide; forming at least one functional layer stacked on one another on a side of the semiconductor layer facing away from the first insulating layer, comprising: forming a second insulating layer on a side of the semiconductor layer facing away from the first insulating layer, wherein the first insulating layer and the second insulating layer have a refractive index smaller than that of the semiconductor layer; bonding the at least one functional layer to a carrier substrate on a side of the at least one functional layer facing away from the semiconductor layer; completely removing the first substrate such that no semiconductor material is provided on the entire surface of the first insulating layer facing away from the semiconductor layer; and forming a first heat regulating resistor on one side of the first insulating layer, which is far away from the second insulating layer, wherein the orthogonal projection of the first heat regulating resistor on the first insulating layer is at least partially overlapped with the orthogonal projection of the optical waveguide on the first insulating layer.

According to some embodiments of the present disclosure, there is provided a semiconductor device including: a first insulating layer; a semiconductor layer on the first insulating layer, the semiconductor layer including an optical waveguide; a carrier substrate disposed opposite to the semiconductor layer; at least one functional layer stacked on top of each other between the semiconductor layer and the carrier substrate, the at least one functional layer comprising a second insulating layer on a side of the semiconductor layer facing away from the first insulating layer, wherein the first insulating layer and the second insulating layer have a refractive index smaller than a refractive index of the semiconductor layer; and a first heat regulating resistor positioned on one side of the first insulating layer away from the second insulating layer, wherein the orthogonal projection of the first heat regulating resistor on the first insulating layer at least partially overlaps with the orthogonal projection of the optical waveguide on the first insulating layer; wherein no semiconductor material is provided on the entire surface of the first insulating layer facing away from the semiconductor layer, such that no semiconductor material is provided on the entire surface of the first insulating layer facing away from the semiconductor layer.

According to some embodiments of the present disclosure, there is provided a semiconductor integrated circuit including the semiconductor device as described above.

These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter.

Drawings

Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments, with reference to the following drawings, wherein:

fig. 1 is a flowchart of a method of fabricating a semiconductor device according to an exemplary embodiment of the present disclosure;

fig. 2A through 2K are schematic diagrams of example structures formed by various steps of the method of fig. 1, according to an example embodiment of the present disclosure;

FIG. 3 is a simplified block diagram of a semiconductor integrated circuit according to an exemplary embodiment of the present disclosure; and is also provided with

Fig. 4 is a simplified block diagram of a semiconductor integrated circuit according to another exemplary embodiment of the present disclosure.

Detailed Description

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

Spatially relative terms, such as "under …," "under …," "lower," "under …," "over …," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features. Thus, the exemplary terms "below …" and "below …" may encompass both orientations above … and below …. Terms such as "before …" or "before …" and "after …" or "followed by" may similarly be used, for example, to indicate the order in which light passes through the elements. The device may be oriented in other ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of a and B" means a alone, B alone, or both a and B.

It will be understood that when an element or layer is referred to as being "on," "connected to," "coupled to," or "adjacent to" another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," or "directly adjacent to" another element or layer, there are no intervening elements or layers present. However, in no event "on …" or "directly on …" should be construed as requiring one layer to completely cover an underlying layer.

Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In conventional CMOS process compatible silicon photofabrication processes, there are typically layers of dielectric material such as SiN or SiCN between the different metal layers, which undesirably block the penetration of light. Therefore, a special mask is often required to etch away these dielectric material layers in order to open the areas requiring light transmission (referred to as a "windowing process"). The windowing process requires etching through multiple layers of dielectric material, making large-scale applications of silicon photofabrication difficult. In addition, in a silicon optical chip integrated with an active device, in order to achieve reduced microwave loss, improved impedance matching, and refractive index matching, such a solution has been proposed: a via is provided that extends from the front side of the silicon photonics chip into the silicon substrate and empties a portion of the silicon substrate under the active device. However, this may lead to deterioration of structural stability of the silicon photo chip.

Embodiments of the present disclosure provide a semiconductor process architecture in which after a front side process is completed on a semiconductor-on-insulator (semiconductor-on-insulator) substrate, the device is bonded from the front side to another carrier substrate and then the underlying substrate material in the semiconductor-on-insulator substrate is completely removed. This provides a solution that can improve the optical and/or electrical properties of the resulting semiconductor device, enabling large scale mass production of semiconductor-based photonic devices.

As used herein, the term "substrate" may refer to a substrate of a diced wafer, or may refer to a substrate of an uncut wafer. Similarly, the terms chip and die may be used interchangeably unless such an interchange would cause a conflict. It should be understood that the term "layer" includes films and should not be construed to indicate vertical or horizontal thickness unless otherwise indicated.

Fig. 1 is a flowchart of a method 100 of fabricating a semiconductor device according to an exemplary embodiment of the present disclosure, and fig. 2A through 2K are schematic diagrams of example structures formed by various steps of the method 100. The method 100 is described below with reference to fig. 1 and 2A-2K.

In step 110, a semiconductor-on-insulator substrate 210 is provided. As shown in fig. 2A, the semiconductor-on-insulator substrate 210 includes a first substrate 211, a first insulating layer 212 on the first substrate 211, and a semiconductor layer 213 on the first insulating layer 212.

Substrate 210 may be any type of semiconductor-on-insulator substrate. In some embodiments, the semiconductor-on-insulator substrate 210 may be a silicon-on-insulator (SOI) substrate. SOI substrates are commercially available and have good characteristics for integrated photonic devices. In such an embodiment, the first substrate 211 may be made of any suitable material (e.g., silicon or germanium). In an example, the first substrate 211 may have a thickness of about 725 um. The first insulating layer 212 may be made of any suitable insulating material (e.g., silicon dioxide) and, in some embodiments, may be generally referred to as a Buried Oxide (BOX) layer. In an example, the first insulating layer 212 may have a thickness of about 2 um. The semiconductor layer 213 may be referred to as a semiconductor device layer in which various semiconductor components are formed. In some embodiments, the semiconductor layer 213 may be made of silicon, but the disclosure is not limited thereto. In an example, the semiconductor layer 213 may have a thickness of about 220 nm. In this context, referring to the orientation shown in fig. 2A, the upper side of the first insulating layer 212 is referred to as the front side, and the lower side of the first insulating layer 212 is referred to as the back side.

At step 120, the semiconductor layer 213 is patterned to form an optical waveguide 217, for example, as shown in fig. 2B and 2C. Fig. 2B schematically shows an arrangement of the semiconductor-on-insulator substrate 210 and the optical waveguide 217 (and a grating coupler 215 to be described later) when seen from above. Fig. 2C schematically shows a cross-sectional view taken along line AA in fig. 2B, wherein optional features 216 and 218 (described later) are shown in addition to the grating coupler 215 and the optical waveguide 217.

The optical waveguide 217 may be optically coupled to the grating coupler 215 as shown in fig. 2B and 2C. In the example of fig. 2C, the optical waveguide 217 is formed as a ridge optical waveguide including an inner ridge region that is thicker and an outer ridge region that is thinner on both sides of the inner ridge region, but the disclosure is not limited thereto. Additionally or alternatively, a variety of other photonic devices may be formed in semiconductor layer 213, such as a strip optical waveguide, an end-face coupler, a waveguide-interleaver, or a beam splitter. A wide variety of optical waveguide-based active devices may also be formed, such as electro-optic modulators, thermo-optic modulators, electro-absorption modulators, or photodetectors.

After the semiconductor layer 213 is patterned, the removed portions of the semiconductor layer 213 may be filled with a suitable dielectric material (e.g., silicon dioxide) to prevent voids in the semiconductor layer 213. In an example, silicon dioxide may be deposited in the patterned semiconductor layer 213 by a High Density Plasma (HDP) deposition process.

In some embodiments, step 120 may further comprise: prior to the formation of the at least one functional layer stacked on top of each other, the semiconductor layer 213 is patterned to form a grating coupler 215. The grating coupler 215 may be optically coupled to the optical waveguide 217, wherein the complete removal of the first substrate is such that an optical transmission channel is provided between the grating coupler 215 and an outside of the semiconductor device on the side of the first insulating layer 212 facing away from the semiconductor layer 213, via the first insulating layer 212, and not via the first substrate, as shown in fig. 2B and 2C. In the example of fig. 2C, in embodiments in which semiconductor layer 213 is made of silicon, silicon grating coupler 215 may be fabricated using any suitable micromachining process (e.g., bulk silicon processing). In the case of a bulk silicon processing process, a portion of the silicon material is selectively removed in the semiconductor (silicon) layer 213 in accordance with the design pattern, forming a designed miniature three-dimensional structure, as illustrated in fig. 2C. In particular, the patterning process of the silicon grating may include etching, such as wet etching and dry etching. Wet etching can be classified into isotropic etching and anisotropic etching depending on the etching rates in the etching liquid along different crystal directions. Dry etching employs physical methods (e.g., sputtering, ion etching) or chemical methods (e.g., reactive ion etching). It will be appreciated that the grating coupler 215 shown in fig. 2B and 2C is merely exemplary, and that in other embodiments, the grating coupler 215 may take any other suitable form.

At step 130, at least one functional layer is formed on the side of the semiconductor layer 213 facing away from the first insulating layer 212. Forming the at least one functional layer stacked on each other may include: a second insulating layer 221 is formed on a side of the semiconductor layer 213 facing away from the first insulating layer 212, wherein the first insulating layer 212 and the second insulating layer 221 have a refractive index smaller than that of the semiconductor layer 213, for example, as shown in fig. 2D. Examples of the first insulating layer 212 and the second insulating layer 221 include, but are not limited to, silicon dioxide. In embodiments in which the optical waveguide 217 is patterned in the semiconductor layer 213, the presence of the first insulating layer 212 and the second insulating layer 221 may provide conditions for total internal reflection of the optical signal in the optical waveguide 217, improving optical transmission efficiency. The silicon dioxide may also provide passivation for semiconductor material (e.g., silicon) in the semiconductor layer 213. In some examples, the second insulating layer 221 may be formed by Plasma Enhanced Chemical Vapor Deposition (PECVD).

As used herein, the term "functional layer" may refer to any suitable layer having electrical and/or optical functionality. By way of example and not limitation, the functional layer may include a conductive layer in which elements such as leads, electrodes, and/or antennas are formed and/or an insulating layer for providing insulation.

In addition to the second insulating layer 221, additional functional layers may be formed according to specific device design requirements, as will be discussed later. For descriptive purposes, some examples of additional functional layers are listed herein: a second patterned conductive layer 222, an inter-layer dielectric (IDL) 223,

electrode structures

224 and 225 comprising two layers of metal (M1 and M2), and a plurality of inter-metal dielectric (IMD) layers formed by repeated stacks of a first dielectric layer 226 and a second dielectric layer 227, as shown in fig. 2D. These additional functional layers will be described in detail later in connection with a specific active photonic device.

In the example of fig. 2D, at least one functional layer includes a second dielectric layer 227 as an uppermost layer. The uppermost second dielectric layer 227 is also referred to in this context as a third insulating layer. The third insulating layer may be made of oxide (e.g., silicon dioxide). In some embodiments, the thickness of the third insulating layer may be adjustable. This may be achieved by, for example, oxide deposition and planarization (e.g., chemical Mechanical Polishing (CMP)). A third insulating layer with an adjustable thickness may be advantageous for some photonic devices. For example, for an end-face coupler, the cladding thickness on the upper and lower sides of semiconductor layer 213 can affect the coupling efficiency. By adjusting (thickening or thinning) the thickness of the third insulating layer to a desired thickness, the coupling efficiency of the end-face coupler can be improved.

It will be appreciated that although fig. 2D illustrates an exemplary plurality of functional layers, the type and/or number of functional layers that need to be formed may be determined according to particular applications and/or requirements.

At step 140, at least one functional layer is bonded to carrier substrate 240 on a side of the at least one functional layer facing away from semiconductor layer 213, for example, as shown in fig. 2E.

Step 140 may be accomplished by a normal bonding process. In the example of fig. 2E, the structure shown in fig. 2D is now flipped so that the third insulating layer 227 located uppermost in fig. 2D is now located lowermost for bonding with the carrier substrate 240. In some embodiments, carrier substrate 240 may include a silicon substrate and a silicon dioxide layer on the silicon substrate. In this case, the third insulating layer 227 (made of, for example, silicon oxide) may be bonded to the silicon oxide layer in the carrier substrate 240 using a low temperature bonding process. After the bonding is completed, the semiconductor device structure shown in fig. 2E may be subjected to a so-called backside process.

At step 150, the first substrate 211 is completely removed such that no semiconductor material is provided on the entire surface of the first insulating layer 212 facing away from the semiconductor layer 213, for example, as shown in fig. 2E and 2F.

In some embodiments, step 150 may be implemented by etching. In an embodiment in which the first insulating layer 212 is made of silicon dioxide and the semiconductor layer 213 is made of silicon, etching may be performed using a tetramethylammonium hydroxide (TMAH) solution having a high selectivity to silicon dioxide. Alternatively, the first substrate 211 may be thinned by wet etching, and then the first substrate 211 is completely removed using dry etching. After step 150, the first substrate 211 is completely removed and the first insulating layer 212 is exposed, as shown in fig. 2F. Fig. 2F also shows some additional details (e.g., back hole 251), which will be further described later.

The complete removal of the first substrate 211 enables the grating coupler 215 in the semiconductor layer 213 to couple in and/or out optical signals from the back side without being affected by the front side dielectric material layer, thereby eliminating the need for a windowing process from the front side. As a result, the metal wiring is not limited any more at the front side of the grating coupler 215, providing a higher degree of freedom of design. Moreover, complete removal of the first substrate 211 may optimize the performance of the active device, e.g., reduced microwave loss, improved impedance matching, and index matching. Such optimization provides additional advantages over the related art of drilling from the front side and then hollowing out a portion of the substrate, such as simple process, structural robustness. In summary, the method 100 may provide a versatile process platform that facilitates large scale mass production of semiconductor photonic devices.

At step 160, a first thermistor 241 is formed on a side of the first insulating layer 212 facing away from the second insulating layer 211, and an orthogonal projection of the first thermistor 241 onto the first insulating layer 212 at least partially overlaps an orthogonal projection of the optical waveguide 217 onto the first insulating layer 212, for example, as shown in fig. 2I. Thus, both the first heat regulating resistor 241 disposed on the back side of the optical waveguide 217 and the optical waveguide 217 form a thermo-optic modulator, wherein the first heat regulating resistor 241 acts as a heat source which transfers heat to the optical waveguide 217 when a modulation signal is applied, thereby affecting its mode field distribution, effecting a change in optical field phase. For clarity of illustration, electrical connection to the first thermally tuned resistor 241 is not shown in these figures, but it will be appreciated that electrical connection may be provided to the first thermally tuned resistor 241 by any suitable means (e.g., a window is opened in passivation layer 265 overlying the first thermally tuned resistor 241 to expose the first thermally tuned resistor 241 so that an external modulation signal can be applied directly to the first thermally tuned resistor 241 as will be described below). In an example, the first heat adjustment resistor 241 may be made of titanium nitride, but the present disclosure is not limited thereto.

In some embodiments, the forming the first heat resistor 241 may include: forming a first conductive layer 264 on a side of the first insulating layer 212 facing away from the second insulating layer 221; and patterning the first conductive layer 264 to form a first patterned conductive layer including the first heat resistor 241, for example, as shown in fig. 2H and 2I.

In some embodiments, patterning the first conductive layer 264 may include: forming a patterned photoresist 301 on a side of the first conductive layer 264 facing away from the first insulating layer 212, the patterned photoresist 301 defining a pattern of the first thermal resistor 241, for example, as shown in fig. 2H; etching the first conductive layer 264 with the patterned photoresist 301 to form a first thermally tuned resistor 241; and stripping the patterned photoresist 301, for example, as shown in fig. 2H and 2I. The first conductive layer 264 may be etched using, but is not limited to, a hydrofluoric acid etching solution.

In some embodiments, the method may further comprise: prior to stripping the patterned photoresist 301, the first insulating layer 212 located in the peripheral region of the first thermistor 241 is thinned to form a thermally insulating region 302 around the periphery of the first thermistor 241, for example, as shown in fig. 2I. So that the heat generated by the first heat regulating resistor 241 can be weakened to spread to the periphery along the transverse direction, so that more heat can be transferred to the optical waveguide 217 along the longitudinal direction, and the heat-light modulation efficiency is improved. In an example, the first insulating layer 212 having a certain thickness may be removed by an etching process of the first conductive layer 264 to be thinned, and a manufacturing process can be simplified. For example, the over etching may be performed by appropriately extending a process time for etching the first conductive layer 264 to remove the first insulating layer 212 having a certain thickness.

In some embodiments, the method 100 may further comprise: after the first substrate 211 is completely removed, the thickness of the first insulating layer 212 is adjusted. In the case where a thicker first insulating layer 212 is required, the first insulating layer 212 may be thickened by an appropriate process. In an example, a material of the first insulating layer 212 is deposited on the first insulating layer 212, and then the deposited material is planarized such that the first insulating layer 212 on which the material is deposited has a predetermined thickness. For example, the original first insulating layer 212 is made of silicon dioxide and has a thickness of 2um, in which case if a thicker first insulating layer 212 is required, a silicon dioxide material may be deposited on the first insulating layer 212, and the deposited silicon dioxide may then be planarized by a CMP process. The resulting first insulating layer 212 may have a thickness of, for example, greater than 2um and less than or equal to 6 um. Of course, in the case where a thinner first insulating layer 212 is required, the first insulating layer 212 may be directly thinned to a desired thickness by an appropriate process (e.g., CMP). The first insulating layer 212 having an adjustable thickness may be advantageous for some specific applications. For example, for an end-face coupler, the cladding thickness on the upper and lower sides of semiconductor layer 213 can affect the coupling efficiency. By thickening the first insulating layer 212, the cladding layers on the upper and lower sides of the semiconductor layer 213 can be made to have approximately equal thicknesses, thereby improving the coupling efficiency of the end-face coupler. For another example, for active photonic devices, a thinner first insulating layer 212 may be advantageous for heat dissipation.

In some embodiments, the method 100 may further comprise: a metal wiring layer 262 is formed on the side of the first insulating layer 212 facing away from the semiconductor layer 213. As shown in fig. 2G, the orthogonal projection of the metal wiring layer 262 onto the carrier substrate 240 does not overlap with the orthogonal projection of the grating coupler 215 onto the carrier substrate 240. This ensures that the back side of the grating coupler 215 is free of metal wiring, thereby preventing the coupling efficiency of the grating coupler 215 from being affected. The metal wiring layer 262 may be formed of any suitable metal (e.g., aluminum). In some embodiments, an oxidation resistant layer may be provided to prevent oxidation of the metal wiring layer 262. In the example of fig. 2G, a first oxidation preventing layer 261, a metal wiring layer 262, and a second oxidation preventing layer 263 are formed stacked in this order in a direction away from the first insulating layer 212 such that the metal wiring layer 262 is sandwiched between the upper and lower

oxidation preventing layers

261 and 263. The oxidation

resistant layers

261 and 263 may be formed of any suitable material (e.g., titanium nitride).

In some embodiments, the metal wiring layer 262 may include a metal isolation frame 270, as shown in fig. 2G. Fig. 2G also shows some additional details, such as the oxidation

resistant layers

261 and 263 described above. The metal isolation frame 270 is used to prevent the optical signals to/from the grating coupler 215 from interfering with other optical elements (e.g., another grating). Fig. 2J schematically shows a top view of the metal spacer 270 and the grating coupler 215. As shown in fig. 2J, the orthogonal projection of the metal isolation frame 270 onto the carrier substrate 240 encloses the orthogonal projection of the grating coupler 215 onto the carrier substrate 240. The metal isolation frame 270 may be formed by patterning the metal wiring layer 262 (and potentially the oxidation resistant layers 261 and 263). After patterning, sidewalls of the metal pattern (e.g., metal isolation frame 270) in the metal wiring layer 262 are exposed. To protect these sidewalls from oxidation, a passivation layer 265 may be further covered on the patterned metal wiring layer 262, as shown in fig. 2K. Passivation layer 265 may be formed of any suitable material (e.g., silicon dioxide).

Embodiments of the method 100 are generally described above in which passive photonic devices (e.g., grating coupler 215 and/or optical waveguide 217) are formed in the semiconductor layer 213. As a semiconductor photonic device process platform, method 100 may be used to fabricate a variety of active photonic devices based on optical waveguides, such as electro-optic modulators and thermo-optic modulators. Such an embodiment of the method 100 is described below.

Referring back to fig. 2C, the method 100 may further include: at least one of the first region 216 and the second region 218 of the semiconductor layer 213, which are respectively located at both sides of the optical waveguide 217, is doped before forming at least one functional layer stacked on each other. Orthogonal projections of the first region 216 and the second region 218 on the first insulating layer 212 are contiguous and non-overlapping with orthogonal projections of the optical waveguide 217 on the first insulating layer 212. In some embodiments, the portion of the optical waveguide 217 between the first region 216 and the second region 218 (hereinafter referred to as the "modulated portion") may also be doped. The first region 216 and the second region 218 (and optionally the modulated portion of the optical waveguide 217) may be doped to a particular type (P-type or N-type, heavily doped or lightly doped) depending on the particular active photonic device to be formed. In an exemplary embodiment forming an electro-optic modulator, the first region 216 and a sub-portion of the modulated portion that adjoins the first region 216 may be doped to one of a P-type semiconductor and an N-type semiconductor, while the second region 218 and a sub-portion of the modulated portion that adjoins the second region 218 may be doped to the other of the P-type semiconductor and the N-type semiconductor. Thus, the first region 216, the modulated parts and the second region 218 form a PN junction. By applying the modulation signal to the first region 216 and the second region 218, the carrier concentration in the modulated portion of the optical waveguide 217 can be changed. This in turn causes the refractive index of the modulated portion of the optical waveguide 217 to change, thereby effecting modulation of light. It will be appreciated that in other embodiments, the electro-optic modulator may be formed in other forms by employing other electrical structures, such as a MOS capacitor modulator (in which an oxide barrier (oxide barrier) is inserted into the modulated portion of the optical waveguide 217 to form a capacitive structure between the first region 216 and the second region 218) or a PIN modulator (in which the modulated portion of the optical waveguide 217 is undoped). It will also be appreciated that the electro-optic modulator may employ various optical structures, such as Mach-Zehnder interferometers (MZIs) or micro-ring resonators (MRRs). In an exemplary embodiment forming a thermo-optic modulator, the first region 216 and the second region 218 may be doped to a heavily doped N-type semiconductor, and the modulated portion of the optical waveguide 217 may be undoped or doped to a lightly doped N-type semiconductor. By applying the modulation signal in the first region 216 and the second region 218, the modulated portion of the optical waveguide 217 can be caused to generate heat, thereby changing the phase of the optical field in the optical waveguide 217. It will be appreciated that in other embodiments, the thermo-optic modulator may be formed in other forms by employing other electrical structures. For example, only the first region 216 (or the second region 218) is lightly doped, and heat may be generated by applying a modulation signal across the first region 216 (or the second region 218). The generated heat may be conducted to the modulated portion of the optical waveguide 217 proximate to the first region 216 (or the second region 218) to change the phase of the optical field in the optical waveguide 217. It will be appreciated that the modulated portion of the optical waveguide 217, whether an electro-optic modulator or a thermo-optic modulator, may occupy only a section of the optical waveguide 217 along the direction of light propagation.

Then, the step 130 of forming at least one functional layer stacked on each other may further include: a second patterned conductive layer 222 is formed on the side of the second insulating layer 221 facing away from the semiconductor layer 213, as shown in fig. 2D. As will be described below, the second patterned conductive layer 222 may include different pattern portions to act as an etch stop layer and/or a heat source (of a thermo-optic modulator). As shown in fig. 2D, an interlayer dielectric 223 is formed overlying the second patterned conductive layer 222.

In some embodiments, the second patterned conductive layer 222 may include a second heat resistor 222b. The orthogonal projection of the second heat regulating resistor 222b onto the first insulating layer 212 at least partially overlaps the orthogonal projection of the optical waveguide 217 onto the first insulating layer 212, as shown in fig. 2D-2I and 2K. In such embodiments, both the second thermal resistor 222b and the optical waveguide 217 can also form a thermo-optic modulator, wherein the second thermal resistor 222b acts as a heat source that transfers heat to the optical waveguide 217 when a modulation signal is applied, thereby affecting its mode field distribution, effecting a change in optical field phase. Thus, the thermo-optical modulation efficiency can be improved by forming the second heat adjustment resistor 222b and the first heat adjustment resistor 241 on the front surface and the back surface of the optical waveguide 217, respectively. For clarity of illustration, electrical connection to second heat adjustment resistor 222b is not shown in these figures, but it will be appreciated that electrical connection may be provided to second heat adjustment resistor 222b by any suitable means (e.g., metal interconnects similar to

electrode structures

224 and 225 and back hole 251). In an example, the second heat adjustment resistor 222b may be made of titanium nitride, but the disclosure is not limited thereto.

Next, respective contact holes 231 and 232 are formed through the second insulating layer 221 (in the example of fig. 2D, along with the interlayer dielectric layer 223) and electrically connected with respective ones of the first and

second regions

216 and 218. In an embodiment, the contact holes 231 and 232 may be filled with a conductive material (e.g., tungsten or copper) to provide electrical connectivity.

Then, the step 130 of forming at least one functional layer stacked on each other may further include:

respective electrode structures

224 and 225 are formed on a side of the second patterned conductive layer 222 facing away from the second insulating layer 221. The corresponding

electrode structures

224 and 225 are electrically connected to corresponding contact holes 231 and 232, respectively, as shown in fig. 2D. In the example of fig. 2D,

electrode structures

224 and 225 are formed as a stack of two layers of metals M1 and M2, but in other embodiments,

electrode structures

224 and 225 may be formed as fewer or more layers of metals. The layers of metals M1 and M2 are electrically connected to each other through vias filled with a conductive material (e.g., copper). A plurality of inter-metal dielectric layers (IMDs) formed from repeated stacks of first dielectric layer 226 and second dielectric layer 227 provide electrical isolation between the metal layers. In an example, the first dielectric layer 226 may be made of silicon nitride and the second dielectric layer 227 may be made of silicon dioxide. Silicon nitride has a good passivation effect, but after its deposition, the defect density at the interface is high. Silicon dioxide has a passivation effect inferior to silicon nitride, but after its deposition, the defect density at the interface is lower. Therefore, the stacked structure using silicon nitride and silicon dioxide provides a combined advantage of both, thereby obtaining a good interlayer insulating effect.

Still referring to fig. 2D, the second patterned conductive layer 222 may include respective first pattern portions 222a corresponding to

respective electrode structures

224 and 225, instead of or in addition to the second heat-regulating resistor 222 b. Although only one first pattern portion 222a corresponding to the electrode structure 225 is shown in the cross-sectional view of fig. 2D, it will be appreciated that there may be another first pattern portion 222a corresponding to the electrode structure 224 in another, different cross-section. The orthogonal projection of each of the respective first pattern portions 222a onto the first insulating layer 212 partially overlaps with the orthogonal projection of a corresponding one of the

respective electrode structures

224 and 225 onto the first insulating layer 212, as shown in fig. 2E. In an embodiment in which the second patterned conductive layer 222 includes both the first pattern portion 222a and the second heat-regulating resistor 222b, the first pattern portion 222a and the second heat-regulating resistor 222b may be simultaneously formed by patterning a layer of conductive material once, thereby simplifying the process.

To provide electrical connection to electrode

structures

224 and 225, a plurality of back holes 251 may be formed from the back side, as shown in fig. 2F. In such an embodiment, the method 100 further comprises: a plurality of back holes 251 are formed by etching, extending from the surface of the first insulating layer 212 facing away from the semiconductor layer 213 to the corresponding first pattern portions 222a. The respective first pattern portions 222a serve as an etch stop layer for the plurality of back holes 251. The etching is then continued such that the plurality of back holes 251 extend through the respective first pattern portions 222a and to the

respective electrode structures

224 and 225. In an embodiment, the plurality of back holes 251 may be filled with a conductive material (e.g., tungsten or copper) to provide electrical connectivity. The presence of the first pattern portion 222a provides advantageous advantages over the case without the etch stop layer. Without the first pattern portion 222a, the etching process would stop directly at the metal layer M1, resulting in excessive loss of electrode material and thus possible electrical defects. Due to the presence of the first pattern portion 222a, etching of the back hole 251 is completed in two stages, thereby allowing more precise control of the amount of loss of the electrode material and thus improving the yield of the product. In some examples, the first pattern portion 222a may be about 150nm from the metal layer M1. It will be appreciated that although only two back holes 251 corresponding to electrode structures 225 are shown in the cross-sectional view of fig. 2F, there may be additional back holes 251 corresponding to electrode structures 224 in a different cross-section. It will also be appreciated that the number of back holes 251 connected to each electrode structure need not be two, but may be fewer or greater.

After forming the back hole 251, the method 100 may further include: on the side of the first insulating layer 212 facing away from the semiconductor layer 213, respective pads 260 are formed, which respective pads 260 are electrically connected to the

respective electrode structures

224 and 225 via corresponding ones of the plurality of back holes 251, respectively. Fig. 2G and 2K show an example structure of the pad 260. In this example, forming the respective pads includes: a first oxidation preventing layer 261, a metal wiring layer 262, and a second oxidation preventing layer 263, which are sequentially stacked in a direction away from the first insulating layer 212, are formed; patterning the first oxidation preventing layer 261, the metal wiring layer 262 and the second oxidation preventing layer 263 to form corresponding pad regions; forming a passivation layer 265 covering the patterned second oxidation resistant layer 263; and removing a portion of the passivation layer 265 and the second oxidation resistant layer 263 in each pad region to expose a portion of the metal wiring layer 262 in the pad region. As shown in fig. 2K, the pad 260 is provided with a window 266 so that an external modulation signal can be directly applied to the metal wiring layer 262 in the pad 260 and transmitted to the first region 216 and the second region 218 in the semiconductor layer 213 through the back hole 251, the

electrode structures

224 and 225, and the contact holes 231 and 232, achieving electro-optic modulation or thermo-optic modulation as described above. It will be appreciated that although only the pads 260 corresponding to the electrode structures 225 are shown in the cross-sectional view of fig. 2G, there may be additional pads 260 corresponding to the electrode structures 224 in a different cross-section.

Method 100 and its various variations are described above with respect to fig. 1 and 2A-2K. It will be appreciated that these operations need not be performed in the particular order described, nor are all of the described operations necessarily performed to achieve desirable results. For example, the step of forming the grating coupler 215 may be performed before the step of forming the optical waveguide 217. For another example, the step of forming the metal spacer frame 270 may be omitted.

Having described embodiments for a method of fabricating a semiconductor device, the structure of the resulting semiconductor device will become apparent. Hereinafter, for completeness, an exemplary embodiment of a semiconductor device is described in connection with fig. 2I. The semiconductor device embodiments provide the same or corresponding advantages as the method embodiments, and detailed descriptions of these advantages are omitted for the sake of brevity.

As shown in fig. 2K, the semiconductor device 200 includes: the semiconductor device includes a first insulating layer 212, a semiconductor layer 213 stacked with the first insulating layer 212, a carrier substrate 240 disposed opposite to the semiconductor layer 213, at least one functional layer stacked with each other between the semiconductor layer 213 and the carrier substrate 240, and a first patterned conductive layer. The semiconductor layer 213 includes an optical waveguide 217. The semiconductor material is not provided on the entire surface of the first insulating layer 212 facing away from the semiconductor layer 213, so that the semiconductor material is not provided on the entire surface of the first insulating layer 212 facing away from the semiconductor layer 213. The at least one functional layer comprises a second insulating layer 221 on the side of the semiconductor layer 213 facing away from the first insulating layer 212, wherein the first insulating layer 212 and the second insulating layer 221 have a refractive index which is smaller than the refractive index of the semiconductor layer 213. The first patterned conductive layer includes a first heat resistor 241 on a side of the first insulating layer 212 facing away from the second insulating layer 221.

In some embodiments, the semiconductor layer 213 may further include: the complete removal of the first substrate enables an optical transmission channel to be provided between the grating coupler 215 and the outside of the semiconductor device on the side of the first insulating layer 212 facing away from the semiconductor layer 213, via the first insulating layer 212, without via the semiconductor material, whereby the grating coupling efficiency can be improved. In some examples, the first insulating layer 212 may have a thickness of 2um to 6 um.

In some embodiments, at least a portion of the first insulating layer 212 located at a peripheral region of the first thermistor 241 is etched away to a thickness to form a thermally insulating region 302 at the periphery of the first thermistor 241, for example, as shown in FIG. 2I. So that the heat generated by the first heat regulating resistor 241 can be weakened to spread to the periphery along the transverse direction, so that more heat can be transferred to the optical waveguide 217 along the longitudinal direction, and the heat-light modulation efficiency is improved.

In some embodiments, the at least one functional layer may further comprise: a second patterned conductive layer 222 on a side of the second insulating layer 221 facing away from the semiconductor layer 213.

In some embodiments, the second patterned conductive layer 222 may include a second heat resistor 222b. The orthogonal projection of the second heat regulating resistor 222b on the first insulating layer 212 at least partially overlaps with the orthogonal projection of the optical waveguide 217 on the first insulating layer 212.

In some embodiments, the semiconductor layer 213 may include: a first doped region 216 and a second doped region 218, one on each side of the optical waveguide 217. The orthogonal projections of the first doped region 216 and the second doped region 218 on the first insulating layer 212 are contiguous and non-overlapping with the orthogonal projection of the optical waveguide 217 on the first insulating layer 212. The semiconductor device 200 may further include: respective contact holes 231 and 232 penetrating the second insulating layer 221 and electrically connected to respective ones of the first and second

doped regions

216 and 218. The at least one functional layer may further include: and corresponding

electrode structures

224 and 225 on a side of the second patterned conductive layer 222 facing away from the second insulating layer 221. The corresponding

electrode structures

224 and 225 are electrically connected to the corresponding contact holes 231 and 232, respectively.

In some embodiments, the second patterned conductive layer 222 may include: corresponding to the respective first pattern portions 222a of the

respective electrode structures

224 and 225. The orthogonal projection of each of the respective first pattern portions 222a onto the first insulating layer 212 partially overlaps with the orthogonal projection of a corresponding one of the

respective electrode structures

224 and 225 onto the first insulating layer 212. The semiconductor device 200 may further include a plurality of back holes 251 and corresponding pads 260. A plurality of back holes 251 extend from a surface of the first insulating layer 212 facing away from the semiconductor layer 213 to the

respective electrode structures

224 and 225. The respective pads 260 are located on a side of the first insulating layer 212 facing away from the semiconductor layer 213 and are electrically connected to the

respective electrode structures

224 and 225 via corresponding ones of the plurality of back holes 251, respectively.

In some embodiments, the corresponding pads 260 may include: the first oxidation preventing layer 261, the metal wiring layer 262, and the second oxidation preventing layer 263 are stacked in this order in a direction away from the first insulating layer 212. The semiconductor device 200 may further include: a passivation layer 265 covering the second oxidation resistant layer 263. The passivation layer 265 and the second oxidation resistant layer 263 in each pad are provided with a window 266 to expose a portion of the metal wiring layer 262 in the pad.

In some embodiments, the semiconductor device 200 may further include a metal wiring layer 262. The metal wiring layer 262 is located on the side of the first insulating layer 212 facing away from the semiconductor layer 213. The orthogonal projection of the metal wiring layer 262 onto the carrier substrate 240 does not overlap with the orthogonal projection of the grating coupler 215 onto the carrier substrate 240.

In some embodiments, the metal wiring layer 262 may include a metal isolation frame 270. The orthogonal projection of the metal isolation frame 270 onto the carrier substrate 240 encloses the orthogonal projection of the grating coupler 215 onto the carrier substrate 240.

Fig. 3 is a simplified block diagram of a semiconductor integrated circuit 300 in which both electronic and photonic devices are fabricated on a single hybrid die (hybrid die) according to an exemplary embodiment of the present disclosure. In one example, the semiconductor integrated circuit 300 includes a single hybrid communication module made of a silicon material. The module includes a substrate member 310 having a surface area, an electrical silicon circuit 320 overlying a first portion of the surface area, a silicon photonic device 330 overlying a second portion of the surface area, a communication bus coupled between the electrical silicon circuit 320 and the silicon photonic device 330, an optical interface 331 coupled to the silicon photonic device 330, and an electrical interface 321 coupled to the electrical silicon circuit 320. Silicon photonic device 330 may embody any of semiconductor device 200 and variations thereof described above with respect to fig. 2I.

Fig. 4 is a simplified block diagram of a semiconductor integrated circuit 400 according to an exemplary embodiment of the present disclosure. In one example, the semiconductor integrated circuit 400 includes a single hybrid communication module. The module includes a substrate member 410 having a surface area, which may be a Printed Circuit Board (PCB) or other member. The module includes an electrical silicon circuit 420 overlaying a first portion of the surface area, a silicon photonic device 430 overlaying a second portion of the surface area, a communication bus 440 (e.g., PCB trace) coupled between the electrical silicon circuit 420 and the silicon photonic device 430, an optical interface 431 coupled to the silicon photonic device 430, and an electrical interface 421 coupled to the electrical silicon circuit 420. The silicon photonic device 430 may embody any of the semiconductor devices 200 and variations thereof described above with respect to fig. 2I.

While the disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative and schematic and not restrictive; the present disclosure is not limited to the disclosed embodiments. Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed subject matter, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps than those listed and the indefinite article "a" or "an" does not exclude a plurality, and the term "plurality" means two or more. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A method of fabricating a semiconductor device, comprising:

providing a semiconductor-on-insulator substrate, wherein the semiconductor-on-insulator substrate comprises a first substrate, a first insulating layer on the first substrate and a semiconductor layer on the first insulating layer;

patterning the semiconductor layer to form an optical waveguide;

forming at least one functional layer stacked on one another on a side of the semiconductor layer facing away from the first insulating layer, comprising: forming a second insulating layer on a side of the semiconductor layer facing away from the first insulating layer, wherein the first insulating layer and the second insulating layer have a refractive index smaller than that of the semiconductor layer;

bonding the at least one functional layer to a carrier substrate on a side of the at least one functional layer facing away from the semiconductor layer;

completely removing the first substrate such that no semiconductor material is provided on the entire surface of the first insulating layer facing away from the semiconductor layer; and

a first thermal resistor is formed on a side of the first insulating layer facing away from the second insulating layer, and an orthogonal projection of the first thermal resistor onto the first insulating layer at least partially overlaps an orthogonal projection of the optical waveguide onto the first insulating layer.

2. The method of claim 1, wherein the forming a first thermally tuned resistor comprises:

forming a first conductive layer on one side of the first insulating layer away from the second insulating layer; and

patterning the first conductive layer to form a first patterned conductive layer, the first patterned conductive layer including the first thermally tuned resistor.

3. The method of claim 2, wherein the patterning the first conductive layer comprises:

forming a patterned photoresist on a side of the first conductive layer facing away from the first insulating layer, the patterned photoresist defining a pattern of the first heat regulating resistor;

etching the first conductive layer with the patterned photoresist to form the first heat-regulating resistor; and

and stripping the patterned photoresist.

4. A method as in claim 3, further comprising:

the first insulating layer in the peripheral region of the first heat-regulating resistor is thinned to form a heat-insulating region around the first heat-regulating resistor before stripping the patterned photoresist.

5. The method of claim 1, wherein the forming at least one functional layer stacked on top of each other further comprises:

And forming a second patterned conductive layer on one side of the second insulating layer, which is away from the semiconductor layer.

6. The method of claim 5, wherein the second patterned conductive layer comprises a second thermistor, wherein an orthogonal projection of the second thermistor onto the first insulating layer at least partially overlaps an orthogonal projection of the optical waveguide onto the first insulating layer.

7. The method of claim 5, further comprising:

doping at least one of a first region and a second region of the semiconductor layer, which are respectively located at both sides of the optical waveguide, before the formation of the at least one functional layer stacked on each other, wherein orthogonal projections of the first region and the second region on the first insulating layer are adjacent to and do not overlap with orthogonal projections of the optical waveguide on the first insulating layer; and

after the forming of the second patterned conductive layer, forming respective contact holes through the second insulating layer and electrically connected to respective ones of the first and second regions,

wherein the forming at least one functional layer stacked on each other further comprises: and forming corresponding electrode structures on one side of the second patterned conductive layer, which is far away from the second insulating layer, wherein the corresponding electrode structures are respectively and electrically connected with the corresponding contact holes.

8. The method of claim 7, wherein the second patterned conductive layer further comprises: a respective first pattern portion corresponding to the respective electrode structure, wherein an orthogonal projection of each of the respective first pattern portions onto the first insulating layer partially overlaps an orthogonal projection of a corresponding one of the respective electrode structures onto the first insulating layer, and

wherein the method further comprises:

forming a plurality of back holes extending from a surface of the first insulating layer facing away from the semiconductor layer to the respective first pattern portions by etching, wherein the respective first pattern portions serve as etch stop layers for the plurality of back holes;

continuing the etching such that the plurality of back holes extend through the respective first pattern portions and to the respective electrode structures; and

and forming corresponding bonding pads on one side of the first insulating layer, which is away from the semiconductor layer, wherein the corresponding bonding pads are respectively and electrically connected to the corresponding electrode structures through corresponding back holes in the plurality of back holes.

9. The method of claim 8, wherein the forming the respective pads comprises:

Forming a first oxidation preventing layer, a metal wiring layer, and a second oxidation preventing layer stacked in this order in a direction away from the first insulating layer;

patterning the first oxidation resistant layer, the metal wiring layer and the second oxidation resistant layer to form corresponding pad areas;

forming a passivation layer covering the patterned second oxidation resistant layer; and

a portion of the passivation layer and the second oxidation resistant layer in each pad region is removed to expose a portion of the metal wiring layer in the pad region.

10. The method of claim 1, further comprising: patterning the semiconductor layer to form a grating coupler, the grating coupler being optically coupled to the optical waveguide,

wherein the complete removal of the first substrate is such that an optical transmission channel is provided between the grating coupler and an outside of the semiconductor device on a side of the first insulating layer facing away from the semiconductor layer, via the first insulating layer, but not via the first substrate.

11. The method of claim 10, further comprising:

after the first substrate is completely removed, the thickness of the first insulating layer is adjusted.

12. The method of claim 11, wherein the adjusting the thickness of the first insulating layer comprises: the first insulating layer is thickened.

13. The method of claim 12, wherein the thickening the first insulating layer comprises:

depositing a material of the first insulating layer on the first insulating layer; and

the deposited material is planarized such that the first insulating layer on which the material is deposited has a predetermined thickness.

14. A semiconductor device, comprising:

a first insulating layer;

a semiconductor layer stacked with the first insulating layer, the semiconductor layer including an optical waveguide;

a carrier substrate disposed opposite to the semiconductor layer;

at least one functional layer stacked on top of each other between the semiconductor layer and the carrier substrate, the at least one functional layer comprising a second insulating layer on a side of the semiconductor layer facing away from the first insulating layer, wherein the first insulating layer and the second insulating layer have a refractive index smaller than a refractive index of the semiconductor layer; and

a first patterned conductive layer on a side of the first insulating layer facing away from the second insulating layer, wherein the first patterned conductive layer comprises a first thermally tunable resistor, and an orthogonal projection of the first thermally tunable resistor onto the first insulating layer at least partially overlaps an orthogonal projection of the optical waveguide onto the first insulating layer,

Wherein no semiconductor material is provided on the entire surface of the first insulating layer facing away from the semiconductor layer.

15. The semiconductor device of claim 14, wherein a portion of the first insulating layer located at a peripheral region of the first thermally tuned resistor is etched away to a thickness to form a thermally insulating region at a periphery of the first thermally tuned resistor.

16. The semiconductor device of claim 14, wherein the at least one functional layer further comprises: and a second patterned conductive layer positioned on one side of the second insulating layer, which is away from the semiconductor layer.

17. The semiconductor device of claim 16, wherein the second patterned conductive layer comprises a second thermal resistor, wherein an orthogonal projection of the second thermal resistor onto the first insulating layer at least partially overlaps an orthogonal projection of the first thermal resistor onto the first insulating layer.

18. The semiconductor device of claim 17, wherein the semiconductor layer further comprises: a first doped region and a second doped region respectively positioned at two sides of the optical waveguide, wherein the orthogonal projection of the first doped region and the second doped region on the first insulating layer is adjacent to and not overlapped with the orthogonal projection of the optical waveguide on the first insulating layer,

Wherein the semiconductor device further comprises: respective contact holes penetrating the second insulating layer and electrically connected to respective ones of the first and second doped regions, and

wherein the at least one functional layer further comprises: and the corresponding electrode structures are positioned on one side of the second patterned conductive layer, which is away from the second insulating layer, and are respectively and electrically connected with the corresponding contact holes.

19. The semiconductor device of claim 18, wherein the second patterned conductive layer further comprises: a respective first pattern portion corresponding to the respective electrode structure, wherein an orthogonal projection of each of the respective first pattern portions onto the first insulating layer partially overlaps an orthogonal projection of a corresponding one of the respective electrode structures onto the first insulating layer, and

wherein the semiconductor device further comprises:

a plurality of back holes extending from a surface of the first insulating layer facing away from the semiconductor layer to the respective electrode structures; and

and corresponding bonding pads are positioned on one side of the first insulating layer, which is away from the semiconductor layer, and are respectively and electrically connected to the corresponding electrode structures through corresponding back holes in the plurality of back holes.

20. The semiconductor device of claim 19, wherein the respective pads comprise: a first oxidation-resistant layer, a metal wiring layer, and a second oxidation-resistant layer stacked in this order in a direction away from the first insulating layer, an

Wherein the semiconductor device further comprises: and a passivation layer covering the second oxidation preventing layer, wherein the passivation layer and the second oxidation preventing layer in each pad region are provided with windows to expose a portion of the metal wiring layer in the pad region.

21. The semiconductor device of claim 14 wherein said semiconductor layer further comprises a grating coupler optically coupled to said optical waveguide,

wherein the complete removal of the semiconductor material is such that an optical transmission channel is provided between the grating coupler and an outside of the semiconductor device on a side of the first insulating layer facing away from the semiconductor layer, via the first insulating layer, and not via the semiconductor material.

22. The semiconductor device of claim 14, wherein the first insulating layer has a thickness of 2um to 6 um.

23. A semiconductor integrated circuit comprising the semiconductor device according to any one of claims 14 to 22.