JP6173488B2 - Inverter device and air conditioner using inverter device - Google Patents

Description

  The present invention relates to an inverter device and an air conditioner using the inverter device.

  A conventional air conditioner includes an inverter device, and performs variable speed control of a compressor or the like by operation of the inverter device (see, for example, Patent Document 1).

JP 2013-162719 A (paragraph [0003])

  However, if the inverter device stops suddenly during operation, there is a problem that a surge voltage is generated by the magnetic energy accumulated in the DC reactor, and the switching element is damaged.

  The present invention has been made to solve the above-described problems, and can prevent the switching element from being damaged by the magnetic energy accumulated in the DC reactor, which is generated when the inverter device is suddenly stopped. An object of the present invention is to provide an inverter device and an air conditioner using the inverter device.

The inverter device according to the present invention is connected between a rectifier and a DC reactor connected to the anode side of the rectifier and smoothing a DC current of the rectifier, an output side of the DC reactor, and a cathode side of the rectifier A smoothing capacitor for smoothing the DC voltage of the rectifier, the DC reactor, and the smoothing capacitor, and an inrush current preventing circuit for preventing an inrush current to the smoothing capacitor; and the smoothing capacitor for smoothing. An inverter for converting the DC voltage into an AC voltage, the inrush current prevention circuit, the inverter board for controlling the inverter, and a first voltage detecting means for detecting a first voltage applied to the inrush current prevention circuit; , and a second voltage detecting means for detecting a second voltage applied to the inverter, the inrush current prevention circuit, the DC REACT And one or more relays connected to the smoothing capacitor, and an inrush current preventing resistor connected in parallel with the one or more relays, the one or more relays Among them, each of the plurality of relays is connected in parallel, and when the second voltage drops to a DC voltage abnormal level, the inverter board decelerates and stops the inverter, and the deceleration control unit until the inverter is stopped by the deceleration control by, among the one or more relays, the at least one relay possess a relay controller which closed, and the deceleration control unit, the first voltage When the voltage rises to the relay failure determination voltage level, the inverter is decelerated and stopped .

  The present invention suppresses surge voltage generated by magnetic energy and prevents damage to the switching element by forming a path for flowing the magnetic energy accumulated in the DC reactor into the smoothing capacitor that is generated when the inverter is suddenly stopped. It has the effect of being able to.

It is a figure which shows an example of the electrical constitution of the inverter apparatus 1 in Embodiment 1 of this invention. It is a figure which shows an example of a functional structure of the inverter board | substrate 45 in Embodiment 1 of this invention. It is a flowchart explaining the example of control of the inverter apparatus 1 in Embodiment 1 of this invention. It is a figure which shows an example of the electrical constitution of the inverter apparatus 1 in a prior art example. It is a timing chart explaining the operation | movement at the time of normal of the inverter apparatus 1 in a prior art example. It is a timing chart explaining the operation | movement at the time of abnormality of the inverter apparatus 1 in a prior art example. It is a timing chart explaining operation | movement when both the 1st relay 27 and the 2nd relay 23 which are included in the inverter apparatus 1 in Embodiment 1 of this invention fail. It is a timing chart explaining operation | movement when a power supply voltage falls in the inverter apparatus 1 in Embodiment 1 of this invention. It is a figure which shows an example of the electrical constitution of the inverter apparatus 1 in Embodiment 2 of this invention. It is a figure which shows an example of a functional structure of the signal arithmetic unit 47 contained in the inverter apparatus 1 in Embodiment 2 of this invention. It is a flowchart explaining the example of control of the signal arithmetic unit 47 contained in the inverter apparatus 1 in Embodiment 2 of this invention. It is a figure which shows the structural example of the electrical component box 9 in Embodiment 3 of this invention. It is a figure which shows an example of the electrical constitution of the signal arithmetic unit 47 in Embodiment 3 of this invention. It is a figure which shows an example of the electrical constitution of the signal arithmetic unit 47 in Embodiment 4 of this invention. It is a figure which shows an example of the electrical constitution of the inverter apparatus 1 in Embodiment 5 of this invention. It is a figure which shows another example of the electric constitution of the inverter apparatus 1 in Embodiment 5 of this invention. It is a figure which shows an example of the air conditioner 110 using the inverter apparatus 1 in Embodiment 6 of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the step of describing the program for performing the operation of the embodiment of the present invention is a process performed in time series in the order described, but it is not always necessary to process in time series. The processing executed may be included.

  It does not matter whether each function described in the present embodiment is realized by hardware or software. That is, each block diagram described in this embodiment may be considered as a hardware block diagram or a software functional block diagram. For example, each block diagram may be realized by hardware such as a circuit device, or may be realized by software executed on an arithmetic device such as a processor (not shown).

  In addition, each block in the block diagram described in this embodiment only needs to perform its function, and the configuration may not be separated by each block. In each of the first to sixth embodiments, items that are not particularly described are the same as those in the first to sixth embodiments, and the same functions and configurations are described using the same reference numerals. In addition, each of Embodiments 1 to 6 may be implemented alone or in combination. In either case, the advantageous effects described below can be obtained. In addition, various specific setting examples described in this embodiment are merely examples, and are not particularly limited thereto.

Embodiment 1 FIG.

(Configuration of Embodiment 1)
FIG. 1 is a diagram showing an example of an electrical configuration of an inverter device 1 according to Embodiment 1 of the present invention. As shown in FIG. 1, the inverter device 1 is provided between a switch 5 that controls supply of electric power from a commercial power source 3 and interruption of power, and a motor 7. 7 is converted into electric power corresponding to 7 and supplied. Although the details will be described later, the inverter device 1 prevents breakdown of the switching element 87 composed of a semiconductor element or the like that is a main component of the inverter 19. For example, the inverter device 1 is mainly composed of three parts, the first being a rectifier circuit part, the second being a smoothing circuit part, and the third being an inverter circuit part, of which the operation of the second smoothing circuit part Alternatively, the breakdown of the switching element 87 of the inverter circuit unit is prevented by the operation of the third inverter circuit unit.

  For example, the inverter device 1 includes, as main circuit elements, a rectifier 11, a DC reactor 13, an inrush current prevention circuit 15, a smoothing capacitor 17, and an inverter 19. A DC reactor 13, an inrush current prevention circuit 15, and a smoothing capacitor 17 are configured, and an inverter circuit unit is configured by an inverter 19. The inverter device 1 includes, for example, first voltage detection means 31 and second voltage detection means 33 as detection means. The inverter device 1 includes, for example, a control board 43 and an inverter board 45 as a control subject.

  Here, the first voltage detection means 31 has a connection configuration that detects the voltage applied to the inrush current prevention circuit 15 and supplies the detection result to the inverter board 45. The second voltage detection means 33 has a connection configuration that detects the voltage applied to the inverter 19 and supplies the detection result to the inverter board 45.

  The inverter 19 includes, for example, a switching element 87 as will be described later, but each switching element 87 may be provided with a feedback diode (not shown). For example, if the inverter 19 is of a voltage type that outputs a rectangular wave voltage, a feedback diode may be provided in parallel with the switching element 87. Further, for example, if the inverter 19 is of a current type that outputs a rectangular wave current, a feedback diode may be provided in series with the switching element 87.

  The rectifier circuit unit converts alternating current into direct current. The rectifier 11 that is a constituent element of the rectifier circuit unit is configured by, for example, a three-phase full-bridge rectifier circuit, and generates a three-phase full-wave rectified waveform from a three-phase AC power source that is supplied from the commercial power source 3 via the switch 5. Form. In the above description, the rectifier 11 that forms the three-phase full-wave rectified waveform is described as an example of the rectifier circuit unit. However, the rectifier 11 is not particularly limited thereto. For example, if the power supplied to the rectifier 11 is a single-phase AC power supply, the rectifier 11 may have a circuit configuration that forms a single-phase full-wave rectified waveform. That is, the rectifier circuit unit is not particularly limited as long as it has a circuit configuration that converts alternating current into direct current.

  For example, the smoothing circuit unit smoothes the three-phase full-wave rectified waveform output from the rectifying circuit unit. Among the smoothing circuit units, the DC reactor 13 is connected to the anode side of the rectifier 11 and smoothes the DC current output from the rectifying circuit unit. Of the smoothing circuit unit, the inrush current prevention circuit 15 and the smoothing capacitor 17 are connected between the output side of the DC reactor 13 and the cathode side of the rectifier 11. In the smoothing circuit unit, the smoothing capacitor 17 has polarity, the anode side of the smoothing capacitor 17 is connected to the inrush current prevention circuit 15, the cathode side of the smoothing capacitor 17 is connected to the cathode side of the rectifier 11, and direct current Smooth the voltage.

  Of the smoothing circuit unit, the inrush current prevention circuit 15 is provided between the DC reactor 13 and the smoothing capacitor 17. The inrush current prevention circuit 15 includes a first relay 27, a second relay 23, and an inrush current prevention resistor 25, and is disposed on a path through which the charging / discharging current of the smoothing capacitor 17 flows. With such a configuration, the inrush current prevention circuit 15 suppresses the inrush current flowing to the smoothing capacitor 17 when the power is turned on and the like, and overvoltage to the inverter circuit section when an abnormal state occurs during the operation of the inverter 19. Is prevented from being applied.

  Specifically, the inrush current prevention circuit 15 is configured, for example, by connecting a first relay 27, a second relay 23, and an inrush current prevention resistor 25 in parallel. Although the details of the inrush current prevention circuit 15 will be described later, either one of the first relay 27 and the second relay 23 connected in parallel with the inrush current prevention resistor 25 is closed during the operation of the inverter 19. Since a closed circuit having a low impedance is formed, an overvoltage is not applied to the inverter 19.

  Even if both the first relay 27 and the second relay 23 are in an uncontrollable state, the inverter board 45, which will be described in detail later, controls the inverter 19 to be decelerated, so that it is supplied from the DC reactor 13 to the inverter 19. As a result, the breakdown voltage of the switching element 87 included in the inverter 19 is prevented.

  That is, the inverter device 1 is configured to control DC of at least one of the control of the open / close state of the first relay 27 included in the inrush current prevention circuit 15 and the control of the open / close state of the second relay 23 included in the inrush current prevention circuit 15. A path for allowing the magnetic energy accumulated in the reactor 13 to flow into the smoothing capacitor 17 is formed. Further, the inverter device 1 forms a load that consumes the magnetic energy accumulated in the DC reactor 13 by the deceleration control of the inverter 19.

  The inverter circuit unit is supplied with the smoothed DC power output from the smoothing circuit unit, converts the supplied DC power into AC power, and drives the motor 7. The motor 7 is a load of the inverter 19 and serves as a driving source for the compressor 131, the indoor fan 143, the outdoor fan 141, and the like of the air conditioner 110 described later. That is, the inverter circuit unit has a circuit configuration for converting a DC power source into an AC power source, and arbitrarily changes the AC power source and its frequency to control the motor 7 at a variable speed.

  The control board 43 is provided, for example, in the electrical component box 9 of the outdoor unit 111 described later, and controls the air conditioner 110 described later. An inverter board 45 is also provided in the electrical component box 9 of the outdoor unit 111 described later. Inter-board mutual communication information is transmitted and received between the control board 43 and the inverter board 45. The control board 43 controls the inverter board 45, for example, when controlling the air conditioner 110 mentioned later. The inverter board 45 controls the inverter 19. That is, the control board 43 controls the inverter 19 via the inverter board 45.

  Specifically, for example, the control board 43 controls the open / close state of the first relay 27 with a first control signal. For example, the inverter board 45 controls the open / close state of the second relay 23 by the second control signal. The inverter board 45 controls the drive of the inverter 19 with an inverter drive signal, for example.

  Here, the inverter board 45 is configured to receive two pieces of voltage information. Specifically, voltage information related to the both-ends voltage of the inrush current preventing resistor 25, the first relay 27, and the second relay 23 and voltage information related to the voltage of the DC power source input to the inverter 19 are input. Among these, the voltage across the first inrush current prevention resistor 25, the first relay 27, and the second relay 23 is a detection result of the first voltage detection means 31. The detection result of the first voltage detection means 31 is input to the inverter board 45 as first voltage information. The voltage of the DC power source input to the second inverter 19 is a detection result of the second voltage detection means 33. The detection result of the second voltage detection means 33 is input to the inverter board 45 as second voltage information. The inverter board 45 performs control of the open / close state of the second relay 23 and deceleration control of the inverter 19 based on such two pieces of voltage information.

  FIG. 2 is a diagram showing an example of a functional configuration of the inverter board 45 in the first embodiment of the present invention. The inverter board 45 includes, for example, an abnormality determination unit 51, a deceleration control unit 53, a relay control unit 55, an inverter control unit 57, and the like. The abnormality determination unit 51 determines an abnormal state of the inverter device 1 based on the first voltage information and the second voltage information. The abnormality determination unit 51 includes, for example, a relay failure determination unit 71 and a DC voltage abnormality determination unit 73. Here, the relay failure determination voltage level is a threshold that is assumed to have caused the failure of the first relay 27 or the second relay 23, and the DC voltage abnormality level is that the power supply voltage decreases due to a power failure or the like. Thus, the threshold value is assumed to cause the inverter 19 to stop suddenly.

  Specifically, as a result of the sudden stop of the inverter 19, it is assumed that magnetic energy is generated in the DC reactor 13 and the DC voltage rapidly rises, so it is necessary to form a load that consumes the magnetic energy. Although details will be described later, the inverter device 1 causes the smoothing capacitor 17 to consume magnetic energy by closing the second relay 23, or causes the inverter 19 and the motor 7 to consume magnetic energy by performing deceleration control of the inverter 19. Or That is, the magnetic energy generated in the DC reactor 13 is converted into electric energy and heat energy by the smoothing capacitor 17, converted into electric energy and heat energy by the inverter 19, and converted into kinetic energy by the motor 7.

  When the first voltage information reaches the relay failure determination voltage level, the relay failure determination unit 71 determines that the inverter device 1 is in an abnormal state, and determines the determination result as the relay control unit 55, the inverter control unit 57, and the deceleration control. To the unit 53. When the second voltage information reaches the DC voltage abnormality level, the DC voltage abnormality determination unit 73 determines that the inverter device 1 is in an abnormal state, and determines the determination results as the relay control unit 55, the inverter control unit 57, and the deceleration control. To the unit 53.

  When the inverter device 1 is in an abnormal state, the deceleration control unit 53 supplies the inverter 19 with various information for controlling the inverter 19 to decelerate, for example. The deceleration control unit 53 includes, for example, an operating rotation speed acquisition unit 75, a deceleration rotation speed acquisition unit 77, and a deceleration time calculation unit 79.

  The operating speed acquisition unit 75 acquires the operating speed of the motor 7 that is driven and controlled by the inverter 19. Here, the rotation speed when the motor 7 is operating is the actual rotation speed of the load of the inverter 19 and is calculated according to, for example, the number of pulses detected by a rotary encoder (not shown). The rotational speed acquisition unit 77 during deceleration acquires the rotational speed of the motor 7 during deceleration control of the inverter 19 such that the inverter 19 decelerates the motor 7. Here, the rotation speed of the motor 7 at the time of the deceleration control is the rotation speed for deceleration of the load of the inverter 19 and may be set in advance or obtained every time. In addition, the rotation speed at the time of the operation | movement of the motor 7 may be calculated | required with the Hall element which is not shown in figure.

  The deceleration time calculation unit 79 obtains a deceleration time required for deceleration based on the rotational speed during operation and the rotational speed during deceleration. The deceleration control unit 53 supplies the deceleration time to the inverter 19. For example, if the rotational speed during operation is 100 rps (rotations per second) and the rotational speed during deceleration is 10 rps, 10 (s) is the deceleration time.

  The relay control unit 55 controls the second relay 23 included in the inrush current prevention circuit 15 based on the determination result. The inverter control unit 57 supplies an inverter drive signal based on the determination result to the inverter 19. Here, for example, it is assumed that the Hi level inverter drive signal is set to the output state where the inverter 19 is driven, and the Lo level inverter drive signal is set to the cutoff state where the inverter 19 stops. In such an assumption, if the inverter device 1 is in an abnormal state, the inverter control unit 57 supplies a Lo level inverter drive signal to the inverter 19.

  The inverter 19 includes an inverter drive signal determination unit 83, a gate control unit 85, a switching element 87, and the like. The inverter drive signal determination unit 83 controls the operation of the switching element 87 by controlling the gate control unit 85 according to the inverter drive signal. If the Lo level inverter drive signal is assumed to be an abnormal state of the inverter device 1, if the Lo level inverter drive signal is supplied to the inverter drive signal determiner 83, the inverter drive signal determiner 83 decelerates the inverter 19. The control is selected, and the gate control unit 85 is caused to generate a signal for decelerating the motor 7. As a result, the switching element 87 performs an operation according to the signal generated by the gate control unit 85.

  For example, the gate control unit 85 controls the ON state and the OFF state of the switching element 87 by controlling a gate drive circuit (not shown) of the switching element 87. Specifically, the gate control unit 85 generates a PWM signal by controlling a duty ratio that is a ratio between the ON state interval of the switching element 87 and the OFF state interval of the switching element 87. That is, the inverter 19 causes the gate control unit 85 to output a PWM signal from the switching element 87 and performs PWM control of the motor 7 with the PWM signal. The motor 7 generates a rotating magnetic field with a PWM signal, rotates a shaft (not shown) provided in the motor 7, and becomes a drive source for various devices. The motor 7 is, for example, a brushless DC motor.

  Here, the gate control unit 85 has a ratio between the ON state interval of the switching element 87 and the OFF state interval of the switching element 87 so as to decelerate the motor 7 by the number of revolutions during deceleration before the deceleration time. By controlling a certain duty ratio and generating a PWM signal for increasing the OFF state interval of the switching element 87 with the passage of time, the inverter 19 is controlled to decelerate, the load of the motor 7 and the like is decelerated, and the motor 7 and the like Stop the load by the deceleration time.

  Although the switching element 87 is comprised by IGBT, for example, it is not limited to this in particular. For example, the switching element 87 may be composed of a wide band gap semiconductor. Since the wide band gap semiconductor has high voltage resistance and high allowable current density, the switching element 87 can be downsized. Further, since the wide band gap semiconductor has high heat resistance, the heat dissipating fins (not shown) of the heat sink can be reduced in size, and the air cooling of the water cooling part (not shown) can be realized. The inverter 19 including it can be further miniaturized. Furthermore, since the wide band gap semiconductor has low power loss, the switching element 87 can be realized with high efficiency, and the inverter 19 can be realized with high efficiency.

  In the above description, an example in which the deceleration control unit 53 calculates the deceleration time and supplies the calculation result to the inverter 19 has been described. However, the present invention is not particularly limited to this. For example, the inverter control unit 57 may supply the inverter 19 with an inverter drive signal including an operation for controlling the deceleration of the inverter 19. In short, the inverter board | substrate 45 should just be the structure which can carry out the deceleration control of the inverter 19, when the inverter apparatus 1 is in an abnormal state.

(Operation of Embodiment 1)
FIG. 3 is a flowchart illustrating a control example of inverter device 1 according to the first embodiment of the present invention. In FIG. 3, as a control example of the inverter device 1, a control example of the first voltage detection unit 31 will be described in step S <b> 11 and step S <b> 12, and a control example of the second voltage detection unit 33 will be described in step S <b> 21 and step S <b> 22. A control example of the inverter board 45 will be described in steps S31 to S39, and a control example of the inverter 19 will be described in steps S51 to S53.

  As a premise of processing, it is assumed that a default value of a flag described later is set to 0. Here, the flag is an identifier that branches to processing based on the second voltage information when the flag is 1, and is not particularly limited to the following example. Further, as a premise of the processing, if the inverter 19 is in operation and the first relay 27 and the second relay 23 are not broken, the first relay 27 and the second relay 23 are maintained in a short-circuit state. Suppose.

(First voltage detection means control process)
(Step S11)
The first voltage detector 31 detects the first voltage.

(Step S12)
The first voltage detection means 31 outputs the detection result as first voltage information.

(Second voltage detection means control process)
(Step S21)
The second voltage detection means 33 detects the second voltage.

(Step S22)
The second voltage detector 33 outputs the detection result as second voltage information.

(Inverter board control processing)
(Step S31)
The inverter board 45 identifies the type of voltage information. When the type of voltage information is the first voltage information, the inverter board 45 proceeds to step S32. On the other hand, the inverter board | substrate 45 progresses to step S33, when the kind of voltage information is 2nd voltage information.

(Step S32)
When the first voltage information reaches the relay failure determination voltage level, the inverter board 45 proceeds to step S35. On the other hand, when the first voltage information does not reach the relay failure determination voltage level, the inverter board 45 returns to step S31.

  Here, when the first voltage information reaches the relay failure determination voltage level, it is assumed that the first relay 27 and the second relay 23 are in an open state due to failure. Even if the second voltage information reaches the DC voltage abnormal level, if the first voltage information does not reach the relay failure determination voltage level, at least one of the first relay 27 and the second relay 23 is short-circuited. Assume that state is maintained.

(Step S33)
When the second voltage information reaches the DC voltage abnormality level, the inverter board 45 proceeds to step S34. On the other hand, when the second voltage information has not reached the DC voltage abnormality level, the inverter board 45 returns to step S31.

(Step S34)
The inverter board 45 sets the flag to 1, and proceeds to step S35.

(Step S35)
The inverter board 45 transmits an inverter drive signal for stopping the inverter 19 to the inverter 19.

(Step S36)
The inverter board 45 transmits deceleration time information for decelerating the inverter 19 to the inverter 19. As described above, if the inverter drive signal includes a command for decelerating the inverter 19 within the deceleration time, the process of step S36 is unnecessary.

(Step S37)
When the preset time has elapsed after the deceleration time has elapsed, the inverter board 45 proceeds to step S38. On the other hand, when the preset time has not elapsed after the deceleration time has elapsed, the inverter board 45 returns to step S37. Here, it is assumed that the state after the elapse of the deceleration time and the preset time has elapsed is a state where the inverter 19 is stopped and the operation of the motor 7 accompanying the moment of inertia is also stopped.

(Step S38)
If the flag is 1, the inverter board 45 proceeds to step S39. On the other hand, if the flag is not 1, the inverter board 45 ends the process.

(Step S39)
The inverter board 45 controls the second relay 23 to the open state and ends the process.

(Inverter control processing)
(Step S51)
The inverter 19 starts decelerating the motor 7 at a constant speed so as to stop at the deceleration time.

(Step S52)
The inverter 19 determines whether the deceleration time has elapsed. When the deceleration time has elapsed, the inverter 19 proceeds to step S53. On the other hand, when the deceleration time has not elapsed, the inverter 19 returns to step S52.

(Step S53)
The inverter 19 stops the motor 7 and ends the process.

(Effect of Embodiment 1)
Next, the effects of the inverter device 1 of the first embodiment will be described by comparing the configuration and operation of the conventional inverter device 1 with the configuration and operation of the inverter device 1 of the first embodiment.

  FIG. 4 is a diagram illustrating an example of an electrical configuration of the inverter device 1 in the conventional example. As shown in FIG. 4, the conventional inverter device 1 is not provided with the first voltage detection means 31 and the second relay 23.

  Here, it is assumed that the control board 43 is powered on. In this case, the control board 43 transmits / receives mutual communication information between the inverter board 45 and the board, supplies various control signals, closes the switch 5, and supplies the inverter apparatus 1 with the power supplied from the commercial power source 3. . Next, the inverter board 45 controls the inverter 19 based on various control signals included in the inter-board mutual communication information from the control board 43, but does not depend on the various control signals from the control board 43 depending on the situation. The inverter 19 may be controlled.

  For example, in the inverter device 1, the first relay 27 or the second relay 23 may be in an open state due to the influence of disturbance such as mechanical life or noise during the operation of the inverter 19. In this case, the charging / discharging current of the smoothing capacitor 17 flows via the inrush current preventing resistor 25. Therefore, the charging / discharging current is suppressed by the inrush current preventing resistor 25, the smoothing function of the smoothing capacitor 17 is lowered, and the DC voltage input to the inverter circuit unit varies. Next, when the inverter device 1 stops operating, the magnetic energy generated by the current flowing through the DC reactor 13 increases the DC voltage. Therefore, an overvoltage is applied to the semiconductor element that constitutes the switching element 87 of the inverter circuit unit, which exceeds the allowable voltage of the semiconductor element, and the semiconductor element may be destroyed.

  Therefore, even when the first relay 27 of the inrush current prevention circuit 15 is opened while the inverter device 1 is in operation, the second relay 23 is connected to the inrush current prevention circuit 15 as described above with reference to FIG. If the voltage between the contacts of the first relay 27 and the second relay 23 and the DC voltage input to the inverter 19 are monitored and the monitored information is fed back to the inverter board 45, the voltage is generated in the DC reactor 13. Can be consumed.

  In other words, the second relay 23 is controlled in conjunction with the inverter 19, thereby obtaining an effect of preventing the semiconductor element constituting the switching element 87 from being destroyed. For example, even when the first relay 27 and the second relay 23 are opened, the magnetic energy generated in the DC reactor 13 is consumed by decelerating and stopping the inverter 19 in stages. Therefore, the magnetic energy generated in the DC reactor 13 can be suppressed, and a rapid increase in the DC voltage applied to the inverter 19 can be prevented.

  In addition, if the circuit configuration includes the second relay 23 separately from the first relay 27, that is, if the circuit configuration includes a plurality of relays, at least one of the relays until the inverter 19 stops. By maintaining the short circuit state, the magnetic energy generated in the DC reactor 13 is absorbed and consumed by the smoothing capacitor 17, so that the magnetic energy generated in the DC reactor 13 is suppressed and applied to the inverter 19. A sudden rise in the DC voltage can be prevented.

  In other words, the inverter device 1 forms a path through which the magnetic energy stored in the DC reactor 13 flows into the smoothing capacitor 17, thereby generating magnetic energy stored in the DC reactor 13 that is generated when the inverter device 1 is suddenly stopped. It is possible to suppress the generated surge voltage and prevent the switching element 87 from being damaged.

  Next, the effect which arises from the difference in operation | movement of the conventional inverter apparatus 1 and the inverter apparatus 1 of this Embodiment 1 is demonstrated concretely using a timing chart.

  FIG. 5 is a timing chart for explaining the normal operation of the inverter device 1 in the conventional example. As shown in FIG. 5, the timing chart shows, in order from the top, the first voltage that is the detection result of the first voltage detection unit 31, the second voltage that is the detection result of the second voltage detection unit 33, and the first relay 27. Each of the first control signal, the second control signal of the second relay 23, the contact portion of the first relay 27, the contact portion of the second relay 23, the inverter drive signal, and the actual rotational speed of the load of the inverter 19 over time. Indicates the transition of various states.

  First, although the first voltage detection means 31 is not provided in the conventional inverter device 1, here, the state transition of the voltage applied to the first relay 27 which is a portion corresponding to the first voltage is shown over time. . For example, a voltage is generated by the contact resistance of the first relay 27 and the conduction current of the first relay 27. Further, in the conventional inverter device 1, since the second relay 23 is not provided, the second control signal of the second relay 23 is not generated, and the state transition of the contact portion of the second relay 23 does not occur.

  Next, transition of various states will be described along the time axis. At time t0, the switch 5 is closed, and power is supplied from the commercial power source 3 to the inverter device 1. Next, the smoothing capacitor 17 is charged from t0 to t1, charging is completed at t1, and the DC voltage as the second voltage is stabilized. Further, since the charging current of the smoothing capacitor 17 flows through the inrush current preventing resistor 25 from t0 to t1, the voltage of the first voltage decreases as the charging of the smoothing capacitor 17 proceeds. At the timing t2, the first control signal is supplied from the control board 43 to the first relay 27 in the Hi level state, and the first relay 27 transitions from the open state to the short circuit state.

  As the state of the first control signal transitions from the Lo level to the Hi level, the contact portion of the first relay 27 transitions from the open state to the short circuit state. At the timing of t3, the inverter drive signal is output from the inverter board 45 to the inverter 19 in a high level state, and the motor 7 that is the load of the inverter 19 is started to be driven. The actual rotational speed of the load of the inverter 19 starts increasing at t3, and trapezoidal control is executed. Further, since the first relay 27 is in a short-circuit state at the timing t3, a voltage of, for example, several volts is detected from the contact resistance of the first relay 27 and the conduction current of the first relay 27.

  At the timing of t5, the inverter drive signal is output from the inverter board 45 to the inverter 19 in the Lo level state, and the drive of the motor 7 which is the load of the inverter 19 is stopped. The actual rotation speed of the load of the inverter 19 starts decelerating from t5, and trapezoidal control is executed.

  FIG. 6 is a timing chart for explaining the operation at the time of abnormality of the inverter device 1 in the conventional example. As shown in FIG. 6, the timing chart shows, in order from the top, the first voltage that is the detection result of the first voltage detection unit 31, the second voltage that is the detection result of the second voltage detection unit 33, and the first relay 27. Each of the first control signal, the second control signal of the second relay 23, the contact portion of the first relay 27, the contact portion of the second relay 23, the inverter drive signal, and the actual rotational speed of the load of the inverter 19 over time. Indicates the transition of various states.

  First, although the first voltage detection means 31 is not provided in the conventional inverter device 1, here, the state transition of the voltage applied to the first relay 27 which is a portion corresponding to the first voltage is shown over time. . For example, a voltage is generated by the contact resistance of the first relay 27 and the conduction current of the first relay 27. Further, in the conventional inverter device 1, since the second relay 23 is not provided, the second control signal of the second relay 23 is not generated, and the state transition of the contact portion of the second relay 23 does not occur.

  Next, transition of various states will be described along the time axis. At time t0, the switch 5 is closed, and power is supplied from the commercial power source 3 to the inverter device 1. Next, the smoothing capacitor 17 is charged from t0 to t1, charging is completed at t1, and the DC voltage as the second voltage is stabilized. Further, since the charging current of the smoothing capacitor 17 flows through the inrush current preventing resistor 25 from t0 to t1, the voltage of the first voltage decreases as the charging of the smoothing capacitor 17 proceeds. At the timing t2, the first control signal is supplied from the control board 43 to the first relay 27 in the Hi level state, and the first relay 27 transitions from the open state to the short circuit state.

  As the state of the first control signal transitions from the Lo level to the Hi level, the contact portion of the first relay 27 transitions from the open state to the short circuit state. At the timing of t3, the inverter drive signal is output from the inverter board 45 to the inverter 19 in a high level state, and the motor 7 that is the load of the inverter 19 starts to be driven. The actual rotational speed of the load of the inverter 19 starts increasing at t3, and trapezoidal control is executed. Further, since the first relay 27 is in a short-circuit state at the timing t3, a voltage of, for example, several volts is detected from the contact resistance of the first relay 27 and the conduction current of the first relay 27.

  Assuming that the first relay 27 has an open failure at the timing t4, the charging / discharging current of the smoothing capacitor 17 passes through the inrush current prevention resistor 25, so the first voltage increases rapidly. The first voltage thus rapidly increased reaches the relay failure determination voltage level. Further, at the timing of t4, the DC voltage fluctuates and the voltage decreases, so the second voltage reaches the DC voltage abnormal level. Since the second voltage has reached the DC voltage abnormal level at the timing t4, the inverter 19 is immediately stopped by outputting the inverter drive signal at the Lo level at the timing t5.

  As a result of suddenly stopping the inverter 19 at the timing t5, the DC voltage rapidly increases due to the generation of magnetic energy in the DC reactor 13, so the second voltage rapidly increases. That is, the conventional inverter device 1 is in a state in which no path for flowing the magnetic energy accumulated in the DC reactor 13 into the smoothing capacitor 17 is formed even if the inverter device 1 reaches an abnormal state.

  FIG. 7 is a timing chart illustrating an operation when both the first relay 27 and the second relay 23 included in the inverter device 1 according to the first embodiment of the present invention fail. As shown in FIG. 7, the timing chart shows, in order from the top, the first voltage that is the detection result of the first voltage detection unit 31, the second voltage that is the detection result of the second voltage detection unit 33, and the first relay 27. Each of the first control signal, the second control signal of the second relay 23, the contact portion of the first relay 27, the contact portion of the second relay 23, the inverter drive signal, and the actual rotational speed of the load of the inverter 19 over time. Indicates the transition of various states.

  Next, transition of various states will be described along the time axis. At time t0, the switch 5 is closed, and power is supplied from the commercial power source 3 to the inverter device 1. Next, the smoothing capacitor 17 is charged from t0 to t1, charging is completed at t1, and the DC voltage as the second voltage is stabilized. Further, since the charging current of the smoothing capacitor 17 flows through the inrush current preventing resistor 25 from t0 to t1, the voltage of the first voltage decreases as the charging of the smoothing capacitor 17 proceeds. At the timing t2, the first control signal is supplied from the control board 43 to the first relay 27 in the Hi level state, and the first relay 27 transitions from the open state to the short circuit state.

  At the timing t2, the second control signal is supplied from the inverter board 45 to the second relay 23 in a Hi level state, and the second relay 23 transitions from the open state to the short circuit state. In the example shown in FIG. 7, the first control signal supplied to the first relay 27 and the second control signal supplied to the second relay 23 have the same timing, but are not particularly limited thereto. Instead, the timing may be shifted.

  As the state of the first control signal transitions from the Lo level to the Hi level, the contact portion of the first relay 27 transitions from the open state to the short circuit state. Similarly, as the state of the second control signal transitions from the Lo level to the Hi level, the contact portion of the second relay 23 transitions from the open state to the short circuit state. Next, at the timing t3, the inverter drive signal is output from the inverter board 45 to the inverter 19 in a Hi level state, and the motor 7 that is the load of the inverter 19 is started to be driven. The actual rotational speed of the load of the inverter 19 starts increasing at t3, and trapezoidal control is executed. Further, since the first relay 27 is in a short-circuit state at the timing t3, a voltage of, for example, several volts is detected from the contact resistance of the first relay 27 and the conduction current of the first relay 27.

  At the timing of t4, it is assumed that both the first relay 27 and the second relay 23 have an open failure. In this case, each of the contact part of the 1st relay 27 and the contact part of the 2nd relay 23 changes from a short circuit state to an open state. Therefore, since the charging / discharging current of the smoothing capacitor 17 passes through the inrush current prevention resistor 25, the first voltage increases rapidly, and the first voltage increased rapidly reaches the relay failure determination voltage level. Next, at the timing of t5, the inverter drive signal is output from the inverter board 45 to the inverter 19 in a Lo level state, and the actual rotational speed of the load of the inverter 19 starts decelerating from t5, and trapezoidal control is executed. .

  Next, since the power supplied to the inverter 19 decreases, the charging / discharging current of the smoothing capacitor 17 via the inrush current prevention resistor 25 decreases. Therefore, the level of the first voltage also decreases. At the timing t6, after the inverter 19 is stopped, the second control signal for controlling the second relay 23 to the open state is supplied from the inverter board 45 to the second relay 23 in the Lo level state. In this state, there is an open failure, and the state is not controlled by the second control signal.

  At the timing of t7, although the first control signal for controlling the first relay 27 to the open state is supplied from the control board 43 to the first relay 27 in the Lo level state, the first relay 27 has an open failure. This is a state and is not controlled by the first control signal.

  In short, when both the first relay 27 and the second relay 23 fail, the inverter 19 is immediately decelerated and the magnetic energy of the DC reactor 13 can be consumed little by little. Can be prevented, and the destruction of the switching element 87 can be avoided.

  FIG. 8 is a timing chart for explaining the operation when the power supply voltage is reduced in inverter device 1 according to the first embodiment of the present invention. As shown in FIG. 8, the timing chart shows, in order from the top, the first voltage that is the detection result of the first voltage detection means 31, the second voltage that is the detection result of the second voltage detection means 33, and the first relay 27. Each of the first control signal, the second control signal of the second relay 23, the contact portion of the first relay 27, the contact portion of the second relay 23, the inverter drive signal, and the actual rotational speed of the load of the inverter 19 over time. Indicates the transition of various states.

  Next, transition of various states will be described along the time axis. At time t0, the switch 5 is closed, and power is supplied from the commercial power source 3 to the inverter device 1. Next, the smoothing capacitor 17 is charged from t0 to t1, charging is completed at t1, and the DC voltage as the second voltage is stabilized. Further, since the charging current of the smoothing capacitor 17 flows through the inrush current preventing resistor 25 from t0 to t1, the voltage of the first voltage decreases as the charging of the smoothing capacitor 17 proceeds. At the timing t2, the first control signal is supplied from the control board 43 to the first relay 27 in the Hi level state, and the first relay 27 transitions from the open state to the short circuit state.

  At the timing t2, the second control signal is supplied from the inverter board 45 to the second relay 23 in a Hi level state, and the second relay 23 transitions from the open state to the short circuit state. In the example shown in FIG. 7, the first control signal supplied to the first relay 27 and the second control signal supplied to the second relay 23 have the same timing, but are not particularly limited thereto. Instead, the timing may be shifted.

  As the state of the first control signal transitions from the Lo level to the Hi level, the contact portion of the first relay 27 transitions from the open state to the short circuit state. Similarly, as the state of the second control signal transitions from the Lo level to the Hi level, the contact portion of the second relay 23 transitions from the open state to the short circuit state. Next, at the timing t3, the inverter drive signal is output from the inverter board 45 to the inverter 19 in a Hi level state, and the motor 7 that is the load of the inverter 19 is started to be driven. The actual rotational speed of the load of the inverter 19 starts increasing at t3, and trapezoidal control is executed. Further, since the first relay 27 is in a short-circuit state at the timing t3, a voltage of, for example, several volts is detected from the contact resistance of the first relay 27 and the conduction current of the first relay 27.

  It is assumed that the commercial power supply 3 is affected by a power failure or the like at the timing t4 and the power supply to the inverter device 1 is stopped. At this time, the second voltage starts to decrease. Next, at the timing of t5, when the DC voltage decreases and the second voltage reaches the DC voltage abnormal level, the second voltage information is output from the second voltage detection means 33 to the inverter board 45, and the inverter board 45 Detects that the DC voltage has become abnormal. Next, the inverter board 45 outputs an inverter drive signal to the inverter 19 in a Lo level state. Further, at the timing of t5, the inverter drive signal is output from the inverter board 45 to the inverter 19 in a state of Lo level, and the actual rotational speed of the load of the inverter 19 starts decelerating from t5, and trapezoidal control is executed.

  At the timing t6, after the inverter 19 is stopped, the second control signal for controlling the second relay 23 to the open state is supplied from the inverter board 45 to the second relay 23 in the Lo level state, and the contact portion of the second relay 23 Is in an open state.

  At the timing t7, the first control signal for controlling the first relay 27 to the open state is supplied from the control board 43 to the first relay 27 in the Lo level state, and the contact portion of the first relay 27 is opened. .

  In short, when the power supply voltage drops in the inverter device 1, the inverter 19 is immediately decelerated, so that the magnetic energy of the DC reactor 13 is gradually reduced, and the second relay is used while the inverter 19 is being controlled. Since the short circuit state 23 is maintained, the DC voltage is prevented from rapidly increasing, and thus the switching element 87 can be prevented from being destroyed.

  From the above description, even if the inverter device 1 is in an abnormal state, the switching element 87 is generated by the magnetic energy of the DC reactor 13 during the operation of the inverter device 1 in order to form a load that consumes the magnetic energy of the DC reactor 13. Can be prevented from being damaged.

  Specifically, even if the inverter device 1 detects an abnormality such as a voltage fluctuation during the operation of the inverter 19, the inverter 19 and the load of the inverter 19, for example, a motor, by decelerating the inverter 19 in stages. 7 and power can be consumed to prevent the DC voltage from rising. Therefore, the inverter device 1 can prevent the switching element 87 from being damaged by the magnetic energy resulting from the abnormal state.

  In addition, if the second relay 23 is not open-failed, the inverter device 1 maintains the short-circuited state of the second relay 23 until the inverter 19 stops, so that the current flowing through the DC reactor 13 flows into the smoothing capacitor 17. Therefore, the smoothing capacitor 17 can consume magnetic energy and prevent the DC voltage from rising. Therefore, the inverter device 1 can prevent the switching element 87 from being damaged by the magnetic energy resulting from the abnormal state. That is, when the inverter 19 is abnormal, the inverter board 45 closes at least one of the one or more relays until the inverter 19 is stopped. As a result, the inverter board 45 can reduce the magnetic energy accumulated in the DC reactor 13 that is generated when the inverter device 1 is suddenly stopped, so that the switching element 87 can be prevented from being damaged.

  In other words, the inverter device 1 can avoid breakdown of the switching element 87 of the inverter 19. Note that the interval between t0 and t1 described above is, for example, 3 (s), the interval between t1 and t2 is, for example, 3 (s), and the interval between t2 and t3 is, for example, 1 (s). , Between t3 and t4 is, for example, 30 (s), between t4 and t5 is, for example, 10 (ms), and between t5 and t6 is, for example, 10 (s). It is not limited.

  Importantly, first, if an abnormality is detected during the operation of the inverter 19, the inverter board 45 can control the opening and closing of the second relay 23, and the second relay 23 until the inverter 19 stops. It is to maintain the short circuit state. Further, the inverter board 45 may immediately shift to the deceleration control of the inverter 19 when an abnormality is detected during the operation of the inverter 19. For example, if an abnormality is detected during the operation of the inverter 19, the inverter board 45 may perform the deceleration control of the inverter 19 even if the opening / closing control of the second relay 23 cannot be performed. In addition, when an abnormality is detected during the operation of the inverter 19, the inverter board 45 may make the second relay 23 in a short-circuited state, that is, a closed state, and may perform the deceleration control of the inverter 19. As a result of the operation described above, the inverter device 1 can prevent the switching element 87 from being damaged by the magnetic energy resulting from the abnormal state.

  As described above, in the first embodiment, the rectifier 11 is connected to the anode side of the rectifier 11, the DC reactor 13 that smoothes the DC current of the rectifier 11, the output side of the DC reactor 13, and the cathode side of the rectifier 11. An inrush current prevention circuit 15 connected between the smoothing capacitor 17 for smoothing the DC voltage of the rectifier 11, the DC reactor 13, and the smoothing capacitor 17 and preventing an inrush current to the smoothing capacitor 17; An inverter 19 that converts the DC voltage smoothed by the smoothing capacitor 17 into an AC voltage, an inrush current prevention circuit 15, and an inverter board 45 that controls the inverter 19 are provided. The inrush current prevention circuit 15 includes a DC reactor. 13 and the smoothing capacitor 17, connected in parallel with one or more relays and one or more relays. An inrush current prevention resistor 25, each of the plurality of relays among one or a plurality of relays are connected in parallel, and the inverter board 45 is connected to the inverter 19 until the inverter 19 is stopped when the inverter 19 is abnormal. The inverter device 1 is configured to close at least one of the one or a plurality of relays.

  Therefore, by forming a path through which the magnetic energy accumulated in the DC reactor 13 flows into the smoothing capacitor 17, a surge voltage generated by the magnetic energy accumulated in the DC reactor 13 that is generated when the inverter device 1 is suddenly stopped is generated. It is possible to prevent the switching element 87 from being damaged.

  In the first embodiment, the inverter 19 includes a switching element 87 and a gate control unit 85 that controls the switching element 87, and the inverter substrate 45 controls the gate control unit 85, and The operation time is decreased stepwise and the inverter 19 is stopped.

  In the first embodiment, the inverter board 45 obtains the deceleration time of the motor 7 based on the current rotational speed of the motor 7 driven by the inverter 19.

  In the first embodiment, the control board 43 that controls the inrush current prevention circuit 15 and the inverter board 45, the first relay 27 that is controlled by the control board 43 as one or more relays, One or a plurality of relays, and the second relay 23 controlled by the inverter board 45, and the inverter board 45 relates to the first relay 27 and the second relay 23 as means for judging the stop of the inverter 19. A first voltage detecting means 31 for detecting the first voltage, and a second voltage detecting means 33 for detecting the second voltage supplied to the inverter 19, wherein the first voltage reaches an abnormal level; When the voltage reaches the relay failure determination voltage level, a stop operation command for the inverter 19 is output based on at least one of them.

  Therefore, the magnetic energy accumulated in the direct current reactor 13 is generated by the magnetic energy accumulated in the direct current reactor 13 that is generated when the inverter device 1 is suddenly stopped by forming a path through which the magnetic energy accumulated in the direct current reactor 13 flows into the smoothing capacitor 17. Surge voltage to be suppressed can be suppressed and damage to the switching element 87 can be prevented.

Embodiment 2. FIG.
(Difference)
A difference from the other embodiments is that a first control signal and a second control signal are supplied to a third relay 29 described later.

(Configuration of Embodiment 2)
FIG. 9 is a diagram illustrating an example of an electrical configuration of the inverter device 1 according to the second embodiment of the present invention. As shown in FIG. 9, the inrush current prevention circuit 15 includes an inrush current prevention resistor 25 and a third relay 29, and the inrush current prevention resistor 25 and the third relay 29 are connected in parallel. That is, the inrush current prevention circuit 15 shown in FIG. 9 has one relay configuration.

  The inverter device 1 includes a signal calculation device 47. The signal calculation device 47 supplies the third control signal to the third relay 29 based on the first control signal supplied from the control board 43 and the second control signal supplied from the inverter board 45.

  FIG. 10 is a diagram illustrating an example of a functional configuration of the signal arithmetic device 47 included in the inverter device 1 according to the second embodiment of the present invention. As shown in FIG. 10, the signal calculation device 47 includes an OR calculation unit 91. The OR operation unit 91 outputs the result of the OR operation between the first control signal and the second control signal as a third control signal and supplies it to the inrush current prevention circuit 15.

  Specifically, the OR operation unit 91 outputs a logical sum of the input signals. For example, if one of the first control signal and the second control signal is in the Hi level, the OR operation unit 91 sets the third control signal in the Hi level.

(Operation of Embodiment 2)
FIG. 11 is a flowchart for explaining a control example of the signal calculation device 47 included in the inverter device 1 according to the second embodiment of the present invention.

(Step S71)
The signal arithmetic unit 47 determines whether the first control signal or the second control signal has arrived. When the first control signal or the second control signal arrives, the signal calculation device 47 proceeds to step S72. On the other hand, when the first control signal or the second control signal does not arrive, the signal calculation device 47 returns to step S71.

(Step S72)
The signal operation device 47 performs an OR operation between the first control signal and the second control signal.

(Step S73)
The signal arithmetic unit 47 supplies the execution result of the OR operation to the inrush current prevention circuit 15 and ends the process.

(Effect of Embodiment 2)
From the above description, the third relay 29 is controlled by one of the first control signal and the second control signal. And since the inrush current prevention circuit 15 only needs one relay structure, it can suppress cost and can be comprised by space saving.

  As described above, in the second embodiment, the control board 43 that controls the inrush current prevention circuit 15 and the inverter board 45 and the control board 43 or the inverter board 45 controlled as one or a plurality of relays. 3, and a signal arithmetic device 47 that controls the third relay 29. The signal arithmetic device 47 includes a first control signal supplied from the control board 43 and a second control supplied from the inverter board 45. Based on at least one of the signals, the third relay 29 is closed.

  Therefore, the inverter device 1 can be reduced in cost and can be configured in a space-saving manner.

Embodiment 3 FIG.
(Difference)
In the third embodiment, a detailed example of the signal calculation device 47 will be described.

(Configuration of Embodiment 3)
FIG. 12 is a diagram illustrating a configuration example of the electrical component box 9 according to the third embodiment of the present invention. As shown in FIG. 12, the electrical component box 9 includes, for example, a power supply board 41, a control board 43, an inverter board 45, a rectifier 11, a DC reactor 13, a smoothing capacitor 17, an inverter 19, a first voltage detecting means 31, and a first voltage detector 31. 2 voltage detection means 33 etc. are provided.

  Here, a heat sink (not shown) is provided on the back side of each of the power supply board 41, the control board 43, and the inverter board 45. The electrical component box 9 is provided in an outdoor unit 111 described later.

  FIG. 13 is a diagram illustrating an example of an electrical configuration of the signal arithmetic device 47 according to Embodiment 3 of the present invention. Here, it is assumed that the reference potential of the control board 43 and the reference potential of the inverter board 45 are the same potential. That is, since the control board 43 and the inverter board 45 are at the same potential, there is no possibility that a short circuit state occurs between the control board 43 and the inverter board 45.

  As shown in FIG. 13, the signal calculation device 47 includes a first semiconductor switch 93 and a second semiconductor switch 95. Specifically, the signal calculation device 47 includes a first semiconductor switch 93 that gate-inputs a first control signal, a second semiconductor switch 95 that gate-inputs a second control signal, and an OR operation unit 91. . The first power supply 101 and the second power supply 102 are power supplies that drive the third relay 29.

  A first semiconductor switch 93 is provided between the first power supply 101 and the OR operation unit 91, and a second semiconductor switch 95 is provided between the second power supply 102 and the OR operation unit 91. By using two semiconductor switches, the signal arithmetic unit 47 can be reduced in size and cost can be reduced.

(Operation of Embodiment 3)
When the first control signal is input to the first semiconductor switch 93, the first semiconductor switch 93 supplies the voltage supplied from the first power supply 101 to the OR operation unit 91. Since the OR operation unit 91 outputs a logical sum of inputs, the voltage supplied from the first power supply 101 is applied to the third relay 29, and the third relay 29 transits from the open state to the short circuit state.

  When the second control signal is input to the second semiconductor switch 95, the second semiconductor switch 95 supplies the voltage supplied from the second power supply 102 to the OR operation unit 91. Since the OR operation unit 91 outputs a logical sum of inputs, the voltage supplied from the second power supply 102 is applied to the third relay 29, and the third relay 29 transitions from the open state to the short circuit state.

  When the first control signal is input to the first semiconductor switch 93 and the second control signal is input to the second semiconductor switch 95, the first semiconductor switch 93 uses the voltage supplied from the first power supply 101 as an OR operation unit. The second semiconductor switch 95 supplies the voltage supplied from the second power supply 102 to the OR operation unit 91. In order to output a logical sum of inputs, the OR operation unit 91 applies a voltage supplied from the first power supply 101 or a voltage supplied from the second power supply 102 to the third relay 29, and the third relay 29 is in an open state. Transition from short circuit to short circuit.

  When the first control signal is not input to the first semiconductor switch 93 and the second control signal is not input to the second semiconductor switch 95, the first semiconductor switch 93 uses the voltage supplied from the first power supply 101 as an OR operation unit. The second semiconductor switch 95 does not supply the voltage supplied from the second power supply 102 to the OR operation unit 91. Since the OR operation unit 91 outputs the logical sum of the inputs, nothing is output to the third relay 29, and the third relay 29 maintains the open state.

(Effect of Embodiment 3)
From the above description, the inverter device 1 can reduce the size of the signal arithmetic device 47 and achieve low cost by using two semiconductor switches.

  The OR operation unit 91 only needs to perform a logical sum operation, and its configuration is not particularly limited. The OR operation unit 91 may be configured by an OR circuit, for example, or may be configured by providing a NOT circuit at each input of the NAND circuit. Further, the OR operation unit 91 may be configured by an analog circuit instead of a digital circuit.

  As described above, in the third embodiment, the signal calculation device 47 has the same reference potential of the inverter substrate 45 and the reference potential of the control substrate 43, and opens and closes based on the second control signal. 95, and a first semiconductor switch 93 that is non-insulated from the second semiconductor switch 95 and opens and closes based on one control signal, and the output of the first semiconductor switch 93 and the output of the second semiconductor switch 95 Based on the result of the logical sum operation, the third relay 29 is closed.

  Therefore, the inverter device 1 can reduce the size of the signal arithmetic device 47 and realize low cost.

Embodiment 4 FIG.
(Difference)
In the fourth embodiment, a detailed example of the signal calculation device 47 will be described.

(Configuration of Embodiment 4)
FIG. 14 is a diagram illustrating an example of an electrical configuration of the signal arithmetic device 47 according to Embodiment 4 of the present invention. Here, it is assumed that the reference potential of the control board 43 is different from the reference potential of the inverter board 45. That is, since the control board 43 and the inverter board 45 are not at the same potential, a short circuit may occur between the control board 43 and the inverter board 45.

  As shown in FIG. 14, the signal calculation device 47 includes a second semiconductor switch 95 and a third semiconductor switch 97. Specifically, the signal calculation device 47 includes a third semiconductor switch 97 that gate-inputs the first control signal, a second semiconductor switch 95 that gate-inputs the second control signal, and an OR operation unit 91. . The first power supply 101 and the second power supply 102 are power supplies that drive the third relay 29.

  A third semiconductor switch 97 is provided between the first power supply 101 and the OR operation unit 91, and a second semiconductor switch 95 is provided between the second power supply 102 and the OR operation unit 91. By using two semiconductor switches, the signal arithmetic unit 47 can be reduced in size and cost can be reduced.

  Further, the third semiconductor switch 97 is constituted by an insulating specification semiconductor switch such as a photocoupler. With this configuration, the potential on the control board 43 side is insulated from the potential on the inverter board 45 side.

(Operation of Embodiment 4)
When the first control signal is input to the third semiconductor switch 97, the third semiconductor switch 97 supplies the voltage supplied from the first power supply 101 to the OR operation unit 91. Since the OR operation unit 91 outputs a logical sum of inputs, the voltage supplied from the first power supply 101 is applied to the third relay 29, and the third relay 29 transits from the open state to the short circuit state.

  When the second control signal is input to the second semiconductor switch 95, the second semiconductor switch 95 supplies the voltage supplied from the second power supply 102 to the OR operation unit 91. Since the OR operation unit 91 outputs a logical sum of inputs, the voltage supplied from the second power supply 102 is applied to the third relay 29, and the third relay 29 transitions from the open state to the short circuit state.

  When the first control signal is input to the third semiconductor switch 97 and the second control signal is input to the second semiconductor switch 95, the third semiconductor switch 97 converts the voltage supplied from the first power supply 101 into an OR operation unit. The second semiconductor switch 95 supplies the voltage supplied from the second power supply 102 to the OR operation unit 91. In order to output a logical sum of inputs, the OR operation unit 91 applies a voltage supplied from the first power supply 101 or a voltage supplied from the second power supply 102 to the third relay 29, and the third relay 29 is in an open state. Transition from short circuit to short circuit.

  When the first control signal is not input to the third semiconductor switch 97 and the second control signal is not input to the second semiconductor switch 95, the third semiconductor switch 97 uses the voltage supplied from the first power supply 101 as an OR operation unit. The second semiconductor switch 95 does not supply the voltage supplied from the second power supply 102 to the OR operation unit 91. Since the OR operation unit 91 outputs the logical sum of the inputs, nothing is output to the third relay 29, and the third relay 29 maintains the open state.

(Effect of Embodiment 4)
From the above description, the inverter device 1 can reduce the size of the signal arithmetic device 47 and achieve low cost by using two semiconductor switches.

  The OR operation unit 91 only needs to perform a logical sum operation, and its configuration is not particularly limited. The OR operation unit 91 may be configured by an OR circuit, for example, or may be configured by providing a NOT circuit at each input of the NAND circuit. Further, the OR operation unit 91 may be configured by an analog circuit instead of a digital circuit.

  Further, the third semiconductor switch 97 is not limited to the photocoupler described above, as long as it can be electrically insulated. For example, a combination of the light emitting element and the light receiving element may correspond to the third semiconductor switch 97. In this case, the light emitting element emits light by the input of the first control signal, and the light receiving element receives light emitted from the light emitting element, so that the light receiving element conducts the first power supply 101 and the OR operation unit 91. I just need it.

  Further, since the potential on the control board 43 side is insulated from the potential on the inverter board 45 side, if the contact side of the third relay 29 and the reference potential of the inverter board 45 are configured with the same potential, The insulation distance between the coil portion of the third relay 29 and the contact portion of the third relay 29 can be shortened. With such a circuit configuration, since the wiring length of each element can be shortened, the substrate pattern can be relatively enlarged by that amount. Therefore, the inverter device 1 can increase the current and suppress the temperature of the substrate.

  As described above, in the fourth embodiment, the signal arithmetic unit 47 is different from the reference potential of the inverter board 45 and the reference potential of the control board 43, and is opened and closed based on the second control signal. A switch 95 and a third semiconductor switch 97 that is insulated from the second semiconductor switch 95 and opens and closes based on the first control signal. The output of the second semiconductor switch 95 and the output of the third semiconductor switch 97 And the third relay 29 is closed based on the result of the logical sum operation.

  Therefore, the inverter device 1 can reduce the size of the signal arithmetic device 47 and realize low cost. Moreover, since the inverter apparatus 1 can enlarge a board | substrate pattern, while being able to increase current, it can suppress the temperature of a board | substrate.

Embodiment 5. FIG.
(Difference)
The difference from the other embodiments is that a chopper circuit 12 or a switching converter 14 is configured as the rectifier 11.

(Configuration of Embodiment 5)
In the first to fourth embodiments, the rectifier 11 that performs three-phase full-wave rectification is described on the assumption that the commercial power supply 3 is a three-phase AC power supply. However, as described in the above differences, the chopper The circuit 12 or the switching converter 14 may be configured.

FIG. 15 is a diagram showing an example of an electrical configuration of inverter device 1 according to the fifth embodiment of the present invention. As shown in FIG. 15, the DC current output from the chopper circuit 12 is supplied to the DC reactor 13, and the DC voltage output from the chopper circuit 12 is supplied to the smoothing capacitor 17. That is, the chopper circuit 12 converts the power supplied from the outside into a DC power and supplies it, so that the same effects as those described in the first to fourth embodiments can be obtained.

  FIG. 16 is a diagram showing another example of the electrical configuration of inverter device 1 according to the fifth embodiment of the present invention. As shown in FIG. 16, the DC current output from the switching converter 14 is supplied to the DC reactor 13, and the DC voltage output from the switching converter 14 is supplied to the smoothing capacitor 17. That is, since the switching converter 14 converts the power supplied from the outside into a DC power and supplies it, the same effects as those described in the first to fourth embodiments can be obtained.

  That is, the circuit configuration to be rectified is not particularly limited as long as it is converted to a DC power source. The commercial power supply 3 may be a single-phase AC power supply.

(Effect of Embodiment 5)
The circuit configuration to be rectified can obtain the same effects as those described in the first to fourth embodiments as long as it is converted to a DC power source.

  As described above, in the fifth embodiment, the rectifier 11 is configured by either one of the chopper circuit 12 and the switching converter 14.

  Therefore, the inverter device 1 can obtain the same effects as those described in the first to fourth embodiments as long as the circuit configuration to be rectified is converted to a DC power source.

Embodiment 6 FIG.
(Difference)
In the sixth embodiment, an air conditioner 110 including a compressor 131 having a motor 7 driven by the inverter device 1 will be described.

(Configuration of Embodiment 6)
FIG. 17 is a diagram illustrating an example of the air conditioner 110 using the inverter device 1 according to Embodiment 6 of the present invention. As shown in FIG. 17, the air conditioner 110 includes an outdoor unit 111 and an indoor unit 112_1 to an indoor unit 112_N. Note that the indoor units 112_1 to 112_N are referred to as indoor units 112 unless particularly distinguished.

  The outdoor unit 111 and the indoor unit 112 are connected by a gas side refrigerant pipe 121 and a liquid side refrigerant pipe 122. Further, in the gas side refrigerant pipe 121, an outdoor unit 111 and an indoor unit 112 are connected by a gas side valve 123. In the liquid side refrigerant pipe 122, the outdoor unit 111 and the indoor unit 112 are connected by a liquid side valve 124. That is, the outdoor unit 111 and the indoor unit 112 are connected by the gas-side refrigerant pipe 121 and the liquid-side refrigerant pipe 122 to constitute a refrigerant circuit as described later. Note that the gas-side refrigerant pipe 121 and the liquid-side refrigerant pipe 122 are referred to as the refrigerant pipe 120 unless particularly distinguished from each other.

  The outdoor unit 111 includes a compressor 131, a four-way valve 132, an outdoor heat exchanger 133, an accumulator 134, a second expansion device 137, an outdoor fan 141, and the like. The indoor unit 112_1 includes an indoor heat exchanger 135_1, a first expansion device 136_1, an indoor fan 143_1, and the like. The outdoor unit 111 includes the electrical component box 9 described above, but since FIG. 17 is a refrigerant system diagram, illustration is omitted here.

  Note that the indoor units 112_2 to 112_N have the same configuration as that of the indoor unit 112_1, and thus description thereof is omitted. Moreover, when not distinguishing each of indoor heat exchanger 135_1-indoor heat exchanger 135_N in particular, it will be called the indoor heat exchanger 135. The first diaphragm 136_1 to the first diaphragm 136_N are referred to as the first diaphragm 136 when not particularly distinguished from each other. When the indoor fans 143_1 to 143_N are not particularly distinguished, they are referred to as indoor fans 143.

  The compressor 131, the four-way valve 132, the outdoor heat exchanger 133, the accumulator 134, the indoor heat exchanger 135, the first expansion device 136, and the second expansion device 137 are sequentially connected by the refrigerant pipe 120, and a refrigerant circuit is configured. Yes. The refrigerant circuit circulates the refrigerant while compressing and expanding the refrigerant. For example, the compressor 131 includes the motor 7 and compresses and discharges the refrigerant according to the driving of the motor 7. The four-way valve 132 switches the refrigerant path according to cooling or heating. The outdoor heat exchanger 133 condenses or evaporates the refrigerant by exchanging heat between the refrigerant and the outside air. The accumulator 134 stores surplus refrigerant. The indoor heat exchanger 135 evaporates or condenses the refrigerant by exchanging heat between the refrigerant and indoor air.

(Operation of Embodiment 6)
In the air conditioner 110, the compressor 131 is driven by the inverter device 1 driving the motor 7. At this time, in the inverter device 1, even if an abnormality occurs in the inverter 19, as described above, the switching element 87 of the inverter 19 is not broken down.

(Effect of Embodiment 6)
Even if the inverter device 1 is in an abnormal state, the switching element 87 can be prevented from being damaged, so that the air conditioner 110 can be operated stably.

  As described above, in the sixth embodiment, the outdoor unit 111, the outdoor unit 111, the indoor unit 112 connected to the gas side refrigerant pipe 121 and the liquid side refrigerant pipe 122, and constituting the refrigerant circuit, are provided. Includes a compressor 131 that compresses and discharges the refrigerant. The compressor 131 includes a motor 7, and the motor 7 is controlled by the inverter device 1.

  Therefore, even if the inverter device 1 is in an abnormal state, the switching element 87 can be prevented from being damaged, so that the air conditioner 110 can be operated stably.

  DESCRIPTION OF SYMBOLS 1 Inverter apparatus, 3 Commercial power supply, 5 Switch, 7 Motor, 9 Electrical box, 11 Rectifier, 12 Chopper circuit, 13 DC reactor, 14 Switching converter, 15 Inrush current prevention circuit, 17 Smoothing capacitor, 19 Inverter, 23 2 relay, 25 inrush current prevention resistor, 27 first relay, 29 third relay, 31 first voltage detection means, 33 second voltage detection means, 41 power supply board, 43 control board, 45 inverter board, 47 signal arithmetic device, 51 abnormality determination unit, 53 deceleration control unit, 55 relay control unit, 57 inverter control unit, 71 relay failure determination unit, 73 DC voltage abnormality determination unit, 75 operating rotation speed acquisition unit, 77 deceleration rotation speed acquisition unit, 79 Deceleration time calculation section, 83 Inverter drive signal determination section, 85 Gate control section, 87 sec Tatching element, 91 OR operation unit, 93 first semiconductor switch, 95 second semiconductor switch, 97 third semiconductor switch, 101 first power source, 102 second power source, 110 air conditioner, 111 outdoor unit, 112, 112_1 to 112_N Indoor unit, 120 refrigerant piping, 121 gas side refrigerant piping, 122 liquid side refrigerant piping, 123 gas side valve, 124 liquid side valve, 131 compressor, 132 four-way valve, 133 outdoor heat exchanger, 134 accumulator, 135, 135_1 135_N indoor heat exchanger, 136, 136_1-136_N 1st expansion device, 137 2nd expansion device, 141 outdoor fan, 143, 143_1-143_N indoor fan.

Claims (9)

A rectifier,
A direct current reactor connected to the anode side of the rectifier and smoothing the direct current of the rectifier;
A smoothing capacitor connected between the output side of the DC reactor and the cathode side of the rectifier and smoothing the DC voltage of the rectifier;
An inrush current prevention circuit that is provided between the DC reactor and the smoothing capacitor and prevents an inrush current to the smoothing capacitor;
An inverter for converting the DC voltage smoothed in the previous SL smoothing capacitor into an AC voltage,
An inverter board for controlling the inrush current prevention circuit and the inverter;
First voltage detection means for detecting a first voltage applied to the inrush current prevention circuit;
Second voltage detecting means for detecting a second voltage applied to the inverter;
With
The inrush current prevention circuit is
One or more relays connected between the DC reactor and the smoothing capacitor;
An inrush current preventing resistor connected in parallel with the one or more relays;
With
Of the one or more relays, each of the plurality of relays is connected in parallel,
The inverter board is
A deceleration control unit that decelerates and stops the inverter when the second voltage drops to a DC voltage abnormal level;
To said inverter by deceleration control by the deceleration control unit is stopped, one of the one or more relays, have at least one relay and a relay controller which closed, and
The deceleration control unit
The inverter device , wherein when the first voltage rises to a relay failure determination voltage level, the inverter is decelerated and stopped . A control board for controlling the inrush current prevention circuit and the inverter board ;
As the one or more relays, to claim 1, wherein the first relay, which is controlled by the control board, a second relay which is controlled by the pre-Symbol inverter board, the Bei obtain <br/> that the The described inverter device. A control board for controlling the inrush current prevention circuit and the inverter board;
A signal arithmetic device for controlling the one or more relays,
Wherein in one or more relays, and a third relays which are controlled by the control board or the inverter board,
The signal arithmetic unit is
The third relay is closed based on at least one of a first control signal supplied from the control board and a second control signal supplied from the relay control unit of the inverter board. The inverter device according to claim 1 . The inverter is
A switching element;
A gate control unit for controlling the switching element;
With
The inverter board is
The inverter device according to claim 3, wherein the inverter is controlled by controlling the gate control unit to gradually reduce an operation time of the switching element. The inverter board is
The inverter apparatus according to claim 4, wherein a deceleration time of the motor is obtained based on a current rotational speed of the motor driven by the inverter. The signal arithmetic unit is
The reference potential of the inverter board is the same as the reference potential of the control board,
A second semiconductor switch that opens and closes based on the second control signal;
A first semiconductor switch that is non-insulated with the second semiconductor switch and opens and closes based on the first control signal;
With
6. The inverter device according to claim 5, wherein the third relay is closed based on a result of an OR operation between the output of the first semiconductor switch and the output of the second semiconductor switch. . The signal arithmetic unit is
The reference potential of the inverter board is different from the reference potential of the control board,
A second semiconductor switch that opens and closes based on the second control signal;
A third semiconductor switch that is insulated from the second semiconductor switch and opens and closes based on the first control signal;
With
6. The inverter device according to claim 5, wherein the third relay is closed based on a result of an OR operation between the output of the second semiconductor switch and the output of the third semiconductor switch. . As the rectifier,
The inverter device according to any one of claims 1 to 7, wherein the inverter device includes any one of a chopper circuit and a switching converter. Outdoor unit,
An indoor unit connected to the outdoor unit by a gas side refrigerant pipe and a liquid side refrigerant pipe to constitute a refrigerant circuit;
With
The outdoor unit is
A compressor that compresses and discharges the refrigerant;
The compressor is
Equipped with a motor,
The motor is
The air conditioner controlled by the inverter apparatus as described in any one of Claims 1-8.

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